Novel memory array structure based on resistive random access memory and operation method thereof

Abstract

The invention discloses a novel memory array structure based on a resistive random access memory and an operation method thereof, and belongs to the technical field of semiconductor integrated circuits. The novel storage array structure comprises storage units distributed in an array mode, each storage unit is formed by connecting a transistor and an RRAM in series, the RRAM is located on a drain electrode of the transistor, every two storage units on the same row share one source electrode, every N columns of storage units share one P-type substrate, the multiple P-type substrates are isolated through DTI deep grooves, and N is larger than or equal to 1. All the storage units share one deep N well DNW, the deep N well DNW is located below the P-type substrate, RRAM top electrodes of the storage units in each row are connected through a bit line BL, and grid electrodes and source electrodes of transistors of the storage units in each column are connected through a word line WL and a source line SL respectively. High-current output can be realized only by applying a small input signal, so that the performance and the reliability of the storage unit are remarkably improved while the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical fields of semiconductors, memories, and CMOS hybrid integrated circuits. More specifically, it relates to a novel memory array structure based on a resistive random access memory and an operation method thereof. Background Art

[0002] With the development of information technology and the popularization of applications in fields such as big data, the Internet of Things, dedicated hardware, and cloud computing, the requirements for storage density and performance of non-volatile memories are constantly increasing. Due to the constant programming voltage of traditional flash memories, the reliability and data retention characteristics are sensitive to device size, and are limited by physical limits such as charge discontinuity, the further improvement of their storage density and performance is restricted, making it difficult to meet future non-volatile storage requirements. A resistive random access memory (RRAM) can switch between a high resistance state and a low resistance state according to the voltage difference between two electrodes, and is an emerging non-volatile memory with great application prospects, having many advantages such as high storage density, fast erasing and writing speed, easy miniaturization and integration, and low power consumption.

[0003] 1T1R (1 Transistor 1 RRAM) is one of the common array structures of resistive random access memories. Each unit of this structure consists of 1 RRAM and 1 transistor connected in series. The transistor is a select transistor. When it is turned on, the RRAM is selected and can be operated; when it is turned off, the RRAM cannot be operated. This structure can achieve random access and eliminate crosstalk.

[0004] However, traditional structure resistive random access memories have high requirements for the driving ability of the select transistor and parasitic resistance, which limits the storage density. When the RRAM performs FORMING, SET, and RESET operations, the RRAM and the series-connected transistor form an equivalent voltage division relationship. When the total applied voltage difference is constant, the larger the equivalent on-resistance of the transistor, the larger the voltage difference between the source and drain, and the smaller the voltage drop between the two electrodes of the RRAM. Therefore, the transistor needs to have a sufficiently small on-resistance, which severely limits the reduction of the transistor gate width, increases the cell volume, and reduces the storage density of the resistive random access memory. Since the area occupied by the RRAM itself is very small, solving the above problems to reduce the area of the select transistor and the select transistor pitch is an important means to improve the storage density of the resistive random access memory. Summary of the Invention

[0005] The present invention proposes a novel memory array structure based on a resistive random access memory and an operation method thereof, which relaxes the limitation on the minimum gate width of the transistor without changing the performance.

[0006] A novel memory array structure based on a resistive random access memory (RRAM), characterized in that it includes memory cells distributed in an array. Each memory cell is formed by connecting a transistor in series with an RRAM, where the RRAM is located at the drain of the transistor. Every two memory cells in the same row share a source electrode, and every N columns of memory cells share a P-type substrate. Multiple P-type substrates are isolated from each other by deep trench isolation (DTI). All memory cells share a deep N-well (DNW), and the deep N-well DNW is located below the P-type substrate. The top electrodes of the RRAMs of each row of memory cells are connected through bit lines (BLs). The gate electrodes and source electrodes of the transistors of each column of memory cells are connected through word lines (WLs) and source lines (SLs), respectively.

[0007] Further, the SL is located below the source electrode of the RRAM of the memory cell and remains grounded.

[0008] Further, on the P-type substrate, a horizontal P+-doped region is provided as a horizontal substrate contact line every M rows of memory cells, and the potential of all memory cells on the entire P-type substrate is controlled through this substrate contact line.

[0009] Further, each P-type substrate is provided with a vertically oriented substrate lead-out line. The substrate contact line is connected to the vertically oriented substrate lead-out line through a via hole above it, and the substrate contact line is controlled through the substrate lead-out line.

[0010] Further, a contact region doped with N+ is provided at the edge of the deep N-well DNW, and this N+-doped contact region is connected to the vertically oriented substrate lead-out line through a via hole.

[0011] Meanwhile, the present invention provides an operation method for a novel memory array structure based on a resistive random access memory (RRAM), and its steps are as follows:

[0012] 1) When writing SET, a high level is applied to the BL and WL where the memory cell is selected, and the remaining connections and the substrate lead-out are kept grounded. After the transistor in the memory cell to be written is turned on, the top electrode of the RRAM is at the high level of the BL and the bottom electrode is grounded, and it is set to the low resistance state.

[0013] 2) When erasing RESET, a high level is applied to the substrate where the memory cell to be erased is located, where the DNW is applied with a level higher than that of the P-type substrate, and the BL where it is located is grounded; all WLs are grounded. At this time, all transistors are turned off, and the array is equivalent to a 1T1R array with a BJT as the select transistor.

[0014] 3) When reading, a logic level is applied to the WL where the memory cell is selected, and a relatively small RRAM read voltage is applied to the BL to achieve random access.

[0015] The beneficial effects of the present invention are as follows:

[0016] Compared with the existing RESET method of resistive random access memory (RRAM) cells based on the forward biasing of the parasitic PN junction between the P-type substrate and the drain, the double bipolar junction transistor (BJT) structure adopted in the present invention for RESET operation can significantly improve the driving ability. Without changing the performance, the minimum gate width limit of the transistor is relaxed, and only a small input signal is required to achieve high current output, thereby reducing power consumption while significantly improving the performance and reliability of the memory cell. Description of the Drawings

[0017] Figure 1 It is a schematic circuit diagram of the memory cell in the novel memory array structure of the present invention;

[0018] Figure 2 It is a schematic diagram of the novel memory array structure of the present invention;

[0019] Figure 3 It is a partial cross-sectional schematic diagram of the novel memory array structure of the present invention;

[0020] Figure 4 It is a cross-sectional schematic diagram of the novel memory array structure of the present invention;

[0021] Figure 5 It is a top view schematic diagram of the novel memory array structure of the present invention. Detailed Embodiments

[0022] The present invention will be further described below with specific embodiments in conjunction with the drawings.

[0023] The novel memory array structure of the present invention based on resistive random access memory includes a plurality of memory cells, as Figure 1 shown. Each memory cell is formed by connecting a transistor in series with an RRAM, and the RRAM is located at the drain of the transistor. Every two memory cells in the same row share a source. In the present invention, every N columns of memory cells share a P-type substrate, and all memory cells share a deep N-well (DNW), and the DNW is located below the P-type substrate. Through this structure, the deep N-well, the P-type substrate and the drain of the transistor together form an NPN-type bipolar junction transistor (BJT). In this BJT, the deep N-well serves as the collector, the P-type substrate serves as the base, and the drain of the transistor serves as the emitter.

[0024] As Figure 2 shown, the top electrodes of the RRAMs of each row of cells in the novel memory array structure of the present invention are connected through bit lines (BLs), and the gate electrodes and source electrodes of each column of memory cells are respectively connected through word lines (WLs) and source lines (SLs); where the SL is located below the source and can be kept grounded.

[0025] During writing (SET), a high level is applied to BL and WL where the selected storage cell is located, and the remaining connections and the substrate lead are kept grounded. When the transistor in the storage cell to be written is turned on, the top electrode of the RRAM is at a high level of BL and the bottom electrode is approximately grounded, and it is set to a low resistance state. Random writing can be achieved through the cross selection of BL and WL.

[0026] During erasing (RESET), a high level is applied to the substrate where the storage cell to be erased is located, where the level applied to DNW is higher than that of the P-type substrate, and the BL where it is located is grounded; WLs are all grounded. At this time, all transistors are turned off, and the array is equivalent to a 1T1R array with a BJT as the gated transistor. The substrate voltage of the storage cell to be erased is relatively high while the top electrode of the RRAM is grounded. The emitter junction of the BJT formed by the substrate and the drain is forward-biased, and the collector junction is reverse-biased. The BJT is in the forward active region (FAR), and can achieve the linear amplification function. The amplified current is output from the transistor drain (i.e., the emitter of the BJT) to the bottom electrode of the RRAM, making the RRAM set to a high resistance state. At the same time, the non-selected BL is connected to the same level as the deep N-well, and the P-type substrate of the non-selected cell is grounded to protect the non-selected cell. At this time, no voltage is directly applied between the two electrodes of the RRAM in the non-selected storage cell; and the reverse breakdown voltage of the parasitic PN junction between the base and the emitter is relatively large, only allowing current to flow unidirectionally, cutting off the crosstalk and leakage paths. Therefore, there is no crosstalk problem in the erasing operation.

[0027] During reading, a logic level is applied to the WL of the target storage cell, and a relatively small RRAM read voltage is applied to the BL, enabling random access.

[0028] The cross-sectional view of the novel storage array structure based on the resistive random access memory of the present invention is as Figure 3 , and each storage cell is formed by connecting a transistor and an RRAM in series. The RRAM is located at the drain of the transistor, and every two storage cells on the same row share a source. Every N columns of storage cells share a P substrate (PW), and all storage cells share a DNW.

[0029] As Figure 4 shown, a total of 4N columns of storage devices can be placed on each P substrate (N is the number of columns of storage cells on the substrate, which is a positive integer). The P-type substrates of each part are isolated by DTI deep trenches. Separate voltages can be applied to each part of the substrate through the substrate lead. The P-type substrates are isolated by DTI deep trenches. The deep N-well DNW is located below the P-type substrate. The top electrodes of the RRAMs of each row of storage cells are connected through the bit line BL, and the gate electrodes and the common source electrodes of each column of storage cells are connected through the word line WL and the source line SL respectively.

[0030] As Figure 5As shown, each P substrate is provided with a vertical substrate lead-out line, and a long, horizontal P+ doped area is provided for every M rows of memory cells on the P substrate as a horizontal substrate contact (M is the number of memory cell rows, which is a positive integer). The potential of all memory cells in a whole P substrate is controlled by the horizontal substrate contact line. The substrate contact line is connected to the vertical substrate lead-out line through a through hole, and the substrate contact line and even the substrate potential are controlled by the metal wire led out. There is a DTI between every two P substrates as a substrate partition. At the edge of the memory array, the DNW is connected to the vertical substrate contact line through a through hole by the contact area with N+ type doping on the top, and led out, or can be led out by back power supply and other technologies. This line can be grounded during use.

[0031] The specific operations of writing, erasing and reading the new storage array structure based on resistive random access memory include the following steps:

[0032] 1) When BL k , W.L. m When the located cell is written, the P substrate where the cell is located is grounded, and DNW is kept connected to a high level, so that the BJT emitter junction is reverse biased, the collector junction is reverse biased, and it works in the cut-off region. m Applying a high level turns on the transistor and k The write operation to the cell can be completed by applying a write voltage and reading a response current through the SL corresponding to the cell.

[0033] 2) When BL k , W.L. m When the located cell is erased, an erase voltage is applied to the P substrate where the cell is located, and DNW is kept connected to a high level. It should be noted that the erase voltage applied to the P substrate should be lower than the high level of DNW, so that the BJT emitter junction is forward biased and the collector junction is reverse biased, working in the amplification area. m and BL k All are grounded, while the non-selected WL is grounded, and the non-selected BL is connected to the same high level as DNW, so that the BJT emitter junction and collector junction on the non-selected unit are reverse biased and work in the cut-off region, thereby protecting the non-selected unit from parasitic effects. k By reading the response current, the erase operation of the cell can be completed.

[0034] 3) When BL k , W.L. m When the located cell is read, the P substrate where the cell is located is grounded, and DNW is kept connected to a high level, so that the BJT emitter junction is reverse biased, the collector junction is reverse biased, and it works in the cut-off region. m Applying a high level turns on the transistor and kApply a read voltage and read the response current through the SL corresponding to the cell, and the reading operation of the cell can be completed.

[0035] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Those of ordinary skill in the art can modify or equivalently replace the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A novel storage array structure based on resistive random access memory, characterized in that: The invention comprises memory cells distributed in an array, each memory cell is formed by a transistor and an RRAM connected in series, the RRAM is located at the drain of the transistor, every two memory cells on the same row share a source, every N columns of memory cells share a P-type substrate, a plurality of P-type substrates are isolated by DTI deep trenches, all memory cells share a deep N-well DNW, the deep N-well DNW is located below the P-type substrate, the RRAM top electrodes of the memory cells in each row are connected through a bit line BL, and the gate and source of the transistors of the memory cells in each column are connected through a word line WL and a source line SL respectively.

2. The novel storage array structure based on resistive random access memory as claimed in claim 1, characterized in that: The SL is located under the RRAM source of the memory cell and is kept grounded.

3. The novel storage array structure based on resistive random access memory as claimed in claim 1, characterized in that: A lateral P+ doping region is provided for every M rows of storage cells on the P-type substrate as a lateral substrate contact line, and the potential of all storage cells on a whole P substrate is controlled through the substrate contact line.

4. The novel storage array structure based on resistive random access memory as claimed in claim 3, characterized in that: Each P substrate is provided with a vertical substrate lead-out line, and the substrate contact line is connected to the vertical substrate lead-out line through a through hole, and the substrate contact line is controlled by the substrate lead-out line.

5. The novel storage array structure based on resistive random access memory as claimed in claim 4, characterized in that: An N+ doped contact region is provided at the edge of the deep N well DNW, and the N+ doped contact region is connected to a vertically extending substrate lead through a through hole.

6. The method for operating the novel memory array structure based on resistive random access memory according to claim 1, wherein the steps include: 1) When writing SET, the BL and WL where the selected storage cell is located are applied with high level, and the other wires and substrate leads are kept grounded. The transistor in the storage cell to be written is turned on, the top electrode of RRAM is BL high level and the bottom electrode is grounded, and is set to a low resistance state; 2) When erasing RESET, a high level is applied to the substrate where the memory cell to be erased is located, where the level applied to DNW is higher than that of the P-type substrate, and the BL where it is located is grounded; WL is also grounded; 3) When reading, the memory cell WL is selected to apply the logic level, and BL applies the RRAM read voltage to achieve random access.

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