Preparation method of semiconductor device, semiconductor device, power module, power conversion circuit and vehicle

Abstract

The invention discloses a preparation method of a semiconductor device, the semiconductor device, a power module, a power conversion circuit and a vehicle, and the method comprises the steps: providing a first semiconductor body, and enabling a first surface of the first semiconductor body to be provided with a first source electrode groove; forming a cushion layer in the first source electrode trench; a second semiconductor body is formed on one side of the first semiconductor body, the second semiconductor body further comprises a well region and a first area, the first area is arranged on the fourth surface of the second semiconductor body, and the well region is arranged on the side, away from the fourth surface, of the first area; the fourth surface is also provided with a second source electrode groove and a grid electrode groove; the second source electrode trench is close to one side of the substrate, and at least part of the cushion layer is exposed; the cushion layer is removed, so that the second source electrode sub-groove and the first source electrode sub-groove are communicated to form a source electrode groove, according to the preparation method of the semiconductor device, the limitation of the design depth of the grid electrode groove on the depth of the source electrode groove is avoided, and the requirements of etching equipment and an etching process are reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of semiconductor devices, and in particular, to a method for manufacturing a semiconductor device, a semiconductor device, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Silicon carbide (SiC) has excellent physical and electrical properties. Currently, semiconductor devices prepared using SiC materials have advantages such as a large current density and a small cell pitch, and are widely used.

[0003] However, when performing trench etching, if the gate trench and the source trench are etched using a common mask, the depth of the source trench will be limited by the designed depth of the gate trench. If the gate trench and the source trench are etched step by step, to achieve a deeper depth for the source trench, high requirements are imposed on the etching equipment and the etching process, which is not conducive to the development requirements of producers for cost reduction and efficiency improvement. Summary of the Invention

[0004] The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, a power module, a power conversion circuit, and a vehicle, which avoids the limitation of the designed depth of the gate trench on the depth of the source trench and reduces the requirements for the etching equipment and the etching process.

[0005] In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:

[0006] Providing a first semiconductor body, which is set to a first conduction type, the first semiconductor body includes a first surface and a second surface that are oppositely arranged, the first surface is provided with a first source sub-trench, and the first source sub-trench extends from the first surface into the first semiconductor body;

[0007] Forming a cushion layer in the first source sub-trench;

[0008] Forming a second semiconductor body on one side of the first semiconductor body, the second semiconductor body includes a third surface and a fourth surface that are oppositely arranged, the third surface is in contact connection with the first surface; the second semiconductor body further includes a well region and a first region, the first region is set to a first conduction type and is disposed on the fourth surface, the well region is set to a second conduction type and is disposed on a side of the first region away from the fourth surface, the first conduction type is different from the second conduction type; the fourth surface is further provided with a second source sub-trench and a gate trench, both the second source sub-trench and the gate trench extend from the fourth surface into the second semiconductor body; the second source sub-trench is close to the first surface side and at least exposes a part of the cushion layer;

[0009] Remove the cushion layer so that the second source trench and the first source trench communicate to form a source trench; the depth of the source trench is greater than the depth of the gate trench.

[0010] Optionally, the first semiconductor body includes a substrate and a first epitaxial layer;

[0011] Provide a first semiconductor body, including:

[0012] Form the first epitaxial layer on one side of the substrate;

[0013] The surface of the first epitaxial layer away from the substrate is used as the first surface, and the first source trench is formed on the first surface; the first source trench extends from the first surface into the first epitaxial layer.

[0014] Optionally, the second semiconductor body includes a second epitaxial layer;

[0015] Form a second semiconductor body on one side of the first semiconductor body, including:

[0016] Form the second epitaxial layer on the first surface;

[0017] Use the surface of the second epitaxial layer away from the substrate as the fourth surface, and form the first region on the fourth surface;

[0018] Form the well region on one side of the second epitaxial layer away from the first region;

[0019] Form the second source trench and the gate trench on the fourth surface; wherein, the second source trench and the gate trench extend from the fourth surface into the second epitaxial layer; the positive projection of the first source trench on the substrate at least covers the positive projection of the second source trench on the substrate; the second source trench and the first source trench communicate to form the source trench.

[0020] Optionally, after removing the cushion layer, it includes:

[0021] Form a second region in the inner extension region of the adjacent epitaxial layer on the side wall and bottom of the source trench, and the second region is of the second conductivity type.

[0022] Optionally, after using the surface of the first epitaxial layer away from the substrate as the first surface and forming the first source trench on the first surface, it includes:

[0023] Form a second region in the inner extension region of the adjacent first epitaxial layer on the side wall and bottom of the first source trench;

[0024] After removing the cushion layer, it includes:

[0025] Form a second region in the inner extension region of the adjacent second epitaxial layer on the sidewall of the second source trench.

[0026] Optionally, the first epitaxial layer and the second epitaxial layer have the same conductivity type as the substrate; the substrate is of the first conductivity type.

[0027] Optionally, after removing the cushion layer, it includes:

[0028] Form a gate structure in the gate trench;

[0029] The gate structure includes a first insulating layer and a trench gate;

[0030] Forming a gate structure in the gate trench includes:

[0031] Form a first insulating layer on the bottom and sidewalls of the gate trench;

[0032] Form a trench gate on the side of the first insulating layer away from the gate trench.

[0033] Optionally, after or simultaneously with forming the gate structure in the gate trench, it further includes:

[0034] Form a source trench structure in the source trench;

[0035] The source trench structure includes a second insulating layer and a filling layer;

[0036] Forming a source trench structure in the source trench includes:

[0037] Form a second insulating layer on the bottom and sidewalls of the source trench;

[0038] Form a filling layer on the side of the second insulating layer away from the source trench;

[0039] After forming the source trench structure in the source trench, it includes:

[0040] Form a source on the fourth surface.

[0041] In a second aspect, an embodiment of the present invention provides a semiconductor device, including:

[0042] A first semiconductor body, including a first surface and a second surface arranged oppositely, the first surface is provided with a first source trench, and the first source trench extends from the first surface into the first semiconductor body; the first semiconductor body is set to be of the first conductivity type;

[0043] A second semiconductor body is located on one side of the first semiconductor body. The second semiconductor body includes a third surface and a fourth surface which are oppositely arranged, and the third surface is in contact connection with the first surface. The second semiconductor body further includes a well region and a first region. The first region is set to a first conduction type and is disposed on the fourth surface. The well region is set to a second conduction type and is disposed on a side of the first region away from the fourth surface, and the first conduction type is different from the second conduction type. The fourth surface is further provided with a second source trench and a gate trench, and both the second source trench and the gate trench extend from the fourth surface into the second semiconductor body, so that the second source trench and the first source trench are penetrated to form a source trench. The depth of the source trench is greater than the depth of the gate trench.

[0044] Optionally, the first semiconductor body includes:

[0045] A substrate;

[0046] A first epitaxial layer is located on one side of the substrate. The surface of the first epitaxial layer away from the substrate is used as the first surface, and the surface of the substrate away from the first epitaxial layer is used as the second surface.

[0047] Optionally, the second semiconductor body includes a second epitaxial layer;

[0048] The second epitaxial layer is located on a side of the first epitaxial layer away from the substrate. The surface of the second epitaxial layer close to the substrate is used as the third surface, and the surface of the second epitaxial layer away from the substrate is used as the fourth surface.

[0049] Optionally, the first semiconductor body and the second semiconductor body further include a second region,

[0050] The second region is located on a side of the side wall and the bottom of the source trench, and the second region extends from the side wall and the bottom of the source trench into the first semiconductor body and the second semiconductor body.

[0051] In a third aspect, an embodiment of the present invention provides a power module, including a substrate and the semiconductor device according to any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0052] In a fourth aspect, an embodiment of the present invention provides a power conversion circuit, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0053] The power conversion circuit includes a circuit board and the semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0054] In a fifth aspect, an embodiment of the present invention provides a vehicle, including a load and the power conversion circuit according to any embodiment of the present invention. The power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input the converted current to the load.

[0055] The method for manufacturing a semiconductor device, the semiconductor device, the power module, the power conversion circuit, and the vehicle provided by the embodiments of the present invention include providing a first semiconductor body, pre-setting a first source sub-groove on the first semiconductor body, filling a cushion layer in the first source sub-groove, and then providing a second semiconductor body on a first surface. The second source sub-groove and the gate groove both extend from a fourth surface of the second semiconductor body into the second semiconductor body. The second source sub-groove is close to the substrate side and at least partially exposes the cushion layer. By removing the cushion layer, the second source sub-groove and the first source sub-groove are connected to form a source groove. Thus, a source groove with a relatively deep depth is obtained through two forming steps, avoiding the limitation of the depth of the gate groove on the depth of the source groove. And by etching the first source sub-groove and the second source sub-groove respectively, compared with forming a source groove with a relatively deep depth in one step, the requirements for etching equipment and etching process are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0057] Figures 2 - 8 is a schematic diagram of an intermediate structure of a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 9 is a schematic flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figures 10 - 11 is a schematic diagram of an intermediate structure of another semiconductor device provided by an embodiment of the present invention;

[0060] Figure 12 is a schematic flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0061] Figures 13 - 15 is a schematic diagram of an intermediate structure of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0063] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 FIG. [X] is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2 - 8 FIG. [X] is a schematic diagram of an intermediate structure in the manufacturing of a semiconductor device according to an embodiment of the present invention. Refer to Figures 1 - 8 , including:

[0064] S110. Provide a first semiconductor body 100. The first semiconductor body 100 includes a first surface and a second surface arranged opposite to each other. A first source sub-groove 10 is formed on the first surface, and the first source sub-groove 10 extends from the first surface into the first semiconductor body 100.

[0065] Specifically, the semiconductor device in the embodiment of the present invention can be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET). The first semiconductor body 100 can include a substrate 50 and a first epitaxial layer 20. The materials of the substrate 50 and the first epitaxial layer 20 can be silicon carbide. The first epitaxial layer 20 is formed on one side of the substrate 50, as Figure 2 shown. Exemplarily, the first epitaxial layer 20 can be formed on the surface of the substrate 50 by epitaxial growth.

[0066] The surface of the first epitaxial layer 20 away from the substrate 50 is used as the first surface. The first source sub-groove 10 is formed on the first surface by an etching process. The first source sub-groove 10 extends from the first surface into the first epitaxial layer 20, as Figure 3 shown.

[0067] S120. Form a cushion layer 12 in the first source sub-groove 10.

[0068] Note: The [X] in "FIG. [X]" needs to be filled with the actual figure number according to the original patent content.Among them, the cushion layer 12 can be an insulating layer for protecting the inner wall of the first source trench 10. The cushion layer 12 can be completely filled into the first source trench 10. For example, the cushion layer 12 can be made of silicon nitride material, and a certain thickness of the cushion layer 12 is deposited on the first surface of the first semiconductor body 100 through a deposition process. Among them, the material of the cushion layer 12 in the first source trench 10 can completely fill the inside of the first source trench 10, and then the first surface is exposed through a grinding process to keep the first surface flat, so as to ensure the structural stability of the subsequent formation of the second semiconductor body, such as Figure 4 shown.

[0069] S130. A second semiconductor body 101 is formed on one side of the first semiconductor body 100. The second semiconductor body 101 includes a third surface and a fourth surface arranged oppositely, and the third surface is in contact connection with the first surface; the second semiconductor body 101 further includes a well region 30 and a first region 40. The first region 40 is arranged on the fourth surface, and the well region 30 is arranged on the side of the first region 40 away from the fourth surface; a second source trench 60 and a gate trench 70 are further arranged on the fourth surface, and both the second source trench 60 and the gate trench 70 extend from the fourth surface into the second semiconductor body 101; on the side of the second source trench 60 close to the first surface, at least a part of the cushion layer 12 is exposed;

[0070] Specifically, the second semiconductor body 101 is arranged on the first surface of the first semiconductor body 100. Exemplarily, the second semiconductor body 101 includes a second epitaxial layer 80, and the second epitaxial layer 80 can be formed on the first surface by epitaxial growth. Among them, the materials of the first epitaxial layer 20 and the second epitaxial layer 80 can be the same, and the first epitaxial layer 20 and the second epitaxial layer 80 form an integral structure.

[0071] The surface of the second epitaxial layer 80 away from the first surface is used as the fourth surface. The first region 40 is arranged on the fourth surface, and the well region 30 is arranged on the side of the first region 40 away from the fourth surface. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation or vapor deposition, etc. The well region 30 and the first region 40 are used to form the conductive channel of the semiconductor device. Among them, the first region 40 is of the first conductivity type, and the well region 30 is of the second conductivity type, such as Figure 5 shown.

[0072] In the embodiments of the present invention, the first conduction type may be an N-type conduction type, the second conduction type may be a P-type conduction type, or the first conduction type may be a P-type conduction type and the second conduction type may be an N-type conduction type. Among them, the N-type conduction type can be obtained by doping P (phosphorus) or N (nitrogen) ions in the semiconductor, and the P-type conduction type can be obtained by doping Al (aluminum) ions or B (boron) ions in the semiconductor. P+ and N+ shown in the drawings indicate that the ion doping concentration in this region is high, and P- and N- indicate that the ion doping concentration in this region is low. Exemplarily, in the embodiments of the present invention, taking the first conduction type as an N-type conduction type and the second conduction type as a P-type conduction type as an example, the first semiconductor body 100 and the second semiconductor body 101 are set to the first conduction type. When the semiconductor device is an N-type device, the substrate 50 is of N+ conduction type, for example, it can be an N+ silicon carbide substrate 50; the first epitaxial layer 20 and the second epitaxial layer 80 are of N- conduction type, for example, it can be N- silicon carbide; when the semiconductor device is a P-type device, the substrate 50 is of P+ conduction type, and the first epitaxial layer 20 and the second epitaxial layer 80 are of P- conduction type.

[0073] A gate trench 70 and a second source trench 60 are formed on the fourth surface through an etching process. Among them, the gate trench 70 and the second source trench 60 can be synchronously etched and formed in the same preparation process. In some other embodiments, the gate trench 70 and the second source trench 60 can be set to different depths and shapes, and the gate trench 70 and the second source trench 60 can be etched separately. The gate trench 70 and the second source trench 60 penetrate through the first region 40 and the well region 30, and extend from the fourth surface to the second epitaxial layer 80. The second source trench 60 is located on one side of the gate trench 70. The second source trench 60 can be an annular trench, configured to surround the gate trench 70. The second source trench 60 can also be an independent trench, and a plurality of source trenches are distributed on both sides of the gate trench 70. Exemplarily, Figure 6 Second source trenches 60 are arranged on both sides of the gate trench 70, and the two second source trenches 60 can be symmetrically or asymmetrically arranged. Among them, the positive projection of the first source trench 10 on the substrate 50 at least covers the positive projection of the second source trench 60 on the substrate 50, that is to say, the first source trench 10 and the second source trench 60 are correspondingly positioned in the thickness direction of the first epitaxial layer 20 and the second epitaxial layer 80. The second source trench 60 penetrates through the second epitaxial layer 80, and at least part of the cushion layer 12 can be exposed at the bottom of the second source trench 60.

[0074] S140. Remove the cushion layer 12 to make the second source trench 60 and the first source trench 10 communicate to form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70.

[0075] Specifically, at the position where the cushion layer 12 is exposed, the cushion layer 12 in the first source sub-groove 10 can be removed by a dry etching process or a wet etching process. Therefore, the second source sub-groove 60 and the first source sub-groove 10 can form a through source groove 90, as Figure 7 shown.

[0076] S150. Form a gate structure in the gate groove 70 and form a source groove structure in the source groove 90;

[0077] S160. Form a source electrode on the fourth surface and form a drain electrode on the second surface, thereby obtaining a semiconductor device in which the depth of the source groove 90 is greater than the depth of the gate groove 70, as Figure 8 shown.

[0078] In the manufacturing method of the semiconductor device provided by the embodiment of the present invention, by providing the first semiconductor body 100, a first source sub-groove 10 is preset on the first semiconductor body 100, and a cushion layer 12 is filled in the first source sub-groove 10. Then, a second semiconductor body 101 is arranged on the first surface. The second source sub-groove 60 and the gate groove 70 both extend from the fourth surface of the second semiconductor body 101 into the second semiconductor body 101; the second source sub-groove 60 is close to the substrate 50 side, and at least part of the cushion layer 12 is exposed. By removing the cushion layer 12, the second source sub-groove 60 and the first source sub-groove 10 are penetrated to form the source groove 90, so that the source groove 90 with a relatively deep depth is obtained through two molding processes, avoiding the limitation of the design depth of the gate groove 70 on the depth of the source groove 90, and by respectively etching to obtain the first source sub-groove 10 and the second source sub-groove 60, compared with obtaining the source groove 90 with a relatively deep depth by one molding process, the requirements for etching equipment and etching process are reduced.

[0079] Figure 9 It is a schematic flow chart of another manufacturing method of the semiconductor device provided by the embodiment of the present invention, Figures 10 - 11 It is a schematic diagram of an intermediate structure of another semiconductor device manufacturing provided by the embodiment of the present invention, including:

[0080] S210. Form a first epitaxial layer 20 on one side of the substrate 50; wherein, the materials of the substrate 50 and the first epitaxial layer 20 can be silicon carbide, and the first epitaxial layer 20 is formed on one side of the substrate 50. Exemplarily, the first epitaxial layer 20 can be formed on the surface of the substrate 50 by an epitaxial growth method, and its structure is as Figure 2 shown.

[0081] S220. The surface of the first epitaxial layer 20 away from the substrate 50 is used as the first surface, and a first source sub-groove 10 is formed on the first surface; the first source sub-groove 10 extends from the first surface into the first epitaxial layer 20.

[0082] Specifically, a first source sub-groove 10 is formed on the first surface through an etching process. The first source sub-groove 10 extends from the first surface into the first epitaxial layer 20, and its structure is as shown in Figure 3 shown.

[0083] S230. Form a cushion layer 12 in the first source sub-groove 10;

[0084] Among them, the cushion layer 12 can be an insulating layer for protecting the inner wall of the first source sub-groove 10. The cushion layer 12 can completely fill the first source sub-groove 10. Exemplarily, the cushion layer 12 can be made of silicon nitride material, and a certain thickness of the cushion layer 12 is deposited on the first surface of the first semiconductor body 100 through a deposition process. Among them, the material of the cushion layer 12 in the first source sub-groove 10 can completely fill the inside of the first source sub-groove 10, and then the first surface is exposed through a polishing process to keep the first surface flat to ensure the structural stability of the subsequent second semiconductor body 101. Its structure is as shown in Figure 4 shown.

[0085] S240. Form a second epitaxial layer 80 on the first surface;

[0086] Specifically, the second semiconductor body 101 is disposed on the first surface of the first semiconductor body 100. Exemplarily, the second semiconductor body 101 includes a second epitaxial layer 80, and the second epitaxial layer 80 can be formed on the first surface by epitaxial growth. Among them, the materials of the first epitaxial layer 20 and the second epitaxial layer 80 can be the same.

[0087] S250. Take the surface of the second epitaxial layer 80 away from the substrate 50 as the fourth surface, and form a first region 40 on the fourth surface; form a well region 30 on one side of the second epitaxial layer 80 away from the first region 40;

[0088] Specifically, the surface of the second epitaxial layer 80 away from the first surface is used as the fourth surface. The well region 30 is disposed on the fourth surface, and the first region 40 is disposed on one side of the well region 30 away from the fourth surface. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, vapor deposition, etc. The well region 30 and the first region 40 are used to form a conductive channel of a semiconductor device. Among them, the first region 40 is of a first conductivity type, and the well region 30 is of a second conductivity type. In the embodiment of the present invention, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type. Its structure is as shown in Figure 5 shown.

[0089] S260. Form a second source sub-groove 60 and a gate groove 70 on the fourth surface; wherein, the second source sub-groove 60 and the gate groove 70 extend from the fourth surface into the second epitaxial layer 80; the positive projection of the first source sub-groove 10 on the substrate 50 at least covers the positive projection of the second source sub-groove 60 on the substrate 50; the second source sub-groove 60 and the first source sub-groove 10 penetrate through to form a source groove 90.

[0090] Specifically, the gate groove 70 and the second source sub-groove 60 are formed on the fourth surface by an etching process, wherein the gate groove 70 and the second source sub-groove 60 can be etched synchronously in the same preparation process. In some other embodiments, the gate groove 70 and the second source sub-groove 60 can be set to different depths and shapes, and the gate groove 70 and the second source sub-groove 60 can be etched separately. The gate groove 70 and the second source sub-groove 60 pass through the first region 40 and the well region 30 and extend from the fourth surface into the second epitaxial layer 80. Among them, the positive projection of the first source sub-groove 10 on the substrate 50 at least covers the positive projection of the second source sub-groove 60 on the substrate 50, that is to say, the first source sub-groove 10 and the second source sub-groove 60 are corresponding in position in the thickness direction of the first epitaxial layer 20 and the second epitaxial layer 80. The second source sub-groove 60 penetrates through the second epitaxial layer 80, and at least part of the buffer layer 12 can be exposed at the bottom of the second source sub-groove 60. The structure is as Figure 6 shown.

[0091] S270. Remove the buffer layer 12 so that the second source sub-groove 60 and the first source sub-groove 10 penetrate through to form a source groove 90; the depth of the source groove 90 is greater than the depth of the gate groove 70.

[0092] Specifically, at the position where the buffer layer 12 is exposed, the buffer layer 12 in the first source sub-groove 10 can be removed by a dry etching or wet etching process. Therefore, the second source sub-groove 60 and the first source sub-groove 10 can form a through source groove 90. The structure is as Figure 7 shown.

[0093] S280. Form a second region 41 in the inner extension region of the adjacent epitaxial layer on the sidewall and bottom of the source groove 90.

[0094] Specifically, a second region 41 is further provided in the first semiconductor body 100 and the second semiconductor body 101. The second region 41 is provided in a region extending from the sidewall and / or bottom of the source trench 90 into the first epitaxial layer 20 and the second epitaxial layer 80. Exemplarily, the second region 41 can be formed by ion implantation. The conductivity type of the second region 41 is the same as that of the well region 30. Therefore, a depletion region can be formed between the second region 41 and the first epitaxial layer 20 and the second epitaxial layer 80, which can shield the electric field of the gate structure, thereby improving the problem of gate oxide breakdown and ensuring the reliability of device operation. Its structure is as Figure 10 shown.

[0095] S290: Form a first insulating layer 71 on the bottom and sidewalls of the gate trench 70;

[0096] Specifically, the first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70. The first insulating layer 71 can be a gate oxide layer, and the gate oxide layer can be a high-k (dielectric constant) material.

[0097] S300: Form a trench gate on the side of the first insulating layer 71 away from the second surface; the trench gate covers the first insulating layer 71 inside the gate recess.

[0098] Specifically, the trench gate can be polysilicon. The gate structure is disposed in the gate trench 70. Vertical conductive channels can be formed in the well regions 30 on both sides of the gate structure, which can eliminate the Junction Field-Effect Transistor (JFET) region and make the on-resistance of the semiconductor device lower.

[0099] S310: Form a second insulating layer 91 on the bottom and sidewalls of the source trench 90;

[0100] Specifically, the second insulating layer 91 is disposed on the inner wall and bottom of the source trench 90. The second insulating layer 91 in the source trench structure can be the same as the first insulating layer 71 in the gate structure. Therefore, during fabrication, the second insulating layer 91 in the source trench structure and the first insulating layer 71 in the gate structure can be formed simultaneously. Exemplarily, the entire first insulating layer 71 can be deposited by means such as Atomic Layer Deposition (ALD). The entire first insulating layer 71 covers the inside of the source trench 90, the inside of the gate trench 70, and the surface of the first region 40 away from the substrate 50, and then the first insulating layer 71 is etched to retain only the first insulating layer 71 inside the source trench 90 and the gate trench 70.

[0101] S320. A filling layer 92 is formed on the side of the second insulating layer 91 away from the second surface. Herein, the materials of the filling layer 92 and the trench gate 72 can both be polysilicon, and the filling layer 92 and the trench gate 72 can also be formed simultaneously. The structure is as shown in Figure 11 shown. In some other embodiments, the filling layer 92 can also be a metal material. In some other embodiments, the filling layer 92 may not be provided in the source trench 90 or a partial filling layer 92 may be provided in the source trench 90.

[0102] S330. A source electrode 120 is formed on the fourth surface; a drain electrode 130 is formed on the second surface.

[0103] Specifically, a third insulating layer 110 is further included between the source electrode 120 and the gate structure. The third insulating layer 110 can be an Inter Layer Dielectric (ILD). The third insulating layer 110 covers the surface of the gate structure, and the third insulating layer 110 isolates the gate structure and the source electrode 120. An ohmic contact metal layer 111 is provided on the side of the third insulating layer 110 away from the gate structure. The ohmic contact metal layer 111 can significantly reduce the contact resistance of the source electrode 120, thereby improving the conduction efficiency of the device. The ohmic contact metal layer 111 can include metals such as nickel (Ni) or titanium (Ti). The source electrode can be formed by means such as sputter coating. The source electrode 120 is a metal conductive layer, and the metal conductive layer can be titanium (Ti), nickel (Ni), or silver (Ag).

[0104] The drain electrode 130 is formed on the first surface of the semiconductor body by means such as sputter coating (Sputter). The drain electrode 130 is a metal conductive layer. Exemplarily, the metal conductive layer can be titanium (Ti), nickel (Ni), or silver (Ag). The drain electrode 130 is located on the second surface. First, the second surface is thinned, and then the drain electrode 130 is formed by means such as sputter coating, so as to obtain a semiconductor device in which the depth of the source trench 90 is greater than the depth of the gate trench 70. The structure is as shown in Figure 8 shown.

[0105] Figure 12 It is a schematic flow chart of a preparation method of another semiconductor device provided by an embodiment of the present invention. Figures 13 - 15 It is a schematic diagram of an intermediate structure of another semiconductor device preparation provided by an embodiment of the present invention, including:

[0106] S410. A first epitaxial layer 20 is formed on one side of the substrate 50. The structure is as shown in Figure 2 shown.

[0107] S420. The surface of the first epitaxial layer 20 away from the substrate 50 serves as the first surface, and a first source trench 10 is formed on the first surface; the first source trench 10 extends from the first surface into the interior of the first epitaxial layer 20. Its structure is as shown in Figure 3 shown.

[0108] S430. A second region 41 is formed in the interior extension region of the adjacent first epitaxial layer 20 on the sidewalls and bottom of the first source trench 10;

[0109] Specifically, the second region 41 is disposed in the region where the sidewalls and / or bottom of the first source trench 10 extend into the first epitaxial layer 20. Exemplarily, the second region 41 can be formed by ion implantation. The conductivity type of the second region 41 is the same as that of the well region 30. Its structure is as shown in Figure 13 shown.

[0110] S440. A cushion layer 12 is formed in the first source trench 10; its structure is as shown in Figure 14 shown.

[0111] S450. A second epitaxial layer 80 is formed on the first surface;

[0112] S460. The surface of the second epitaxial layer 80 away from the substrate 50 is used as the fourth surface, and a first region 40 is formed on the fourth surface; a well region 30 is formed on the side of the second epitaxial layer 80 away from the first region 40;

[0113] S470. A second source trench 60 and a gate trench 70 are formed on the fourth surface; wherein, the second source trench 60 and the gate trench 70 extend from the fourth surface into the interior of the second epitaxial layer 80; the orthographic projection of the first source trench 10 on the substrate 50 at least covers the orthographic projection of the second source trench 60 on the substrate 50; the second source trench 60 and the first source trench 10 are connected through to form a source trench 90.

[0114] S480. The cushion layer 12 is removed so that the second source trench 60 and the first source trench 10 are connected through to form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70. Its structure is as shown in Figure 15 shown.

[0115] S490. A second region 41 is formed in the interior extension region of the adjacent epitaxial layer on the sidewalls and bottom of the second source trench 60.

[0116] Specifically, the region where the sidewalls of the second source trench 60 extend into the second epitaxial layer 80 is implanted to form the second region 41, and the second region 41 at the bottom and / or sidewall positions of the source trench 90 is formed by two implantations, reducing the influence on the ion implantation uniformity when the depth of the source trench 90 is relatively deep. Its structure is as shown inFigure 10 as shown

[0117] S500. Form a first insulating layer 71 at the bottom and sidewalls of the gate trench 70;

[0118] S510. Form a trench gate 72 on the side of the first insulating layer 71 away from the second surface; the trench gate 72 covers the first insulating layer 71 inside the gate groove.

[0119] S520. Form a second insulating layer 91 at the bottom and sidewalls of the source trench 90; during fabrication, the second insulating layer 91 in the source trench structure and the first insulating layer 71 in the gate structure can be formed simultaneously.

[0120] S530. Form a filling layer 92 on the side of the second insulating layer 91 away from the second surface. Among them, the materials of the filling layer 92 and the trench gate 72 are both polysilicon, and the filling layer 92 and the trench gate 72 can also be formed simultaneously. In some other embodiments, the filling layer 92 can also be a metal material. In some other embodiments, the filling layer 92 may not be provided in the source trench 90 or a partial filling layer 92 may be provided in the source trench 90.

[0121] S540. Form a third insulating layer 110 on the fourth surface; the third insulating layer 110 covers the gate structure; form a source electrode 120 on the side of the third insulating layer away from the substrate 50; the source electrode 120 covers the third insulating layer 110 and the area of the fourth surface not covered by the third insulating layer 110. Form a drain electrode 130 on the second surface.

[0122] Specifically, the third insulating layer 110 can be an interlayer dielectric layer, the third insulating layer 110 covers the surface of the gate structure, and the third insulating layer 110 isolates the gate structure and the source electrode 120. An ohmic contact metal layer 111 is provided on the side of the third insulating layer 110 away from the gate structure. The ohmic contact metal layer 111 can significantly reduce the contact resistance of the source electrode 120, thereby improving the conduction efficiency of the device. The ohmic contact metal layer 111 can include metals such as nickel (Ni) or titanium (Ti). The source electrode 120 can be formed by means such as sputter coating, and the source electrode 120 is a metal conductive layer, and the metal conductive layer can be titanium (Ti), nickel (Ni), or silver (Ag).

[0123] Form a drain electrode 130 on the first surface of the semiconductor body by means such as sputter coating (Sputter). The drain electrode 130 is a metal conductive layer. Exemplarily, the metal conductive layer can be titanium (Ti), nickel (Ni), or silver (Ag). The drain electrode 130 is located on the second surface. First, the second surface is thinned, and then the drain electrode 130 is formed by means such as sputter coating, so as to obtain a semiconductor device in which the depth of the source trench 90 is greater than the depth of the gate trench 70. Its structure is as Figure 8as shown

[0124] On the basis of the above embodiments, an embodiment of the present invention further provides a semiconductor device, which is prepared by using the preparation method of the semiconductor device according to any embodiment of the present invention. Among them, the semiconductor device includes:

[0125] A first semiconductor body 100, including a first surface and a second surface arranged opposite to each other, the first surface is provided with a first source sub-groove 10, and the first source sub-groove 10 extends from the first surface into the first semiconductor body 100; the first semiconductor body 100 is set to a first conductivity type;

[0126] A second semiconductor body 101, located on one side of the first semiconductor body 100, the second semiconductor body 101 includes a third surface and a fourth surface arranged opposite to each other, and the third surface is in contact connection with the first surface; the second semiconductor body 101 further includes a well region 30 and a first region 40, the first region 40 is set to a first conductivity type and is arranged on the fourth surface, the well region 30 is set to a second conductivity type and is arranged on the side of the first region 40 away from the fourth surface; the first conductivity type is different from the second conductivity type; the fourth surface is further provided with a second source sub-groove 60 and a gate trench 70, and both the second source sub-groove 60 and the gate trench 70 extend from the fourth surface into the second semiconductor body 101; wherein, the second source sub-groove 60 and the first source sub-groove 10 penetrate to form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70.

[0127] Optionally, the first semiconductor body 100 includes:

[0128] A substrate 50;

[0129] A first epitaxial layer 20, located on one side of the substrate 50; the surface of the first epitaxial layer 20 away from the substrate 50 serves as the first surface, and the surface of the substrate 50 away from the first epitaxial layer 20 serves as the second surface.

[0130] Optionally, the second semiconductor body 101 includes a second epitaxial layer 80;

[0131] The second epitaxial layer 80 is located on the side of the first epitaxial layer 20 away from the substrate 50, the surface of the second epitaxial layer 80 close to the substrate 50 serves as the third surface, and the surface of the second epitaxial layer 80 away from the substrate 50 serves as the fourth surface.

[0132] Optionally, the first semiconductor body 100 and the second semiconductor body 101 further include a second region 41, the second region 41 is located on one side of the side wall and the bottom of the source trench 90, and the second region 41 extends from the side wall and the bottom of the source trench 90 into the first semiconductor body 100 and the second semiconductor body 101.

[0133] The semiconductor device provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the manufacturing method of the semiconductor device of any embodiment of the present invention.

[0134] Based on the above embodiment, the embodiment of the present invention provides a power module, which includes a substrate and the semiconductor device of any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0135] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0136] Based on the above embodiment, the embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device such as that of any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0137] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0138] Based on the above embodiment, the embodiment of the present invention provides a vehicle, which includes a load and a power conversion circuit such as that of any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a first semiconductor body, which is set to a first conductivity type, wherein the first semiconductor body comprises a first surface and a second surface which are arranged opposite to each other, wherein a first source sub-groove is arranged on the first surface, and wherein the first source sub-groove extends from the first surface into the first semiconductor body; forming a pad layer in the first source sub-trench; A second semiconductor body is formed on one side of the first semiconductor body, wherein the second semiconductor body comprises a third surface and a fourth surface arranged opposite to each other, wherein the third surface is in contact with and connected to the first surface; the second semiconductor body further comprises a well region and a first region, wherein the first region is set to be of a first conductivity type and is arranged on the fourth surface, and the well region is set to be of a second conductivity type and is arranged on a side of the first region away from the fourth surface, wherein the first conductivity type is different from the second conductivity type; a second source sub-groove and a gate groove are further arranged on the fourth surface, wherein the second source sub-groove and the gate groove both extend from the fourth surface into the second semiconductor body; the second source sub-groove is close to the side of the first surface, and at least a portion of the pad layer is exposed; removing the pad layer so that the second source sub-groove and the first source sub-groove are connected to form a source groove; The depth of the source trench is greater than the depth of the gate trench.

2. The method for preparing a semiconductor device according to claim 1, wherein: The first semiconductor body comprises a substrate and a first epitaxial layer; A first semiconductor body is provided, comprising: forming the first epitaxial layer on one side of the substrate; The surface of the first epitaxial layer away from the substrate serves as the first surface, and the first source sub-groove is formed on the first surface; the first source sub-groove extends from the first surface to the inside of the first epitaxial layer.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The second semiconductor body includes a second epitaxial layer; A second semiconductor body is formed on one side of the first semiconductor body, comprising: forming the second epitaxial layer on the first surface; Using a surface of the second epitaxial layer away from the substrate as a fourth surface, and forming the first region on the fourth surface; forming the well region on a side of the second epitaxial layer away from the first region; The second source sub-groove and the gate groove are formed on the fourth surface; wherein the second source sub-groove and the gate groove extend from the fourth surface to the inside of the second epitaxial layer; the orthographic projection of the first source sub-groove on the substrate at least covers the orthographic projection of the second source sub-groove on the substrate; the second source sub-groove and the first source sub-groove are connected to form the source groove.

4. The method for preparing a semiconductor device according to any one of claims 1 to 3, characterized in that: After removing the cushion layer, the method comprises: A second region is formed in the area extending from the sidewall and the bottom of the source trench toward the inner portion of the adjacent epitaxial layer, and the second region is of the second conductivity type.

5. The method for preparing a semiconductor device according to claim 3, characterized in that: The first epitaxial layer has a surface away from the substrate as the first surface, and after the first source sub-trench is formed on the first surface, the method comprises: Forming a second region on the sidewall and bottom of the first source sub-trench toward the inner extension region of the adjacent first epitaxial layer; After removing the cushion layer, the method comprises: A second region is formed in a region extending from a sidewall of the second source sub-trench toward an inner portion of the adjacent second epitaxial layer.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The first epitaxial layer and the second epitaxial layer have the same conductivity type as the substrate; and the substrate is of the first conductivity type.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: After removing the cushion layer, the method comprises: forming a gate structure in the gate trench; The gate structure includes a first insulating layer and a trench gate; A gate structure is formed in the gate trench, comprising: forming a first insulating layer at the bottom and sidewalls of the gate trench; A trench gate is formed on a side of the first insulating layer away from the gate trench.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: After or while forming a gate structure in the gate trench, the method further includes: forming a source trench structure in the source trench; The source trench structure includes a second insulating layer and a filling layer; A source trench structure is formed in the source trench, comprising: forming a second insulating layer at the bottom and sidewalls of the source trench; forming a filling layer on a side of the second insulating layer away from the source trench; After forming a source trench structure in the source trench, the method comprises: A source electrode is formed on the fourth surface.

9. A semiconductor device, characterized in that: include: A first semiconductor body comprises a first surface and a second surface arranged opposite to each other, wherein the first surface is provided with a first source sub-groove, and the first source sub-groove extends from the first surface into the first semiconductor body; the first semiconductor body is set to a first conductivity type; A second semiconductor body is located on one side of the first semiconductor body, the second semiconductor body includes a third surface and a fourth surface that are arranged opposite to each other, the third surface is in contact with the first surface; the second semiconductor body also includes a well region and a first region, the first region is set to a first conductivity type and is arranged on the fourth surface, the well region is set to a second conductivity type and is arranged on a side of the first region away from the fourth surface, the first conductivity type is different from the second conductivity type; the fourth surface is also provided with a second source sub-groove and a gate groove, the second source sub-groove and the gate groove both extend from the fourth surface into the second semiconductor body, so that the second source sub-groove and the first source sub-groove are connected to form a source groove; The depth of the source trench is greater than the depth of the gate trench.

10. The semiconductor device according to claim 9, characterized in that The first semiconductor body comprises: substrate; A first epitaxial layer is located on one side of the substrate; a surface of the first epitaxial layer away from the substrate is used as the first surface, and a surface of the substrate away from the first epitaxial layer is used as the second surface.

11. The semiconductor device according to claim 10, characterized in that The second semiconductor body includes a second epitaxial layer; The second epitaxial layer is located on a side of the first epitaxial layer away from the substrate, a surface of the second epitaxial layer close to the substrate serves as a third surface, and a surface of the second epitaxial layer away from the substrate serves as a fourth surface.

12. The semiconductor device according to any one of claims 9 to 11, characterized in that: The first semiconductor body and the second semiconductor body further include a second region, The second region is located on one side of the sidewall and the bottom of the source trench, and the second region extends from the sidewall and the bottom of the source trench into the first semiconductor body and the second semiconductor body.

13. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 9 to 12, wherein the substrate is used for carrying the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 10 to 13, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images