Control circuit, thin film transistor and manufacturing method thereof

Abstract

The invention discloses a control circuit, a thin film transistor and a manufacturing method thereof. The thin film transistor comprises a buffer layer, a semiconductor layer, a gate dielectric layer, a first gate, a source and a drain. The buffer layer is disposed on the substrate. The upper surface of the buffer layer is provided with a first surface, a second surface, a third surface, a fourth surface and a fifth surface. The first surface, the second surface, the third surface, the fourth surface and the fifth surface are sequentially connected to form a recess. The semiconductor layer is disposed in the recess. The gate dielectric layer is disposed on the substrate, the semiconductor layer and the buffer layer. The first gate is disposed on the gate dielectric layer and corresponds to the semiconductor layer. The source electrode and the drain electrode are arranged on the substrate and connected to the semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a control circuit, a thin film transistor, and a manufacturing method thereof. Background Art

[0002] A thin film transistor is a control element that can be applied to various control circuits. The thin film transistor includes a gate, a semiconductor layer disposed corresponding to the gate, a gate insulating layer disposed between the gate and the semiconductor layer, and a source electrode and a drain electrode each connected to the semiconductor layer. Generally, to increase the current of the thin film transistor, the gate insulating layer can be thinned, or a gate insulating layer with a high dielectric constant can be used. However, while thinning the gate insulating layer or using a gate insulating layer with a high dielectric constant, the electric field between the gate and the semiconductor layer will increase, resulting in an excessive electric field near the corners of the semiconductor layer, making the gate insulating layer prone to deterioration, and ultimately may cause the thin film transistor to fail to turn off properly. Summary of the Invention

[0003] The present invention provides a thin film transistor with excellent performance.

[0004] The present invention provides a control circuit including the thin film transistor with excellent performance.

[0005] The present invention provides a manufacturing method of a thin film transistor, which can manufacture a thin film transistor with excellent performance.

[0006] The thin film transistor of the present invention includes a buffer layer, a semiconductor layer, a gate dielectric layer, a first gate, a source electrode, and a drain electrode. The buffer layer is disposed on a substrate. The upper surface of the buffer layer has a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface, the second surface, the third surface, the fourth surface, and the fifth surface are sequentially connected to form a depression. The semiconductor layer is disposed in the depression. The gate dielectric layer is disposed on the substrate, the semiconductor layer, and the buffer layer. The first gate is disposed on the gate dielectric layer and corresponds to the semiconductor layer. The source electrode and the drain electrode are disposed on the substrate and connected to the semiconductor layer.

[0007] The control circuit of the present invention includes a plurality of control elements. At least one control element includes the aforementioned thin film transistor.

[0008] The manufacturing method of the thin film transistor of the present invention includes the following steps: forming a buffer layer on a substrate, wherein the upper surface of the buffer layer has a first surface, a second surface, a third surface, a fourth surface and a fifth surface, and the first surface, the second surface, the third surface, the fourth surface and the fifth surface are sequentially connected to form a depression; forming a semiconductor material layer on the buffer layer, wherein the semiconductor material layer includes a first part and a second part connected to the first part, the first part of the semiconductor material layer is disposed on the second surface, the third surface and the fourth surface of the buffer layer, and the second part of the semiconductor material layer is disposed on the first surface and the fifth surface of the buffer layer; removing the second part of the semiconductor material layer and retaining the first part of the semiconductor material layer to form a semiconductor layer; forming a gate dielectric layer on the buffer layer and the semiconductor layer; forming a first gate on the gate dielectric layer; forming a source electrode and a drain electrode on the substrate, wherein the source electrode and the drain electrode are connected to the semiconductor layer. Brief Description of the Drawings

[0009] Figures 1A to 1G It is a schematic cross-sectional view of the manufacturing process of the thin film transistor according to an embodiment of the present invention;

[0010] Figure 2 It is a schematic cross-sectional view of the thin film transistor according to an embodiment of the present invention;

[0011] Figures 3A to 3D It is a schematic cross-sectional view of the manufacturing process of the thin film transistor according to another embodiment of the present invention;

[0012] Figures 4A to 4D It is a schematic cross-sectional view of the manufacturing process of the thin film transistor according to still another embodiment of the present invention;

[0013] Figure 5 It is a three-dimensional schematic view of the material layer of the thin film transistor according to still another embodiment of the present invention;

[0014] Figure 6 It is an equivalent circuit schematic diagram of the control circuit according to an embodiment of the present invention.

[0015] Symbol Description

[0016] 1: Control circuit

[0017] 2: Control element

[0018] 3: Pixel element

[0019] 10, 10A, 10B: Thin film transistor

[0020] 110: Substrate

[0021] 110a: Outer surface

[0022] 120: Buffer material layer

[0023] 122: Buffer layer

[0024] 122s: Upper surface

[0025] 122s1: First side

[0026] 122s2: Second side

[0027] 122s3: Third side

[0028] 122s4: Fourth side

[0029] 122s5: Fifth side

[0030] 130: Semiconductor material layer

[0031] 130a: First part

[0032] 130b: Second part

[0033] 132: Semiconductor layer

[0034] 132a: Top surface

[0035] 132b: Bottom surface

[0036] 140: Gate dielectric layer

[0037] 150: First gate

[0038] 160: Interlayer dielectric layer

[0039] 162, 164: Opening

[0040] 172: Source

[0041] 174: Drain

[0042] 180: Material layer

[0043] 182: First part

[0044] 184: Second part

[0045] 186: Opening

[0046] 190: Conductive layer

[0047] 192: Second gate

[0048] C1: Capacitance

[0049] D: Depth

[0050] PR: Photoresist

[0051] T, T 180 : Thickness

[0052] T 180+122 : Thickness sum

[0053] T1, T2, T3, T4, T5, T6, T7: Thin film transistors

[0054] U1, U2: Depressions

[0055] W: Width Detailed implementation manners

[0056] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0057] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, no intervening elements are present. As used herein, "connected" can refer to physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" can mean that there are other elements between two elements.

[0058] As used herein, "about", "approximate", or "substantially" includes the stated value and the average within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art, taking into account the particular amounts of the measurements and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximate", or "substantially" as used herein can be selected according to optical properties, etching properties, or other properties to choose a more acceptable deviation range or standard deviation, rather than applying one standard deviation to all properties.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0060] Figures 1A to 1G It is a cross-sectional schematic diagram of the manufacturing process of a thin film transistor according to an embodiment of the present invention. Please refer to Figures 1A to 1D , first, a buffer layer 122 is formed on a substrate 110 (labeled in Figure 1D ). Please refer to Figure 1D, the upper surface 122s of the buffer layer 122 has a first surface 122s1, a second surface 122s2, a third surface 122s3, a fourth surface 122s4, and a fifth surface 122s5, and the first surface 122s1, the second surface 122s2, the third surface 122s3, the fourth surface 122s4, and the fifth surface 122s5 are sequentially connected to form a concave U1.

[0061] Please refer to Figure 1A , for example, in some embodiments, a buffer material layer 120 may be first formed on the substrate 110; please refer to Figure 1B , then, a photoresist PR is formed on the buffer material layer 120; please refer to Figure 1B and Figure 1C , then, using the photoresist PR as a mask, the buffer material layer 120 is patterned to form a buffer layer 122 having a concave U1; please refer to Figure 1C and Figure 1D , finally, the photoresist PR on the buffer layer 122 is removed. However, the present invention is not limited thereto, and in other embodiments, the buffer layer 122 having a concave U1 may also be formed by other means.

[0062] Please refer to Figure 1D , in some embodiments, the material of the substrate 110 may be glass, quartz, organic polymer, light-blocking / reflective material (e.g., conductive material, wafer, ceramic, or other applicable materials), or other applicable materials. In some embodiments, the buffer layer 122 may be a single-layer or multi-layer structure. In some embodiments, the material of the buffer layer 122 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof. In some embodiments, the concave U1 has a bottom area close to the substrate 110 and a top area far from the substrate 110, where the top area is larger than the bottom area. In some embodiments, the width W of the concave U1 may gradually increase as it is farther from the substrate 110.

[0063] Please refer to Figure 1E , then, a semiconductor material layer 130 is formed on the buffer layer 122. The semiconductor material layer 130 includes a first portion 130a and a second portion 130b connected to the first portion 130a. The first portion 130a of the semiconductor material layer 130 is disposed on the second surface 122s2, the third surface 122s3, and the fourth surface 122s4 of the buffer layer 122. That is, the first portion 130a of the semiconductor material layer 130 is disposed in the concave U1 of the buffer layer 122. The second portion 130b of the semiconductor material layer 130 is disposed on the first surface 122s1 and the fifth surface 122s5 of the buffer layer 122. That is, the second portion 130b of the semiconductor material layer 130 is disposed in other regions outside the concave U1 of the upper surface 122s.

[0064] Please refer to Figure 1E and Figure 1F , then, remove the second portion 130b of the semiconductor material layer 130 while retaining the first portion 130a of the semiconductor material layer 130 to form the semiconductor layer 132. The semiconductor layer 132 is disposed in the recess U1 of the buffer layer 122. In some embodiments, the semiconductor layer 132 may fill the recess U1 of the buffer layer 122. For example, in some embodiments, the second portion 130b of the semiconductor material layer 130 may be removed using chemical mechanical polishing (CMP). In some embodiments, during the chemical mechanical polishing process, the substrate 110, the buffer layer 122 on the substrate 110, and the semiconductor material layer 130 on the buffer layer 122 may be placed on a turntable (not shown), and then a polishing head (not shown) is used to polish the semiconductor material layer 130 on the turntable, and during the polishing process, a slurry is added. In some embodiments, the rotational speed of the lower turntable may be 20 rpm, the rotational speed of the upper polishing head may be 30 rpm, the pressure applied by the polishing head to the semiconductor material layer 130 may be 0.47 psi, the polishing time may be 150 sec, the slurry may include water and a plurality of silica particles mixed in the water, wherein the weight percentage of water may be greater than 51%, the weight percentage of the plurality of silica particles may be less than 49%, and the particle size of the silica particles may be 35 nm, but the present invention is not limited thereto.

[0065] Please refer to Figure 1F , in some embodiments, the material of the semiconductor layer 132 may be a silicon-containing semiconductor material, such as but not limited to: polysilicon, microcrystalline silicon, single crystal silicon, amorphous silicon, silicon-rich dielectric material. Taking polysilicon as a preferred example, the semiconductor layer 132 has a channel region (not labeled), between the double-doped regions (not labeled). In other embodiments, a lightly doped region (not labeled) may be located between the channel region and the heavily doped region; that is, a lightly doped region and a heavily doped region may be provided on each side of the channel region. In one embodiment, a heavily doped region and an extension region (not labeled) may be provided on one side of the channel region, and a lightly doped region and a heavily doped region may be provided on the other side of the channel region.

[0066] Please refer to Figure 1G, then, a gate dielectric layer 140 is formed on the buffer layer 122 and the semiconductor layer 132. The gate dielectric layer 140 is disposed on the substrate 110, the semiconductor layer 132, and the buffer layer 122. In some embodiments, the gate dielectric layer 140 may entirely cover the semiconductor layer 132 and the buffer layer 122, but the present invention is not limited thereto. In some embodiments, the material of the gate dielectric layer 140 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination of the above.

[0067] Please refer to Figure 1G , then, a first gate 150 is formed on the gate dielectric layer 140. The first gate 150 is disposed on the gate dielectric layer 140 and corresponds to the semiconductor layer 132. The gate dielectric layer 140 is located between the first gate 150 and the semiconductor layer 132 and between the first gate 150 and the buffer layer 122. In some embodiments, based on considerations of conductivity, the first gate 150 generally uses a metal material. However, the present invention is not limited thereto. According to other embodiments, the first gate 150 may also use other conductive materials. For example: an alloy, a nitride of a metal material, an oxide of a metal material, a oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.

[0068] Figure 2 is a cross-sectional schematic diagram of a thin-film transistor according to an embodiment of the present invention. Figure 1G shows a cross-section of the thin-film transistor 10 in its width direction. Figure 2 shows a cross-section of the thin-film transistor 10 in its length direction. Please refer to Figure 1G and Figure 2 , in some embodiments, then, an interlayer dielectric layer 160 may be formed to cover the gate dielectric layer 140 and the first gate 150, wherein the interlayer dielectric layer 160 has a plurality of openings 162, 164. In some embodiments, the material of the interlayer dielectric layer 160 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination of the above.

[0069] Please refer to Figure 2 , then, a source electrode 172 and a drain electrode 174 are formed on the substrate 110, wherein the source electrode 172 and the drain electrode 174 are disposed on the substrate 110 and connected to the semiconductor layer 132. In some embodiments, the source electrode 172 and the drain electrode 174 may be formed on the interlayer dielectric layer 160. The source electrode 172 and the drain electrode 174 are disposed on the interlayer dielectric layer 160, and the source electrode 172 and the drain electrode 174 are connected to the semiconductor layer 132 through the plurality of openings 162, 164 of the interlayer dielectric layer 160. Hereby, the thin-film transistor 10 is completed.

[0070] Please refer to Figure 1G andFigure 2 , It should be noted that the semiconductor layer 132 of the thin film transistor 10 is disposed in the recess U1 of the buffer layer 122. Thus, an overly strong tip electric field between the semiconductor layer 132 and the first gate 150 can be avoided, thereby achieving the effect of eliminating the tip electric field. In some embodiments, the area of the top surface 132a of the semiconductor layer 132 away from the substrate 110 is larger than the area of the bottom surface 132b of the semiconductor layer 132 close to the substrate 110. Please refer to Figure 2 , in some embodiments, the depth D of the recess U1 (marked in Figure 2 ) substantially falls within the range of 15% to 45% of the thickness T of the buffer layer 122 (marked in Figure 2 ).

[0071] It must be noted here that in the following embodiments, the component numbers and some contents of the foregoing embodiments are adopted, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0072] Figures 3A to 3D is a cross-sectional schematic view of the manufacturing process of a thin film transistor according to another embodiment of the present invention. Figures 3A to 3D The manufacturing process of the thin film transistor 10A of Figures 1A to 1G is similar to the manufacturing process of the thin film transistor 10 of

[0073] Please refer to Figure 3A and Figure 3B , specifically, in this embodiment, before forming the buffer layer 122, a material layer 180 can be first formed on the substrate 110, where the material layer 180 has an opening 186, a first part 182, and a second part 184, and the opening 186 of the material layer 180 separates the first part 182 and the second part 184 of the material layer 180. In some embodiments, the material layer 180 can be a single-layer or multi-layer structure, and the material of the material layer 180 can be an organic material, an inorganic material, a conductive material, or a semiconductor material. The material layer 180 can be a single-layer or multi-layer structure, and the multiple film layers of the multi-layer structure can use the same material or different materials.

[0074] Please refer to Figure 3B, then, a buffer layer 122 is conformally formed on the material layer 180. The material layer 180 is disposed on the substrate 110 and is located between the buffer layer 122 and the substrate 110. The first portion 182 and the second portion 184 of the material layer 180 respectively correspond to and overlap the first surface 122s1 and the fifth surface 122s5 of the buffer layer 122. The recess U1 of the buffer layer 122 is formed because a part of the buffer layer 122 sinks into the opening 186 of the material layer 180. Therefore, the recess U1 of the buffer layer 122 corresponds to the opening 186 of the material layer 180. That is to say, the positions of the opening 186 of the material layer 180 and the recess U1 of the buffer layer 122 overlap.

[0075] Please refer to Figure 3D , in some embodiments, the recess U1 of the buffer layer 122 may be located within the area of the opening 186 of the material layer 180. In some embodiments, a thickness T of either the first portion 182 or the second portion 184 of the material layer 180 180 may fall within the range of 7% to 25% of the sum of the thicknesses of the buffer layer 122 and either the first portion 182 or the second portion 184 of the material layer 180, but the present invention is not limited thereto. 180+122

[0076] Figures 4A to 4D is a cross-sectional schematic view of the manufacturing process of a thin film transistor according to another embodiment of the present invention. Figures 4A to 4D The manufacturing process of the thin film transistor 10B Figures 3A to 3D is similar to the manufacturing process of the thin film transistor 10A Figures 4A to 4D , and the differences between the two are as follows. In the manufacturing process of the thin film transistor 10B Figure 5 is a three-dimensional schematic view of the material layer of a thin film transistor according to another embodiment of the present invention. Please refer to Figure 4D and Figure 5 , in some embodiments, the material layer 180 may optionally be in a ring shape and define a closed opening 186.

[0077] Please refer to Figure 4D, in some embodiments, the conductive layer 190 may include a second gate 192. In some embodiments, the thin film transistor 10B includes a first gate 150 and a second gate 192 and is a double-gate thin film transistor, but the present invention is not limited thereto. In some embodiments, the conductive layer 190 may be a single-layer or multi-layer structure. In some embodiments, the material of the conductive layer 190 may be a transparent material or a reflective material. If the conductive layer 190 is a multi-layer structure, the multiple film layers of the conductive layer 190 may use the same material or different materials. If the conductive layer 190 includes a reflective material or a stack structure of a reflective material and a transparent material, in addition to serving as the second gate 192, the conductive layer 190 may also serve as a light-shielding layer to block light from entering the semiconductor layer 132 from the outer surface 110a of the substrate 110.

[0078] Figure 6 is an equivalent circuit diagram of a control circuit according to an embodiment of the present invention. Please refer to Figure 6 , the control circuit 1 includes a plurality of control elements 2, and at least one control element 2 may be the aforementioned thin film transistors 10, 10A or 10B. In some embodiments, the control circuit 1 may be a pixel control circuit, wherein at least one control element 2 of the pixel control circuit is electrically connected to a pixel element 3. At least one control element 2 electrically connected to the pixel element 3 may be referred to as a driving element, a light-emitting control element or other elements. In some embodiments, the pixel element 3 may be an inorganic self-luminous element, an organic self-luminous element, a non-self-luminous element or other suitable pixel elements.

[0079] In some embodiments, the pixel control circuit is, for example, Figure 6 the architecture of 7T1C shown, the architecture of 7T1C includes seven thin film transistors T1, T2, T3, T4, T5, T6, T7 and a capacitor C1. The plurality of control elements 2 of the control circuit 1 may include seven thin film transistors T1, T2, T3, T4, T5, T6, T7, and at least one of the thin film transistors T1, T2, T3, T4, T5, T6, T7 may be the aforementioned thin film transistors 10, 10A or 10B. However, the present invention is not limited thereto. If the control circuit 1 is a pixel control circuit, the architecture of the pixel control circuit is not limited to Figure 6 the architecture of 7T1C shown. In other embodiments, if the control circuit 1 is a pixel control circuit, the pixel control circuit may also be an architecture of 1T1C, 2T1C, 3T1C, 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T2C, 7T2C or any possible architecture. In addition, the present invention does not limit that the control circuit 1 must be a pixel control circuit. In other embodiments, the control circuit 1 may also be other types of circuits, such as but not limited to: a gate control circuit, a data control circuit, etc.

Claims

1. A thin film transistor, comprising: A buffer layer is disposed on the substrate, wherein the upper surface of the buffer layer has a first surface, a second surface, a third surface, a fourth surface and a fifth surface, and the first surface, the second surface, the third surface, the fourth surface and the fifth surface are connected sequentially to form a recess; A semiconductor layer is disposed in the recess; A gate dielectric layer is disposed on the substrate, the semiconductor layer and the buffer layer; A first gate is disposed on the gate dielectric layer and corresponds to the semiconductor layer; The source electrode and the drain electrode are arranged on the substrate and connected to the semiconductor layer. 2 . The thin film transistor as claimed in claim 1 , wherein a depth of the recess substantially falls within a range of 15% to 45% of a thickness of the buffer layer.

3. The thin film transistor according to claim 1, further comprising: A material layer is disposed on the substrate and located between the buffer layer and the substrate, wherein the material layer has an opening, a first portion and a second portion, the opening of the material layer separates the first portion and the second portion of the material layer, the first portion and the second portion of the material layer respectively correspond to and overlap the first surface and the fifth surface of the buffer layer, and the opening of the material layer corresponds to the recess of the buffer layer. 4 . The thin film transistor as claimed in claim 3 , wherein the recess of the buffer layer is located within an area of ​​the opening of the material layer. 5 . The thin film transistor as claimed in claim 3 , wherein a thickness of either the first portion or the second portion of the material layer is in a range of 7% to 25% of a sum of a thickness of the buffer layer and either the first portion or the second portion of the material layer.

6. The thin film transistor according to claim 3, further comprising: The conductive layer is disposed on the substrate, wherein the conductive layer covers the first portion and the second portion of the material layer and a portion of the substrate located between the first portion and the second portion of the material layer. The thin film transistor as claimed in claim 6 , wherein the conductive layer comprises a second gate electrode.

8. The thin film transistor according to claim 1, further comprising: The interlayer dielectric layer is arranged and covers the substrate, the gate dielectric layer and the first gate, wherein the interlayer dielectric layer has a plurality of openings, the source and the drain are arranged on the interlayer dielectric layer, and the source and the drain are connected to the semiconductor layer through the openings.

9. A control circuit comprising: A plurality of control elements, wherein at least one of the control elements comprises the thin film transistor as claimed in claim 1. 10 . The control circuit as claimed in claim 9 , wherein the control circuit comprises at least one of a pixel control circuit, a gate control circuit and a data control circuit.

11. A method for manufacturing a thin film transistor, comprising: Forming a buffer layer on the substrate, wherein the upper surface of the buffer layer has a first surface, a second surface, a third surface, a fourth surface and a fifth surface, and the first surface, the second surface, the third surface, the fourth surface and the fifth surface are sequentially connected to form a recess; forming a semiconductor material layer on the buffer layer, wherein the semiconductor material layer includes a first portion and a second portion connected to the first portion, the first portion of the semiconductor material layer is disposed on the second surface, the third surface, and the fourth surface of the buffer layer, and the second portion of the semiconductor material layer is disposed on the first surface and the fifth surface of the buffer layer; removing the second portion of the semiconductor material layer and retaining the first portion of the semiconductor material layer to form a semiconductor layer; forming a gate dielectric layer on the buffer layer and the semiconductor layer; forming a first gate on the gate dielectric layer; as well as A source electrode and a drain electrode are formed on the substrate, wherein the source electrode and the drain electrode are connected to the semiconductor layer. 12 . The method for manufacturing a thin film transistor as claimed in claim 11 , wherein a depth of the recess substantially falls within a range of 15% to 45% of a thickness of the buffer layer.

13. The method for manufacturing a thin film transistor according to claim 11, further comprising: Before forming the buffer layer, forming a material layer on the substrate, wherein the material layer has an opening, a first portion and a second portion, and the opening of the material layer separates the first portion and the second portion of the material layer; The step of forming the buffer layer on the substrate includes: conformally forming the buffer layer on the material layer, wherein the first portion and the second portion of the material layer respectively correspond to and overlap the first surface and the fifth surface of the buffer layer, and the opening of the material layer corresponds to the recess of the buffer layer. 14 . The method for manufacturing a thin film transistor as claimed in claim 13 , wherein the recess of the buffer layer is located within an area of ​​the opening of the material layer. 15 . The method for manufacturing a thin film transistor as claimed in claim 13 , wherein a thickness of either the first portion or the second portion of the material layer is in a range of 7% to 25% of a sum of a thickness of the buffer layer and either the first portion or the second portion of the material layer.

16. The method for manufacturing a thin film transistor according to claim 13, further comprising: After forming the material layer and before forming the buffer layer, a conductive layer is conformally formed on the material layer. 17 . The method for manufacturing a thin film transistor as claimed in claim 16 , wherein the conductive layer comprises a second gate.

18. The method for manufacturing a thin film transistor according to claim 11, further comprising: An interlayer dielectric layer is formed to cover the gate dielectric layer and the first gate, wherein the interlayer dielectric layer has a plurality of openings, the source and the drain are arranged on the interlayer dielectric layer, and the source and the drain are connected to the semiconductor layer through the openings.

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