Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device. In a silicon carbide semiconductor device, electric field concentration at a shoulder portion of a trench of a gate pull-up portion is prevented. A semiconductor device (100) is provided with a gate pull-up section (103), which is a region where a part of a gate wiring (10) is pulled up from a trench (8) to the upper surface of a semiconductor substrate (1). The side wall of the trench (8) of the gate pull-up section is provided with a vertical section (8a) that is vertical to the upper surface of the semiconductor substrate (1), a horizontal section (8c) that is parallel to the upper surface of the semiconductor substrate (1), and an inclined section (8b) that is provided between the vertical section and the horizontal section (8c). The inclined portion (8b) is inclined such that the width of the groove (8) expands upward, and is linear in a cross-sectional view. In a cross-sectional view, a corner section formed by the vertical section and the inclined section does not protrude toward the inside of the groove (8) from a region sandwiched between a tangent line (L1) of the vertical section and a tangent line (L2) of the inclined section.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In a semiconductor device including a trench gate type semiconductor element, in order to electrically connect a gate wiring buried in a trench to a gate pad, a region for lifting a part of the gate wiring above a substrate, that is, a "gate lift portion" is provided. In the gate lift portion, in order to prevent dielectric breakdown of a gate insulating film, it is preferable to make the shape of a corner portion between a surface of the substrate, which is an upper end portion of the trench, and a side surface of the trench gentle. Hereinafter, the upper end portion of the trench is referred to as a "shoulder of the trench".

[0003] For example, in Patent Document 1 below, a technique is disclosed in which a shoulder of a trench in which a gate wiring is buried in a trench gate type MOSFET is formed in an arc shape to suppress a decrease in gate breakdown voltage and an increase in channel resistance. In addition, in Patent Document 2 below, a technique is disclosed in which a plurality of etching processes are combined to make only the shoulder of the trench inclined.

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2022-164865

[0005] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2016-048747

[0006] In the technique of Patent Document 1, in order to make the shoulder of the trench in an arc shape, a thermal process is used. Therefore, there are problems that the production cycle of manufacturing the semiconductor device becomes long, or the channel region changes to an n-type or an i-type due to diffusion or rearrangement of atoms on the side wall of the trench, and current leakage occurs in the channel portion. In particular, when an impurity layer is formed on the side wall of the trench, there are also problems that impurities implanted into the side wall of the trench are unevenly lost, or local accelerated oxidation occurs in a portion of the side wall of the trench where impurities are implanted, and thus the same inclination of the side wall of the trench cannot be obtained, and the characteristics of the semiconductor device tend to become unstable.

[0007] On the other hand, in the technique of Patent Document 2, since only the shape of the shoulder of the trench is processed, the characteristics of the semiconductor device tend to be stable even when an impurity layer is formed on the side wall of the trench. However, when an inclined portion is formed on the shoulder of the trench by a dry etching process, a corner portion formed by the inclined portion and the vertical portion of the trench protrudes inward of the trench, and the reliability of the gate insulating film is reduced at the protruding portion.

[0008] Particularly in a silicon carbide (SiC) semiconductor device, the inventors of the technology related to the present disclosure have identified a failure mode unique to the SiC semiconductor device as described below. That is, when a voltage is generated between the semiconductor substrate and the gate wiring, if the corner formed by the inclined portion and the vertical portion of the groove of the gate lift portion protrudes, a high voltage is applied to the gate of the semiconductor element, the electric field concentrates on this corner, and the gate oxide film is damaged. Or when a voltage is applied between the drain and source while applying a negative bias voltage to the gate to expand the depletion layer, the electric field concentrates on this corner and the gate oxide film is damaged. Summary of the Invention

[0009] The present disclosure has been completed to solve the above problems, and an object thereof is to prevent electric field concentration at the shoulder of the groove of the gate lift portion in a trench gate type silicon carbide semiconductor device.

[0010] The semiconductor device according to the present disclosure includes: a semiconductor substrate made of silicon carbide; a trench formed on the upper surface of the semiconductor substrate; a gate insulating film formed on the inner surface of the trench; a gate wiring formed on the gate insulating film and buried in the trench; and a gate lift portion which is a region where a part of the gate wiring is lifted from the trench to the upper surface of the semiconductor substrate. The side wall of the trench of the gate lift portion includes: a vertical portion perpendicular to the upper surface of the semiconductor substrate; a horizontal portion located above the trench and parallel to the upper surface of the semiconductor substrate; and an inclined portion located at the shoulder of the trench and provided between the vertical portion and the horizontal portion. The inclined portion is inclined in a manner of expanding upward with the width of the trench and is linear when observed in cross section. When observed in cross section, the corner formed by the vertical portion and the inclined portion does not protrude into the trench from the region between the tangents of the vertical portion and the inclined portion.

[0011] According to the present disclosure, by suppressing electric field concentration at the shoulder of the groove of the gate lift portion, it is possible to prevent damage to the gate oxide film and improve the reliability of the semiconductor device. Brief Description of the Drawings

[0012] Figure 1 It is a top view of the semiconductor device according to Embodiment 1.

[0013] Figure 2 It is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1.

[0014] Figure 3 It is an enlarged view of the shoulder of the trench of the semiconductor device according to Embodiment 1.

[0015] Figure 4 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0016] Figure 5 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0017] Figure 6 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0018] Figure 7 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0019] Figure 8 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0020] Figure 9 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0021] Figure 10 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0022] Figure 11 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0023] Figure 12 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0024] Figure 13 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0025] Figure 14 It is a manufacturing process diagram of the semiconductor device according to Embodiment 1.

[0026] Figure 15 It is a diagram showing the relationship between the wet etching amount in the reduction process of the hard mask, the dry etching amount in the first etching process, and the shape of the trench shoulder.

[0027] Explanation of reference numerals:

[0028] 100... semiconductor device; 101... cell part; 102... gate lead part; 102a... gate pad area; 103... gate lift part; 1... semiconductor substrate; 2... channel doping layer; 3... source layer; 4... contact layer; 5... electric field relaxation layer; 6... trench sidewall P-type layer; 7... trench sidewall N-type layer; 8... trench; 8a... vertical part; 8b... inclined part; 8c... horizontal part; 9... gate insulating film; 10... gate wiring; 11... interlayer insulating film; 12... metal electrode; 20... hard mask. Detailed implementation mode

[0029] In the following embodiments, the first conductivity type is set to N-type and the second conductivity type is set to P-type for description. However, conversely, the first conductivity type may be set to P-type and the second conductivity type may be set to N-type. The high or low impurity concentration of each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration refers to a region with a high (or low) peak concentration of impurities.

[0030] <Embodiment 1>

[0031] Figure 1 It is a top view showing the structure of the semiconductor device 100 according to Embodiment 1. Figure 2 It is a cross-sectional view of the main part of the semiconductor device 100. Here, the semiconductor element included in the semiconductor device 100 is described as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, as long as it is a trench gate type semiconductor element, the semiconductor element may be any type such as an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (reverse conducting IGBT), etc.

[0032] As Figure 1 shown, the semiconductor device 100 includes a cell portion 101, a gate lead portion 102, and a gate lift portion 103.

[0033] The cell portion 101 is a region where cells of semiconductor elements (MOSFETs) are formed.

[0034] The gate lead portion 102 is a region where, for example, gate lead wirings made of aluminum are arranged to connect the gate pad to the gate wiring of the semiconductor element. Therefore, in the gate lead portion 102, a gate pad region 102a where the gate pad is arranged is included.

[0035] The gate lift portion 103 is a region for lifting a part of the gate wiring above the semiconductor substrate in order to connect the gate wiring of the semiconductor element to the gate lead wiring. Therefore, the gate lift portion 103 is provided at the boundary between the cell portion 101 and the gate lead portion 102.

[0036] Figure 2 It is a cross-sectional view of the cell portion 101 and the gate lift portion 103 of the semiconductor device 100 according to Embodiment 1.

[0037] The semiconductor device 100 is formed using an N-type semiconductor substrate 1 made of silicon carbide semiconductor. In the cell section 101, a P-type channel doping layer 2 is formed in the surface layer section of the semiconductor substrate 1. Further, an N-type source layer 3 and a P-type contact layer 4 having an impurity concentration higher than that of the channel doping layer 2 are selectively formed in the surface layer section of the channel doping layer 2, respectively.

[0038] On the upper surface of the semiconductor substrate 1, a trench 8 is formed so as to penetrate the source layer 3 and the channel doping layer 2. A gate insulating film 9 made of, for example, a silicon oxide film is formed on the inner surface of the trench 8. Further, a gate wiring 10 made of, for example, polysilicon is formed so as to fill the trench 8 above the gate insulating film 9. The basic structure of the MOSFET is constituted by the semiconductor substrate 1, the channel doping layer 2, the source layer 3, the gate insulating film 9, and the gate wiring 10. In addition, the N-type region under the source layer 3 in the semiconductor substrate 1 becomes a so-called drift layer, and the trench 8 reaches the drift layer.

[0039] In the present embodiment, in addition to the above basic structure, a P-type electric field relaxation layer 5 formed at the bottom of the trench 8, a trench sidewall P-type layer 6 formed on the sidewall of the trench 8, and a trench sidewall N-type layer 7 are provided. The electric field relaxation layer 5 relaxes the electric field generated at the bottom of the trench 8. The trench sidewall P-type layer 6 applies the source potential to the electric field relaxation layer 5 by connecting between the electric field relaxation layer 5 and the channel doping layer 2. The trench sidewall N-type layer 7 suppresses the current path between the trenches 8 from being narrowed by the electric field relaxation layer 5, and helps to reduce the on-resistance of the MOSFET.

[0040] On the semiconductor substrate 1, an interlayer insulating film 11 is formed so as to cover the gate wiring 10. Further, a metal electrode 12 serving as a source electrode is formed on the interlayer insulating film 11. The metal electrode 12 is electrically connected to the source layer 3 and the contact layer 4 through a contact hole formed in the interlayer insulating film 11. Although not shown, a drain electrode of the MOSFET is provided on the lower surface of the semiconductor substrate 1.

[0041] In the gate lift portion 103, the gate insulating film 9 and the gate wiring 10 extend from the inside of the trench 8 over the upper surface of the semiconductor substrate 1, whereby the gate wiring 10 is lifted above the semiconductor substrate 1.

[0042] In the gate lift portion 103, since the gate insulating film 9 and the gate wiring 10 are provided to straddle a plurality of trenches 8, and the interlayer insulating film 11 is formed to cover the gate wiring 10 extending along the upper surface of the semiconductor substrate 1, no contact hole for connecting the metal electrode 12 to the source layer 3 is provided in the interlayer insulating film 11. Therefore, there is no need to provide the contact layer 4 in the gate lift portion 103. In addition, since the gate lift portion 103 does not form a current path, there is also no need to provide the trench sidewall N-type layer 7. However, as described later, in order to suppress the leakage current generated in the gate lift portion 103, at least a portion of the source layer 3 in the gate lift portion 103 adjacent to the inclined portion 8b of the trench 8 may also be changed to a P-type semiconductor layer identical to the contact layer 4.

[0043] Here, the shape of the trench 8 will be described. As Figure 2 shown, the sidewall of the trench 8 includes a vertical portion 8a perpendicular to the upper surface of the semiconductor substrate 1, a horizontal portion 8c located at the upper part of the trench 8 and parallel to the upper surface of the semiconductor substrate 1, and an inclined portion 8b located at the shoulder of the trench 8 and provided between the vertical portion 8a and the horizontal portion 8c. The inclined portion 8b is inclined in such a manner that the width of the trench 8 expands upward. In addition, the inclined portion 8b is not in an arc shape but in a straight line shape when observed in cross section. Furthermore, the "vertical", "parallel", and "straight line shape" mentioned here do not mean strictly vertical, parallel, and straight line shape respectively, but substantially vertical, parallel, and straight line shape is sufficient.

[0044] The gate insulating film 9 formed on the sidewall of the trench 8 is formed uniformly over the vertical portion 8a, the inclined portion 8b, and the horizontal portion 8c. The gate wiring 10 of the cell portion 101 is received at a position lower than the corner formed by the inclined portion 8b and the vertical portion 8a of the trench 8. The gate wiring 10 of the gate lift portion 103 is formed to cover the vertical portion 8a, the inclined portion 8b, and the horizontal portion 8c of the trench 8.

[0045] Figure 3 is an enlarged view of the shoulder of the trench 8. In Figure 3 the illustration of the gate wiring 10 is omitted. As Figure 3 shown, when observed in cross section, the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 does not protrude into the trench 8 from the region sandwiched between the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b. That is, the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 does not protrude more into the trench 8 than the tangent line L1 of the vertical portion 8a, and does not protrude more upward than the tangent line L2 of the inclined portion 8b.

[0046] Particularly in the gate lift portion 103, since the shoulder of the trench 8 is covered by the gate wiring 10, if the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 protrudes, electric field concentration is likely to occur in this portion. By making the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 not protrude into the trench 8 from the region between the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b of the trench 8 as in this embodiment, the situation where the electric field is concentrated on the shoulder of the trench 8 covered by the gate wiring 10 is suppressed. As a result, breakdown of the gate insulating film 9 can be prevented, and the reliability of the semiconductor device can be improved.

[0047] Refer to Figures 4 to 14 the process drawing to describe the manufacturing method of the semiconductor device 100 according to Embodiment 1.

[0048] First, a semiconductor substrate 1 made of N-type silicon carbide is prepared. The semiconductor substrate 1 is formed by forming an epitaxial layer made of silicon carbide on a substrate made of silicon carbide.

[0049] Next, a P-type channel doping layer 2 and an N-type source layer 3 are formed by implanting impurity ions into the surface layer portion (epitaxial layer) of the semiconductor substrate 1. As an impurity for forming a P-type semiconductor layer, for example, Al (aluminum) can be used. As an impurity for forming an N-type semiconductor layer, for example, N (nitrogen) can be used.

[0050] Next, an oxide film is deposited on the semiconductor substrate 1, a resist having an opening with a pattern of the trench 8 is formed thereon, and the oxide film is etched using the resist as a mask. Thus, as Figure 4 shown, a hard mask 20 made of an oxide film having an opening in the formation region of the trench 8 is formed on the semiconductor substrate 1.

[0051] Next, the semiconductor substrate 1 is etched using the hard mask 20 as a mask, and the trench 8 is formed as Figure 5 shown. Although the vertical portion 8a of the trench 8 is formed by this etching, at this time, a cap-shaped protrusion A is formed at the interface between the shoulder of the trench 8 (the upper end portion of the vertical portion 8a) and the hard mask 20.

[0052] After that, by wet-etching the hard mask 20, for example, the size of the hard mask 20 is reduced by a certain size, and the shoulder of the trench 8 is exposed from the hard mask 20 as Figure 6 shown.

[0053] Then, using the reduced hard mask 20 as a mask, anisotropic dry etching such as reactive ion etching is performed on the shoulder of the trench 8. As a result, as Figure 7 shown, an inclined portion 8b is formed on the shoulder of the trench 8. Hereinafter, this process will be referred to as the "first etching process".

[0054] By performing the first etching process with anisotropic etching, the shoulders of the trench 8 can be selectively processed. Specifically, if etching using an etchant such as Freon with a large molecular diameter and a short mean free path (compared to hydrogen treatment) is applied to the first etching process, the etching rate near the shoulders of the trench 8 can be appropriately increased. In addition, at the shoulders of the trench 8, since the reaction progresses from both the upper surface and the side surface, the etching rate is high, and at the bottom of the trench 8, since only the surface reaction occurs, the etching rate is low, which also contributes to the selective etching of the shoulders of the trench 8. Due to these effects, the shape change at the bottom of the trench 8 in the first etching process is suppressed, which can contribute to improving the reliability of the semiconductor device 100.

[0055] If the inclined portion 8b is formed in the first etching process, at least the upper part of the protrusion A is removed. However, when the width of the protrusion A in the vertical direction is wide, even after the first etching process, sometimes, as Figure 7 shown, the protrusion B, which is the remaining part of the protrusion A, protrudes into the trench 8 from the region sandwiched by the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b.

[0056] Therefore, after the first etching process, isotropic dry etching using the hard mask 20 as a mask is performed to remove the protrusion B. As a result, as Figure 8 shown, the corner formed by the vertical portion 8a and the inclined portion 8b becomes the inflection point C accommodated in the region sandwiched by the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b. Hereinafter, this process will be referred to as the "second etching process".

[0057] In this way, the first etching process and the second etching process for forming the inclined portion 8b at the shoulders of the trench 8 are self-alignment processes that use the hard mask 20 used in the trench formation process as a mask. Therefore, the photolithography process is not increased, and the inclined portion 8b can be formed with good positional accuracy.

[0058] In Figure 15 the relationship between the wet etching amount in the reduction process of the hard mask 20, the dry etching amount in the first etching process, and the shape of the shoulders of the trench 8 is shown. As Figure 15 shown, if the etching amount in the reduction process of the hard mask 20 is reduced and the etching amount in the first etching process is increased, the shape of the shoulders of the trench 8 can be improved (the protrusion A becomes smaller). It is preferable that the etching amount in the reduction process of the hard mask 20 is less than the etching amount in the first etching process. In this way, the protrusion B remaining after the first etching process can be reduced, and the protrusion B can be easily removed in the second etching process.

[0059] After the second etching process, the hard mask 20 is removed. Then, by selective ion implantation, as Figure 9The electric field relaxation layer 5, the trench sidewall P-type layer 6, and the trench sidewall N-type layer 7 are formed in this way. The electric field relaxation layer 5 can also be formed during the process of forming the trench 8 ( Figure 5 ) and the process of reducing the hard mask 20 ( Figure 6 ). In this case, the electric field relaxation layer 5 can be formed by vertical ion implantation using the hard mask 20 before reduction as a mask, which can suppress the injection of impurities into the sidewalls of the trench 8 when forming the electric field relaxation layer 5, and improve the reliability of the semiconductor device 100.

[0060] Furthermore, a P-type contact layer 4 is formed by selective ion implantation, as Figure 10 . At this time, P-type impurities can also be implanted into the gate pull-up portion 103 to change at least the portion of the N-type source layer 3 formed in the gate pull-up portion 103 adjacent to the vertical portion 8a of the trench 8 into a P-type semiconductor layer. Since the source layer 3 of the gate pull-up portion 103 is surrounded by the gate wiring 10, it sometimes causes an increase in leakage current. It can be presumed that the reason for the increase in leakage current in the N-type semiconductor is that the leakage current is likely to increase because there is an excess of electrons with high mobility.

[0061] After all the impurity implantation processes are implemented, a heat treatment for activating the implanted impurities is implemented. After that, as Figure 11 shown, a gate insulating film 9 is formed on the upper surface of the semiconductor substrate 1 including the inside of the trench 8. In addition, as Figure 12 , a conductive film such as polysilicon is deposited on the gate insulating film 9 to form the gate wiring 10.

[0062] Then, the gate wiring 10 is patterned by selective etching, as Figure 13 . In the patterning process of the gate wiring 10, the etching of the gate wiring 10 for the cell portion 101 is performed, and while leaving the gate wiring 10 in the trench 8 of the cell portion 101, the gate wiring 10 is removed from the upper surface of the semiconductor substrate 1 of the cell portion 101. At this time, the etching is performed until the upper surface of the gate wiring 10 remaining in the trench 8 is received at a position lower than the inflection point C of the shoulder of the trench 8.

[0063] Then, an interlayer insulating film 11 is formed on the semiconductor substrate 1. After forming contact holes in the interlayer insulating film 11, as Figure 14 , a metal electrode 12 and a gate pad (not shown) are formed on the interlayer insulating film 11. As needed, a protective film such as a passivation film is formed on the metal electrode 12 and the gate pad, and the protective film is opened so as to expose a part of the metal electrode 12 and the gate pad.

[0064] In addition, after thinning the semiconductor substrate 1 by grinding the back surface of the semiconductor substrate 1, a drain electrode made of metal is formed on the back surface of the semiconductor substrate 1, thereby completing the semiconductor device 100.

[0065] After that, a dicing process for singulating the semiconductor device 100 and a testing process for the semiconductor device 100 are performed. The semiconductor device 100 is ultimately configured as an inverter circuit or the like by being modularized or the like.

[0066] In addition, the above-described embodiments can be appropriately modified or omitted.

[0067] <Supplementary Note>

[0068] Hereinafter, each aspect of the present disclosure will be collectively described as supplementary notes.

[0069] (Supplementary Note 1)

[0070] A semiconductor device, wherein:

[0071] It includes:

[0072] A semiconductor substrate made of silicon carbide;

[0073] A trench formed on the upper surface of the above semiconductor substrate;

[0074] A gate insulating film formed on the inner surface of the above trench;

[0075] A gate wiring formed on the above gate insulating film and buried in the above trench; and

[0076] A gate lift portion, which is a region where a part of the above gate wiring is lifted from the above trench to the above upper surface of the semiconductor substrate,

[0077] The side wall of the above trench of the above gate lift portion includes:

[0078] A vertical portion perpendicular to the above upper surface of the semiconductor substrate;

[0079] A horizontal portion located above the above trench and parallel to the above upper surface of the semiconductor substrate; and

[0080] An inclined portion located at the shoulder of the above trench and provided between the above vertical portion and the above horizontal portion,

[0081] The above inclined portion is inclined in a manner of expanding upward with the width of the above trench, and is linear when observed in cross section,

[0082] When observed in cross section, the corner formed by the above vertical portion and the above inclined portion does not protrude into the above trench from the region between the tangent of the above vertical portion and the tangent of the above inclined portion.

[0083] (Supplementary Note 2)

[0084] In the semiconductor device described in Supplementary Note 1,

[0085] the above-mentioned trench reaches the drift layer of the first conductivity type,

[0086] and an electric field relaxation layer of the second conductivity type is formed at the bottom of the above-mentioned trench.

[0087] (Supplementary Note 3)

[0088] In the semiconductor device described in Supplementary Note 2,

[0089] a second-conductivity-type impurity layer connected to the above-mentioned electric field relaxation layer is formed on a part of the side wall of the above-mentioned trench.

[0090] (Supplementary Note 4)

[0091] In the semiconductor device described in any one of Supplementary Notes 1 to 3,

[0092] in the above-mentioned gate lift portion, at least a portion of the semiconductor substrate adjacent to the vertical portion of the above-mentioned trench is a P-type semiconductor layer.

[0093] (Supplementary Note 5)

[0094] A method for manufacturing a semiconductor device, comprising:

[0095] forming a mask on the upper surface of a semiconductor substrate;

[0096] forming a trench having a vertical portion perpendicular to the above-mentioned upper surface in the above-mentioned semiconductor substrate by etching using the above-mentioned mask;

[0097] shrinking the above-mentioned mask;

[0098] a first etching process of forming an inclined portion at the shoulder of the above-mentioned trench by etching using the shrunk above-mentioned mask; and

[0099] a second etching process of etching a corner formed by the above-mentioned vertical portion and the above-mentioned inclined portion by etching using the shrunk above-mentioned mask after the above-mentioned first etching process.

[0100]

[0101] (Supplementary Note 6)

[0102] In the method for manufacturing a semiconductor device described in Supplementary Note 5,

[0103] the etching in the above-mentioned first etching process is anisotropic etching,

[0104] ​The etching in the second etching process described above is isotropic etching.

[0105] (Supplementary Note 7)

[0106] In the method for manufacturing a semiconductor device described in Supplementary Note 5 or Supplementary Note 6,

[0107] the etching amount in the process of reducing the mask is made smaller than the etching amount in the first etching process.

Claims

1. A semiconductor device, wherein: have: A semiconductor substrate composed of silicon carbide; A groove formed on the upper surface of the semiconductor substrate; a gate insulating film formed on an inner surface of the trench; A gate wiring is formed on the gate insulating film and buried in the trench; and a gate pull-up portion, the gate pull-up portion being a region where a portion of the gate wiring is pulled up from the trench to the upper surface of the semiconductor substrate, The sidewall of the trench of the gate pull-up portion comprises: a vertical portion, perpendicular to the upper surface of the semiconductor substrate; a horizontal portion, located at an upper portion of the trench and parallel to the upper surface of the semiconductor substrate; and An inclined portion, located at the shoulder of the groove, is disposed between the vertical portion and the horizontal portion, The inclined portion is inclined in such a manner that the width of the groove expands upward and is linear when viewed in cross section. When viewed in cross section, a corner formed by the vertical portion and the inclined portion does not protrude toward the inside of the groove from a region sandwiched between a tangent line of the vertical portion and a tangent line of the inclined portion.

2. The semiconductor device according to claim 1, wherein The trench reaches the drift layer of the first conductivity type, A second conductivity type electric field relaxation layer is formed at the bottom of the trench.

3. The semiconductor device according to claim 2, wherein: The second conductivity type impurity layer connected to the electric field relaxation layer is formed on a portion of the side wall of the trench.

4. The semiconductor device according to any one of claims 1 to 3, wherein In the gate pull-up portion, at least a portion of the semiconductor substrate adjacent to the vertical portion of the trench is a P-type semiconductor layer.

5. A method for manufacturing a semiconductor device, wherein: have: forming a mask on the upper surface of the semiconductor substrate; forming a groove having a vertical portion perpendicular to the upper surface in the semiconductor substrate by etching using the mask; A process of shrinking the mask; A first etching step of forming an inclined portion at a shoulder of the trench by etching using the reduced mask; and After the first etching step, a second etching step is performed to etch a corner portion formed by the vertical portion and the inclined portion by etching using the reduced mask.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The etching in the first etching step is anisotropic etching, The etching in the second etching step is isotropic etching.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein: The etching amount in the step of shrinking the mask is made smaller than the etching amount in the first etching step.

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