Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, and the method comprises the steps: opening a mask layer on a medium-voltage gate oxide layer in a low-voltage region after forming a medium-voltage gate oxide layer which at least covers a medium-voltage region and a low-voltage region and forming a patterned mask layer which is used for limiting the medium-voltage gate oxide layer needing to be reserved on the medium-voltage region; and opening the mask layer on the beak region of the high-voltage gate oxide layer in the high-voltage region, so that the beak region of the high-voltage gate oxide layer in the high-voltage region is thinned or removed while the medium-voltage gate oxide layer in the low-voltage region is thinned or removed by using a wet etching process, thereby avoiding increasing extra photomask cost and process cost and improving the yield. The problem that source and drain ions injected into the source electrode region subsequently are blocked due to the fact that the thickness of the beak region is increased is solved, the transverse distance from a metal silicide and a contact plug on the source electrode region subsequently to a channel is shortened, the resistance of the source electrode region is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to a manufacturing method of a semiconductor device. Background Art

[0002] In some current integrated circuit products, it is necessary to integrate MOS transistors with different operating voltages to achieve the required functions and performances. For example, high-voltage transistors, medium-voltage transistors, and low-voltage transistors are manufactured together on the same substrate through a CMOS process. Among them, the manufacturing of the gate oxide layer is one of the most important process steps in the manufacturing process of such products, which directly affects the threshold voltage, saturation current, gate leakage current, gate breakdown voltage, and reliability of each transistor. Moreover, the thicknesses of the gate oxide layers required for high-voltage transistors, medium-voltage transistors, and low-voltage transistors are different. Among them, the gate oxide layer of the high-voltage transistor is thicker than that of other transistors.

[0003] In addition, for more and more current application scenarios, in order to achieve effects such as reducing the layout area, facilitating low-power consumption and low-cost control, etc., asymmetric HVMOS transistors are widely used. The drain region 100d is separated from the gate (not shown, which is formed on the high-voltage gate oxide layer HOX 103) through shallow trench isolation (STI), so as to form an asymmetric structure at the source region 100s and the drain region 100d. When working, a high voltage is applied to the drain region and the gate.

[0004] The high-voltage gate oxide layer HOX 103 of the above-mentioned asymmetric HVMOS transistor is usually formed by a thermal oxidation process. Since a relatively long thermal oxidation process time is required to form the relatively thick high-voltage gate oxide layer HOX 103, oxygen will diffuse laterally to the surface layer of the source region 100s masked by the silicon nitride mask layer 102 near the high-voltage gate oxide layer HOX 103 region, forming a bird's beak structure 103a. On the one hand, the bird's beak structure 103a will block the subsequent source-drain ion implantation in the source region 100s. The thicker the thickness of the bird's beak structure 103a, the more the dose loss of the source-drain ions implanted into the source region 100s, thereby reducing the device performance. On the other hand, the bird's beak structure 103a occupies a certain area of the source region 100s, causing the metal silicide formed subsequently on the source region 100s to shift outward relatively and the area to decrease, thereby resulting in too small an area of the metal silicide contacted at the bottom of the subsequent contact plug, causing an increase in the contact resistance, and causing an inevitable increase in the lateral distance between the contact plug on the source region 100s and the channel (i.e., the active region under the high-voltage gate oxide layer HOX 103) due to the lateral extension length of the bird's beak structure 103a, which will also lead to an increase in the source resistance and thus reduce the device performance.

[0005] The above problems may also exist in symmetric HVMOS transistors.

[0006] Therefore, a new solution is needed to improve the defects caused by the bird's beak structure in the high-voltage transistor region. Summary of the Invention

[0007] The object of the present invention is to provide a manufacturing method of a semiconductor device, which can improve the defects caused by the bird's beak structure in the high-voltage transistor region.

[0008] To achieve the above object, the present invention provides a manufacturing method of a semiconductor device, including the following steps:

[0009] Provide a substrate, and form a plurality of shallow trench isolation structures in the substrate to define a high-voltage region, a medium-voltage region, and a low-voltage region;

[0010] Mask the medium-voltage region and the low-voltage region and expose the substrate surface of the high-voltage region, and form a high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process, and the high-voltage gate oxide layer has a bird's beak region;

[0011] Expose at least the substrate surfaces of the low-voltage region and the medium-voltage region, and form a medium-voltage gate oxide layer, and the medium-voltage gate oxide layer covers at least the substrate surfaces of the medium-voltage region and the low-voltage region;

[0012] Form a patterned mask layer, and the patterned mask layer masks the medium-voltage gate oxide layer to be retained on the medium-voltage region and exposes the medium-voltage gate oxide layer on the low-voltage region and the bird's beak region of the high-voltage gate oxide layer;

[0013] Using the patterned mask layer as a mask, a wet etching process is used to simultaneously thin or remove the medium-voltage gate oxide layer on the low-voltage region and the bird's beak region of the high-voltage gate oxide layer.

[0014] Optionally, at the end of the wet etching process, the remaining medium-voltage gate oxide layer on the low-voltage region serves as the low-voltage gate oxide layer with the required thickness in the low-voltage region; or, after using the wet etching process to remove the medium-voltage gate oxide layer on the low-voltage region and expose the substrate surface of the low-voltage region, the manufacturing method further includes: removing the patterned mask layer, and forming a low-voltage gate oxide layer on the exposed substrate surface of the low-voltage region by using a third thermal oxidation process or a chemical vapor deposition process.

[0015] Optionally, the thicknesses of the low-voltage gate oxide layer, the medium-voltage gate oxide layer, and the high-voltage gate oxide layer increase in sequence.

[0016] Optionally, after removing the patterned mask layer and forming the low-voltage gate oxide layer, the manufacturing method further includes:

[0017] Form a gate on the high-voltage gate oxide layer in the high-voltage region, the medium-voltage gate oxide layer in the medium-voltage region, and the low-voltage gate oxide layer in the low-voltage region;

[0018] Form sidewalls on the sidewalls of the gate;

[0019] Use a source-drain ion implantation process to form a source region and a drain region in the substrate on both sides of the gate;

[0020] Use a salicide process to form a salicide on the top of the gate, the source region, and the drain region;

[0021] Form contact plugs on the salicide on the top of the gate, the source region, and the drain region.

[0022] Optionally, the source region and the drain region in the high-voltage region are of an asymmetric structure.

[0023] Optionally, the drain region in the high-voltage region is separated from the gate by the corresponding shallow trench isolation structure, and the gate continuously extends from the high-voltage gate oxide layer onto the shallow trench isolation structure between the gate and the drain region.

[0024] Optionally, the source region and the drain region in the high-voltage region are of a first conductivity type, and the manufacturing method further includes: before forming the high-voltage gate oxide layer, forming a well of a second conductivity type in the high-voltage region, forming a drift region of the first conductivity type on both sides of the high-voltage gate oxide layer and a drift region of the second conductivity type outside the drift region in the well, and, after forming the sidewalls and before forming the salicide, forming a body contact region in the drift region of the second conductivity type; wherein, the source region and the drain region in the high-voltage region are respectively formed in the drift regions of the first conductivity type on both sides of the high-voltage gate oxide layer.

[0025] Optionally, after forming the high-voltage gate oxide layer, first mask the high-voltage region and expose the substrate surfaces of the low-voltage region and the medium-voltage region, and use a corresponding second thermal oxidation process or a chemical vapor deposition process to form a medium-voltage gate oxide layer on the medium-voltage region and the low-voltage region together; wherein, before masking the high-voltage region, first remove the hard mask layer, or, after using the wet etching process to thin or remove the bird's beak regions of the medium-voltage gate oxide layer and the high-voltage gate oxide layer on the low-voltage region together, remove the hard mask layer.

[0026] Optionally, after forming the high-voltage gate oxide layer, the hard mask layer is removed to expose the substrate surfaces of the low-voltage region and the medium-voltage region and the remaining surfaces of the high-voltage region, and the medium-voltage gate oxide layer is formed on the high-voltage region, the bird's beak region, the medium-voltage region, and the low-voltage region together by using a corresponding second thermal oxidation process or a chemical vapor deposition process.

[0027] Compared with the prior art, in the technical solution of the present invention, after forming the medium-voltage gate oxide layer covering at least the medium-voltage region and the low-voltage region and when forming the patterned mask layer for defining the medium-voltage gate oxide layer to be retained on the medium-voltage region, not only the mask layer on the medium-voltage gate oxide layer in the low-voltage region is opened, but also the mask layer on the bird's beak region of the high-voltage gate oxide layer in the high-voltage region is opened. Thus, while thinning or removing the medium-voltage gate oxide layer on the low-voltage region by using a wet etching process, the bird's beak region of the high-voltage gate oxide layer in the high-voltage region is thinned or removed together. Therefore, on the one hand, additional mask costs and process costs can be avoided, and on the other hand, the problem that the source-drain ions injected into the source region subsequently are blocked due to the excessive thickness of the bird's beak region can be improved, and the problem that the device performance is reduced due to the reduction of the ion doping dose in the source region of the high-voltage region can be avoided. In addition, at least part of the bird's beak region of the high-voltage gate oxide layer is removed, which can shorten the lateral distance between the metal silicide and the contact plug on the source region subsequently and the channel, reduce the resistance of the source region, and improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0029] Figure 1 is a schematic cross-sectional structure diagram of a device when forming a high-voltage gate oxide layer of an existing high-voltage transistor.

[0030] Figure 2 is a schematic flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0031] Figures 3A to 3E is a schematic cross-sectional structure diagram of a device in a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0032] Figures 4 to 5 is a schematic cross-sectional structure diagram of a high-voltage transistor formed in a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0033] Figures 6A to 6E is a schematic cross-sectional structure diagram of a device in a manufacturing method of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to specify the presence of the features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0035] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be more clearly understood. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0036] Please refer to Figure 2 , an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps:

[0037] S1, providing a substrate, and forming a plurality of shallow trench isolation structures in the substrate to define a high-voltage region, a medium-voltage region, and a low-voltage region;

[0038] S2, masking the medium-voltage region and the low-voltage region and exposing the substrate surface of the high-voltage region, and forming a high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process, the high-voltage gate oxide layer having a bird's beak region;

[0039] S3, at least exposing the substrate surfaces of the low-voltage region and the medium-voltage region, and forming a medium-voltage gate oxide layer, the medium-voltage gate oxide layer covering at least the substrate surfaces of the medium-voltage region and the low-voltage region;

[0040] S4. Form a patterned mask layer, where the patterned mask layer masks the middle - voltage gate oxide layer to be retained on the middle - voltage region and exposes the middle - voltage gate oxide layer on the low - voltage region and the bird's - beak region of the high - voltage gate oxide layer.

[0041] S5. Using the patterned mask layer as a mask, adopt a wet etching process to simultaneously thin or remove the middle - voltage gate oxide layer on the low - voltage region and the bird's - beak region of the high - voltage gate oxide layer.

[0042] Please refer to Figure 3A , in step S1, the provided substrate 200 can be any suitable semiconductor substrate material such as bulk silicon, silicon - on - insulator, silicon carbide, etc. Then, a pad oxide layer (PAD oxide, not shown) is formed on the substrate 200 through a thermal oxidation process, and a hard mask layer (hard mask, not shown) is deposited by processes such as chemical vapor deposition of materials such as silicon nitride. Next, a plurality of shallow trench isolation structures STI are formed through a shallow trench isolation process, and this shallow trench isolation process includes: coating a photoresist on the hard mask layer and performing photolithography on the photoresist; using the photoresist after photolithography as a mask and the pad oxide layer as an etch stop layer to etch the hard mask layer 202; then removing the photoresist, using the hard mask layer as a mask to etch the pad oxide layer and the substrate 200, thereby forming shallow trenches (not shown) in the substrate 200; forming a line oxide layer (not shown) on the sidewalls and bottom surfaces in the shallow trenches and filling the shallow trenches with an insulating dielectric material such as silicon oxide through a deposition process, and performing chemical mechanical polishing or back - etching on the top surface of the filled insulating dielectric material, thereby forming shallow trench isolation structures STI filled in the shallow trenches; then removing the remaining hard mask layer and pad oxide layer.

[0043] Please refer to Figure 3A , in step S1, a part of the shallow trench isolation structures STI are located at the junctions of different device regions, thereby respectively defining a high - voltage region HV (i.e., the active region of high - voltage components), a middle - voltage region MV (i.e., the active region of middle - voltage components), and a low - voltage region LV (i.e., the active region of low - voltage components) in the substrate 200. The high - voltage region HV is used to form high - voltage components such as high - voltage transistors with a high operating voltage, the middle - voltage region MV is used to form middle - voltage components such as middle - voltage transistors with a middle operating voltage, and the low - voltage region LV is used to form low - voltage components such as low - voltage transistors and static random - access memories SRAM with a low operating voltage. Another part of the shallow trench isolation structures STI can be formed in the high - voltage region HV, the middle - voltage region MV, or the low - voltage region LV to achieve local isolation in these active regions. For example, corresponding shallow trench isolation structures STI are provided in the high - voltage region HV, which are used as a spacer structure between the subsequently formed gate and drain regions in the high - voltage region HV, and make the source and drain regions formed subsequently in the high - voltage region HV asymmetric, thereby making the high - voltage transistors formed in the high - voltage region HV asymmetric high - voltage transistors.

[0044] Optionally, before or after forming a plurality of shallow trench isolation structures STI to define a high voltage region HV, a medium voltage region MV, and a low voltage region LV, corresponding N-type or P-type ion implantation is performed first to form wells, drift regions, etc. in the substrate 200 of the high voltage region HV, medium voltage region MV, or low voltage region LV. For example, before or after forming a plurality of shallow trench isolation structures STI to define the high voltage region HV, ions of a second conductivity type (e.g., P-type) are implanted into the substrate 200 of the high voltage region HV to form a high voltage well (HVPW) 200e of the second conductivity type in the substrate 200 of the high voltage region HV, and further ions of a first conductivity type (e.g., N-type) are implanted into the substrate 200 on both sides of the high voltage gate oxide layer HOX to be formed in the high voltage region HV to form the required drift regions of the first conductivity type (e.g., N drift) 200a, 200b, and ions of the second conductivity type (e.g., P-type) are implanted into the substrate 200 outside each drift region to form the required drift regions of the second conductivity type (e.g., P drift) 200c, 200e. Among them, please refer to Figure 3A and Figure 4 , the drift region 200a is used to provide a region for subsequently forming the drain region 200d, the drift region 200b is used to provide a region for subsequently forming the source region 200s, and the drift regions 200c, 200e are used to provide regions for subsequently forming the body contact region 200p.

[0045] In step S2, the required high voltage gate oxide layer (HOX) 203 on the high voltage region HV can be formed by any suitable high voltage gate oxide process.

[0046] As an example, please refer to Figure 3A , in step S2, the steps of forming the high voltage gate oxide layer (HOX) 203 include:

[0047] First, materials such as silicon oxide are deposited on the substrate 200 and the shallow trench isolation structure STI to form an etching protection layer 201, and further materials such as silicon nitride are deposited on the etching protection layer 201 to form a hard mask layer 202;

[0048] Next, a patterned photoresist layer for defining the formation region of the high voltage gate oxide layer 203 is formed through photolithography processes such as photoresist coating, exposure, and development, and using the patterned photoresist layer as a mask, the hard mask layer 202 and the etching protection layer 201 of the high voltage region HV are etched and opened. Thus, the patterned hard mask layer 202 can expose the surface of the region of the substrate 200 of the high voltage region HV to be formed with the high voltage gate oxide layer 203 while masking the medium voltage region MV and the low voltage region LV, and then the patterned photoresist layer is removed;

[0049] Then, using the hard mask layer 202 as a mask, the substrate in the exposed high-voltage region HV is etched to form a first trench (not shown) with a desired depth; alternatively, first, the substrate in the exposed high-voltage region HV is thermally oxidized through a thermal oxidation process to form a sacrificial oxide layer (not shown), and the sacrificial oxide layer is etched away to form a first trench (not shown) with a desired depth; thereafter, any suitable first thermal oxidation process such as high-temperature furnace tube oxidation is used to thermally oxidize the substrate 200 exposed at the first trench to form a high-voltage gate oxide layer 203 with a desired thickness. And the process time of this first thermal oxidation process is relatively long. In this first thermal oxidation process, mainly the longitudinal diffusion of oxygen occurs at the first trench to form a high-voltage gate oxide layer 203 with a relatively large thickness. However, there is also a certain degree of lateral diffusion of oxygen. This oxygen laterally diffuses into the substrate 200 of the high-voltage region HV masked by the hard mask layer 202 around the first trench and forms a bird's beak region 203a of the high-voltage gate oxide layer 203.

[0050] In step S3, any suitable medium-voltage gate oxide process can be used to form the required medium-voltage gate oxide layer (GOX) 204a on the medium-voltage region MV. In this step, this medium-voltage gate oxide process will simultaneously form a medium-voltage gate oxide layer (GOX) 204b with the same thickness as the medium-voltage gate oxide layer (GOX) 204a on the high-voltage region HV and the low-voltage region LV.

[0051] As an example of this embodiment, in step S3, the steps of forming the medium-voltage gate oxide layer include:

[0052] First, please refer to Figure 3B , first remove the hard mask layer 202 and the etching protection layer 201 thereunder, thereby not only exposing the surfaces of the substrates 200 in the medium-voltage region MV and the low-voltage region LV and the high-voltage gate oxide layer 203, but also exposing the tops of the shallow trench isolation structures STI in each region, the bird's beak region 203a of the high-voltage region HV, and the surfaces of the substrates 200 in the regions of the high-voltage region HV where the high-voltage gate oxide layer 203 is not formed.

[0053] Then, any suitable second thermal oxidation process such as a high-temperature furnace tube oxidation process (the process time of which is shorter than that of the above-mentioned first thermal oxidation process) is adopted to thermally oxidize the surface of the substrate 200 exposed in the high-voltage region HV, low-voltage region LV, and medium-voltage region MV. The silicon of the exposed substrate in each of the high-voltage region HV, low-voltage region LV, and medium-voltage region MV reacts with oxygen, so that a medium-voltage gate oxide layer is formed on the surfaces of the substrates 200 exposed in the high-voltage region HV (including the substrate exposed in the bird's beak region and other regions), low-voltage region LV, and the medium-voltage region MV. The silicon of the substrate 200 in other regions is blocked by the hard mask layer 202 and the high-voltage gate oxide layer 203 and will not react with oxygen. Among them, a medium-voltage gate oxide layer 204b is formed on the substrate 200 in the low-voltage region LV, a medium-voltage gate oxide layer 204a is formed on the substrate 200 in the medium-voltage region MV, and a medium-voltage gate oxide layer 204c is formed on the substrate 200 in the high-voltage region HV. In addition, oxygen molecules in the second thermal oxidation process will also perform vertical diffusion and lateral diffusion near the bird's beak region 203a in the high-voltage region HV, thereby further widening and thickening the oxide layer in the bird's beak region 203a in the high-voltage region HV.

[0054] As another example of this embodiment, in step S3, after removing the hard mask layer 202 and the etching protection layer 201 thereunder, any suitable vapor deposition process such as chemical vapor deposition, atomic layer deposition, plasma-enhanced deposition, etc. can be adopted to replace the above-mentioned second thermal oxidation process, so as to deposit and form a medium-voltage gate oxide layer GOX on the exposed device surface. The medium-voltage gate oxide layer GOX formed at this time not only covers the exposed substrate surface, but also covers the surfaces of the shallow trench isolation structure STI, the high-voltage gate oxide layer 203, and the bird's beak region 203a. Moreover, the stacked thickness of the high-voltage gate oxide layer 203 and the medium-voltage gate oxide layer GOX covering its top needs to meet the thickness requirement range of the gate oxide required for device manufacturing in the high-voltage region.

[0055] In step S4, please refer to Figure 3C, a photoresist is coated on the surfaces of the high-voltage gate oxide layer 203, the medium-voltage gate oxide layers 204a, 204b, 204c, and the shallow trench isolation structure STI, etc. Then, by means of a photomask for defining the medium-voltage gate oxide layer to be retained in the medium-voltage region MV, the coated photoresist is exposed, and the exposed photoresist is developed, etc., to form a patterned photoresist layer as the required patterned mask layer 301. The patterned mask layer 301 can mask the medium-voltage gate oxide layer 204a to be retained in the medium-voltage region MV and the regions such as the region of the high-voltage gate oxide layer 203 in the high-voltage region HV except for the bird's beak region 203a, and expose the surface of the medium-voltage gate oxide layer 204b on the low-voltage region LV, the top of the bird's beak region 203a, and the medium-voltage gate oxide layer 204c in the high-voltage region HV. In this embodiment, the patterned mask layer 301 also exposes part or all of the top surface of the shallow trench isolation structure near the medium-voltage gate oxide layer. In this step, compared with the prior art, the number of photomasks does not increase. It only modifies the pattern of the photomask, specifically, a pattern (such as an opening) for opening the bird's beak region 203a is added to the photomask for defining the gate oxide layer to be retained in the medium-voltage region MV.

[0056] Please refer to Figure 3D , in step S5, using the patterned mask layer 301 as a mask, the medium-voltage gate oxide layers 204b, 204c exposed on the low-voltage region LV and the high-voltage region HV and the bird's beak region 203a exposed on the high-voltage region HV are thinned or removed in one pass by any suitable wet etching process. As an example, an HF acid solution, SPM (H 2 SO4, H 2 O 2 , H 2 O mixture), or SC1 (NH 4 OH, H 2 O 2 , H 2Any suitable etching solution, such as a mixture of HF and H₂O₂, is used to perform wet etching on the exposed medium - voltage gate oxide layers 204b and 204c on the low - voltage region LV and the high - voltage region HV, and the exposed bird's - beak region 203a on the high - voltage region HV together until the medium - voltage gate oxide layer 204b exposed on the low - voltage region LV is thinned to the low - voltage gate oxide layer (not shown) with the required thickness on the low - voltage region LV. At this time, the exposed bird's - beak region 203a on the high - voltage region HV is also thinned by this wet etching and even partially or completely removed laterally. Even if only part of the bird's - beak region 203a is removed, the remaining bird's - beak region 203a will be further removed during various cleaning steps of the wafer in subsequent steps. Before forming the metal silicide, this part of the bird's - beak will no longer affect the formation quality of the metal silicide, that is, it will not affect the formation quality of the subsequent contact plug, which can reduce the lateral distance between the metal silicide and the contact plug to the channel on the source region, reduce the resistance of the source region, and improve the device performance. In this example, the exposed medium - voltage gate oxide layers 204b and 204c on the low - voltage region LV and the high - voltage region HV are completely removed, and the exposed bird's - beak region 203a on the high - voltage region HV is also completely removed by this wet etching.

[0057] It should be understood that, compared with the prior art, the manufacturing method of this embodiment does not increase the number of photomasks. It only adds a pattern (such as an opening) for opening the bird's - beak region 203a in the photomask for defining the gate oxide of the medium - voltage region MV. Thus, it is possible to thin or remove the bird's - beak region 203a of the high - voltage gate oxide layer 203 while thinning or removing the medium - voltage gate oxide layer on the low - voltage region LV subsequently. Thus, on the basis of not increasing the number of photomasks and process steps, the defects caused by the existence of the bird's - beak region 203a in the prior art are improved.

[0058] Optionally, after step S5, please refer to Figure 3E , the patterned mask layer 301 is also removed, and a third thermal oxidation process or a chemical vapor deposition process is further used to form a low - voltage gate oxide layer 212 on the surface of the substrate 200 exposed in the low - voltage region LV. Optionally, the thicknesses of the formed low - voltage gate oxide layer 212, the remaining medium - voltage gate oxide layer 204a, and the remaining high - voltage gate oxide layer 203 increase in sequence.

[0059] As an example, when forming the low - voltage gate oxide layer 212 on the low - voltage region LV, the third thermal oxidation process or the chemical vapor deposition process also forms a low - voltage oxide layer on the surface of the substrate in the high - voltage region HV exposed after removing the bird's - beak region 203a and the medium - voltage gate oxide layer 204c. This low - voltage oxide layer can be retained in subsequent processes and used as a protective layer for the substrate in its covered area, or can be removed by any suitable process at any suitable process node in the subsequent process, such as being etched and removed together when etching the deposited metal silicide barrier layer (SAB) in the subsequent process.

[0060] Optionally, after removing the patterned mask layer 301 and forming the low-pressure gate oxide layer 212 as described above, the manufacturing method in this embodiment further includes:

[0061] (1), please refer to Figure 3E and Figure 4 , deposit an etch protection layer 205 on the top surfaces of the substrate 200, the high-pressure gate oxide layer 203, the medium-pressure gate oxide layer 204a, the low-pressure gate oxide layer 212, and the shallow trench isolation structure STI.

[0062] (2), please continue to refer to Figure 3E and Figure 4 , form gates 206 on the high-pressure gate oxide layer 203 in the high-voltage region HV, the medium-pressure gate oxide layer 204a in the medium-voltage region MV, and the low-pressure gate oxide layer 212 in the low-voltage region MV respectively through any suitable gate process. Optionally, the gate 206 in the high-voltage region HV extends from above a part of the top of the high-pressure gate oxide layer 203 to above a part of the top of the adjacent shallow trench isolation structure STI.

[0063] (3), please continue to refer to Figure 3E and Figure 4 , form sidewalls 207 on the sidewalls of each of the gates 206 through any suitable sidewall process.

[0064] (4), please continue to refer to Figure 3E and Figure 4 , use a source-drain ion implantation process to implant ions of the first conductivity type (for example, N-type) into the substrate 200 (i.e., the drift regions 200a and 200b) on both sides of each of the gates 206 to form source regions and drain regions. Optionally, a source region 200s is formed in the substrate 200 on one side of the gate 206 in the high-voltage region HV, and there is no shallow trench isolation structure STI separating the source region 200s and the gate 206. A drain region 200d is formed in the substrate 200 on the other side of the gate 206 in the high-voltage region HV, and there is a shallow trench isolation structure STI separating the drain region 200d and the gate 206. Thus, the drain region 200d and the source region 200s formed in the high-voltage region HV constitute an asymmetric structure.

[0065] Optionally, implant ions of the second conductivity type into the drift regions 200c and 200e to form body contact regions 200p on the outer sides of both the source region 200s and the drain region 200d. As an example, the source region 200s and the body contact region 200p near it are adjacent to each other, and the drain region 200d and the body contact region 200p near it are separated by a shallow trench isolation structure STI.

[0066] It should be understood that in this step, the original bird's beak region 203a in the high-voltage region HV is thinned or at least partially removed in the transverse direction. Therefore, when source-drain ion implantation is performed, the source-drain ion implantation will not be blocked due to the excessive thickness of the bird's beak region 203a in the longitudinal direction. As a result, the blocking loss of the source-drain ions implanted in the drift region 200 is relatively less than that in the prior art, and the implantation depth and implantation dose of the source-drain ions in the formed source region 200s can be ensured, avoiding the problem of device performance degradation caused by the performance reduction of the formed source region 200s.

[0067] (5), please refer to Figure 5 , a metal silicide 209 is formed on the tops of the gate 206, the source region, and the drain region by using a salicide process. For example, a silicide blocking layer 208 is first deposited and the silicide blocking layer 208 is etched through photolithography and etching processes to open the silicide blocking layer 208 on the tops of the gate 206, the source region, and the drain region, the etch protection layer 205, and the thermal oxide layer on the top of the source region 200s in the high-voltage region HV. Then, a metal such as cobalt is deposited, and two annealing processes are performed and the unreacted metal is removed to form the metal silicide 209. In this step, since the original bird's beak region 203a in the high-voltage region HV is thinned in the longitudinal direction or at least partially removed in the transverse direction, in the high-voltage region HV, when the metal silicide 209 is formed on the source region 200s, the problem that the area of the metal silicide 209 formed on the source region 200s is too small or relatively far from the gate 206 will not occur due to the excessive length of the bird's beak region 203a in the transverse direction. Thus, it can be ensured that the bottom of the subsequent formed contact plug 211s is in contact with a sufficient area of the metal silicide 209, thereby reducing the resistance at the source region 200s end and improving the performance of the high-voltage region transistor.

[0068] (6) First, deposit an interlayer dielectric layer 210 and perform contact hole etching to form contact holes (not shown) on the metal silicide on top of the gate 206, the source region, and the drain region. Then, fill the contact holes with metal through processes such as copper electroplating or tungsten deposition to form corresponding contact plugs on top of the gate 206, the source region, and the drain region. For example, form a contact plug 211g on top of the gate 206 in the high-voltage region HV, form a contact plug 211s on top of the source region 200s, and form a contact plug 211d on top of the drain region 200d. Since there is a large enough area of metal silicide 209 at the bottom of the contact plug 211d, its contact resistance is reduced. Additionally, since at least a partial region of the bird's beak region 203a of the high-voltage gate oxide layer 203 is removed in the lateral direction, the occupation of the contact region between the metal silicide formed on the silicon substrate can be reduced, that is, the lateral distance between the metal silicide 209 and the contact plug 211s on the source region 200s to the channel (i.e., the substrate 200 region near the remaining high-voltage gate oxide layer 203) is shortened, the resistance of the source region 200s is reduced, and the device performance is improved.

[0069] In the above embodiment, the hard mask layer 202 and the etch protection layer 201 are removed first in step S3, so that a medium-voltage gate oxide layer GOX can be formed on the high-voltage region HV, the medium-voltage region MV, and the low-voltage region LV at the same time. However, the technical solution of the present invention is not limited thereto.

[0070] In other embodiments of the present invention, in step S3, the high-voltage region HV can also be masked, and only the substrate surfaces of the medium-voltage region MV and the low-voltage region LV are exposed. Then, when forming a medium-voltage gate oxide layer on the substrate surfaces of the medium-voltage region MV and the low-voltage region LV at the same time, a medium-voltage gate oxide layer will not be formed on the substrate surface of the high-voltage region HV at the same time. The specific process is as follows:

[0071] Please refer to Figure 6A, a patterned photoresist layer 300 is formed through photolithography processes such as photoresist coating, exposure, and development. In one example, the patterned photoresist layer 300 not only covers the hard mask layer 202 and the high-pressure thermal oxide layer 203 in the high-voltage region HV outside the bird's beak region 203a, but also covers a part of the top of the hard mask layer 202 above the shallow trench isolation structure STI at the boundary between the low-voltage region LV and the medium-voltage region MV, and exposes the top of the hard mask layer 202 in other regions of the low-voltage region LV and the medium-voltage region MV, thereby defining the formation regions for the medium-voltage gate oxide layer on the medium-voltage region MV and the low-voltage region LV. In another example, the patterned photoresist layer 300 only covers the hard mask layer 202 and the high-pressure thermal oxide layer 203 in the high-voltage region HV outside the bird's beak region 203a, thereby exposing the hard mask layer 202 on the low-voltage region LV, the medium-voltage region MV, and the shallow trench isolation structure STI at the boundary between the low-voltage region LV and the medium-voltage region MV.

[0072] Next, please continue to refer to Figure 6A , using the patterned photoresist layer 300 as a mask, a dry etching process is used to simultaneously etch and open the hard mask layer 202 in the low-voltage region and the medium-voltage region until the surface of the substrate 200 in the low-voltage region LV and the medium-voltage region MV is exposed. Optionally, the exposed substrate 200 in the low-voltage region LV and the medium-voltage region MV is further etched to form a second trench (not shown), which is used to form the medium-voltage gate oxide layer in the subsequent process and is used to reduce the top surface height of the formed medium-voltage gate oxide layer, and the bottom depth of the second trench is shallower than the bottom depth of the first trench formed before forming the high-voltage gate oxide layer 203.

[0073] Then, please refer to Figure 6B , any suitable photoresist removal process such as a dry photoresist removal process or a wet photoresist removal process is used to remove the patterned photoresist layer 300, and any suitable second thermal oxidation process such as a high-temperature furnace tube oxidation process (the process time of which is shorter than the process time of the above-mentioned first thermal oxidation process) is used to thermally oxidize the exposed substrate 200 in the low-voltage region LV and the medium-voltage region MV. The exposed silicon of the substrate 200 in the low-voltage region LV and the medium-voltage region MV reacts with oxygen, thereby forming a medium-voltage gate oxide layer on the surfaces of the exposed substrates 200 in the low-voltage region LV and the medium-voltage region MV together. The silicon of the substrate 200 in other regions is blocked by the hard mask layer 202 and the high-voltage gate oxide layer 203 and will not react with oxygen. Among them, a medium-voltage gate oxide layer 204b is formed on the substrate 200 in the low-voltage region LV, and a medium-voltage gate oxide layer 204a is formed on the substrate 200 in the medium-voltage region MV.

[0074] Optionally, in step S4 of the above embodiment, please refer to Figure 6C, the hard mask layer 202 can be retained first, and photoresist is coated on the hard mask layer 202, the high-voltage gate oxide layer 203, and the medium-voltage gate oxide layers 204a and 204b. By means of a photomask for defining the gate oxide of the medium-voltage region MV, the coated photoresist is exposed, and the exposed photoresist is developed, etc., to form a patterned photoresist layer as the required patterned mask layer 301. The patterned mask layer 301 not only masks regions such as the medium-voltage gate oxide layer 204a in the medium-voltage region MV and the region of the high-voltage gate oxide layer 203 in the high-voltage region HV except for the bird's beak region 203a, but also exposes the surface of the medium-voltage gate oxide layer 204b on the low-voltage region LV and the hard mask layer 202 above the top of the bird's beak region 203a. In this step, compared with the prior art, the number of photomasks does not increase. It only modifies the pattern of the photomask. Specifically, a pattern (such as an opening) for opening the bird's beak region 203a is added to the photomask for defining the gate oxide of the medium-voltage region MV. Thus, in step S5, using the patterned mask layer 301 as a mask, the exposed medium-voltage gate oxide layer 204b on the low-voltage region LV and the exposed bird's beak region 203a on the high-voltage region HV are thinned (as shown in Figure 6D ), or removed (as shown in Figure 6E ) by any suitable wet etching process in one step. After that, the patterned mask layer 301, the hard mask layer 202, and the etch protection layer 201 are removed, and subsequent processes such as forming the low-voltage gate oxide layer, the gate and sidewall processes are carried out.

[0075] In summary, in the technical solution of the present invention, after forming the medium-voltage gate oxide layer covering at least the medium-voltage region and the low-voltage region and when forming the patterned mask layer for defining the medium-voltage gate oxide layer to be retained on the medium-voltage region, not only the mask layer on the medium-voltage gate oxide layer in the low-voltage region is opened, but also the mask layer on the bird's beak region of the high-voltage gate oxide layer in the high-voltage region is opened. Thus, while thinning or removing the medium-voltage gate oxide layer on the low-voltage region by using the wet etching process, the bird's beak region of the high-voltage gate oxide layer in the high-voltage region is thinned or removed at the same time. Therefore, on the one hand, it is possible to avoid increasing the additional photomask cost and process cost. On the other hand, it can improve the problem that the source-drain ions injected into the source region subsequently are blocked due to the excessive thickness of the bird's beak region, and avoid the problem of reducing the device performance due to the reduction of the ion doping dose in the source region of the high-voltage region. In addition, at least a part of the bird's beak region of the high-voltage gate oxide layer is removed in the horizontal direction, which can shorten the horizontal distance between the metal silicide and the contact plug on the source region and the channel subsequently, reduce the resistance of the source region, and improve the device performance.

[0076] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, it includes the following steps: providing a substrate, and forming a plurality of shallow trench isolation structures in the substrate to define a high-voltage region, a medium-voltage region, and a low-voltage region; masking the medium-voltage region and the low-voltage region and exposing the substrate surface of the high-voltage region, and forming a high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process, the high-voltage gate oxide layer having a bird's beak region; exposing at least the substrate surface of the low-voltage region and the medium-voltage region, and forming a medium-voltage gate oxide layer, the medium-voltage gate oxide layer covering at least the substrate surfaces of the medium-voltage region and the low-voltage region; forming a patterned mask layer, the patterned mask layer masking the medium-voltage gate oxide layer to be retained on the medium-voltage region, and exposing the medium-voltage gate oxide layer on the low-voltage region and the bird's beak region of the high-voltage gate oxide layer; using the patterned mask layer as a mask, and thinning or removing the medium-voltage gate oxide layer on the low-voltage region and the bird's beak region of the high-voltage gate oxide layer in one step by using a wet etching process.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, at the end of the wet etching process, the remaining medium-voltage gate oxide layer thinned on the low-voltage region serves as the low-voltage gate oxide layer with the required thickness for the low-voltage region; or, after removing the medium-voltage gate oxide layer on the low-voltage region by using the wet etching process and exposing the substrate surface of the low-voltage region, the manufacturing method further includes: removing the patterned mask layer, and forming a low-voltage gate oxide layer on the exposed substrate surface of the low-voltage region by using a third thermal oxidation process or a chemical vapor deposition process.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, the thicknesses of the low-voltage gate oxide layer, the medium-voltage gate oxide layer, and the high-voltage gate oxide layer increase in sequence.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, after removing the patterned mask layer and forming the low-voltage gate oxide layer, the manufacturing method further includes: forming a gate on the high-voltage gate oxide layer in the high-voltage region, the medium-voltage gate oxide layer in the medium-voltage region, and the low-voltage gate oxide layer in the low-voltage region; forming sidewalls on the sidewalls of the gate; forming a source region and a drain region in the substrate on both sides of the gate by using a source-drain ion implantation process; forming metal silicides on the tops of the gate, the source region, and the drain region by using a metal silicidation process; forming contact plugs on the metal silicides on the tops of the gate, the source region, and the drain region.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, the source region and the drain region in the high-voltage region are of an asymmetric structure.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, the drain region in the high-voltage region is spaced apart from the gate by the corresponding shallow trench isolation structure, and the gate continuously extends from the high-voltage gate oxide layer to the shallow trench isolation structure between the gate and the drain region.

7. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The source region and the drain region of the high-voltage region are of a first conduction type, and the manufacturing method further includes: before forming the high-voltage gate oxide layer, forming a well of a second conduction type in the high-voltage region, forming a drift region of the first conduction type on both sides of the high-voltage gate oxide layer in the well, and a drift region of the second conduction type outside the drift region, and, after forming the sidewall and before forming the metal silicide, forming a body contact region in the drift region of the second conduction type; wherein, the source region and the drain region of the high-voltage region are respectively formed in the drift regions of the first conduction type on both sides of the high-voltage gate oxide layer.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that the step of masking the medium-voltage region and the low-voltage region and exposing the substrate surface of the high-voltage region, and forming the high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process includes: depositing a hard mask layer on the substrate, and opening the hard mask layer of the high-voltage region by using photolithography and etching processes to expose the substrate surface of the high-voltage region; using the hard mask layer as a mask to etch the substrate to form a trench, or first forming a sacrificial oxide layer by using a thermal oxidation process and etching away the sacrificial oxide layer to form a trench; forming the high-voltage thermal oxide layer at the trench by using a first thermal oxidation process.

9. The manufacturing method of the semiconductor device according to claim 8, characterized in that after forming the high-voltage gate oxide layer, first masking the high-voltage region and exposing the substrate surfaces of the low-voltage region and the medium-voltage region, and forming a medium-voltage gate oxide layer on the medium-voltage region and the low-voltage region together by using a corresponding second thermal oxidation process or a vapor deposition process; wherein, before masking the high-voltage region, first removing the hard mask layer, or after thinning or removing the bird's beak regions of the medium-voltage gate oxide layer and the high-voltage gate oxide layer on the low-voltage region by using the wet etching process together, removing the hard mask layer.

10. The manufacturing method of the semiconductor device according to claim 8, characterized in that after forming the high-voltage gate oxide layer, removing the hard mask layer to expose the substrate surfaces of the low-voltage region and the medium-voltage region and the remaining surfaces of the high-voltage region, and forming the medium-voltage gate oxide layer on the high-voltage region, the bird's beak region, the medium-voltage region and the low-voltage region together by using a corresponding second thermal oxidation process or a vapor deposition process.

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