Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a substrate which at least comprises a first region and a second region; a first gate oxide layer and a first gate electrode layer are formed on the first region, a second gate oxide layer and a second gate electrode layer are formed on the second region, and the first gate oxide layer comprises a first part which is located on the outer side of the first gate electrode layer and has a first thickness; the second gate oxide layer comprises a second part which is located on the outer side of the second gate oxide layer and has a second thickness, and the first thickness is smaller than the second thickness; an oxidation process is performed, the first portion is thickened to a third thickness, the second portion is thickened to a fourth thickness, and the thickness difference between the third thickness and the fourth thickness is smaller than the thickness difference between the first thickness and the second thickness; forming a side wall material layer; and etching the side wall material layer to form a side wall. According to the scheme, the thickness difference between the first part and the second part can be reduced, so that a process window of an etching process for etching the side wall material layer to form the side wall is enlarged.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of integrated circuits, complementary metal-oxide-semiconductor (CMOS) chips integrate various devices with different voltages. For example, devices with breakdown voltages of 1.2V, 2.5V, and 5V are integrated in a CMOS chip. Among them, the breakdown voltage of the device is achieved by gate oxide layers with different thicknesses.

[0003] In a related-art CMOS chip integrating various devices with different voltages, during the process of etching to form the gate electrode layer, gate oxide layer residues with different thicknesses are formed outside the gate electrode layer. The thickness difference of the remaining gate oxide layers with different thicknesses will narrow the process window during subsequent etching to form sidewalls, easily resulting in incomplete etching or undercut, thereby affecting device performance.

[0004] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further elaborated in the Detailed Description section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, on the one hand, this application provides a manufacturing method of a semiconductor device, including:

[0007] Providing a substrate, the substrate including at least a first region and a second region;

[0008] Forming a first gate oxide layer and a first gate electrode layer covering part of the first gate oxide layer on the first region of the substrate, and forming a second gate oxide layer and a second gate electrode layer covering part of the second gate oxide layer on the second region of the substrate. Wherein, the first gate oxide layer includes a first part with a first thickness located outside the first gate electrode layer, the second gate oxide layer includes a second part with a second thickness located outside the second gate electrode layer, and the first thickness is less than the second thickness;

[0009] Perform an oxidation process to oxidize a portion of the substrate below the first portion to thicken the first portion to a third thickness and to oxidize a portion of the substrate below the second portion to thicken the second portion to a fourth thickness, wherein the thickness difference between the third thickness and the fourth thickness is less than the thickness difference between the first thickness and the second thickness;

[0010] Form a sidewall material layer covering the first gate electrode layer, the first portion, the second gate electrode layer, and the second portion;

[0011] Etch the sidewall material layer to form sidewalls on the sidewalls of the first gate electrode layer and the second gate electrode layer, respectively.

[0012] Exemplarily, forming a first gate oxide layer and a first gate electrode layer covering a portion of the first gate oxide layer on a first region of the substrate, and forming a second gate oxide layer and a second gate electrode layer covering a portion of the second gate oxide layer on a second region of the substrate, includes:

[0013] Form the first gate oxide layer on the first region of the substrate and form the second gate oxide layer on the second region of the substrate;

[0014] Form a gate material layer that covers the first gate oxide layer and the second gate oxide layer;

[0015] Form a patterned mask layer on the gate material layer;

[0016] In an etching apparatus, etch the gate material layer using the mask layer as a mask to form the first gate electrode layer and the second gate electrode layer, and continue to etch to remove a portion of the first gate oxide layer outside the first gate electrode layer and a portion of the second gate oxide layer outside the second gate electrode layer, wherein a first portion with the first thickness remains outside the first gate electrode layer and a second portion with the second thickness remains outside the second gate electrode layer.

[0017] Exemplarily, performing an oxidation process to oxidize a portion of the substrate below the first portion to thicken the first portion to a third thickness and to oxidize a portion of the substrate below the second portion to thicken the second portion to a fourth thickness, includes:

[0018] After the step of etching the gate material layer to form the first gate electrode layer and the second gate electrode layer and continuing to etch to remove a portion of the first gate oxide layer outside the first gate electrode layer and a portion of the second gate oxide layer outside the second gate electrode layer, introduce an oxygen-containing gas into the etching apparatus to perform the oxidation process.

[0019] Exemplarily, the oxidation process includes an ashing process or a furnace tube oxidation process.

[0020] Exemplarily, the method further includes:

[0021] In the step of etching away a part of the first gate oxide layer outside the first gate electrode layer and a part of the second gate oxide layer outside the second gate electrode layer, a part of the substrate is exposed, and a native oxide layer is formed on the exposed substrate.

[0022] Exemplarily, a wet etching process is used to etch the sidewall material layer to form the sidewalls on the sidewalls of the first gate electrode layer and the second gate electrode layer respectively.

[0023] Exemplarily, after forming the sidewalls, the method further includes a step of forming metal silicide on the tops of the first gate electrode layer and the second gate electrode layer.

[0024] Exemplarily, the sidewall includes a first oxide layer, a nitride layer, and a second oxide layer which are stacked.

[0025] On the other hand, the present application provides a semiconductor device, which is manufactured by using the above method.

[0026] On still another aspect, the present application provides an electronic device, which includes the above semiconductor device.

[0027] The semiconductor device, its manufacturing method, and the electronic device according to the embodiments of the present application perform an oxidation process to oxidize a part of the substrate under the first part to thicken the first part to a third thickness, and oxidize a part of the substrate under the second part to thicken the second part to a fourth thickness. The thickness difference between the third thickness and the fourth thickness is less than the thickness difference between the first thickness and the second thickness. That is, the thickness difference between the first part and the second part is reduced through the oxidation process, so that the process window of the etching process for etching the sidewall material layer to form the sidewalls can be increased, the occurrence of incomplete etching or undercut phenomenon is avoided, and the device performance is improved. Description of the Drawings

[0028] The following drawings of the present application are used as a part of the present application to understand the present application. The embodiments of the present application and their descriptions are shown in the drawings to explain the principles of the present application.

[0029] In the drawings:

[0030] Figure 1 A schematic topographic diagram showing undercut after etching to form sidewalls in the related art is shown;

[0031] Figure 2 A flowchart of a manufacturing method of a semiconductor device according to a specific embodiment of the present application is shown;

[0032] Figures 3A - 3F Shows a cross-sectional schematic diagram of a semiconductor device obtained by successively implementing a manufacturing method of a semiconductor device according to a specific embodiment of the present application;

[0033] Figures 4A - 4B Shows a cross-sectional schematic diagram of a semiconductor device obtained by successively implementing a manufacturing method of a semiconductor device according to another specific embodiment of the present application;

[0034] Figure 5 Shows a morphological schematic diagram of a semiconductor device according to a specific embodiment of the present application after performing an oxidation process.

[0035] Description of reference numerals:

[0036] 300 - Substrate, 301 - First gate oxide layer, 3011 - First part, 302 - Second gate oxide layer, 3021 - Second part, 303 - Gate material layer, 304 - Mask layer, 305 - First gate electrode layer, 306 - Second gate electrode layer, 307 - Native oxide layer, 308 - Sidewall material layer, 3081 - First oxide material layer, 3082 - Nitride material layer, 3083 - Second oxide material layer, 309 - Sidewall, 3091 - First oxide layer, 3092 - Nitride layer, 3093 - Second oxide layer, 310 - Metal silicide, 311 - Third gate oxide layer, 3111 - Third part, 312 - Third gate electrode layer. Detailed embodiments

[0037] Next, the present application will be described more completely with reference to the accompanying drawings, in which embodiments of the present application are shown. However, the present application can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present application.

[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present application should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It will also be understood that terms such as those defined in commonly used dictionaries should be understood as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] To fully understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present application. Preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0044] In a CMOS chip integrating multiple different-voltage devices in related technologies, generally, a gate material layer is first formed, and then the gate material layer is etched using a patterned photoresist layer as a mask to form a gate electrode layer, and the gate oxide layer outside the gate electrode layer is continuously etched away. However, in this process, a residue of the gate oxide layer is formed outside the gate electrode layer, and since the gate oxide layer thicknesses of different-voltage devices are different, the thicknesses of the residues of the gate oxide layer outside different gate electrode layers are also different.

[0045] When forming sidewalls subsequently, generally, a sidewall material layer is first deposited, and then an etching process (such as a wet etching process) is performed to etch the sidewall material layer to form sidewalls. The thickness difference of the remaining gate oxide layers with different thicknesses will cause the process window of the etching process for etching the sidewall material layer to form sidewalls to become narrower, which is likely to result in incomplete etching, or as Figure 1 shown, side etching is likely to occur, resulting in undercutting, thereby affecting device performance.

[0046] In the related art, optimization is generally carried out by adjusting the concentration of the acid and the etching time during the process of removing the gate oxide layer by wet etching. However, for the case where the thickness difference of the gate oxide layer is relatively large, the optimization space of the acid concentration and the etching time in the wet etching process is small. If the etching is too weak, it is likely that the gate oxide layer with a relatively thick thickness cannot be etched cleanly. If the etching is too strong, it will cause undercutting in the device where the gate oxide layer with a relatively thin thickness is located.

[0047] In view of the existence of the foregoing technical problems, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:

[0048] Step S1: Provide a substrate, where the substrate includes at least a first region and a second region;

[0049] Step S2: Form a first gate oxide layer and a first gate electrode layer covering part of the first gate oxide layer on the first region of the substrate, and form a second gate oxide layer and a second gate electrode layer covering part of the second gate oxide layer on the second region of the substrate. Wherein, the first gate oxide layer includes a first part with a first thickness located outside the first gate electrode layer, the second gate oxide layer includes a second part with a second thickness located outside the second gate electrode layer, and the first thickness is less than the second thickness;

[0050] Step S3: Perform an oxidation process to oxidize a part of the substrate under the first part to thicken the first part to a third thickness, and oxidize a part of the substrate under the second part to thicken the second part to a fourth thickness. Wherein, the thickness difference between the third thickness and the fourth thickness is less than the thickness difference between the first thickness and the second thickness;

[0051] Step S4: Form a sidewall material layer covering the first gate electrode layer, the first part, the second gate electrode layer, and the second part;

[0052] Step S5: Etch the sidewall material layer to form sidewalls on the sidewalls of the first gate electrode layer and the second gate electrode layer respectively.

[0053] In the method for manufacturing a semiconductor device according to the embodiment of the present application, an oxidation process is performed to oxidize a part of the substrate under the first part to thicken the first part to a third thickness, and oxidize a part of the substrate under the second part to thicken the second part to a fourth thickness. The thickness difference between the third thickness and the fourth thickness is less than the thickness difference between the first thickness and the second thickness. That is, the thickness difference between the first part and the second part is reduced through the oxidation process, so that the process window of the etching process for forming sidewalls by etching the sidewall material layer can be increased, the occurrence of the phenomena of unclean etching or undercutting is avoided, and the device performance is improved.

[0054] Embodiment 1

[0055] Next, refer to Figures 2 to 5A detailed description is given of the method for manufacturing the semiconductor device of the present application. Among them, Figure 2 FIG. shows a flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application. Figures 3A - 3F FIG. shows a cross-sectional schematic view of a semiconductor device obtained by successively implementing the method for manufacturing a semiconductor device according to a specific embodiment of the present application. Figures 4A - 4B FIG. shows a cross-sectional schematic view of a semiconductor device obtained by successively implementing the method for manufacturing a semiconductor device according to another specific embodiment of the present application. Figure 5 FIG. shows a schematic topographic view of a semiconductor device according to a specific embodiment of the present application after performing an oxidation process.

[0056] The semiconductor device may be any suitable device well known to those skilled in the art. In this embodiment, the technical solution of the present invention is mainly explained and illustrated by taking the semiconductor device as a CMOS device as an example.

[0057] Exemplarily, the method for manufacturing a semiconductor device according to an embodiment of the present application includes the following steps:

[0058] First, perform step S1. As Figure 3A shown, provide a substrate 300, and the substrate 300 includes at least a first region and a second region.

[0059] Specifically, as Figure 3A shown, the substrate 300 may include at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the substrate 300 may further include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 300 are described herein, any material that can be used as the substrate 300 falls within the spirit and scope of the present application.

[0060] In one example, the substrate 300 at least includes a first region and a second region. Among them, the first region is the region where the first gate oxide layer and the first gate electrode layer are subsequently formed, and the second region is the region where the second gate oxide layer and the second gate electrode layer are subsequently formed. Exemplarily, the substrate 300 may further include other regions other than the first region and the second region, and the present application does not limit this. Exemplarily, the first region and the second region are respectively used to form devices with different breakdown voltages. For example, the first region is used to form a device with a first breakdown voltage, and the second region is used to form a device with a second breakdown voltage. The first breakdown voltage is less than the second breakdown voltage. Among them, the higher the breakdown voltage, the higher the thickness of the gate oxide layer corresponding to the device under the gate electrode layer. The device may be a CMOS device or other suitable devices.

[0061] In one example, the substrate 300 may include a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Optionally, the semiconductor substrate and the epitaxial layer may have the same conduction type. Exemplarily, the semiconductor substrate and the epitaxial layer may have different doping concentrations. For example, the doping concentration of the epitaxial layer may be lower than that of the semiconductor substrate.

[0062] Next, step S2 is executed. As Figure 3B shown, a first gate oxide layer 301 and a first gate electrode layer 305 covering a part of the first gate oxide layer 301 are formed on the first region of the substrate 300, and a second gate oxide layer 302 and a second gate electrode layer 306 covering a part of the second gate oxide layer 302 are formed on the second region of the substrate 300. Among them, the first gate oxide layer 301 includes a first part 3011 with a first thickness located outside the first gate electrode layer 305, and the second gate oxide layer 302 includes a second part 3021 with a second thickness located outside the second gate electrode layer 306. The first thickness is less than the second thickness. Exemplarily, the materials of the first gate electrode layer 305 and the second gate electrode layer 306 include but are not limited to polysilicon; the materials of the first gate oxide layer 301 and the second gate oxide layer 302 include but are not limited to silicon oxide.

[0063] In one example, as Figures 3A to 3BAs shown, a first gate oxide layer 301 is formed on a first region of a substrate 300, and a first gate electrode layer 305 covering a part of the first gate oxide layer 301 is formed, and a second gate oxide layer 302 is formed on a second region of the substrate 300, and a second gate electrode layer 306 covering a part of the second gate oxide layer 302 is formed, including: forming the first gate oxide layer 301 on the first region of the substrate 300, and forming the second gate oxide layer 302 on the second region of the substrate 300; forming a gate material layer 303, the gate material layer 303 covering the first gate oxide layer 301 and the second gate oxide layer 302; forming a patterned mask layer 304 on the gate material layer 303; in an etching device, etching the gate material layer 303 using the mask layer 304 as a mask to form the first gate electrode layer 305 and the second gate electrode layer 306, and continuing to etch to remove a part of the first gate oxide layer 301 outside the first gate electrode layer 305 and a part of the second gate oxide layer 302 outside the second gate electrode layer 306, wherein, a first part 3011 with a first thickness remains outside the first gate electrode layer 305, and a second part 3021 with a second thickness remains outside the second gate electrode layer 306. Exemplarily, the mask layer 304 includes a photoresist layer.

[0064] In one example, after etching to form the first gate electrode layer 305 and the second gate electrode layer 306, over-etching is continued to remove the first gate oxide layer 301 outside the first gate electrode layer 305 and the second gate oxide layer 302 outside the second gate electrode layer 306. Due to the influence of the loading effect, a part of the first gate oxide layer 301 remains outside the first gate electrode layer 305, and a part of the second gate oxide layer 302 remains outside the second gate electrode layer 306, that is, a first part 3011 with a first thickness and a second part 3021 with a second thickness remain.

[0065] In one example, various processes commonly used in the art can be employed to form the first gate oxide layer 301, the second gate oxide layer 302, and the gate material layer 303. For example, the first gate oxide layer 301 and the second gate oxide layer 302 can be formed by thermal oxidation or chemical vapor deposition (CVD) methods, etc., and the first gate oxide layer 301, the second gate oxide layer 302, and the gate material layer 303 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) methods, etc. Exemplarily, etching processes commonly used in the art can be used to etch the first gate oxide layer 301, the second gate oxide layer 302, and the gate material layer 303, such as dry etching processes or wet etching processes, etc.

[0066] In one example, as Figure 3BAs shown, in the step of etching away a part of the first gate oxide layer 301 outside the first gate electrode layer 305 and a part of the second gate oxide layer 302 outside the second gate electrode layer 306, a part of the substrate 300 is exposed. A native oxide layer 307 is formed on the exposed substrate 300, where the native oxide layer 307 is formed by oxidizing the exposed substrate 300. Or, in some other examples, a part of the substrate 300 may be exposed without forming a native oxide layer 307.

[0067] Next, step S3 is executed. As Figure 3C , an oxidation process is performed to oxidize a part of the substrate 300 under the first part 3011 to thicken the first part 3011 to a third thickness, and to oxidize a part of the substrate 300 under the second part 3021 to thicken the second part 3021 to a fourth thickness, where the thickness difference between the third thickness and the fourth thickness is less than the thickness difference between the first thickness and the second thickness.

[0068] In one example, the oxidation rate of the substrate 300 decreases as the thickness of the gate oxide layer on the substrate 300 increases. The first part 3011 has a first thickness, the second part 3021 has a second thickness, and the first thickness is less than the second thickness. Therefore, the oxidation rate of the substrate 300 under the first part 3011 is greater than the oxidation rate under the second part 3021. That is, in the oxidation process, the thickness increase of the first part 3011 is greater than the thickness increase of the second part 3021, so that the thickness difference between the thickened first part 3011 with the third thickness and the thickened second part 3021 with the fourth thickness is less than the thickness difference between the first part 3011 with the first thickness and the second part 3021 with the second thickness before thickening. Exemplarily, the oxidation process can reduce the thickness difference between the first part 3011 and the second part 3021, thereby increasing the process window of the etching process for forming sidewalls by etching the sidewall material layer and improving the device performance. Exemplarily, in the oxidation process, a part of the substrate 300 under the native oxide layer 307 is also oxidized.

[0069] In one example, taking the device with the first gate oxide layer 301 corresponding to a breakdown voltage of 1.2V and the second gate oxide layer 302 corresponding to a breakdown voltage of 2.5V as an example, the first thickness is 20.3 Å, the second thickness is 50 Å, and the thickness difference between the first thickness and the second thickness is 29.7 Å; after performing the oxidation process, the third thickness is 46 Å, the fourth thickness is 52 Å, and the thickness difference between the third thickness and the fourth thickness is 2 Å, that is, the oxidation process can significantly reduce the thickness difference between the first part 3011 and the second part 3021.

[0070] In one example, an oxidation process is performed to oxidize a partial substrate 300 below a first portion 3011 to thicken the first portion 3011 to a third thickness and to oxidize a partial substrate 300 below a second portion 3021 to thicken the second portion 3021 to a fourth thickness, including: after etching a gate material layer 303 to form a first gate electrode layer 305 and a second gate electrode layer 306 and continuing to etch away a partial first gate oxide layer 301 outside the first gate electrode layer 305 and a partial second gate oxide layer 302 outside the second gate electrode layer 306, introducing an oxygen-containing gas into the etching equipment to perform the oxidation process. Exemplarily, by introducing an oxygen-containing gas into the etching equipment to perform the oxidation process, there is no need to use additional equipment for performing the oxidation process, which simplifies the process and reduces costs. Exemplarily, the oxidation process can also use an ashing process or a furnace tube oxidation process. Among them, the ashing process is generally used to remove a photoresist layer. For example, the mask layer 304 in the present application can be removed by the ashing process; in the ashing process, a gas (usually oxygen) is generally excited by radio frequency (RF) power to generate a plasma. The plasma is an ionized gas state composed of ions, electrons, and neutral active particles (such as free radicals). Among them, oxygen radicals have strong oxidizing properties and can be used to oxidize the partial substrate 300 below the first portion 3011 and the partial substrate 300 below the second portion 3021.

[0071] Next, step S4 is performed, as Figure 3D shown, to form a sidewall material layer 308 covering the first gate electrode layer 305, the first portion 3011, the second gate electrode layer 306, and the second portion 3021. Exemplarily, a deposition process commonly used in the art can be used to form the sidewall material layer 308. For example, the sidewall material layer 308 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0072] Next, step S5 is performed, as Figure 3E shown, to etch the sidewall material layer 308 to form sidewalls 309 on the sidewalls of the first gate electrode layer 305 and the second gate electrode layer 306 respectively. Exemplarily, a wet etching process is used to etch the sidewall material layer 308 to form sidewalls 309 on the sidewalls of the first gate electrode layer 305 and the second gate electrode layer 306 respectively. Since the thickness difference between the first portion 3011 and the second portion 3021 is reduced by the oxidation process in the foregoing steps, the process window of the etching process for etching the sidewall material layer 308 to form the sidewalls 309 is increased, avoiding the occurrence of incomplete etching or undercutting phenomena, thereby improving the device performance.

[0073] In one example, as Figure 3EAs shown, the sidewall 309 includes a first oxide layer 3091, a nitride layer 3092, and a second oxide layer 3093 that are stacked. Exemplarily, the materials of the first oxide layer 3091 and the second oxide layer 3093 include silicon oxide, and the material of the nitride layer 3092 includes silicon nitride; silicon nitride has a larger dielectric constant and better isolation effect, while the silicon oxides on both sides of the silicon nitride can be used to relieve the stress effect of the silicon nitride. Exemplarily, when the sidewall 309 includes the first oxide layer 3091, the nitride layer 3092, and the second oxide layer 3093 that are stacked, the sidewall material layer 308 correspondingly includes a first oxide material layer 3081, a nitride material layer 3082, and a second oxide material layer 3083 that are stacked. In the process of etching the sidewall material layer 308 to obtain the sidewall 309, etching the first oxide material layer 3081 obtains the first oxide layer 3091, etching the nitride material layer 3082 obtains the nitride layer 3092, and etching the second oxide material layer 3083 obtains the second oxide layer 3093. Exemplarily, the sidewall 309 can also be a single-layer, double-layer, or more than three-layer structure, and the present application does not limit this.

[0074] In one example, after forming the sidewall 309, it further includes the step of forming a metal silicide 310 on the top of the first gate electrode layer 305 and the top of the second gate electrode layer 306. Specifically, the metal silicide 310 can be formed by a self-aligned process: depositing a metal silicide blocking layer to define the range of the subsequently formed metal silicide. For example, a metal silicide blocking layer is formed in an area where metal silicide is not desired to form to prevent the formation of metal silicide in this area. When removing part of the metal silicide blocking layer by etching, if the thickness difference of the remaining gate oxide layer under the sidewall or outside the sidewall is large, then when removing the metal silicide blocking layer outside the sidewall, if the etching time is too long, it is easy to cause undercut of the sidewall, and if the etching duration is short, it is easy to cause residue of the remaining thicker gate oxide layer, which affects the formation of the subsequent metal silicide. However, through the solution of the present application, since the thickness difference of the gate oxide layer in different regions is small, it is easier to simultaneously remove part of the metal silicide blocking layer during etching without causing undercut; depositing a metal layer covering the first gate electrode layer 305 and the second gate electrode layer 306, where the material of the metal layer includes but is not limited to, such as titanium, nickel, etc.; then, performing a first annealing to cause the metal layer to react with the first gate electrode layer 305 and the second gate electrode layer 306 to form a high-resistance phase silicide; removing the unreacted metal layer; performing a second annealing to cause the high-resistance phase silicide to undergo a phase transformation to obtain a low-resistance phase silicide, that is, obtaining the metal silicide 310.

[0075] In one example, the substrate 300 may further include other regions in addition to the first region and the second region, and other regions may also be formed with gate oxide layers of other thicknesses. For example, as Figure 4A shown, the substrate 300 includes a first region, a second region, and a third region. A third gate oxide layer 311 and a third gate electrode layer 312 covering a part of the third gate oxide layer 311 are formed on the third region of the substrate 300. Among them, the third gate oxide layer 311 includes a third part 3111 with a fifth thickness located outside the third gate electrode layer 312, and the fifth thickness is greater than the second thickness.

[0076] In one example, as Figure 4B shown, during the oxidation process, a part of the substrate 300 below the third part 3111 is also oxidized to thicken the third part 3111 to a sixth thickness. The thickness differences among the third thickness, the fourth thickness, and the sixth thickness are smaller than the thickness differences among the first thickness, the second thickness, and the fifth thickness. Among them, since the fifth thickness is greater than the second thickness, the thickness by which the third part 3111 thickens during the oxidation process is also smaller than the thickness by which the second part 3021 thickens.

[0077] In one example, taking the device with a breakdown voltage of 1.25V corresponding to the first gate oxide layer 301, the device with a breakdown voltage of 2.5V corresponding to the second gate oxide layer 302, and the device with a breakdown voltage of 5V corresponding to the third gate oxide layer 311 as an example, as Figure 5 shown, after the oxidation process is performed, the third thickness, the fourth thickness, and the sixth thickness are 4.11nm, 4.11nm, and 4.36nm respectively, and the thickness differences between the first part 3011, the second part 3021, and the third part 3111 are significantly reduced.

[0078] So far, the description of the key steps of the manufacturing method of the semiconductor device of the present application has been completed. For the complete manufacturing of the semiconductor device, other steps may also be included, which will not be elaborated one by one here. It is worth mentioning that the above step sequence can be adjusted on the premise of no conflict.

[0079] In summary, for the manufacturing method of the semiconductor device according to the embodiment of the present application, an oxidation process is performed to oxidize a part of the substrate below the first part to thicken the first part to the third thickness, and to oxidize a part of the substrate below the second part to thicken the second part to the fourth thickness. The thickness difference between the third thickness and the fourth thickness is smaller than the thickness difference between the first thickness and the second thickness, that is, the thickness difference between the first part and the second part is reduced through the oxidation process, thereby enabling the process window of the etching process for forming the sidewall of the etched sidewall material layer to be increased, avoiding the occurrence of incomplete etching or undercutting phenomena, and improving the device performance.

[0080] Embodiment 2

[0081] The present application also provides a semiconductor device, which is manufactured by the method in the first embodiment above. Since the device of the present application is manufactured by the foregoing method, it has the same advantages as the foregoing method.

[0082] The semiconductor device of the present application can be any suitable device well-known to those skilled in the art. In this embodiment, the technical solution of the present application will be mainly explained and described by taking the case where the semiconductor device is a CMOS device as an example.

[0083] The semiconductor device of the embodiment of the present application is manufactured by the above method and performs an oxidation process to oxidize a part of the substrate under the first part to thicken the first part to a third thickness and oxidize a part of the substrate under the second part to thicken the second part to a fourth thickness. The thickness difference between the third thickness and the fourth thickness is smaller than the thickness difference between the first thickness and the second thickness. That is, the thickness difference between the first part and the second part is reduced through the oxidation process, so that the process window of the etching process for forming sidewalls by etching the sidewall material layer can be increased, the occurrence of incomplete etching or undercutting is avoided, and the device performance is improved.

[0084] Embodiment 3

[0085] Another embodiment of the present application also provides an electronic device, which includes the foregoing semiconductor device.

[0086] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or can also be any intermediate product including the foregoing semiconductor device. The electronic device of the embodiment of the present application has better performance because it uses the above semiconductor device.

[0087] Although multiple embodiments are described herein, it should be understood that those skilled in the art can conceive of various other modifications and embodiments, and they will all fall within the spirit and scope of the concept disclosed in the present application. More particularly, various modifications and changes can be made in the arrangement and / or components of the combination of the subject matter within the scope of the present application, the accompanying drawings, and the appended claims. In addition to the modifications and changes in the components and / or arrangement, the use of alternative methods is also an obvious choice for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a substrate, the substrate comprising at least a first region and a second region; Forming a first gate oxide layer and a first gate electrode layer covering a portion of the first gate oxide layer on a first region of the substrate, and forming a second gate oxide layer and a second gate electrode layer covering a portion of the second gate oxide layer on a second region of the substrate, wherein the first gate oxide layer includes a first portion having a first thickness located outside the first gate electrode layer, and the second gate oxide layer includes a second portion having a second thickness located outside the second gate oxide layer, and the first thickness is less than the second thickness; performing an oxidation process to oxidize a portion of the substrate below the first portion to thicken the first portion to a third thickness, and to oxidize a portion of the substrate below the second portion to thicken the second portion to a fourth thickness, wherein a thickness difference between the third thickness and the fourth thickness is smaller than a thickness difference between the first thickness and the second thickness; forming a spacer material layer covering the first gate electrode layer, the first portion, the second gate electrode layer and the second portion; The spacer material layer is etched to form spacers on the sidewalls of the first gate electrode layer and the sidewalls of the second gate electrode layer respectively.

2. The manufacturing method according to claim 1, characterized in that: Forming a first gate oxide layer and a first gate electrode layer covering a portion of the first gate oxide layer on a first region of the substrate, and forming a second gate oxide layer and a second gate electrode layer covering a portion of the second gate oxide layer on a second region of the substrate, comprising: forming the first gate oxide layer on the first region of the substrate, and forming the second gate oxide layer on the second region of the substrate; forming a gate material layer, wherein the gate material layer covers the first gate oxide layer and the second gate oxide layer; forming a patterned mask layer on the gate material layer; In the etching equipment, the gate material layer is etched with the mask layer as a mask to form the first gate electrode layer and the second gate electrode layer, and etching is continued to remove a portion of the first gate oxide layer outside the first gate electrode layer and a portion of the second gate oxide layer outside the second gate electrode layer, wherein the first portion of the first thickness remains outside the first gate electrode layer and the second portion of the second thickness remains outside the second gate electrode layer.

3. The manufacturing method according to claim 2, characterized in that: Performing an oxidation process to oxidize a portion of the substrate below the first portion to thicken the first portion to a third thickness, and oxidize a portion of the substrate below the second portion to thicken the second portion to a fourth thickness, comprising: After etching the gate material layer to form the first gate electrode layer and the second gate electrode layer, and continuing to etch and remove a portion of the first gate oxide layer outside the first gate electrode layer and a portion of the second gate oxide layer outside the second gate electrode layer, oxygen-containing gas is introduced into the etching equipment to perform the oxidation process.

4. The manufacturing method according to claim 1, characterized in that: The oxidation process includes an ashing process or a furnace tube oxidation process.

5. The manufacturing method according to claim 2, characterized in that: The method further comprises: In the step of etching and removing a portion of the first gate oxide layer outside the first gate electrode layer and a portion of the second gate oxide layer outside the second gate electrode layer, a portion of the substrate is exposed, and a natural oxide layer is formed on the exposed substrate.

6. The manufacturing method according to claim 1, characterized in that: The spacer material layer is etched by a wet etching process to form the spacers on the sidewalls of the first gate electrode layer and the sidewalls of the second gate electrode layer respectively.

7. The manufacturing method according to claim 1, characterized in that: After forming the sidewall spacer, the method further includes forming metal silicide on the top of the first gate electrode layer and the top of the second gate electrode layer.

8. The manufacturing method according to claim 1, characterized in that: The sidewall spacer includes a first oxide layer, a nitride layer and a second oxide layer which are stacked.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes the semiconductor device according to claim 9.

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