Driving substrate and manufacturing method thereof, display panel and display device

Abstract

The application provides a driving substrate, a manufacturing method thereof, a display panel and a display device. The driving substrate comprises a first insulating layer, a trace, a second insulating layer, a planar layer, a first electrode and a second electrode. The planar layer is provided with a first via, the second insulating layer is provided with a second via, the second via is communicated with the first via, the trace is exposed to the second via, part of the first electrode is arranged in the first via and the second via, and the first electrode is connected with the trace. The second electrode comprises an electrode body and a plurality of sub-electrodes, two adjacent sub-electrodes are arranged at intervals to form a gap, the sub-electrodes and part of the electrode body are located in the first via, part of the first electrode is located in the gap, and the first electrode is connected with the electrode body and the plurality of sub-electrodes respectively. Therefore, the application forms a plurality of gaps for the second electrode at the opening of the second via, so that the first electrode can be deposited in the gap, and the first electrode will not have a breakpoint at the opening of the second via.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving substrate, a method for manufacturing a driving substrate, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, touch display panels have been widely accepted and used, such as in smartphones and tablets. Touch display panels typically employ embedded touch technology to combine the touch panel and the LCD panel into one unit, embedding the touch panel functionality into the LCD panel, thus enabling the LCD panel to simultaneously display and sense touch input.

[0003] Currently, to further simplify the structure of touch display panels, a common electrode used to generate the electric field and a touch electrode used to implement touch functionality are connected via traces, allowing the common electrode and touch electrode to perform their respective functions at different times. Since the traces are not on the same layer as the common electrode and touch electrode, the common electrode and touch electrode need to extend into a half-aperture above the trace, allowing them to overlap with the trace. However, the special structure of the half-aperture can easily lead to disconnections between the touch electrode and the common electrode.

[0004] Therefore, how to solve the problem that the touch electrodes and common electrodes of the existing touch display panel are prone to disconnection within the half-hole is an urgent problem for those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a driving substrate, a method for manufacturing a driving substrate, a display panel, and a display device, which aims to solve the problem in the prior art that the touch electrodes and common electrodes of the touch display panel are prone to disconnection in the half-hole.

[0006] In a first aspect, embodiments of this application provide a driving substrate, which includes a plurality of touch areas arranged in an array. The driving substrate further includes a first insulating layer, a plurality of traces, a second insulating layer, a planarization layer, a plurality of first electrodes, and a plurality of second electrodes. The second insulating layer covers the plurality of traces to the first insulating layer, and the planarization layer is disposed on the surface of the second insulating layer opposite to the first insulating layer. The planarization layer has a plurality of first vias, and the second insulating layer has a plurality of second vias, with one second via communicating with one first via. A portion of the traces is exposed within the second vias, and a portion of the first electrodes is disposed within the first and second vias, and the first electrodes are connected to the traces. One second electrode is located in one of the touch areas, and the second electrode includes an electrode body and a plurality of sub-electrodes. The plurality of sub-electrodes are connected to one side of the electrode body, and adjacent sub-electrodes are spaced apart to form at least one gap. The sub-electrodes and a portion of the electrode body are located within the first vias, a portion of the first electrode is located within the gap, and the first electrode is connected to both the electrode body and the plurality of sub-electrodes, such that the second electrode is electrically connected to the traces. The first electrode is used to send touch signals through the trace, and the second electrode is used to receive display signals through the trace.

[0007] In the prior art, the special structure of the semi-drilled via can easily lead to a break in the connection between the touch electrode and the common electrode. The driving substrate provided in this application forms multiple gaps at the opening of the second via with the second electrode, allowing the first electrode to be deposited within the gaps, thus preventing a break in the first electrode at the opening of the second via.

[0008] In an exemplary embodiment, the width of the gap is the distance between two adjacent sub-electrodes, ranging from 1µm to 3µm.

[0009] In an exemplary embodiment, the length of the gap, or the length of the sub-electrode, is 2µm to 4µm.

[0010] In an exemplary embodiment, the electrode body includes at least one connecting surface facing the gap, the connecting surface being connected to the sub-electrode respectively, the connecting surface being an inclined surface, and the connecting surface facing the first through hole.

[0011] In an exemplary embodiment, the first via includes a first sidewall and a bottom wall, the first sidewall being connected to the bottom wall. The second via includes a second sidewall, the second sidewall being connected to both the first sidewall and the bottom wall. A plurality of sub-electrodes are disposed on the bottom wall, a portion of the electrode body is disposed on the first sidewall, and a portion of the first electrode is disposed on the second sidewall.

[0012] In an exemplary embodiment, the inclination angle of the connecting surface relative to the bottom wall is 50 to 80 degrees.

[0013] In an exemplary embodiment, the driving substrate further includes a third insulating layer disposed on the first sidewall, the second sidewall, the surface of the second electrode facing away from the planarization layer, and the surface of the planarization layer facing away from the second insulating layer.

[0014] Secondly, embodiments of this application also provide a method for fabricating a driving substrate. The method for fabricating the driving substrate includes: sequentially forming a trace, a second insulating layer, and a planarization layer on a first insulating layer; the second insulating layer covering the trace to a surface of the first insulating layer; and the planarization layer located on the surface of the second insulating layer opposite to the first insulating layer. A first via is formed in the planarization layer, and a second via is formed in the second insulating layer. The first via communicates with the second via, and a portion of the trace is exposed in the second via. A second electrode is formed within the first via and on the surface of the planarization layer opposite to the second insulating layer. A third insulating layer is formed within the first via and the second via, wherein a portion of the trace's surface opposite to the first insulating layer is exposed in the third insulating layer. A first electrode is formed within the first via and the second via, and the first electrode is connected to the second electrode and the trace, respectively.

[0015] Thirdly, embodiments of this application also provide a display panel, the display panel including a touch unit and the aforementioned driving substrate, each first electrode of the driving substrate being electrically connected to the touch unit, the first electrode being used to send touch signals to the touch unit through wiring.

[0016] In summary, the display panel provided in this application embodiment includes a touch unit and a driving substrate. The driving substrate forms multiple gaps at the opening of the second via with the second electrode, so that the first electrode can be deposited in the gaps and the first electrode will not have a break at the opening of the second via.

[0017] Fourthly, embodiments of this application also provide a display device, which includes a power board and the aforementioned display panel. The power board is electrically connected to the display panel and is used to supply power to the display panel.

[0018] In summary, the display device provided in this application includes a power board and a display panel. The display panel includes a touch unit and a driving substrate. The driving substrate forms multiple gaps at the opening of the second via with the second electrode, so that the first electrode can be deposited in the gaps and the first electrode will not have a break at the opening of the second via. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the layer structure of the display device disclosed in the first embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the layer structure of the display panel disclosed in the second embodiment of this application;

[0022] Figure 3 This is a schematic diagram showing the distribution of the touch area on the driving substrate disclosed in the third embodiment of this application;

[0023] Figure 4 This is a schematic diagram showing the distribution of the first electrode of the driving substrate disclosed in the third embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the layer structure of the driving substrate disclosed in this embodiment;

[0025] Figure 6 for Figure 5 A schematic diagram of the first structure of the second electrode is shown;

[0026] Figure 7 This is a schematic diagram of the layer structure of a driving substrate in the prior art;

[0027] Figure 8 for Figure 5 The diagram shows a second structural representation of the second electrode.

[0028] Figure 9 for Figure 5 A schematic diagram of a specific structure of the driving substrate shown;

[0029] Figure 10 This is a schematic flowchart of the method for manufacturing the driving substrate disclosed in the fourth embodiment of this application;

[0030] Figure 11 for Figure 10 The schematic diagram of the structure formed corresponding to step S10 shown;

[0031] Figure 12 for Figure 10 The schematic diagram of the structure formed corresponding to step S20 shown;

[0032] Figure 13 for Figure 10 The schematic diagram of the structure formed corresponding to step S30 is shown below;

[0033] Figure 14 for Figure 10 The schematic diagram of the structure formed corresponding to step S40 shown;

[0034] Figure 15 for Figure 10 A schematic diagram illustrating a specific process for fabricating the driving substrate;

[0035] Figure 16 for Figure 15 The schematic diagram of the structure formed corresponding to step S110 shown;

[0036] Figure 17 for Figure 15 The schematic diagram of the structure formed corresponding to step S120 is shown below;

[0037] Figure 18 for Figure 15 The schematic diagram of the structure formed corresponding to step S130 is shown below;

[0038] Figure 19 for Figure 15 The schematic diagram of the structure formed corresponding to step S140 is shown.

[0039] Explanation of reference numerals in the attached figures:

[0040] 1-Display device; 10-Display panel; 11-Driver substrate; 12-Liquid crystal layer; 13-Color filter substrate; 15-Touch unit; 30-Backlight module; 111-Substrate; 112-First insulating layer; 113-Trace; 114-Second insulating layer; 114a-Second via; 114b-Third via; 115-Planing layer; 115a-First via; 115b-Fourth via; 116-Third insulating layer; 117-First electrode; 118-Second electrode; 121-Connecting electrode; 122-Transistor; 123-Third electrode; 141-Side surface; 142-First conductive layer; 143 - Second conductive layer; 144-Wire; 145-Bottom surface; 1181-Electrode body; 1181a-Connection surface; 1182-Sub-electrode; 1183-Gap; T-Touch area; P-Sub-pixel area; a1-First sidewall; a2-Bottom wall; a3-Second sidewall; a11-First sub-sidewall; a12-Second sub-sidewall; a31-Third sub-sidewall; a32-Fourth sub-sidewall; b1-Gate; b2-Active layer; b3-Source; b4-Drain; Step S10-Step S50-Steps of the method for fabricating the driving substrate; Step S110-Step S150-Steps of the method for fabricating the driving substrate. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0042] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0043] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding disclosed function, operation, element, etc., and do not limit one or more other functions, operations, elements, etc. Moreover, the terms "comprising" or "include" indicate the presence of the corresponding features, number, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, number, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. It is also important to understand that “at least one” as described in this article means one or more, such as one, two or three, while “multiple” means at least two, such as two or three, unless otherwise explicitly specified.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0045] Please see Figure 1 , Figure 1 This is a schematic diagram of the layer structure of the display device disclosed in the first embodiment of this application. The display device 1 can be used in electronic devices including but not limited to televisions, smartphones, tablets, laptops, desktop computers, mobile phones, and in-vehicle displays. According to the embodiments of this application, the specific type of the display device 1 is not particularly limited, and those skilled in the art can design it accordingly based on the specific usage requirements of the display device 1, which will not be elaborated here.

[0046] The display device 1 includes a display panel 10 and a backlight module 30 stacked together. The display panel 10 is disposed on the light-emitting side of the backlight module 30. The backlight module 30 is used to provide backlight, and the display panel 10 is used to display images under the backlight provided by the backlight module 30.

[0047] In the embodiments of this application, Figure 1The backlight module 30 shown can be an edge-lit backlight module, or it can be a direct-lit backlight module. The display panel 10 can be a twisted nematic (TN) display panel, a vertical alignment (VA) display panel, an in-plane switching (IPS) display panel, or a fringe field switching (FFS) display panel; this application does not impose specific limitations on this.

[0048] In an exemplary embodiment, the display device 1 may also include other necessary components and parts such as a driver board, a power board, a high-voltage board, and a button control board. Those skilled in the art can make corresponding additions according to the specific type and actual function of the display device 1, which will not be elaborated here.

[0049] In some embodiments, the display device 1 may further include a processor and a memory. The processor is electrically connected to the display panel 10 and is used to control the display panel 10 to display content. The memory is electrically connected to the processor and is used to store program code required for the processor to run, control the display content of the display panel 10, etc.

[0050] In an exemplary embodiment, the memory may include volatile memory, such as random access memory (RAM); the memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory (FM), hard disk drive (HDD), or solid-state drive (SSD). The memory may also include combinations of the above types of memory.

[0051] In an exemplary embodiment, the processor includes one or more general-purpose processors, wherein the general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (CPU), microprocessor, microcontroller, main processor, and controller, etc. The processor is used to execute various types of digital storage instructions, such as software or firmware programs stored in memory, which enable the computing device to provide a wide range of services.

[0052] Please see Figure 2 , Figure 2This is a schematic diagram of the layer structure of the display panel disclosed in the second embodiment of this application. The display panel 10 includes a driving substrate 11, a liquid crystal layer 12, and a color filter substrate 13. The driving substrate 11 and the color filter substrate 13 are disposed opposite to each other and spaced apart. The driving substrate 11 is used to form a preset electric field, which is used to drive the liquid crystal molecules of the liquid crystal layer 12 to deflect, thereby changing the transmittance of the liquid crystal layer 12. The driving substrate 11 is also the array substrate of the liquid crystal display panel.

[0053] It should be noted that the driving substrate 11 of this application can also be applied to organic light-emitting diode (OLED) display panels, mini light-emitting diode (Mini LED) display panels and micro light-emitting diode (Micro LED) display panels, and this application does not impose any specific limitations on this.

[0054] Please see Figure 3 , Figure 3 This is a schematic diagram showing the distribution of the touch area on the driving substrate disclosed in the third embodiment of this application. For ease of description, the following definitions are used. Figure 3 The length direction of the driving substrate 11 is the X-axis direction, the width direction of the driving substrate 11 is the Y-axis direction, and the thickness direction of the driving substrate 11 is the Z-axis direction. The X-axis, Y-axis and Z-axis directions are perpendicular to each other.

[0055] Specifically, the driving substrate 11 includes multiple touch areas T and multiple sub-pixel areas P. The multiple touch areas T are arranged in multiple rows along the X-axis and multiple columns along the Y-axis, i.e., the multiple touch areas T are arranged in a multi-row, multi-column array. Each touch area T contains multiple sub-pixel areas P. Within a single touch area T, the multiple sub-pixel areas P are arranged in multiple rows along the X-axis and multiple columns along the Y-axis, i.e., the multiple sub-pixel areas P are arranged in a multi-row, multi-column array. The sub-pixel areas P are used to display images, and the touch areas T are used to implement touch functionality.

[0056] Please refer to the following: Figure 3 and Figure 4 , Figure 4This is a schematic diagram showing the distribution of the first electrodes of the driving substrate disclosed in the third embodiment of this application. The driving substrate 11 further includes a plurality of first electrodes 117 and a plurality of traces 113. The plurality of first electrodes 117 are distributed in multiple rows along the X-axis direction and in multiple columns along the Y-axis direction, that is, the plurality of first electrodes 117 are distributed in a multi-row, multi-column array. One first electrode 117 is disposed within a sub-pixel region P. One trace 113 is electrically connected to one first electrode 117. The display panel 10 further includes a touch unit 15. Each trace 113 is electrically connected to the touch unit 15, and each first electrode 117 is electrically connected to the touch unit 15 through a corresponding trace 113. The first electrode 117 is used to send a touch signal to the touch unit 15 through the trace 113, and the touch unit 15 is used to determine the touch position based on the touch signal.

[0057] Please see Figure 5 , Figure 5 This is a schematic diagram of the layer structure of the driving substrate disclosed in this embodiment. The driving substrate 11 further includes a substrate 111, a first insulating layer 112, a second insulating layer 114, a planarization layer 115, a third insulating layer 116, and a plurality of second electrodes 118. For ease of illustration and description, Figure 5 Only one first electrode 117 and one second electrode 118 are shown.

[0058] In this embodiment, the first insulating layer 112 is disposed on the surface of the substrate 111 facing the Z-axis direction, that is, the first insulating layer 112 is disposed on one side of the substrate 111. The trace 113 and the second insulating layer 114 are both disposed on the surface of the first insulating layer 112 facing away from the substrate 111. The second insulating layer 114 also covers the peripheral side surface of the trace 113 and a portion of the surface of the trace 113 facing away from the first insulating layer 112. In other words, the second insulating layer 114 covers the trace 113 to the surface of the first insulating layer 112 facing away from the substrate 111, meaning that the orthographic projection of the trace 113 on the substrate 111 partially coincides with the orthographic projection of the second insulating layer 114 on the substrate 111.

[0059] The planarization layer 115 is disposed on the surface of the second insulating layer 114 opposite to the first insulating layer 112. The planarization layer 115 has a first via 115a extending along the Z-axis through the planarization layer 115, and the second insulating layer 114 has a second via 114a extending along the Z-axis through the second insulating layer 114, and the second via 114a communicates with the first via 115a. That is, the bottom wall of the first via 115a has the second via 114a. A portion of the trace 113 is exposed on the surface of the second insulating layer 114, away from the second via 114a.

[0060] The second electrode 118 is disposed within the first via 115a and on the surface of the planarization layer 115 opposite to the second insulating layer 114; that is, a portion of the second electrode 118 is disposed within the first via 115a, and a portion of the second electrode 118 is disposed on the surface of the planarization layer 115 opposite to the second insulating layer 114. The third insulating layer 116 is disposed within the second via 114a and the first via 115a, and the third insulating layer 116 is located on the surface of the second electrode 118 opposite to the planarization layer 115 and the surface of the planarization layer 115 opposite to the second insulating layer 114. The first electrode 117 is disposed on the surface of the third insulating layer 116 opposite to the planarization layer 115, the surface of the trace 113 opposite to the first insulating layer 112, and the surface of the second electrode 118 opposite to the second insulating layer 114. The first electrode 117 extends into the first via 115a and the second via 114a, and the first electrode 117 is connected to the second electrode 118 and the trace 113, respectively. That is, part of the first electrode 117 is disposed on the surface of the third insulating layer 116 opposite to the planarization layer 115, and part of the first electrode 117 extends into the first via 115a and the second via 114a, and is disposed on the surface of the trace 113 opposite to the first insulating layer 112 and the surface of the second electrode 118 opposite to the second insulating layer 114, and is respectively connected to the second electrode 118 and the trace 113.

[0061] It should be noted that the first via 115a and the second via 114a constitute a half-connected via. A half-connected via refers to a via in which one film layer is connected to two other film layers within a single via. In this application, the first electrode 117 is connected to both the trace 113 and the second electrode 118 within the half-connected via.

[0062] The first via 115a includes a first sidewall a1 and a bottom wall a2, with the first sidewall a1 connected to the bottom wall a2. The second via 114a includes a second sidewall a3, which is connected to both the first sidewall a1 and the bottom wall a2. The bottom wall a2 is formed from a portion of the surface of the second insulating layer 114 facing away from the trace 113.

[0063] The second electrode 118 is disposed on the bottom wall a2, the first side wall a1, and the surface of the planarization layer 115 facing away from the second insulating layer 114. The third insulating layer 116 is disposed on the first side wall a1 and the second side wall a3, and the third insulating layer 116 covers part of the second electrode 118. The first electrode 117 is disposed on the third insulating layer 116, the trace 113 is exposed on the surface of the second via 114a and the second side wall a3, and the first electrode 117 is also connected to the second electrode 118. That is, the first side wall a1 is provided with the third insulating layer 116 and the second electrode 118, the bottom wall a2 is provided with the second electrode 118, and the second side wall a3 is provided with the third insulating layer 116 and the first electrode 117.

[0064] More specifically, the first sidewall a1 includes a first sub-sidewall a11 and a second sub-sidewall a12 that are opposite to and spaced apart. The first sub-sidewall a11 is connected to the bottom wall a2, and the second sub-sidewall a12 is spaced apart from the bottom wall a2. The first sub-sidewall a11 is provided with a second electrode 118. A third insulating layer 116 is provided on the surface of the second electrode 118 facing away from the first sub-sidewall a11, and a first electrode 117 is provided on the surface of the third insulating layer 116 facing away from the second electrode 118. The bottom wall a2 is provided with a second electrode 118, and the first electrode 117 is provided on the surface of the second electrode 118 facing away from the bottom wall a2.

[0065] The second sidewall a3 includes a third sub-sidewall a31 and a fourth sub-sidewall a32 that are opposite to and spaced apart. The third sub-sidewall a31 is connected to the bottom wall a2, and the fourth sub-sidewall a32 is spaced apart from the bottom wall a2. The fourth sub-sidewall a32 is connected to the second sub-sidewall a12. The third sub-sidewall a31 is provided with a first electrode 117, and the fourth sub-sidewall a32 is provided with a third insulating layer 116. The surface of the third insulating layer 116 facing away from the fourth sub-sidewall a32 is provided with the first electrode 117.

[0066] The second electrode 118 is electrically connected to the trace 113 through the first electrode 117, and the second electrode 118 is used to receive signals for display through the trace 113.

[0067] Please see Figure 6 , Figure 6 for Figure 5The diagram shows a first structural schematic of the second electrode. The second electrode 118 includes an electrode body 1181 and a plurality of sub-electrodes 1182. The plurality of sub-electrodes 1182 are connected to one side of the electrode body 1181, and adjacent sub-electrodes 1182 are spaced apart to form at least one gap 1183. A portion of the electrode body 1181 is located between a first sub-sidewall a11 and a bottom wall a2, and the plurality of sub-electrodes 1182 are located on the bottom wall a2. A portion of the first electrode 117 is located within the gap 1183, and the first electrode 117 is connected to both the electrode body 1181 and the plurality of sub-electrodes 1182, thereby electrically connecting the second electrode 118 to the wiring 113.

[0068] Understandably, please refer to Figure 7 , Figure 7 This is a schematic diagram of the layer structure of a driving substrate in the prior art. Because the side surface 141 is relatively steep (i.e., the slope of the side surface 141 is large), and because the first conductive layer 142 is formed by a deposition process, a break occurs in the first conductive layer 142 at the connection between the bottom surface 145 and the side surface 141. Consequently, the second conductive layer 143 cannot be connected to the wire 144 through the first conductive layer 142. Therefore, this application forms multiple gaps 1183 at the connection between the second electrode 118 and the second side wall a3, allowing the first electrode 117 to be deposited within the gaps 1183. The first electrode 117 located within the gaps 1183 is connected to the second electrode 118, preventing a break in the first electrode 117 at the second side wall a3. The second electrode 118 is electrically connected to the trace 113 through the first electrode 117.

[0069] It should be noted that the first electrode 117 and the second electrode 118 operate during different time periods. The display time of one frame includes a display period and a touch period. During the display period, the second electrode 118 receives display signals for display via trace 113. During the touch period, the first electrode 117 sends touch signals to the touch unit 15 via trace 113.

[0070] In one possible implementation, the third insulating layer 116 only covers the electrode body 1181, and the third insulating layer 116 does not cover the sub-electrode 1182.

[0071] In exemplary embodiments, such as Figure 6 As shown, the distance W between two adjacent sub-electrodes 1182, i.e. the width of the gap 1183, is 1um to 3um, for example, 1um, 1.3um, 1.5um, 1.9um, 2um, 2.4um, 3um, or other values. This application does not impose specific limitations on this.

[0072] In an exemplary embodiment, the length L of the sub-electrode 1182, i.e. the length of the gap 1183, is 2um to 4um, for example, 2um, 2.4um, 2.7um, 3um, 3.5um, 3.8um, 4um, or other values. This application does not impose specific limitations on this. The length of the gap is along the X-axis direction, and the width of the gap is along the Y-axis direction.

[0073] For one possible implementation, please refer to Figure 8 , Figure 8 for Figure 5 The diagram shows a second structural design of the second electrode. The electrode body 1181 includes at least one connecting surface 1181a, which faces the gap 1183 and is connected to each of the sub-electrodes 1182. Alternatively, a connecting surface 1181a may be located between two adjacent sub-electrodes 1182 and connected to each of the two adjacent sub-electrodes 1182. The connecting surface 1181a is an inclined surface and faces the first through-hole 115a.

[0074] Understandably, by setting the connection surface 1181a between two adjacent sub-electrodes 1182 as an inclined surface, the contact between the electrode body 1181 and the first electrode 117 is increased, thereby improving the connection stability between the electrode body 1181 and the first electrode 117.

[0075] In exemplary embodiments, such as Figure 8 As shown, the inclination angle α of the connecting surface 1181a relative to the bottom wall a2 is 50 degrees to 80 degrees, for example, 50 degrees, 58 degrees, 60 degrees, 65 degrees, 67 degrees, 70 degrees, 72 degrees, 80 degrees, or other values. This application does not impose specific limitations on this. The bottom wall a2 is parallel to the upper surface of the sub-electrode 1182.

[0076] It should be noted that, for ease of demonstration, Figure 5 Only one first electrode 117 and one second electrode 118 are shown. In reality, there are multiple first electrodes 117 and multiple second electrodes 118. One first electrode 117 is located within a touch area T, and one second electrode 118 is located within a touch area T or within a sub-pixel P. The number of first vias 115a within a touch area T can be one or more, and the number of second vias 114a within a touch area T can be one or more.

[0077] For one possible implementation, please refer to Figure 9 , Figure 9 for Figure 5The diagram shows a specific structural schematic of the driving substrate 11. The driving substrate 11 is used in a liquid crystal display panel. The driving substrate 11 also includes a connecting electrode 121, a transistor 122, and a third electrode 123. Each transistor 122 includes a gate b1, an active layer b2, a source b3, and a drain b4. The gate b1, the connecting electrode 121, and the first insulating layer 112 are disposed on a surface of the substrate 111. The first insulating layer 112 also covers the peripheral side surface of the gate b1 and the surface of the gate b1 facing away from the substrate 111, that is, the first insulating layer 112 covers the gate b1 and the connecting electrode 121 to a surface of the substrate 111. The active layer b2 is disposed on the surface of the first insulating layer 112 facing away from the substrate 111, and the orthographic projection of the active layer b2 in the Z-axis direction at least partially coincides with the orthographic projection of the gate b1 in the Z-axis direction, that is, the orthographic projection of the active layer b2 on the substrate 111 at least partially coincides with the orthographic projection of the gate b1 on the substrate 111. The source electrode b3 and drain electrode b4 are both disposed on the surface of the first insulating layer 112 facing away from the substrate 111. The source electrode b3 and drain electrode b4 are disposed opposite each other and spaced apart along the X-axis direction, and are respectively connected to opposite sides of the active layer b2. The orthogonal projection of a portion of the source electrode b3 in the Z-axis direction coincides with the orthogonal projection of the gate electrode b1 in the Z-axis direction, and the orthogonal projection of a portion of the drain electrode b4 in the Z-axis direction coincides with the orthogonal projection of the gate electrode b1 in the Z-axis direction. That is, the orthogonal projections of a portion of the source electrode b3 and a portion of the drain electrode b4 on the substrate 111 both coincide with the orthogonal projection of the gate electrode b1 on the substrate 111. The second insulating layer 114 covers the active layer b2, the source electrode b3, and the drain electrode b4.

[0078] The planarization layer 115 also has a third via 115b extending through the planarization layer 115 along the Z-axis direction, and the second insulating layer 114 also has a fourth via 114b extending through the second insulating layer 114 along the Z-axis direction. The fourth via 114b communicates with the third via 115b, and the orthographic projection of the fourth via 114b in the Z-axis direction coincides with the orthographic projection of the third via 115b in the axial direction. Part of the source electrode b3 is exposed in the fourth via 114b. The third insulating layer 116 is disposed within the third via 115b and the fourth via 114b, and the third electrode 123 is disposed on the third insulating layer 116, and the third electrode 123 is located within the third via 115b and the fourth via 114b.

[0079] The first insulating layer 112 is used to insulate the gate b1 from the active layer b2, from the source b1 to b3, and from the drain b4. The source b3 is electrically connected to the active layer b2, and the drain b4 is electrically connected to the active layer b2. The connecting electrode 121 is electrically connected to the gate b1 and can provide a scan signal to the gate b1. The gate b1 turns on the active layer b2 according to the scan signal, thereby turning on the source b3 and the drain b4. The source b3 is electrically connected to the third electrode 123. The data signal transmitted by the data line (not shown) is transmitted to the third electrode 123 through the drain b4, the active layer b2, and the source b3 to control the potential of the third electrode 123.

[0080] It should be noted that, for ease of demonstration, Figure 9 Only one connecting electrode 121, one transistor 122, and one third electrode 123 are shown. In reality, there are multiple connecting electrodes 121, multiple transistors 122, and multiple third electrodes 123. One connecting electrode 121 is located in one sub-pixel region P, one transistor 122 is located in one sub-pixel region P, and one third electrode 123 is located in one sub-pixel region P.

[0081] In an exemplary embodiment, the first electrode 117 is a touch electrode, the second electrode 118 is a common electrode, and the third electrode 123 is a pixel electrode. A preset electric field is formed between the third electrode 123 and the second electrode 118 to drive the liquid crystal molecules of the liquid crystal layer 12 to deflect.

[0082] In other embodiments, the driving substrate 11 can also be applied to an OLED display panel or a Micro LED display panel. The second electrode 118 can be an anode or cathode electrically connected to the light-emitting element.

[0083] In summary, the driving substrate 11 provided in this application embodiment includes a first insulating layer 112, a trace 113, a second insulating layer 114, a planarization layer 115, a first electrode 117, and a second electrode 118. The second insulating layer 114 covers the trace 113 to one surface of the first insulating layer 112, and the planarization layer 115 is disposed on the surface of the second insulating layer 114 opposite to the first insulating layer 112. The planarization layer 115 has a first via 115a extending along the Z-axis through the planarization layer 115, and the second insulating layer 114 has a second via 114a extending along the Z-axis through the second insulating layer 114, and the second via 114a communicates with the first via 115a, with the trace 113 exposed in the second via 114a. The first electrode 117 is disposed within the first via 115a and the second via 114a, and the first electrode 117 is connected to the trace 113. The second electrode 118 includes an electrode body 1181 and a plurality of sub-electrodes 1182. Multiple sub-electrodes 1182 are connected to one side of the electrode body 1181, and adjacent sub-electrodes 1182 are spaced apart to form at least one gap 1183. The sub-electrodes 1182 and a portion of the electrode body 1181 are located within a first via 115a. A portion of the first electrode 117 is located within the gaps 1183, and the first electrode 117 is connected to both the electrode body 1181 and the multiple sub-electrodes 1182. The second electrode 118 is electrically connected to the trace 113 via the first electrode 117. Therefore, by forming multiple gaps 1183 at the opening of the second via 114a, this application allows the first electrode 117 to be deposited within the gaps 1183, preventing any breakpoints in the first electrode 117 at the opening of the second via 114a.

[0084] Please see Figure 10 , Figure 10 This is a schematic flowchart illustrating the method for fabricating a driving substrate according to the fourth embodiment of this application. The method for fabricating the driving substrate is used to form the driving substrate 11 of the third embodiment. For descriptions of the similarities between the structure involved in the method for fabricating the driving substrate and the structure of the driving substrate 11, please refer to the relevant descriptions of the driving substrate 11 in the above embodiments; they will not be repeated here. Please refer to... Figure 10 The manufacturing method of the driving substrate 11 specifically includes the following steps.

[0085] Step S10: Provide a substrate 111, and sequentially form a first insulating layer 112, a trace 113, a second insulating layer 114, and a planarization layer 115 on the substrate 111. The first insulating layer 112 is located on one surface of the substrate 111, the second insulating layer 114 covers the trace 113 to the surface of the first insulating layer 112 opposite to the substrate 111, and the planarization layer 115 is located on the surface of the second insulating layer 114 opposite to the first insulating layer 112.

[0086] Specifically, please refer to Figure 11 , Figure 11 for Figure 10 The schematic diagram of the structure corresponding to step S10 is shown below. A substrate 111 is provided, and a first insulating layer 112 is formed on one surface of the substrate 111. A trace 113 is formed on the surface of the first insulating layer 112 opposite to the substrate 111 through deposition, exposure, etching, and stripping processes. A second insulating layer 114 is formed on the surface of the first insulating layer 112 opposite to the substrate 111 through a chemical vapor deposition process, and the second insulating layer 114 covers the trace 113. A planarization layer 115 is formed on the surface of the second insulating layer 114 opposite to the first insulating layer 112 through a deposition, exposure, and drying process.

[0087] Step S20: A first via 115a is opened in the planarization layer 115 and a second via 114a is opened in the second insulating layer 114. The first via 115a and the second via 114a are connected, and part of the trace 113 is exposed in the second via 114a.

[0088] Please see Figure 12 , Figure 12 for Figure 10 The schematic diagram shows the structure formed corresponding to step S20. A first via 115a is formed in the planarization layer 115 and a second via 114a is formed in the second insulating layer 114 by an etching process. The first via 115a and the second via 114a are connected, and a portion of the trace 113 is exposed in the second via 114a.

[0089] Step S30: A second electrode 118 is formed in the first via 115a and on the surface of the planarization layer 115 opposite to the second insulating layer 114.

[0090] Please see Figure 13 , Figure 13 for Figure 10 The schematic diagram of the structure corresponding to step S30 is shown. A second electrode 118 is formed in the first via 115a and on the surface of the planarization layer 115 opposite to the second insulating layer 114 through deposition, exposure, etching and stripping processes.

[0091] Step S40: A third insulating layer 116 is formed in the first via 115a and the second via 114a, wherein the portion of the surface of the trace 113 facing away from the first insulating layer 112 exposes the third insulating layer 116.

[0092] Please see Figure 14 , Figure 14 for Figure 10The schematic diagram of the structure corresponding to step S40 is shown. A third insulating layer 116 is formed in the first via 115a, the second via 114a, the surface of the planarization layer 115 facing away from the second insulating layer 114, and the surface of the second electrode 118 facing away from the planarization layer 115 through deposition, exposure, etching, and stripping processes. The third insulating layer 116 is exposed on a portion of the surface of the trace 113 facing away from the first insulating layer 112, meaning that the third insulating layer 116 does not completely cover the trace 113.

[0093] Step S50: A first electrode 117 is formed in the first via 115a and the second via 114a. The first electrode 117 is connected to the second electrode 118 and the trace 113, respectively.

[0094] Please see Figure 5 A first electrode 117 is formed in the first via 115a, the second via 114a, and on the surface of the third insulating layer 116 opposite to the planarization layer 115 through deposition, exposure, etching, and stripping processes. The first electrode 117 is connected to the second electrode 118 in the first via 115a and to the trace 113 at the second via 114a.

[0095] Understandably, by forming the first via 115a and the second via 114a in the same process, an etching process is saved, thus reducing costs. Moreover, by connecting the second electrode 118 to the trace 113 through the first electrode 117, it is not necessary to create additional openings and set conductive elements to connect the second electrode 118 to the trace 113, saving the space required for openings and improving design and process margins.

[0096] Please see Figure 15 , Figure 15 for Figure 10 The diagram shows a specific process flow diagram of the manufacturing method of the driving substrate. Figure 15 The flowchart shown is used to form Figure 9 The driving substrate shown. Please refer to [link / reference]. Figure 15 The method for manufacturing the driving substrate may specifically include the following steps.

[0097] Step S110: A substrate 111 is provided, and a gate b1, a connecting electrode 121, a first insulating layer 112, an active layer b2, a source electrode b3, a drain electrode b4, a trace 113, a second insulating layer 114, and a planarization layer 115 are sequentially formed on the substrate 111. The first insulating layer 112 covers the gate b1 and the connecting electrode 121 to the substrate 111. The second insulating layer 114 covers the source layer b2, the source electrode b3, the drain electrode b4, and the trace 113 to the surface of the first insulating layer 112 opposite to the substrate 111. The planarization layer 115 is disposed on the surface of the second insulating layer 114 opposite to the first insulating layer 112.

[0098] Specifically, please refer to Figure 16 , Figure 16 for Figure 15 The schematic diagram corresponding to step S110 is shown below. A substrate 111 is provided, and a gate b1 and a connection electrode 121 are formed on one surface of the substrate 111. A first insulating layer 112 is formed on the substrate 111, covering the gate b1 and the connection electrode 121. An active layer b2 is formed on the surface of the first insulating layer 112 opposite to the gate b1. A source b3 and a drain b4 are formed on the surface of the first insulating layer 112 opposite to the gate b1, and a trace 113 is formed on the surface of the first insulating layer 112 opposite to the connection electrode 121. A second insulating layer 114 is formed on the first insulating layer 112, covering the active layer b2, the source b3, the drain b4, and the trace 113. A planarization layer 115 is formed on the surface of the second insulating layer 114 opposite to the first insulating layer 112.

[0099] Step S120: A first via 115a and a third via 115b are formed in the planarization layer 115, and a second via 114a and a fourth via 114b are formed in the second insulating layer 114. The first via 115a and the second via 114a are connected, and part of the trace 113 is exposed in the second via 114a. The third via 115b and the fourth via 114b are connected, and part of the source electrode b3 is exposed in the fourth via 114b.

[0100] Specifically, please refer to Figure 17 , Figure 17 for Figure 15 The schematic diagram shows the structure formed corresponding to step S120. A first via 115a and a third via 115b are formed in the planarization layer 115 using an etching process. A second via 114a and a fourth via 114b are formed in the second insulating layer 114 using an etching process. The first via 115a and the second via 114a are connected, with a portion of the trace 113 exposed in the second via 114a. The third via 115b and the fourth via 114b are connected, with a portion of the source electrode b3 exposed in the fourth via 114b.

[0101] Step S130: A second electrode 118 is formed in the first via 115a and on the portion of the planarization layer 115 facing away from the second insulating layer 114.

[0102] Specifically, please refer to Figure 18 , Figure 18 for Figure 15 The schematic diagram shows the structure formed corresponding to step S130. A second electrode 118 is formed in the first via 115a and on the portion of the planarization layer 115 facing away from the second insulating layer 114 through deposition, exposure, etching and stripping processes.

[0103] Step S140: A third insulating layer 116 is formed in the first via 115a, the second via 114a, the third via 115b, and the fourth via 114b, wherein the third insulating layer 116 is exposed on the surface of the trace 113 and the source electrode b3 facing away from the first insulating layer 112.

[0104] Please see Figure 19 , Figure 19 for Figure 15 The schematic diagram shows the structure formed corresponding to step S140. A third insulating layer 116 is formed through deposition, exposure, etching, and stripping processes within the first via 115a, the second via 114a, the third via 115b, the fourth via 114b, the surface of the second electrode 118 facing away from the planarization layer 115, and the planarization layer 115 facing away from the second insulating layer 114. The third insulating layer 116 exposes portions of the surfaces of the trace 113 and the source electrode b3 facing away from the first insulating layer 112; that is, the third insulating layer 116 does not completely cover the trace 113 and the source electrode b3.

[0105] Step S150: A first electrode 117 is formed in the first via 115a and the second via 114a, and a third electrode 123 is formed in the third via 115b and the fourth via 114b. The first electrode 117 is connected to the second electrode 118 and the trace 113, respectively, and the third electrode 123 is connected to the source electrode b3.

[0106] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0107] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A driving substrate, comprising a plurality of touch areas arranged in an array, characterized in that, The driving substrate further comprises a first insulating layer, a plurality of traces, a second insulating layer, a planar layer, a plurality of first electrodes and a plurality of second electrodes, the second insulating layer covers the plurality of traces to the first insulating layer, the planar layer is arranged on a surface of the second insulating layer away from the first insulating layer, the planar layer is provided with a plurality of first through holes, the second insulating layer is provided with a plurality of second through holes, and one second through hole and one first through hole are in communication, part of the traces are exposed to the second through hole, part of the first electrodes are arranged in the first through hole and the second through hole, and the first electrode is connected with the trace; One second electrode is located in one touch area, the second electrode comprises an electrode body and a plurality of sub-electrodes, the plurality of sub-electrodes are connected to one side of the electrode body, and adjacent two sub-electrodes are spaced apart to form at least one gap, the sub-electrodes and part of the electrode body are located in the first through hole, part of the first electrode is located in the gap, and the first electrode is connected with the electrode body and the plurality of sub-electrodes respectively, so that the second electrode is electrically connected with the trace, the first electrode is used to send a touch signal through the trace, and the second electrode is used to receive a signal for display through the trace.

2. The drive substrate according to claim 1, wherein The width of the gap is the distance between adjacent two sub-electrodes, and is 1 um to 3 um.

3. The drive substrate according to claim 1, wherein The length of the gap is the length of the sub-electrode, and is 2 um to 4 um.

4. The drive substrate according to claim 1, wherein The electrode body comprises at least one connecting surface, the connecting surface faces the gap, the connecting surface is connected with the sub-electrode respectively, the connecting surface is an inclined surface, and the connecting surface faces the first through hole.

5. The drive substrate according to claim 4, wherein The first through hole comprises a first side wall and a bottom wall, the first side wall is connected with the bottom wall, the second through hole comprises a second side wall, the second side wall is connected with the first side wall and the bottom wall respectively; The plurality of sub-electrodes are arranged on the bottom wall, part of the electrode body is arranged on the first side wall, and part of the first electrode is arranged on the second side wall.

6. The drive substrate according to claim 5, wherein The inclination angle of the connecting surface relative to the bottom wall is 50 degrees to 80 degrees.

7. The drive substrate according to claim 5, wherein The driving substrate further comprises a third insulating layer, the third insulating layer is arranged on the first side wall, the second side wall, a surface of the second electrode away from the planar layer and a surface of the planar layer away from the second insulating layer.

8. A method for manufacturing a driving substrate, comprising the steps of: The manufacturing method of the driving substrate comprises: forming traces, a second insulating layer and a planar layer on a first insulating layer in sequence, the second insulating layer covers the traces to a surface of the first insulating layer, and the planar layer is arranged on a surface of the second insulating layer away from the first insulating layer; forming first through holes on the planar layer and second through holes on the second insulating layer, the first through holes and the second through holes are in communication, and part of the traces are exposed to the second through holes; forming a second electrode in the first through hole and on a surface of the planar layer away from the second insulating layer; forming a third insulating layer in the first via and the second via, wherein a part of the surface of the trace facing away from the first insulating layer is exposed to the third insulating layer; forming a first electrode in the first via and the second via, wherein the first electrode is connected to the second electrode and the trace respectively.

9. A display panel, characterized by, The display panel comprises a driving substrate and a power board, wherein each first electrode of the driving substrate is electrically connected to the touch unit, and the first electrode is used to send a touch signal to the touch unit through the trace.

10. A display device, characterized by comprising: The display panel comprises a driving substrate and a power board, wherein each first electrode of the driving substrate is electrically connected to the touch unit, and the first electrode is used to send a touch signal to the touch unit through the trace.

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