Multi-effect phototransistor and preparation method thereof
By using two-dimensional materials such as graphene, α-In2Se3, h-BN and MoS2 in the transistor, combined with their unique physical effects, a multi-effect phototransistor was prepared, which solved the problems of high power consumption and single performance of traditional transistors, and achieved low power consumption, high performance and multi-functional effects.
Patent Information
- Application Number
- CN202510218316.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-27
AI Technical Summary
When integrating traditional transistors, there are problems such as high power consumption, heat dissipation problems, single performance, and incompatibility between structure and materials, which is difficult to meet the needs of future electronic devices for higher performance.
Graphene is used as the gate electrode, α-In2Se3 is used as the ferrodielectric layer, h-BN is used as the capacitance matching layer, and MoS2 is used as the semiconductor channel layer. Multi-effect phototransistors are prepared through mechanical peeling and dry transfer processes, combining the tunable Fermi level effect of graphene, spontaneous polarization of ferroelectric materials, capacitance matching effect and the lasting photoconductivity effect of semiconductor channels.
It realizes low power consumption, high performance, high stability and multifunctional transistors, which can show digital logic switching behavior and artificial synaptic functions, and are suitable for the high-performance needs of future electronic devices.
Smart Images
Figure CN120051016A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of optoelectronic devices, and particularly to a multi-effect phototransistor and a preparation method thereof. Background Art
[0002] In traditional electronic components, transistors are widely used in signal amplification and switching circuits and have become the basis of modern electronic technology. The working principle of transistors can be explained by the characteristics of current, voltage, and semiconductor materials, mainly based on the electronic behavior of PN junctions. With the continuous progress of integrated circuit technology, the size of transistors has been continuously reduced, and the power consumption and heat dissipation problems of transistors have become increasingly prominent. In addition, transistors have problems such as single performance during integration and incompatibility in terms of structure and materials, making it difficult to meet the requirements of future electronic devices for higher performance.
[0003] Two-dimensional materials such as graphene and transition metal chalcogenides have received extensive attention in the past ten years due to their unique electronic structures and physical properties. At the same time, van der Waals heterostructures constructed from different two-dimensional materials have always shown excellent performance and have attracted much attention. In recent years, due to the extremely excellent properties of two-dimensional materials, they have become the main candidate materials for constructing transistors. Therefore, based on the characteristics of different two-dimensional materials, the present invention provides a multi-effect transistor simply prepared from thin layers of Graphene, α-In 2 Se 3 、h-BN and MoS 2 formed, which has the advantages of low power consumption, high performance, high stability, multi-function, and easy preparation. Summary of the Invention
[0004] Aiming at the technical problems existing in the prior art, the primary object of the present invention is to provide a multi-effect phototransistor and a preparation method thereof. The transistor uses graphene as the gate electrode, α-phase indium triselenide and h-BN as the ferroelectric dielectric layer and the capacitance matching layer respectively, and molybdenum disulfide as the semiconductor channel. It combines the tunable Fermi level effect of graphene, the negative capacitance effect caused by the polarization of ferroelectric materials, the capacitance matching effect for optimizing dielectric properties, and the persistent photoconductivity effect and grating effect exhibited by the semiconductor channel layer. The behavior of this transistor shows the application ability of integrated digital logic and neuromorphic computing. This transistor is prepared by a mechanical exfoliation process and a dry transfer process, and the process is mature, simple, and easy to operate, and the prepared device has high stability.
[0005] On the one hand, the present invention provides a multi-effect phototransistor, including a substrate, a graphene thin layer disposed on a SiO 2 / Si substrate, an α-In 2 Se 3 thin layer disposed on the graphene thin layer, an α-In2 Se 3 The h-BN thin layer on the thin layer, and the MoS 2 thin layer provided on the h-BN thin layer 2 The source electrode and the drain electrode at both ends of the MoS thin layer, and the gate electrode provided on the graphene thin layer;
[0006] The α-In 2 Se 3 After the Se thin layer is provided on the graphene thin layer, it is annealed in air and then quenched in acetone to enhance the ferroelectricity.
[0007] On the one hand, the present invention provides a preparation method of a multi-effect phototransistor, including the following steps:
[0008] Transfer the graphene thin layer to the SiO 2 / Si substrate by using mechanical exfoliation and dry transfer processes;
[0009] Transfer the α-In 2 Se 3 thin layer to the graphene thin layer by using mechanical exfoliation and dry transfer processes, then anneal the substrate in air, and then quench it in acetone to enhance the ferroelectricity;
[0010] Transfer the h-BN thin layer to the α-In 2 Se 3 thin layer by using mechanical exfoliation and dry transfer processes;
[0011] Transfer the MoS 2 thin layer to the h-BN thin layer by using mechanical exfoliation and dry transfer processes;
[0012] Prepare source metal and drain metal on the MoS 2 thin layer, and prepare gate metal on the graphene thin layer;
[0013] Anneal in an inert atmosphere.
[0014] Furthermore, the thickness of the graphene thin layer is 2 nm to 5 nm;
[0015] The α-In 2 Se 3 thin layer has a thickness of 35 nm to 55 nm;
[0016] The h-BN thin layer has a thickness of 2 nm to 5 nm;
[0017] The MoS 2 thin layer has a thickness of 10 nm to 20 nm.
[0018] Further, the temperature of annealing in air is 240°C to 280°C, and the annealing time is 8 to 15 minutes;
[0019] The quenching time in acetone is half a minute, and then it is rinsed with deionized water.
[0020] Further, when the h-BN thin layer is transferred to the α-In 2 Se 3 thin layer, the h-BN thin layer completely covers the α-In 2 Se 3 thin layer, which is used to improve the device stability and reduce interface defects, and high stability and high mobility are obtained.
[0021] Further, in the step of annealing in an inert atmosphere, the annealing time is 20 to 40 minutes, and the annealing temperature is 100 to 150°C.
[0022] Further, the distance between the source and the drain is 3 μm.
[0023] Further, the boundary of the MoS 2 thin layer does not exceed the boundary of the α-In 2 Se 3 thin layer.
[0024] Further, the source, the drain and the gate adopt an Au layer, and the thickness of the Au layer is 45 to 65 nm.
[0025] On the one hand, the present invention also provides an application of the above multi-effect phototransistor in the field of artificial synapses.
[0026] Compared with the prior art, the present invention has at least the following beneficial effects:
[0027] By using Graphene with a tunable Fermi level effect as the gate, the present invention obtains a defect-free high-quality interface and a diode-like rectifying contact; by replacing the traditional dielectric with the ferroelectric material α-In 2 Se 3 due to the spontaneous polarization, the negative capacitance effect is caused, and a steep subthreshold swing (SS) is realized, so as to obtain lower power consumption; the layered two-dimensional thin layer MoS with persistent photoconductivity effect and grating effect characteristics 2As an application of the channel layer, it realizes reversible conductance change and non-volatile "memory" function, which is highly similar to the role of biological neuron synapses in information transmission and storage, providing a potential way to simulate artificial synaptic function; an insulating thin layer h-BN introducing capacitance matching effect between the ferroelectric material and the semiconductor channel ensures good electrical insulation, improves the stability of the transistor and reduces the leakage current. The transistor exhibits excellent switching and optoelectronic characteristics, an extremely low subthreshold swing (17 mV / dec) and a high current on-off ratio (10 9 ), and can realize NOT gate digital logic function and handwritten digit recognition and classification functions through switching different physical effects. The present invention has the advantages of low power consumption and multi-function, and the device preparation process is simple, the technology is mature, the equipment is easy to obtain, and the cost is low.
[0028] The transistor prepared by the present invention has digital logic switching behavior. In one embodiment, a NOT gate logic circuit constructed by series-connected n-type MoS 2 and p-type WSe 2 transistors is set with a power supply voltage of 1V. Due to the negative capacitance effect and capacitance matching effect, the power consumption is greatly reduced, and the static power consumption is only 5 nW. This logic circuit has the characteristics of low power consumption, high stability, and easy preparation, which is conducive to promoting the further development and application in the fields of transistors and digital logic applications.
[0029] In addition, the transistor prepared by the present invention also has artificial synaptic function. Due to the excellent optoelectronic characteristics of the persistent photoconductivity effect and grating effect of MoS 2 , by respectively setting the control enhancement of 32 optical pulses and the control suppression of 32 gate voltage electrical pulses, it can simulate artificial synaptic function and realize the image recognition and classification of handwritten digits, with a recognition rate as high as 90.97%, and the power consumption can be as low as 0.47 pJ. This artificial synaptic has the characteristics of low power consumption, high recognition rate, and easy preparation, which is conducive to promoting the further development and application in the fields of artificial synapses and neuromorphic computing. Description of the Drawings
[0030] Figure 1 It is a device schematic diagram of a multi-effect optoelectronic transistor (substrate omitted) according to an embodiment of the present invention.
[0031] Figure 2 It is an optical microscope image of a multi-effect optoelectronic transistor prepared according to an embodiment of the present invention.
[0032] Figure 3 In FIG. a is the transfer curve of a multi-effect optoelectronic transistor prepared according to an embodiment of the present invention; FIG. b is the subthreshold swing curve of the transistor.
[0033] Figure 4Figure a shows an optical microscope image of a NOT gate prepared according to an embodiment of the present invention, and Figure b shows the static power consumption diagram of the NOT gate.
[0034] Figure 5 Figure a shows the test of a multi-effect phototransistor prepared according to an embodiment of the present invention for artificial synaptic function, where in Figure a, light and electrical pulses are respectively applied to regulate the conductance change; Figure b shows the verification accuracy of handwritten digital images with the number of training epochs. Detailed implementation manners
[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. In the following embodiments, the experimental methods, unless otherwise specified, are all conventional methods; the reagents and materials, unless otherwise specified, can all be obtained from public commercial channels.
[0036] In this specification, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those shown in the figures.
[0037] In addition, terms such as "first", "second", etc. are used to describe each element, layer, region, section, etc., and are not intended to be limiting. The terms "having", "containing", "including", "comprising", etc. are open-ended terms, indicating the presence of the stated element or feature, but not excluding additional elements or features, unless the context clearly dictates otherwise.
[0038] As Figure 1 shown, an embodiment of the present invention provides a multi-effect phototransistor, which includes a substrate (not shown), and the substrate is selected as a SiO 2 / Si substrate; a graphene thin layer with a tunable Fermi level effect, an α-In 2 Se 3 thin layer, an h-BN thin layer, and a MoS 2 thin layer are sequentially stacked on the substrate. The thickness of the graphene thin layer is 2 nm to 5 nm; the thickness of the α-In 2 Se 3 thin layer is 35 nm to 55 nm; the thickness of the h-BN thin layer is 2 nm to 5 nm; the thickness of the MoS 2 thin layer is 10 nm to 20 nm.
[0039] In α-In 2 Se3 After the thin layer is disposed on the graphene thin layer, it is annealed in air and then quenched in acetone to enhance ferroelectricity. Specifically, the annealing temperature in air is 240°C to 280°C, and the annealing time is 8 to 15 minutes; the quenching time in acetone is half a minute, and then it is rinsed with deionized water.
[0040] The h-BN thin layer is disposed on the α-In 2 Se 3 When on the thin layer, the h-BN thin layer completely covers the α-In 2 Se 3 thin layer to improve device stability and reduce interface defects. The boundary of the MoS 2 thin layer does not exceed the boundary of the α-In 2 Se 3 thin layer.
[0041] The source electrode and the drain electrode are disposed at both ends of the MoS 2 thin layer, and a gate electrode is disposed on the surface of the graphene. The source electrode, the drain electrode, and the gate electrode are made of an Au layer, and the thickness of the Au layer is 45 to 65 nm.
[0042] This device uses Graphene with a tunable Fermi level effect as the gate electrode to obtain a high-quality interface and rectifying contact; the spontaneous polarization of the ferroelectric material α-In 2 Se 3 results in a negative capacitance effect, achieving a steep subthreshold swing (SS) and greatly reducing power consumption; the persistent photoconductivity effect and grating effect of the thin layer MoS 2 are used to achieve reversible conductance changes and non-volatile "memory" functions; a capacitive matching effect is achieved by disposing an insulating thin layer h-BN between the ferroelectric material α-In 2 Se 3 thin layer and the MoS 2 channel layer, improving device stability and realizing Figure 1 the structure of the device diagram schematic.
[0043] An embodiment of the present invention further provides a preparation method of the multi-effect phototransistor, which includes the following steps:
[0044] First, the SiO 2 / Si growth substrate is soaked in an ethanol solution and deionized water respectively, and the soaking time each time is 5 minutes.
[0045] Then, a mechanical peeling process and a dry transfer process are adopted. A single crystal tape is obtained by sticking a blue tape to the single crystal, and Graphene / PDMS is obtained by sticking the single crystal tape with PDMS. A 2-5 nm thin layer of Graphene is selected under an optical microscope, and the PDMS with the Graphene side adhered is covered on the SiO2 On the surface of the / Si substrate, by utilizing the difference in material adhesion, a thin layer of Graphene is obtained. The Graphene thin layer obtained by this exfoliation method is easier to control the thickness and shape and has less residual glue compared to the Graphene thin layer directly exfoliated from the substrate using a single-crystal tape; subsequently, according to this exfoliation method, the thin layer of α-In 2 Se 3 is transferred onto Graphene by dry transfer. One end of Graphene needs to cross α-In 2 Se 3 , and the other end needs to be located within α-In 2 Se 3 . The thickness of the thin layer of α-In 2 Se 3 is 35 nm to 55 nm.
[0046] Next, the substrate is placed on a heating stage and annealed in air. The annealing temperature is 240 - 280 °C, and the annealing time is 8 - 15 min. Subsequently, the substrate is immediately placed in acetone for quenching and rinsed with deionized water after half a minute.
[0047] Next, using a mechanical exfoliation process and a dry transfer process, a single-crystal tape is obtained by sticking a single crystal with blue tape. A thin layer of h-BN with a thickness of 2 nm to 5 nm is selected, and h-BN / PDMS is obtained by sticking the single-crystal tape with PDMS. The PDMS with the h-BN side adhered is completely covered on the surface of α-In 2 Se 3 ; Subsequently, using the same mechanical exfoliation process and dry transfer process, when transferring the thin layer of MoS 2 onto the thin layer of h-BN, it is necessary to make the thin layer of Graphene cross the thin layer of MoS 2 in the horizontal direction. At the same time, the boundary of the MoS 2 thin layer does not exceed the boundary of the α-In 2 Se 3 thin layer. The thickness of the thin layer of MoS 2 is 10 nm to 20 nm.
[0048] Next, a positive photoresist is selected. The spin coater is set to 3500 rpm mode and spin-coated for 60 s; subsequently, it is baked on a heating stage at 100 °C for 5 - 10 min; using an ultraviolet laser lithography source, electrode pattern windows are formed at both ends on the MoS 2 channel layer and on the graphene. The channel length is 3 μm.
[0049] Next, an Au layer with a thickness of 45 - 65 nm is deposited using an electron beam evaporation process at a deposition rate of 0.01 nm / s. After deposition, it is placed in acetone for ten minutes to dissolve the photoresist, thereby removing the excess Au layer. Finally, this device is placed in a glove box and annealed in argon at 150 °C for 30 minutes to increase the contact degree between different materials and improve the stability of the device, thus obtaining the final Graphene / α-In 2 Se 3 / h-BN / MoS 2 multi-effect phototransistor device.
[0050] Figure 2 Figure 10 shows the Graphene / α-In 2 Se 3 / h-BN / MoS 2 multi-effect phototransistor obtained by the above-mentioned embodiments of the present invention. The source electrode and the drain electrode are respectively arranged at both ends of the thin layer MoS 2 , and the gate electrode is arranged above one end of the thin layer Graphene. The scale bar is 5 μm.
[0051] Figure 3 In Fig. 11, Fig. a shows the transfer curve of the transistor. The source-drain bias voltage is set to 0.5 V. The transfer curve is in the counterclockwise direction, indicating that ferroelectric regulation is dominant, and the current on-off ratio is about 10 9 ; Fig. b shows the subthreshold swing curve of the transistor. The source-drain bias voltage is set to 0.1 V. The subthreshold swing (SS) of the forward sweep and the reverse sweep both break the room-temperature Boltzmann limit of 60 mV / dec, and the lowest SS is 17 mV / dec.
[0052] Figure 4 In Fig. 12, Fig. a shows the optical microscope image of the NOT gate fabricated based on this transistor. By connecting in series a transistor with n-type MoS 2 and a transistor with p-type WSe 2 (the rest of the structure of this transistor is the same as that of the above embodiments, except that the channel layer is different), the gates of the two transistors are connected as the input (V IN ), the p-type WSe 2 transistor is connected to the power supply voltage (V DD ), the n-type MoS 2 transistor is grounded (GND), and the other ends of the channels of the two transistors are connected as the output (V OUT ). The scale bar is 5 μm; Fig. b shows the static power consumption level of the NOT gate. The power supply voltage is set to 1 V. The static power consumption in the "0" and "1" states is approximately zero, and it is only 5 nW during the switching process.
[0053] Figure 5 In it, Figure a shows the regulation of conductance change by applying light and electrical pulses respectively. The source-drain bias voltage is set to 0.1V. By applying 32 light pulses and 32 electrical pulses respectively, the conductance varies between 0 and 1 after normalization; Figure b shows the verification accuracy of handwritten digit images with the number of training epochs. Based on the conductance change data obtained from this multi-effect transistor and combined with a neural network model, the digital image recognition and classification function is realized. After 30 times of training, the recognition accuracy reaches 90.97%; the inset shows the minimum power consumption required for single-pulse excitation. The source-drain bias voltage is set to 0.1V, the pulse width is 100ms, and the pulse excitation current magnitude is 47.4pA. The minimum power consumption calculated according to the formula is 0.47pJ.
[0054] According to the Graphene / α-In 2 Se 3 / h-BN / MoS 2 data curve of the multi-effect optoelectronic transistor, this transistor utilizes the tunable Fermi level effect of the thin layer of Graphene, the negative capacitance effect brought by the ferroelectric polarization of the thin layer of α-In 2 Se 3 and the capacitance matching effect of the insulating thin layer of h-BN to realize a low-power transistor and a NAND digital logic circuit with a high current switching ratio and a low subthreshold swing; in addition, this transistor also has an artificial synaptic function. Due to the persistent photoconductivity effect and the grating effect of MoS 2 the reversible conductance change and non-volatility obtained by applying light and electrical pulses respectively, combined with a neural network model, can realize the image recognition and classification of handwritten digits with a recognition rate as high as 90.97%, and the power consumption can be as low as 0.47pJ. The described Graphene / α-In 2 Se 3 / h-BN / MoS 2 The multi-effect optoelectronic transistor has the characteristics of low power consumption, easy preparation, high performance, and multi-function, which is conducive to promoting the further development and application in the fields of transistors and optoelectronic devices.
[0055] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.
Claims
1. A multi-effect phototransistor, characterized in that: It includes a graphene thin layer arranged on a SiO2 / Si substrate, an α-In2Se3 thin layer arranged on the graphene thin layer, an h-BN thin layer arranged on the α-In2Se3 thin layer, a MoS2 thin layer arranged on the h-BN thin layer, a source electrode and a drain electrode arranged at both ends of the MoS2 thin layer, and a gate electrode arranged on the graphene thin layer; After the α-In2Se3 thin layer is disposed on the graphene thin layer, it is annealed in air and then quenched in acetone.
2. A method for preparing a multi-effect phototransistor, characterized in that: The following steps are involved: The graphene thin layer was transferred onto SiO2 / Si substrate using mechanical exfoliation and dry transfer processes; The α-In2Se3 thin layer was transferred onto the graphene thin layer using mechanical exfoliation and dry transfer processes, followed by annealing the substrate in air and then quenching in acetone; The h-BN thin layer was transferred onto the α-In2Se3 thin layer using mechanical exfoliation and dry transfer processes; The MoS2 thin layer was transferred onto the h-BN thin layer using mechanical exfoliation and dry transfer processes; Prepare source metal and drain metal on the MoS2 thin layer, and prepare gate metal on the graphene thin layer; Anneal in an inert atmosphere.
3. The multi-effect phototransistor according to claim 1, or the preparation method according to claim 2, characterized in that: The thickness of the graphene thin layer is 2nm to 5nm; The thickness of the α-In2Se3 thin layer is 35nm to 55nm; The thickness of the h-BN thin layer is 2nm to 5nm; The thickness of the MoS2 thin layer is 10nm to 20nm.
4. The multi-effect phototransistor according to claim 1, or the preparation method according to claim 2, characterized in that: The annealing temperature in air is 240°C to 280°C, and the annealing time is 8 to 15 minutes; The quenching time in acetone was half a minute, followed by rinsing with deionized water.
5. The multi-effect phototransistor according to claim 1, or the preparation method according to claim 2, characterized in that: When the h-BN thin layer is transferred onto the α-In2Se3 thin layer, the h-BN thin layer completely covers the α-In2Se3 thin layer.
6. The preparation method according to claim 2, characterized in that: In the step of annealing in the inert atmosphere, the annealing time is 20 to 40 minutes and the annealing temperature is 100 to 150°C.
7. The multi-effect phototransistor or the preparation method according to claim 3, characterized in that: The spacing between the source and drain electrodes is 3 μm.
8. The multi-effect phototransistor or the preparation method according to claim 7, characterized in that: The boundary of the MoS2 thin layer does not exceed the boundary of the α-In2Se3 thin layer.
9. The multi-effect phototransistor or the preparation method according to claim 8, characterized in that: The source electrode, the drain electrode and the gate electrode are made of Au layer, and the thickness of the Au layer is 45-65 nm.
10. Application of the multi-effect phototransistor according to any one of claims 1 to 9 in the field of artificial synapses.