Display panel and method of manufacturing the same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes: a base layer; a pixel defining film on the base layer, and in which a light emitting opening is defined; a partition wall on the pixel defining film, and in which a partition wall opening overlapping the light emitting opening is defined; a light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall, and located in the partition wall opening; a lower encapsulation inorganic pattern including a first portion in the partition wall opening, a second portion extending from the first portion in a thickness direction of the base layer, and a third portion extending from the second portion in a direction away from the partition wall opening and spaced apart from the partition wall in a cross section; and a lower organic layer between the third portion of the lower encapsulation inorganic pattern and the partition wall.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167271 filed in the Korean Intellectual Property Office on November 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel. Background Art

[0004] Display devices that display images to users, such as televisions, monitors, smart phones, and tablet personal computers (PCs), include display panels that display images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels have been developed as display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated for each of the light emitting regions, and the cathode may provide a common voltage to each of the light emitting regions.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel, and, for example, to a display panel having relatively improved display quality.

[0008] Aspects of some embodiments of the present disclosure include a display panel that forms a light emitting element without using a metal mask and has relatively improved display quality, and a method of manufacturing the display panel.

[0009] According to some embodiments of the present disclosure, a display panel includes: a substrate layer; a pixel defining film on the substrate layer and defining a light-emitting opening in the pixel defining film; a partition wall on the pixel defining film and defining a partition wall opening overlapping the light-emitting opening in the partition wall; a light-emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall and located in the partition wall opening; a lower encapsulation inorganic pattern including a first portion in the partition wall opening, a second portion extending from the first portion in a thickness direction of the substrate layer, and a third portion extending from the second portion in a direction away from the partition wall opening and spaced apart from the partition wall in a cross section; and a lower organic layer between the third portion of the lower encapsulation inorganic pattern and the partition wall.

[0010] According to some embodiments, the display panel may further include: an encapsulation organic film on the lower encapsulation inorganic pattern, wherein the lower organic layer may be in contact with the encapsulation organic film.

[0011] According to some embodiments, the lower organic layer may include an inner portion and a boundary portion formed by surrounding the inner portion in a plan view, and the boundary portion and the encapsulation organic film may contact each other.

[0012] According to some embodiments, the lower encapsulation inorganic pattern may include a first lower encapsulation inorganic pattern on the cathode and a second lower encapsulation inorganic pattern on the first lower encapsulation inorganic pattern, and the first lower encapsulation inorganic pattern may include a plurality of inorganic patterns repeatedly laminated.

[0013] According to some embodiments, a thickness of one inorganic pattern among the plurality of inorganic patterns may be in a range of 175 nm to 200 nm.

[0014] According to some embodiments, the plurality of inorganic patterns may reflect light having a wavelength of 350 nanometers (nm) to 400 nm.

[0015] According to some embodiments, thicknesses of each of the plurality of inorganic patterns may be equal.

[0016] According to some embodiments, each of the plurality of inorganic patterns may include silicon nitride (SiN x ).

[0017] According to some embodiments, each of the plurality of inorganic patterns may include a first sub-pattern and a second sub-pattern, and the first sub-pattern and the second sub-pattern may be sequentially and repeatedly laminated.

[0018] According to some embodiments, the first sub-pattern may be silicon-rich (eg, have a higher silicon concentration) than the second sub-pattern, and the second sub-pattern may be nitrogen-rich (eg, have a higher nitrogen concentration) than the first sub-pattern.

[0019] According to some embodiments, a thickness of the first sub-pattern may be the same as a thickness of the second sub-pattern.

[0020] According to some embodiments of the present disclosure, a display panel includes: a base layer; a pixel defining film on the base layer and defining a light-emitting opening in the pixel defining film; a partition wall on the pixel defining film and defining a partition wall opening overlapping the light-emitting opening in the partition wall; a light-emitting element including an anode, an intermediate layer and a cathode in contact with the partition wall and located in the partition wall opening; a first lower encapsulation inorganic pattern on the cathode and reflecting light having an ultraviolet wavelength region; a second lower encapsulation inorganic pattern on the first lower encapsulation inorganic pattern; and a lower organic layer between the first lower encapsulation inorganic pattern and the partition wall.

[0021] According to some embodiments, the display panel may further include: an encapsulation organic film on the second lower encapsulation inorganic pattern, wherein the lower organic layer may include an inner portion and a boundary portion contacting the encapsulation organic film.

[0022] According to some embodiments, the first lower encapsulation inorganic pattern may include a plurality of inorganic patterns that are repeatedly laminated.

[0023] According to some embodiments, thicknesses of the plurality of inorganic patterns may be the same, and a thickness of one inorganic pattern among the plurality of inorganic patterns may be in a range of 175 nm to 200 nm.

[0024] According to some embodiments, each of the plurality of inorganic patterns may include a first sub-pattern and a second sub-pattern sequentially and repeatedly laminated, and the first sub-pattern may include silicon nitride (SiN) rich in silicon (eg, having a higher silicon concentration) than the second sub-pattern. x ), and the second sub-pattern may include silicon nitride (SiN) rich in nitrogen (eg, having a higher nitrogen concentration) than the first sub-pattern. x ).

[0025] According to some embodiments of the present disclosure, a method for manufacturing a display panel includes: providing a preliminary display panel, the preliminary display panel including a base layer, a pixel defining film on the base layer, a first preliminary partition wall layer on the pixel defining film, and a second preliminary partition wall layer on the first preliminary partition wall layer; etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a first partition wall layer and a second partition wall layer, wherein partition wall openings are defined in the first partition wall layer and the second partition wall layer; forming a light-emitting pattern and a cathode in the partition wall opening; forming a lower encapsulation inorganic pattern on the cathode; and forming a lower organic layer between the second partition wall layer and the lower encapsulation inorganic pattern.

[0026] According to some embodiments, the formation of the lower organic layer may include: depositing a preliminary lower organic layer on the second partition wall layer and the lower encapsulation inorganic pattern; irradiating the preliminary lower organic layer with light; and removing the remaining portion of the preliminary lower organic layer except for a portion of the preliminary lower organic layer formed under the lower encapsulation inorganic pattern.

[0027] According to some embodiments, the formation of the lower encapsulation inorganic pattern may include: depositing a 1-1 sublayer on the cathode; and depositing a 2-1 sublayer on the 1-1 sublayer, wherein the 1-1 sublayer and the 2-1 sublayer form a first inorganic layer, and the thickness of the first inorganic layer may be half the wavelength of the light.

[0028] According to some embodiments, depositing the 1-1th sub-layer on the cathode may include: inputting a silicon-containing gas and an argon gas; and inputting a nitrogen-containing gas and an argon gas.

[0029] According to some embodiments, depositing the 2-1 sub-layer on the 1-1 sub-layer may include: inputting a silicon-containing gas, a nitrogen-containing gas, and an argon gas; and inputting a nitrogen-containing gas and an argon gas. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0031] Figure 1A is a perspective view of a display device according to some embodiments of the present disclosure.

[0032] Figure 1B is an exploded perspective view of a display device according to some embodiments of the present disclosure.

[0033] Figure 2 is a cross-sectional view of a display module according to some embodiments of the present disclosure.

[0034] Figure 3 is a plan view of a display panel according to some embodiments of the present disclosure.

[0035] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to some embodiments of the present disclosure.

[0036] Figure 5 According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the display panel taken along line II'.

[0037] Figure 6 yes Figure 5 Magnified view of area AA'.

[0038] Figure 7 It is along Figure 4 Cross-sectional view along line II-II'.

[0039] FIG. 8A to FIG. 8N are cross-sectional views or schematic diagrams illustrating some of the operations of a method of manufacturing a display panel according to some embodiments of the present disclosure.

[0040] 9A to 9E are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] In the specification, the expression that a first component (or region, layer, portion, part, etc.) is "on", "connected with" or "coupled to" a second component means that the first component is directly on, connected with or coupled to the second component, or that a third component is located therebetween.

[0042] The same reference numerals refer to the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, ratio and size of the components are exaggerated. The expression "and / or" includes one or more combinations that the related components can define.

[0043] Although the terms "first", "second", etc. can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise clearly stated in the context, a singular expression includes a plural expression.

[0044] In addition, the terms "under", "below", "on", "above" and the like are used to describe the relationship between components illustrated in the drawings. Conceptually relative terms are described based on directions illustrated in the drawings.

[0045] It will be understood that the terms "include", "comprising", "having" and the like indicate the presence of the features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with that in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0047] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1A is a perspective view of a display device DD according to some embodiments of the present disclosure, and Figure 1B is an exploded perspective view of a display device DD according to some embodiments of the present disclosure.

[0049] According to some embodiments, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer (PC) (e.g., a laptop), a personal digital terminal, a vehicle navigation unit, a game console, a smart phone, a tablet PC, and a camera. However, this is illustrative, and other display devices may be employed as long as they do not deviate from the concept of the embodiments according to the present disclosure. Figure 1A and Figure 1B It is illustratively illustrated that the display device DD is a smartphone.

[0050] refer to Figure 1A and Figure 1B , the display device DD can display an image IM in a third direction DR3 on a display surface FS parallel to the first direction DR1 and the second direction DR2. The image IM may include a still image (eg, a static image) and a dynamic image (eg, a video image). Figure 1A , a clock window and an icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0051] According to some embodiments, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may face each other in a third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. At the same time, the directions indicated by the first direction to the third directions DR1, DR2, and DR3 are relative concepts and may be changed to other directions. In the specification, the phrase "on a plane" or "in a plan view" refers to a state when viewed in the third direction DR3 or from the third direction DR3.

[0052] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to constitute an appearance of the display device DD.

[0053] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0054] The border area BZA may be an area having a relatively lower transmittance than the transmittance of the transmission area TA. The border area BZA may define the shape of the transmission area TA. The border area BZA may be adjacent to the transmission area TA (e.g., at its periphery or outside its coverage area) and surround the transmission area TA. However, this is illustrative, and the border area BZA of the window WP may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited thereto.

[0055] The display module DM may be located under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and is visually recognized by a user from the outside through the transmission area TA.

[0056] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA (e.g., at its periphery or outside its coverage area). The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the bezel area BZA and may not be visually recognized or perceived by a user from the outside.

[0057] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide an inner space (eg, a set or predetermined inner space) or cavity. The display module DM may be accommodated in the inner space.

[0058] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the components of the display device DD housed in the internal space from external impacts.

[0059] Figure 2 is a cross-sectional view of a display module DM according to some embodiments of the present disclosure.

[0060] refer to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. According to some embodiments, the display device DD according to some embodiments of the present disclosure (see Figure 1A ) may further include a protection member on the lower surface of the display panel DP or an anti-reflection member and / or a window member on the upper surface of the input sensor INS.

[0061] The display panel DP may be a light-emitting display panel. However, this is illustrative, and the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro light-emitting diodes (LEDs). Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0062] The display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE arranged on the base layer BL. The input sensor INS may be directly located on the thin film encapsulation layer TFE. In the specification, the wording "component A is directly located on component B" means that there is no adhesive layer between component A and component B.

[0063] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The display area DA and the non-display area NDA described in FIG.

[0064] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and pixel driving circuits, etc.

[0065] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0066] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be arranged to relatively improve optical efficiency, and some of which may be arranged to protect the organic light emitting diode.

[0067] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. In addition, the input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may sense the external input in a capacitive manner. However, this is illustrative, and the present disclosure is not limited thereto. For example, according to some embodiments, the input sensor INS may also sense the external input in an electromagnetic induction manner or a pressure sensing manner. Meanwhile, according to some embodiments of the present disclosure, the input sensor INS may be omitted.

[0068] Figure 3 is a plan view of a display panel DP according to some embodiments of the present disclosure.

[0069] refer to Figure 3 , a display area DA and a non-display area NDA around the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished depending on whether the pixel PX is set. The pixel PX may be located in the display area DA. The drive circuit GDC and the pad portion PLD may be arranged in the non-display area NDA.

[0070] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0071] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel among the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0072] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0073] The pad portion PLD may be a portion to which the flexible circuit board is connected. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pad D-PD may be connected to a corresponding pixel PX through the signal line SGL. In addition, any one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0074] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see Figure 2 However, the present disclosure is not limited thereto, and the input pad may be arranged on the input sensor INS (see Figure 2 ) and connected to the pixel pad D-PD and a separate circuit board. Alternatively, the input sensor INS (see Figure 2 ) may be omitted and may not further include an input pad. Figure 4is a display panel DP according to some embodiments of the present disclosure (see Figure 2 ) display area DA (see Figure 2 ) is an enlarged plan view of a portion of the ). Figure 4 The diagram shows the operation of the display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) is a plan view of the display module DM when viewed from above, and illustrates the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0075] refer to Figure 4 , the display area DA may include first to third light-emitting areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA surrounding the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may correspond to areas from which light provided from the light-emitting element is emitted, respectively. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged according to the direction toward the display module DM (see Figure 2 ) is classified by the color of the light emitted externally.

[0076] The first to third light emitting areas PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0077] Each of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be defined as an area in which the upper surface of the anode is exposed by a light-emitting opening to be described below. The peripheral area NPXA may set a boundary between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B, and prevent color mixing between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B.

[0078] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be provided so that the number thereof is all plural, and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be repeatedly arranged in a specific arrangement form in the display area DA. For example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may be alternately arranged in the first direction DR1 to constitute a "first group". The second light-emitting area PXA-G may be arranged in the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0079] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0080] at the same time, Figure 4 The arrangement form of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B is illustratively illustrated, but according to the embodiments of the present disclosure, it is not limited thereto and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged in various forms. According to some embodiments, as Figure 4 As shown in FIG. 1 , the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have Alternatively, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may also have a stripe arrangement or a diamond arrangement. Layout form.

[0081] On a plane (or in a plan view), the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have various shapes. For example, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have a shape such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a diamond shape) on a plane (or in a plan view) and the second light emitting region PXA-G having an octagonal shape are illustratively illustrated.

[0082] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape on a plane (or in a plan view), or may have at least partially different shapes. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape on a plane (or in a plan view) and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are illustratively illustrated.

[0083] At least some of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different areas on a plane (or in a plan view). According to some embodiments, the area of ​​the first light-emitting area PXA-R emitting red light may be larger than the area of ​​the second light-emitting area PXA-G emitting green light, and may be smaller than the area of ​​the third light-emitting area PXA-B emitting blue light. However, the size relationship between the areas of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B according to the color of the emitted light is not limited thereto, and may depend on the display module DM (see Figure 2 ) is changed in design. In addition, the embodiment according to the present disclosure is not limited thereto, and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may also have the same area on a plane (or in a plan view).

[0084] Meanwhile, the display module DM (see Figure 2 The shapes, areas, and arrangements of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B can be determined according to the color of the emitted light or the display module DM (see Figure 2 ) are variously designed in size and configuration and are not limited to Figure 4 The embodiment shown in FIG.

[0085] Figure 5 According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the display panel DP taken along line II'. Figure 5 In the description of Figure 2 Description will be made, and description of the same figure numbers will be omitted.

[0086] Figure 5 The display area DA is shown in an enlarged manner (see Figure 4 ) in a light emitting area PXA, and Figure 5 The luminous area PXA can be Figure 4 The first to third light-emitting areas PXA-R, PXA-G and PXA-B correspond to one of the first to third light-emitting areas. Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0087] The display panel DP may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, a plurality of signal lines, etc. The insulating layers, the semiconductor layers, and the conductive layers are formed by coating or deposition, etc. Thereafter, the insulating layers, the semiconductor layers, and the conductive layers may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0088] The circuit element layer DP-CL may be located on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0089] The buffer layer BFL may be located on the base layer BL. The buffer layer BFL may relatively improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately laminated.

[0090] The semiconductor pattern may be located on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the embodiment according to the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 A portion of the semiconductor pattern is illustratively illustrated, and the semiconductor pattern may be further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 4 ). The semiconductor pattern may be arranged in a specific rule throughout the plurality of light emitting regions PXA-R, PXA-G, and PXA-B. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0091] The conductivity of the first region is greater than that of the second region, and the first region can substantially act as an electrode or a signal line. The second region can substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be an active region of a transistor, another portion of the semiconductor pattern can be a source or drain of the transistor, and another portion of the semiconductor pattern can be a conductive region.

[0092] The source S, the active area A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is illustrated. According to some embodiments, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane (or in a plan view).

[0093] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, and 50 may be inorganic layers or organic layers.

[0094] The first insulating layer 10 may be located on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active area A, the drain D, and the signal transmission area SCL of the transistor TR1 located on the buffer layer BFL. The gate G of the transistor TR1 may be located on the first insulating layer 10. The second insulating layer 20 may be located on the first insulating layer 10 to cover the gate G. The electrode EE may be located on the second insulating layer 20. The third insulating layer 30 may be located on the second insulating layer 20 to cover the electrode EE.

[0095] The first connection electrode CNE1 may be located on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be located on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0096] The second connection electrode CNE2 may be located on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be located on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0097] The display element layer DP-OLED may be located on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, and a partition wall PW.

[0098] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0099] The anode AE ​​may be located on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter, referred to as a lower ITO layer), a layer located on the lower ITO layer and including Ag (hereinafter, referred to as an Ag layer), and a layer located on the Ag layer and including ITO (hereinafter, referred to as an upper ITO layer).

[0100] The sacrificial pattern SP may be located between the anode AE ​​and the pixel defining film PDL. A sacrificial opening OP-S through which a portion of the upper surface of the anode AE ​​is exposed may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with the light emitting opening OP-E, which will be described below.

[0101] The pixel defining film PDL may be located on the fifth insulating layer 50 of the circuit element layer DP-CL. The light emitting opening OP-E may be defined by the pixel defining film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0102] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to some embodiments, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in a cross section, the sacrificial pattern SP is interposed between the upper surface of the anode AE ​​and the pixel defining film PDL, and accordingly, damage to the anode AE ​​may be prevented in a process of forming the light emitting opening OP-E.

[0103] On a plane (or in a plan view), the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner surface of the pixel defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the embodiments according to the present disclosure are not limited thereto, and the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel defining film PDL defining the light-emitting opening OP-E. In this case, the light-emitting area PXA may be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0104] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be located between the anode AE ​​and the partition wall PW, and blocks electrical connection between the anode AE ​​and the partition wall PW.

[0105] The light emitting pattern EP may be located on the anode AE. The light emitting pattern EP may include a light emitting layer including a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the light emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light emitting layer. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0106] The light emitting pattern EP may be patterned by a tip portion defined by the partition wall PW. The light emitting pattern EP may be located inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0107] The cathode CE may be located on the light emitting pattern EP. The cathode CE may be patterned by a tip portion defined by the partition wall PW. At least a portion of the cathode CE may be located in the partition wall opening OP-P. The cathode CE may be adjacent to the first inner surface S-L1 (see FIG. 1 ) of the first partition wall layer L1. Fig.8D ) contact. The cathode CE may be conductive. The cathode CE may be formed of various materials such as metals, transparent conductive oxides (TCOs), and conductive polymer materials, as long as these materials can conduct electricity. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0108] The partition wall PW may be located on the pixel defining film PDL. A partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE.

[0109] In cross section, the partition wall PW may have an undercut shape. The partition wall PW may include a plurality of layers laminated sequentially, and at least one of the plurality of layers may be recessed compared to the other layers. Accordingly, the partition wall PW may include a tip portion.

[0110] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be located on the pixel definition layer PDL, and the second partition wall layer L2 may be located on the first partition wall layer L1. Figure 5 As shown in FIG. 1 , the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but embodiments according to the present disclosure are not limited thereto.

[0111] The first partition wall layer L1 may be relatively recessed relative to the light emitting area PXA compared to the second partition wall layer L2. The first partition wall layer L1 may be formed to be undercut relative to the second partition wall layer L2. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the light emitting area PXA may be defined as a tip portion inside the partition wall PW.

[0112] The partition wall opening OP-P defined in the partition wall PW may include a first area A1 and a second area A2. The first partition wall layer L1 may include a first inner surface of the first area A1 defining the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner surface defining the second area A2. In cross section, the second inner surface of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the first inner surface of the first partition wall layer L1. The first inner surface may be recessed from the second inner surface in a direction away from the center of the anode AE. Accordingly, the second partition wall layer L2 protruding toward the light emitting area PXA may include a tip portion.

[0113] The width of the first region A1 may be different from the width of the second region A2. The width of the first region A1 may be greater than the width of the second region A2. In this case, the second region A2 of the partition wall opening OP-P may be a region defining a tip portion.

[0114] The first partition wall layer L1 and the second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a TCO, or a combination thereof. For example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0115] Figure 5 It is illustratively illustrated that each of the first inner surface and the second inner surface is perpendicular to the upper surface of the pixel defining film PDL, but embodiments according to the present disclosure are not limited thereto. For example, the partition wall PW may have a tapered shape or an inverse tapered shape.

[0116] The partition wall PW may receive the second driving voltage, and accordingly, the cathode CE may be electrically connected to the partition wall PW to receive the second driving voltage.

[0117] The thin film encapsulation layer TFE may be located on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0118] The lower encapsulation inorganic pattern LIL may correspond to the light emitting opening OP-E. The lower encapsulation inorganic pattern LIL may be located on the cathode CE. For example, the lower encapsulation inorganic pattern LIL may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 of the lower encapsulation inorganic pattern LIL may be located inside the partition wall opening OP-P, and the second portion P2 of the lower encapsulation inorganic pattern LIL may extend from the first portion P1 in the thickness direction of the base layer BL (e.g., the third direction DR3). The third portion P3 of the lower encapsulation inorganic pattern LIL may extend from the second portion P2 in a direction away from the partition wall opening OP-P, and may be spaced apart from the partition wall PW in cross section. That is, a portion of the lower encapsulation inorganic pattern LIL may be formed inside the partition wall opening OP-P, and another portion of the lower encapsulation inorganic pattern LIL may be formed on the partition wall PW.

[0119] In addition, the lower encapsulation inorganic pattern LIL may include a first lower encapsulation inorganic pattern LIL1 and a second lower encapsulation inorganic pattern LIL2. The first lower encapsulation inorganic pattern LIL1 and the second lower encapsulation inorganic pattern LIL2 may be sequentially arranged on the cathode CE.

[0120] The lower organic layer BOL may be located between the lower encapsulation inorganic pattern LIL and the partition wall PW. For example, in a cross section, the lower organic layer BOL may be located between the third portion P3 of the lower encapsulation inorganic pattern LIL and the partition wall PW. The region in which the lower organic layer BOL is formed may be a region in which a dummy layer (e.g., a first dummy layer DMP1-I, see FIG. 1 ) is formed and removed during a process of manufacturing a display panel. Figure 8F ) area, which will be described below.

[0121] The lower organic layer BOL may include an inner portion IP and a boundary portion BP. The inner portion IP of the lower organic layer BOL may be a portion located between the third portion P3 of the lower encapsulation inorganic pattern LIL and the partition wall PW. The boundary portion BP of the lower organic layer BOL may be formed by surrounding the inner portion IP on a plane (or in a plan view). The inner portion IP and the boundary portion BP may have an integral shape, but may have different materials. For example, the boundary portion BP may include a material obtained by changing a portion of the inner portion IP by means of a chemical reaction.

[0122] exist Figure 5 In the embodiment, the side surface of the lower encapsulation inorganic pattern LIL has a shape inclined at an angle (e.g., a set or predetermined angle) relative to the side surface of the lower organic layer BOL, but the embodiments according to the present disclosure are not limited to the above examples. For example, the side surface of the lower encapsulation inorganic pattern LIL and the side surface of the lower organic layer BOL may be aligned with each other.

[0123] The encapsulation organic film OL may be located on the lower encapsulation inorganic pattern LIL. The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The lower organic layer BOL may contact the encapsulation organic film OL. For example, a boundary portion BP of the lower organic layer BOL may contact the encapsulation organic film OL.

[0124] The upper encapsulation inorganic film UIL may be located on the encapsulation organic film OL. The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign matter such as dust particles.

[0125] According to some embodiments of the present disclosure, the display panel DP may further include a capping pattern. The capping pattern may be located inside the partition wall opening OP-P and on the cathode CE. The capping pattern may be patterned by a tip portion formed in the partition wall PW.

[0126] Figure 6 yes Figure 5 Magnified view of area AA'.

[0127] refer to Figure 5 and Figure 6 , the first lower package inorganic pattern LIL1 may include a plurality of inorganic patterns S1, S2, S3, S4, and S5 that are repeatedly laminated. Each of the plurality of inorganic patterns S1, S2, S3, S4, and S5 may include silicon nitride (SiN x ). Each of the plurality of inorganic patterns S1, S2, S3, S4, and S5 may include a first sub-pattern SB1 and a second sub-pattern SB2. The first sub-pattern SB1 may include first sub-patterns SB11, SB12, SB13, SB14, and SB15, and the second sub-pattern SB2 may include second sub-patterns SB21, SB22, SB23, SB24, and SB25. The first sub-patterns SB11, SB12, SB13, SB14, and SB15 and the second sub-patterns SB21, SB22, SB23, SB24, and SB25 may be sequentially and repeatedly laminated.

[0128] For example, the plurality of inorganic patterns S1, S2, S3, S4, and S5 may include a first inorganic pattern S1, a second inorganic pattern S2, a third inorganic pattern S3, a fourth inorganic pattern S4, and a fifth inorganic pattern S5. The first inorganic pattern S1 may include a 1-1st sub-pattern SB11 as a first sub-pattern SB1 and a 2-1st sub-pattern SB21 as a second sub-pattern SB2. The second inorganic pattern S2 may include a 1-2nd sub-pattern SB12 as a first sub-pattern SB1 and a 2-2nd sub-pattern SB22 as a second sub-pattern SB2. The third inorganic pattern S3 may include a 1-3rd sub-pattern SB13 as a first sub-pattern SB1 and a 2-3rd sub-pattern SB23 as a second sub-pattern SB2. The fourth inorganic pattern S4 may include a 1-4th sub-pattern SB14 as a first sub-pattern SB1 and a 2-4th sub-pattern SB24 as a second sub-pattern SB2. The fifth inorganic pattern S5 may include 1-5th sub-pattern SB15 as the first sub-pattern SB1 and 2-5th sub-pattern SB25 as the second sub-pattern SB2.

[0129] The 1-1st sub-pattern SB11, the 2-1st sub-pattern SB21, the 1-2nd sub-pattern SB12, the 2-2nd sub-pattern SB22, the 1-3rd sub-pattern SB13, the 2-3rd sub-pattern SB23, the 1-4th sub-pattern SB14, the 2-4th sub-pattern SB24, the 1-5th sub-pattern SB15, and the 2-5th sub-pattern SB25 may be sequentially laminated on the cathode CE. In this case, one of the first sub-patterns SB11, SB12, SB13, SB14, and SB15 and one of the second sub-patterns SB21, SB22, SB23, SB24, and SB25 may be sequentially and alternately laminated.

[0130] Each of the first sub-pattern SB1 and the second sub-pattern SB2 may include silicon nitride (SiN x The first sub-pattern SB1 may be rich in silicon (Si-rich) (e.g., having a relatively high concentration) compared to the second sub-pattern SB2, and the second sub-pattern SB2 may be rich in nitrogen (N-rich) (e.g., having a relatively high concentration) compared to the first sub-pattern SB1. That is, the first sub-pattern SB1 may be a silicon-rich (Si-rich) silicon nitride (SiN x ) layer, and the second sub-pattern SB2 may be a nitrogen-rich (N-rich) silicon nitride (SiN x )layer.

[0131] The thickness T_S of one of the plurality of inorganic patterns S1, S2, S3, S4 and S5 may be 175nm or more and 200nm or less. The thickness T_S of each of the plurality of inorganic patterns S1, S2, S3, S4 and S5 may be substantially the same. The plurality of inorganic patterns S1, S2, S3, S4 and S5 may have a distributed Bragg reflector (DBR) characteristic. That is, the plurality of inorganic patterns S1, S2, S3, S4 and S5 may reflect light having a specific wavelength range. For example, the plurality of inorganic patterns S1, S2, S3, S4 and S5 may reflect light having a wavelength of 350nm to 400nm.

[0132] The thickness of the first sub-pattern SB1 may be the same as the thickness of the second sub-pattern SB2. However, this is illustrative, and the thickness of the first sub-pattern SB1 and the thickness of the second sub-pattern SB2 are not limited to the above examples. For example, the thickness of the first sub-pattern SB1 may be less than or greater than the thickness of the second sub-pattern SB2.

[0133] Figure 6 The plurality of inorganic patterns S1, S2, S3, S4 and S5 are illustratively illustrated to include five inorganic patterns S1, S2, S3, S4 and S5, but the embodiments according to the present disclosure are not limited to the above examples. For example, the plurality of inorganic patterns may include two to four inorganic patterns, or may include six or more inorganic patterns.

[0134] The second lower encapsulation inorganic pattern LIL2 may be located on the first lower encapsulation inorganic pattern LIL1. The thickness of the second lower encapsulation inorganic pattern LIL2 may be greater than the thickness of the first lower encapsulation inorganic pattern LIL1. However, the embodiment according to the present disclosure is not limited to the above example, and the thickness of the second lower encapsulation inorganic pattern LIL2 may be equal to or less than the thickness of the first lower encapsulation inorganic pattern LIL1.

[0135] According to the present disclosure, the lower package inorganic pattern LIL may include a plurality of inorganic patterns S1, S2, S3, S4, and S5, and the plurality of inorganic patterns S1, S2, S3, S4, and S5 may include silicon nitride (SiN x ). Due to the inclusion of silicon nitride (SiN x ) cover the partition wall PW, so the phenomenon of the lower package inorganic pattern LIL being oxidized by foreign matter introduced from the side surface of the first partition wall layer L1, the lower surface of the second partition wall layer L2 and the side surface of the second partition wall layer L2 can be relatively reduced or eliminated.

[0136] In addition, since the display panel DP includes the lower organic layer BOL between the partition wall PW and the lower encapsulation inorganic pattern LIL, the phenomenon of foreign matter being introduced between the partition wall PW and the lower encapsulation inorganic pattern LIL can be relatively reduced or eliminated. Therefore, pixel defects (dark spots or pixel shrinkage, etc.) of the display panel DP caused by foreign matter can be relatively reduced or eliminated.

[0137] Figure 7 It is along Figure 4 Cross-sectional view along line II-II'. Figure 7 A first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B are shown in an enlarged manner, and Figure 5 The description of a luminous area PXA can be applied similarly to Figure 7 The first to third light-emitting areas PXA-R, PXA-G and PXA-B.

[0138] refer to Figure 7 According to some embodiments, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, and a partition wall PW.

[0139] The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided in a plurality of patterns. According to some embodiments, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0140] The first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the pixel defining film PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3. According to some embodiments, the first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 that is exposed by the first light emitting opening OP1-E. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 that is exposed by the second light emitting opening OP2-E. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 that is exposed by the third light emitting opening OP3-E.

[0141] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, and SP3 may be arranged on upper surfaces of the first to third anodes AE1, AE2, and AE3, respectively. First to third sacrificial openings OP1-S, OP2-S, and OP3-S overlapping the first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the first to third sacrificial patterns SP1, SP2, and SP3, respectively.

[0142] According to some embodiments, first to third partition wall openings OP1-P, OP2-P, and OP3-P respectively overlapping the first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the partition wall PW. Each of the first to third partition wall openings OP1-P, OP2-P, and OP3-P may include Figure 5 The first area A1 described in Figure 5 ) and the second area A2 (see Figure 5 ). The first partition wall layer L1 may include a first inner surface S-L1 (see FIG. 2 ) of a first region A1 defining first to third partition wall openings OP1-P, OP2-P, and OP3-P. Fig.8D ), and the second partition wall layer L2 may include a second inner surface S-L2 (see FIG. 1 ) of the second region A2 defining the first partition wall opening to the third partition wall openings OP1-P, OP2-P, and OP3-P. Fig.8D ).

[0143] The first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P.

[0144] According to some embodiments, the first to third light emitting patterns EP1, EP2, and EP3 and the first to third cathodes CE1, CE2, and CE3 may be physically separated by a second partition wall layer L2 forming a tip portion, and may be formed inside the light emitting openings OP1-E, OP2-E, and OP3-E and the partition wall openings OP1-P, OP2-P, and OP3-P.

[0145] According to the present disclosure, a plurality of first light emission patterns EP1 may be patterned and deposited in units of pixels through tip portions defined in the partition wall PW. That is, the plurality of first light emission patterns EP1 may be commonly formed using an open mask but may be easily divided in units of pixels through the partition wall PW.

[0146] On the other hand, when the first light emitting pattern EP1 is patterned using a fine metal mask (FMM), a support spacer protruding from the conductive partition wall to support the FMM should be provided. In addition, since the FMM is spaced from the height of the partition wall PW and the spacer from the substrate surface on which patterning is performed, the realization of high resolution may be limited. In addition, since the FMM is in contact with the spacer, after the patterning process of the first light emitting pattern EP1, the spacer may be damaged due to foreign matter remaining on the spacer or stamping of the FMM. Accordingly, a defective display panel may be formed.

[0147] According to some embodiments, a partition wall PW is included so that physical separation between the light emitting elements ED1, ED2, and ED3 can be easily performed. Accordingly, current leakage or driving errors between adjacent light emitting areas PXA-R, PXA-G, and PXA-B can be prevented, and independent driving of each of the light emitting elements ED1, ED2, and ED3 can be performed.

[0148] Specifically, since the plurality of first light emitting patterns EP1 are not used in the display area DA (see Figure 1B ) is patterned without a mask that contacts the internal components inside, so the defect rate is relatively reduced, and thus a display panel DP with relatively improved process reliability can be provided. Since patterning can be performed even when a separate supporting spacer protruding from the partition wall PW is not provided, the areas of the light emitting areas PXA-R, PXA-G, and PXA-B can be minimized, and thus a display panel DP that easily achieves high resolution can be provided.

[0149] In addition, when manufacturing a large-area display panel DP, a display panel DP in which process cost can be relatively reduced due to the omission of production of a large-area mask can be provided, and since the display panel DP is not affected by defects that may occur in the large-area mask, process reliability can be relatively improved. The description of the plurality of first light emitting patterns EP1 can be similarly applied to the plurality of second light emitting patterns EP2 and the plurality of third light emitting patterns EP3.

[0150] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1 and LIL2 , lower organic layers BOL1 , BOL2 , and BOL3 , an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0151] According to some embodiments, the lower encapsulation inorganic patterns LIL1 and LIL2 may include a first lower encapsulation inorganic pattern LIL1 and a second lower encapsulation inorganic pattern LIL2. The first lower encapsulation inorganic pattern LIL1 may include a 1-1 lower encapsulation inorganic pattern LIL11, a 1-2 lower encapsulation inorganic pattern LIL12, and a 1-3 lower encapsulation inorganic pattern LIL13, and the 1-1 lower encapsulation inorganic pattern LIL11, the 1-2 lower encapsulation inorganic pattern LIL12, and the 1-3 lower encapsulation inorganic pattern LIL13 may be provided in a pattern form in which the 1-1 lower encapsulation inorganic pattern LIL11, the 1-2 lower encapsulation inorganic pattern LIL12, and the 1-3 lower encapsulation inorganic pattern LIL13 are spaced apart from each other. The second lower encapsulation inorganic pattern LIL2 may include a 2-1st lower encapsulation inorganic pattern LIL21, a 2-2nd lower encapsulation inorganic pattern LIL22, and a 2-3rd lower encapsulation inorganic pattern LIL23, and the 2-1st lower encapsulation inorganic pattern LIL21, the 2-2nd lower encapsulation inorganic pattern LIL22, and the 2-3rd lower encapsulation inorganic pattern LIL23 may be provided in a pattern form in which the 2-1st lower encapsulation inorganic pattern LIL21, the 2-2nd lower encapsulation inorganic pattern LIL22, and the 2-3rd lower encapsulation inorganic pattern LIL23 are spaced apart from each other.

[0152] The first lower package inorganic pattern LIL1 and the second lower package inorganic pattern LIL2 may overlap with the first to third light emitting openings OP1-E, OP2-E, and OP3-E. For example, the 1-1st lower package inorganic pattern LIL11 and the 2-1st lower package inorganic pattern LIL21 may overlap with the first light emitting opening OP1-E, the 1-2nd lower package inorganic pattern LIL12 and the 2-2nd lower package inorganic pattern LIL22 may overlap with the second light emitting opening OP2-E, and the 1-3rd lower package inorganic pattern LIL13 and the 2-3rd lower package inorganic pattern LIL23 may overlap with the third light emitting opening OP3-E.

[0153] The lower organic layers BOL1, BOL2, and BOL3 may include a first lower organic layer BOL1, a second lower organic layer BOL2, and a third lower organic layer BOL3. In cross section, the first lower organic layer BOL1 may be formed between the 1-1 lower encapsulation inorganic pattern LIL11 and the partition wall PW defining the first partition wall opening OP1-P. In cross section, the second lower organic layer BOL2 may be formed between the 1-2 lower encapsulation inorganic pattern LIL12 and the partition wall PW defining the second partition wall opening OP2-P. In cross section, the third lower organic layer BOL3 may be formed between the 1-3 lower encapsulation inorganic pattern LIL13 and the partition wall PW defining the third partition wall opening OP3-P.

[0154] FIG. 8A to FIG. 8N are cross-sectional views or schematic diagrams illustrating some of the operations of a method of manufacturing a display panel according to some embodiments of the present disclosure. 9A to 9E are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to some embodiments of the present disclosure. FIG. 8A to FIG. 9E In the description of Figures 1A to 7 For the same / similar parts, the same / similar reference numerals will be used and their repeated description will be omitted.

[0155] The method for manufacturing a display panel according to the present disclosure may include: an operation of providing a preliminary display panel, the preliminary display panel including a base layer, a pixel defining film located on the base layer, a first preliminary partition wall layer located on the pixel defining film, and a second preliminary partition wall layer located on the first preliminary partition wall layer; an operation of etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a first partition wall layer and a second partition wall layer defining a partition wall opening therein; an operation of forming a light-emitting pattern and a cathode within the partition wall opening; an operation of forming a lower encapsulation inorganic pattern on the cathode; and an operation of forming a lower organic layer between the second partition wall layer and the lower encapsulation inorganic pattern.

[0156] In the following, we will FIG. 8A to FIG. 9E A method of forming two light emitting elements ED1 and ED2, lower encapsulation inorganic patterns LIL11, LIL12, LIL21, and LIL22 covering the light emitting elements ED1 and ED2, lower organic layers BOL1 and BOL2, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL is described. FIG. 8A to FIG. 9E The display panel DP formed can be Figure 3 Corresponding to a portion of the display panel DP.

[0157] refer to Fig. 8AThe method of manufacturing a display panel according to some embodiments may include an operation of providing a preliminary display panel DP-I. The preliminary display panel DP-I according to some embodiments may include a base layer BL, a circuit element layer DP-CL, a first anode AE1 and a second anode AE2, a first sacrificial layer SP1-I and a second sacrificial layer SP2-I, a pixel defining layer PDL, a first preliminary partition wall layer L1-I, and a second preliminary partition wall layer L2-I.

[0158] The circuit element layer DP-CL can be formed by a general method of manufacturing circuit elements in which an insulating layer, a semiconductor layer, and a conductive layer are formed by a coating method or a deposition method, the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned by a photolithography and etching process, and a semiconductor pattern, a conductive pattern, or a signal line is formed.

[0159] The first anode AE1 and the first sacrificial layer SP1-I may be formed by the same patterning process, and the second anode AE2 and the second sacrificial layer SP2-I may be formed by the same patterning process. The pixel defining film PDL may be located on the base layer BL. The pixel defining film PDL may cover all of the first anode AE1 and the second anode AE2 and the first sacrificial layer SP1-I and the second sacrificial layer SP2-I.

[0160] The first preliminary partition wall layer L1-I may be located on the pixel definition film PDL. The first preliminary partition wall layer L1-I may be formed by a process of depositing a conductive material. The second preliminary partition wall layer L2-I may be located on the first preliminary partition wall layer L1-I. The second preliminary partition wall layer L2-I may also be formed by a process of depositing a conductive material. According to some embodiments, each of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include a conductive material. For example, the conductive material may include a metal, a TCO, or a combination thereof. For example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. However, the materials of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are not limited thereto. The first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may form a preliminary partition wall PW-I.

[0161] Afterwards, refer to Figure 8B, the method of manufacturing a display panel according to some embodiments may include an operation of forming a first photoresist layer PR1 on the preliminary partition wall PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first optical opening OP1-PR overlapping the first anode AE1 and a second optical opening OP2-PR overlapping the second anode AE2 may be formed in the first photoresist layer PR1.

[0162] Afterwards, refer to Figure 8C and Fig.8D , the method of manufacturing a display panel according to some embodiments may include forming a first partition wall layer L1 and a second partition wall layer L2 defining partition wall openings OP1-P and OP2-P therein by etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I so that the partition wall PW is formed by the preliminary partition wall PW-I (see Figure 8B ) operation.

[0163] First, if Figure 8C As shown in, the initial etching of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include an operation of forming preliminary partition wall openings OP1-PI and OP2-PI in the preliminary partition wall PW-I by using the first photoresist layer PR1 as a mask and dry etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I. The preliminary partition wall openings OP1-PI and OP2-PI may include a first preliminary partition wall opening OP1-PI and a second preliminary partition wall opening OP2-PI. The first preliminary partition wall opening OP1-PI may be formed to overlap with the first anode AE1, and the second preliminary partition wall opening OP2-PI may be formed to overlap with the second anode AE2.

[0164] The primary dry etching process according to some embodiments may be performed in an etching environment in which the etching selectivity ratio between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is substantially the same. Accordingly, the inner surface of the first preliminary partition wall layer L1-I and the inner surface of the second preliminary partition wall layer L2-I defining the preliminary partition wall openings OP1-PI and OP2-PI may be substantially aligned with each other.

[0165] Afterwards, if Fig.8D As shown in FIG. 1 , the first preliminary partition wall layer L1-I is etched twice (see Figure 8C The operation of performing etching may include using the first photoresist layer PR1 as a mask and wet etching the first preliminary partition wall layer L1-I to form preliminary partition wall openings OP1-PI and OP2-PI (see FIG. Figure 8C) Operation of forming partition wall openings OP1-P and OP2-P. The partition wall openings OP1-P and OP2-P may include a first partition wall opening OP1-P and a second partition wall opening OP2-P. The first partition wall opening OP1-P may be formed to overlap with the first anode AE1, and the second partition wall opening OP2-P may be formed to overlap with the second anode AE2.

[0166] Each of the partition wall openings OP1-P and OP2-P may include a first region A1 and a second region A2 sequentially formed in the thickness direction (i.e., the third direction DR3). The first partition wall layer L1 may include a first inner surface S-L1 of the first region A1 defining the partition wall openings OP1-P and OP2-P, and the second partition wall layer L2 may include a second inner surface S-L2 defining the second region A2.

[0167] The secondary wet etching process according to some embodiments may be performed in an environment where the etching selectivity ratio between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is large. Accordingly, the inner surface of the partition wall PW defining the partition wall openings OP1-P and OP2-P may have an undercut shape in cross section. For example, since the etching rate of the first partition wall layer L1 relative to the etching solution is greater than the etching rate of the second partition wall layer L2 relative to the etching solution, the first partition wall layer L1 may be mainly etched. Accordingly, the first inner surface S-L1 of the first partition wall layer L1 may be formed to be recessed inwardly than the second inner surface S-L2 of the second partition wall layer L2. A tip portion may be formed in the partition wall PW by a portion of the second partition wall layer L2 that further protrudes from the first partition wall layer L1.

[0168] According to some embodiments of the present disclosure, the operation of forming the partition wall opening OP-P may include simultaneously forming the partition wall openings OP1-P, OP2-P, and OP3-P (see Figure 7 ) operation. For ease of description, Figure 8C and Fig.8D The formation of the first light emitting region PXA-R (see Figure 4 ) and the second light emitting area PXA-G (see Figure 4) are formed. However, the embodiments according to the present disclosure are not limited to the above examples, and according to some embodiments of the present disclosure, the operation of forming the partition wall opening OP-P may include an operation of forming only the first partition wall opening OP1-P corresponding to the first light-emitting area PXA-R. For example, after the first partition wall opening OP1-P corresponding to the first light-emitting area PXA-R is formed and the first light-emitting element is formed by a subsequent process, the second partition wall opening OP2-P corresponding to the second light-emitting area PXA-G may be formed. In addition, by a subsequent process, the second light-emitting element may be formed, and the third partition wall opening OP3-P corresponding to the third light-emitting area PXA-B may be formed.

[0169] Afterwards, refer to Fig. 8E According to some embodiments, the method of manufacturing a display panel may include an operation of etching a pixel definition film PDL and an operation of etching a first sacrificial layer SP1-I (see Fig.8D ) and the second sacrificial layer SP2-I (see Fig.8D ). The etching of the pixel defining film PDL may be performed in a dry etching method, and the etching may be performed using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as a mask. A first light emitting opening OP1-E and a second light emitting opening OP2-E corresponding to the first partition wall opening OP1-P and the second partition wall opening OP2-P, respectively, may be formed in the pixel defining film PDL.

[0170] The etching of the sacrificial layers SP1-I and SP2-I may be performed in a wet etching method, and the etching may be performed using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as a mask. Sacrificial openings OP1-S and OP2-S overlapping the light-emitting openings OP1-E and OP2-E may be formed in the sacrificial patterns SP1 and SP2 formed by etching the sacrificial layers SP1-I and SP2-I. The sacrificial openings OP1-S and OP2-S may include a first sacrificial opening OP1-S overlapping the first light-emitting opening OP1-E and a second sacrificial opening OP2-S overlapping the second light-emitting opening OP2-E. At least a portion of the anodes AE1 and AE2 may be exposed from the sacrificial patterns SP1 and SP2 and the pixel defining film PDL through the sacrificial openings OP1-S and OP2-S and the light-emitting openings OP1-E and OP2-E.

[0171] The etching process of the sacrificial patterns SP1 and SP2 may be performed in an environment in which an etching selectivity ratio between the sacrificial patterns SP1 and SP2 and the anodes AE1 and AE2 is high, and thus, the anodes AE1 and AE2 may be prevented from being etched together. That is, since the sacrificial patterns SP1 and SP2 having an etching rate higher than that of the anodes AE1 and AE2 are arranged between the pixel defining film PDL and the anodes AE1 and AE2, the anodes AE1 and AE2 may be prevented from being etched together and damaged during the etching process.

[0172] Afterwards, refer to Figure 8F According to some embodiments, the method for manufacturing a display panel may include: removing the first photoresist layer PR1 (see Fig. 8E ), after which an operation of forming a first light emitting pattern EP1 and a first cathode CE1 inside the partition wall openings OP1-P and OP2-P.

[0173] The operation of forming the first light emitting pattern EP1 may be performed by a deposition process. According to some embodiments, the operation of forming the first light emitting pattern EP1 may include a thermal evaporation process. The first light emitting pattern EP1 may be formed on the anodes AE1 and AE2. The first light emitting pattern EP1 may be separated by a tip portion formed in the partition wall PW and located inside the light emitting openings OP1-E and OP2-E and the partition wall openings OP1-P and OP2-P.

[0174] In the operation of forming the first light emitting pattern EP1, a 1-1 dummy layer D11-I spaced apart from the first light emitting pattern EP1 may be formed together on the partition wall PW. The 1-1 dummy layer D11-I may include an organic material. For example, the 1-1 dummy layer D11-I may include the same material as that of the first light emitting pattern EP1. The 1-1 dummy layer D11-I may be simultaneously formed with the first light emitting pattern EP1 through one process, and may be formed separately from the first light emitting pattern EP1 by the undercut shape of the partition wall PW.

[0175] The operation of forming the first cathode CE1 may be performed by a deposition process. According to some embodiments, the operation of forming the first cathode CE1 may include a sputtering process. The first cathode CE1 may be formed on the first light emitting pattern EP1. The first cathode CE1 may be separated by a tip portion formed in the partition wall PW and located inside the partition wall openings OP1-P and OP2-P. The first cathode CE1 may be provided at an incident angle higher than that of the first light emitting pattern EP1, and the first cathode CE1 may be formed to contact the first inner surface S-L1 of the first partition wall layer L1. The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may constitute the first light emitting element ED1.

[0176] In the operation of forming the first cathode CE1, a 2-1st dummy layer D21-I spaced apart from the first cathode CE1 may be formed together on the partition wall PW. The 2-1st dummy layer D21-I may include a conductive material. For example, the first cathode CE1 and the 2-1st dummy layer D21-I may include the same material. The 2-1st dummy layer D21-I may be simultaneously formed with the first cathode CE1 through one process, and is formed separately from the first cathode CE1 by the undercut shape of the partition wall PW.

[0177] The 1-1st dummy layer D11-I and the 2-1st dummy layer D21-I may be sequentially laminated on the upper surface of the partition wall PW in the third direction DR3. The 1-1st dummy layer D11-I and the 2-1st dummy layer D21-I may form a first dummy layer DMP1-I, and dummy openings OP1-D and OP2-D may be formed in the first dummy layer DMP1-I. Each of the dummy openings OP1-D and OP2-D may include a first area AA1 and a second area AA2 sequentially formed in the thickness direction (i.e., the third direction DR3). The first area AA1 of the dummy openings OP1-D and OP2-D may be defined by the inner surface of the 1-1st dummy layer D11-I, and the second area AA2 of the dummy openings OP1-D and OP2-D may be defined by the inner surface of the 2-1st dummy layer D21-I.

[0178] According to some embodiments of the present disclosure, the method of manufacturing a display panel may further include an operation of forming a capping pattern. The operation of forming the capping pattern may include a thermal evaporation process. The capping pattern may be formed on the first cathode CE1. In the operation of forming the capping pattern, the capping pattern may be separated by a tip portion formed in the partition wall PW and located inside the partition wall openings OP1-P and OP2-P.

[0179] In the operation of forming the capping pattern, a 3-1st dummy layer spaced apart from the capping pattern may be formed together on the partition wall PW. The 3-1st dummy layer may include a conductive material. For example, the 3-1st dummy layer may include the same material as the capping pattern. The 3-1st dummy layer may be formed simultaneously with the capping pattern through one process, and may be formed separately from the capping pattern by the undercut shape of the partition wall PW. In this case, the first dummy layer DMP1-I may include a 1-1st dummy layer D11-I, a 2-1st dummy layer D21-I, and a 3-1st dummy layer.

[0180] Afterwards, refer to Figure 8G to Figure 8K, the method of manufacturing a display panel according to some embodiments may include an operation of forming lower encapsulation inorganic patterns LIL11 and LIL21 on the first cathode CE1. The operation of forming the lower encapsulation inorganic patterns LIL11 and LIL21 may include an operation of depositing a 1-1th lower encapsulation inorganic layer LIL11_I on the first cathode CE1, an operation of depositing a 2-1th lower encapsulation inorganic layer LIL21_I on the 1-1th lower encapsulation inorganic layer LIL11_I, and an operation of etching the 1-1th lower encapsulation inorganic layer LIL11_I and the 2-1th lower encapsulation inorganic layer LIL21_I to form the 1-1th lower encapsulation inorganic pattern LIL11 and the 2-1th lower encapsulation inorganic pattern LIL21.

[0181] In the following, through FIG. 8G to FIG. 8I Describe the operation of depositing the 1-1 lower encapsulation inorganic layer LIL11_I, by Figure 8J Describe the operation of depositing the 2-1 lower encapsulation inorganic layer LIL21_I, and by Figure 8K An operation of forming the 1-1th lower encapsulation inorganic pattern LIL11 and the 2-1th lower encapsulation inorganic pattern LIL21 is described.

[0182] Figure 8G 1 is a schematic diagram illustrating the gases Ar, G_Si and G_N injected over time in the process of depositing the 1-1 lower encapsulation inorganic layer LIL11_I. The process of depositing the 1-1 lower encapsulation inorganic layer LIL11_I may be to inject the reaction gas into the substrate (e.g., the preliminary display panel DP-I (see FIG. 1 ) on which the partition wall PW is formed) Fig. 8A )) is a process for forming a thin film on a substrate. Figure 8G The first reaction operation TS1, the second reaction operation TS2, the third reaction operation TS3 and the fourth reaction operation TS4 are illustratively illustrated. The first reaction operation TS1 may be combined with the deposition of the 1-1 sub-layer SB11_I (see Figure 8H ) corresponds to the operation of depositing the 2-1st sub-layer SB21_I (see Figure 8H The third reaction operation TS3 may correspond to the operation of depositing the 1-2 sub-layer SB12_I (see Fig.8I ) corresponds to the operation of, and the fourth reaction operation TS4 may correspond to the operation of depositing the 2-2 sub-layer SB22_I (see Fig.8I ) operation.

[0183] The third reaction operation TS3 and the fourth reaction operation TS4 may be substantially the same as the first reaction operation TS1 and the second reaction operation TS2, respectively. The third reaction operation TS3 and the first reaction operation TS1 may be substantially the same, and the fourth reaction operation TS4 and the second reaction operation TS2 may be substantially the same. That is, the process of depositing the 1-1 lower encapsulation inorganic layer LIL11_I may be a process in which the first reaction operation TS1 and the second reaction operation TS2 are repeated.

[0184] First, refer to Figure 8G and Figure 8H , the operation of depositing the 1-1 lower encapsulation inorganic layer LIL11_I on the first cathode CE1 may include the operation of depositing the 1-1 sublayer SB11_I on the first cathode CE1 and the operation of depositing the 2-1 sublayer SB21_I on the 1-1 sublayer SB11_I, wherein the 1-1 sublayer SB11_I and the 2-1 sublayer SB21_I form the first inorganic layer S1_I.

[0185] The operation of depositing the 1-1 sub-layer SB11_I on the first cathode CE1 may include an operation of inputting a silicon-containing gas G_Si and an argon gas Ar and an operation of inputting a nitrogen-containing gas G_N and an argon gas Ar. For example, the silicon-containing gas G_Si may be silane (SiH 4 ), and the nitrogen-containing gas G_N may be ammonia (NH 3 ).

[0186] For example, the first reaction operation TS1 may include an initial operation T1-1 and a post-operation T1-2. After performing the initial operation T1-1, the post-operation T1-2 may be performed. The initial operation T1-1 of the first reaction operation TS1 may be an operation of inputting a silicon-containing gas G_Si and an argon gas Ar. Amorphous silicon may be formed on the first cathode CE1 through the initial operation T1-1. The post-operation T1-2 of the first reaction operation TS1 may be an operation of inputting a nitrogen-containing gas G_N and an argon gas Ar. The amorphous silicon formed in the initial operation T1-1 may be nitrided through the post-operation T1-2. As a result, a 1-1 sub-layer SB11_I may be formed on the first cathode CE1, and the 1-1 sub-layer SB11_I may be Si-rich silicon nitride (SiN x )layer.

[0187] The operation of depositing the 2-1 sub-layer SB21_I on the 1-1 sub-layer SB11_I may include an operation of inputting a silicon-containing gas G_Si, a nitrogen-containing gas G_N, and an argon gas Ar, and an operation of inputting a nitrogen-containing gas G_N and an argon gas Ar. For example, the silicon-containing gas G_Si may be silane (SiH 4 ), and the nitrogen-containing gas G_N may be ammonia (NH 3 ).

[0188] For example, the second reaction operation TS2 may include an initial operation T2-1 and a post-operation T2-2. After the initial operation T2-1 is performed, the post-operation T2-2 may be performed. The initial operation T2-1 of the second reaction operation TS2 may be an operation of inputting silicon-containing gas G_Si, nitrogen-containing gas G_N, and argon gas Ar. Silicon nitride (SiN) may be formed on the 1-1 sub-layer SB11_I through the initial operation T2-1. x The post-operation T2-2 of the second reaction operation TS2 may be an operation of inputting nitrogen-containing gas G_N and argon gas Ar. The silicon nitride (SiN) formed in the initial operation T2-1 x ) may be nitrided by post-operation T2-2. As a result, a 2-1st sub-layer SB21_I may be formed on the 1-1st sub-layer SB11_I, and the 2-1st sub-layer SB21_I may be N-rich silicon nitride (SiN x )layer.

[0189] The 1-1 sub-layer SB11_I and the 2-1 sub-layer SB21_I may form a first inorganic layer S1_I. The thickness of the first inorganic layer S1_I may be between Figure 8N The wavelength of the light LT irradiated toward the preliminary lower organic layer BOL-I is half.

[0190] First, refer to Figure 8G and Fig.8I The operation of depositing the 1-1 lower encapsulation inorganic layer LIL11_I on the first cathode CE1 may include the operation of depositing the 1-2 sublayer SB12_I on the first inorganic layer S1_I and the operation of depositing the 2-2 sublayer SB22_I on the 1-2 sublayer SB12_I, wherein the 1-2 sublayer SB12_I and the 2-2 sublayer SB22_I form a second inorganic layer S2_I.

[0191] The operation of depositing the 1-2 sub-layer SB12_I on the first inorganic layer S1_I may include an operation of inputting a silicon-containing gas G_Si and an argon gas Ar and an operation of inputting a nitrogen-containing gas G_N and an argon gas Ar. For example, the silicon-containing gas G_Si may be silane (SiH 4 ), and the nitrogen-containing gas G_N may be ammonia (NH 3 ).

[0192] For example, the third reaction operation TS3 may include an initial operation T3-1 and a post-operation T3-2. After performing the initial operation T3-1, the post-operation T3-2 may be performed. The initial operation T3-1 of the third reaction operation TS3 may be an operation of inputting silicon-containing gas G_Si and argon gas Ar. Amorphous silicon may be formed on the 2-1 sub-layer SB21_I through the initial operation T3-1. The post-operation T3-2 of the third reaction operation TS3 may be an operation of inputting nitrogen-containing gas G_N and argon gas Ar. The amorphous silicon formed in the initial operation T3-1 may be nitrided through the post-operation T3-2. As a result, the 1-2 sub-layer SB12_I may be formed on the first inorganic layer S1_I, and the 1-2 sub-layer SB12_I may be Si-rich silicon nitride (SiN x )layer.

[0193] The operation of depositing the 2-2 sub-layer SB22_I on the 1-2 sub-layer SB12_I may include an operation of inputting a silicon-containing gas G_Si, a nitrogen-containing gas G_N, and an argon gas Ar, and an operation of inputting a nitrogen-containing gas G_N and an argon gas Ar. For example, the silicon-containing gas G_Si may be silane (SiH 4 ), and the nitrogen-containing gas G_N may be ammonia (NH 3 ).

[0194] For example, the fourth reaction operation TS4 may include an initial operation T4-1 and a post-operation T4-2. After the initial operation T4-1 is performed, the post-operation T4-2 may be performed. The initial operation T4-1 of the fourth reaction operation TS4 may be an operation of inputting silicon-containing gas G_Si, nitrogen-containing gas G_N, and argon gas Ar. Silicon nitride (SiN) may be formed on the 1-2 sub-layer SB12_I through the initial operation T4-1. x The post-operation T4-2 of the fourth reaction operation TS4 may be an operation of inputting nitrogen-containing gas G_N and argon gas Ar. The silicon nitride (SiN) formed in the initial operation T4-1 x ) may be nitrided by post-operation T4-2. As a result, a 2-2 sub-layer SB22_I may be formed on the 1-2 sub-layer SB12_I, and the 2-2 sub-layer SB22_I may be N-rich silicon nitride (SiN x )layer.

[0195] The 1-2 sub-layer SB12_I and the 2-2 sub-layer SB22_I may form a second inorganic layer S2_I. The thickness of the second inorganic layer S2_I may be between Figure 8N The wavelength of the light LT irradiated toward the preliminary lower organic layer BOL-I is half.

[0196] The 1-1 sublayer SB11_I of the first inorganic layer S1_I and the 1-2 sublayer SB12_I of the second inorganic layer S2_I may refer to the first sublayers SB11_I and SB12_I, and the 2-1 sublayer SB21_I of the first inorganic layer S1_I and the 2-2 sublayer SB22_I of the second inorganic layer S2_I may refer to the second sublayers SB21_I and SB22_I. Each of the first sublayers SB11_I and SB12_I and the second sublayers SB21_I and SB22_I may include silicon nitride (SiN x ). The first sublayers SB11_I and SB12_I may be rich in silicon (eg, have a relatively high concentration) compared to the second sublayers SB21_I and SB22_I, and the second sublayers SB21_I and SB22_I may be rich in nitrogen (eg, have a relatively high concentration) compared to the first sublayers SB11_I and SB12_I.

[0197] FIG. 8G to FIG. 8I It is illustratively illustrated that two inorganic layers S1_I and S2_I are deposited, but the embodiments according to the present disclosure are not limited thereto. For example, the method of manufacturing a display panel according to the present disclosure may include an operation of depositing three or more inorganic layers. For reference, Figure 6 1 and 2. The display panel DP (see FIG. 1 ) including first to fifth inorganic patterns S1, S2, S3, S4, and S5 obtained by depositing and then etching five inorganic layers is illustrated. Figure 5 ).

[0198] Afterwards, refer to Figure 8J , the method of manufacturing a display panel according to the present disclosure may include an operation of depositing a 2-1st lower encapsulation inorganic layer LIL21_I on the 1-1st lower encapsulation inorganic layer LIL11_I. Fig.8I The first inorganic layer S1_I and the second inorganic layer S2_I shown in the figure may form a 1-1 lower encapsulation inorganic layer LIL11_I. The 1-1 lower encapsulation inorganic layer LIL11_I may include a plurality of inorganic layers S1_I and S2_I. The plurality of inorganic layers S1_I and S2_I may have DBR characteristics. That is, the plurality of inorganic layers S1_I and S2_I may reflect light having a specific wavelength range.

[0199] The 2-1st lower encapsulation inorganic layer LIL21_I may be formed by a deposition process. According to some embodiments, the 2-1st lower encapsulation inorganic layer LIL21_I may be formed by a chemical vapor deposition (CVD) process. The 2-1st lower encapsulation inorganic layer LIL21_I may be formed to cover the 1-1st lower encapsulation inorganic layer LIL11_I.

[0200] Afterwards, refer to Figure 8K, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a second photoresist layer PR2 and an operation of forming a 1-1th lower encapsulation inorganic pattern LIL11 and a 2-1th lower encapsulation inorganic pattern LIL21.

[0201] In the operation of forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 may be formed in a pattern corresponding to the first light emitting opening OP1-E.

[0202] In the operation of forming the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21, the 1-1 lower encapsulation inorganic layer LIL11_I and the 2-1 lower encapsulation inorganic layer LIL21_I are dry-etched and patterned to remove the portions of the 1-1 lower encapsulation inorganic layer LIL11_I and the 2-1 lower encapsulation inorganic layer LIL21_I that overlap with the remaining anodes (e.g., the second anode AE2) except the corresponding first anode AE1. The 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21 that overlap with the corresponding first light emitting opening OP1-E may be formed by the patterned 1-1 lower encapsulation inorganic layer LIL11_I and the 2-1 lower encapsulation inorganic layer LIL21_I.

[0203] Figure 8K The 1-1st and 2-1st lower encapsulation inorganic patterns LIL11 and LIL21 having inclined side surfaces are illustratively illustrated, but embodiments according to the present disclosure are not limited thereto. For example, side surfaces of the 1-1st and 2-1st lower encapsulation inorganic patterns LIL11 and LIL21 may be vertically aligned.

[0204] Afterwards, refer to Figure 8L The method for manufacturing a display panel according to the present disclosure may include removing the first dummy layer DMP1-I (see Figure 8K ) and the first light emitting pattern EP1 (see Figure 8K ) and the first cathode CE1 (see Figure 8K ) operation.

[0205] In the operation of removing the first dummy layer DMP1-I and the first light emitting pattern EP1 and the first cathode CE1 formed inside the second partition wall opening OP2-P, the first dummy layer DMP1-I formed on the partition wall PW and the first light emitting pattern EP1 and the first cathode CE1 formed in the second partition wall opening OP2-P may be removed by wet etching.

[0206] Afterwards, refer to Figure 8M and Figure 8N , the method of manufacturing a display panel according to the present disclosure may include an operation of forming a first lower organic layer BOL1 (or a lower organic layer) between a second partition wall layer L2 and the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21 (or a lower encapsulation inorganic pattern). The operation of forming the first lower organic layer BOL1 may include an operation of depositing a preliminary lower organic layer BOL-I on the partition wall PW and the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21, an operation of irradiating the preliminary lower organic layer BOL-I with light LT, and an operation of removing the remaining portion of the preliminary lower organic layer BOL-I except for a portion of the preliminary lower organic layer BOL-I formed under the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21.

[0207] First, refer to Figure 8M , before forming the first lower organic layer BOL1 (see Figure 8N ), a preliminary lower organic layer BOL-I may be deposited on the partition wall PW and the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21. For example, the preliminary lower organic layer BOL-I may be deposited on the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21 and the partition wall PW, and may also be deposited in the second partition wall opening OP2-P. The preliminary lower organic layer BOL-I may include an organic material.

[0208] Afterwards, refer to Figure 8N , the operation of forming the first lower organic layer BOL1 may include an operation of irradiating the preliminary lower organic layer BOL-I with light LT and an operation of removing the remaining portion of the preliminary lower organic layer BOL-I except for a portion of the preliminary lower organic layer BOL-I formed under the 1-1 lower encapsulation inorganic pattern LIL11 and the 2-1 lower encapsulation inorganic pattern LIL21.

[0209] The light LT with which the preparation lower organic layer BOL-I is irradiated may have an ultraviolet wavelength range. For example, the light LT may have a wavelength of 350 nm to 400 nm.

[0210] The 1-1 lower encapsulation inorganic pattern LIL11 may include a plurality of inorganic patterns (eg, a plurality of etched inorganic layers S1_I and S2_I or S1, S2, S3, S4, and S5 (see Figure 6)). The plurality of inorganic patterns S1, S2, S3, S4, and S5 may have DBR characteristics. That is, the plurality of inorganic patterns S1, S2, S3, S4, and S5 may reflect light having a specific wavelength range. For example, the plurality of inorganic patterns S1, S2, S3, S4, and S5 may reflect light having a wavelength of 350 nm to 400 nm.

[0211] As a result, the remaining portion of the preliminary lower organic layer BOL-I except for the portion of the preliminary lower organic layer BOL-I formed under the 1-1 lower encapsulation inorganic pattern LIL11 may be removed by the light LT. The first lower organic layer BOL1 may be formed from the portion of the preliminary lower organic layer BOL-I formed under the 1-1 lower encapsulation inorganic pattern LIL11.

[0212] 9A to 9D The operation of forming the second light emitting element ED2 is illustrated, and Fig.9E The operation of forming the encapsulation organic film OL and the upper encapsulation inorganic film UIL is shown in FIG. The operation of forming the second light emitting element ED2 can be the same as the operation of forming the first light emitting element ED1 (see FIG. FIG. 8A to FIG. 8N ) are basically the same.

[0213] refer to Fig.9A , the method of manufacturing a display panel according to the present disclosure may include an operation of forming a second light emitting pattern EP2 and a second cathode CE2 and an operation of forming a 1-2 lower encapsulation inorganic layer LIL12_I and a 2-2 lower encapsulation inorganic layer LIL22_I. Figures 1A to 8N The same / similar components are denoted and described using the same / similar reference numerals, and their repeated description will be omitted.

[0214] The operation of forming the second light emitting pattern EP2 and the second cathode CE2 can be performed with Figure 8F The operation of forming the first light emitting pattern EP1 and the first cathode CE1 is substantially the same. In the operation of forming the second light emitting pattern EP2, the 1-2 dummy layer D12-I spaced apart from the second light emitting pattern EP2 may be formed together on the partition wall PW, and in the operation of forming the second cathode CE2, the 2-2 dummy layer D22-I spaced apart from the second cathode CE2 may be formed together on the partition wall PW. The 1-2 dummy layer D12-I and the 2-2 dummy layer D22-I may form a second dummy layer DMP2-I.

[0215] The operation of forming the 1-2 lower encapsulation inorganic layer LIL12_I and the 2-2 lower encapsulation inorganic layer LIL22_I can be performed by Figure 8G to Figure 8JThe operations of forming the 1-1 lower encapsulation inorganic layer LIL11_I and the 2-1 lower encapsulation inorganic layer LIL21_I are substantially the same. The 1-2 lower encapsulation inorganic layer LIL12_I may include a plurality of inorganic layers S1_I and S2_I (see Fig.8I ). The plurality of inorganic layers S1_I and S2_I may have DBR characteristics. That is, the plurality of inorganic layers S1_I and S2_I may reflect light having a specific wavelength range.

[0216] Afterwards, refer to Fig. 9B , the method of manufacturing a display panel according to the present disclosure may include an operation of forming a third photoresist layer PR3 and an operation of forming a 1-2 lower encapsulation inorganic pattern LIL12 and a 2-2 lower encapsulation inorganic pattern LIL22.

[0217] In the operation of forming the third photoresist layer PR3, the third photoresist layer PR3 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the third photoresist layer PR3 may be formed in a pattern corresponding to the second light emitting opening OP2-E.

[0218] In the operation of forming the 1-2 lower encapsulation inorganic pattern LIL12 and the 2-2 lower encapsulation inorganic pattern LIL22, the 1-2 lower encapsulation inorganic layer LIL12_I and the 2-2 lower encapsulation inorganic layer LIL22_I are dry-etched and patterned to remove the portions of the 1-2 lower encapsulation inorganic layer LIL12_I and the 2-2 lower encapsulation inorganic layer LIL22_I that overlap with the remaining anodes (e.g., the first anode AE1) except the corresponding second anode AE2. The 1-2 lower encapsulation inorganic pattern LIL12 and the 2-2 lower encapsulation inorganic pattern LIL22 that overlap with the corresponding second light emitting opening OP2-E may be formed by the patterned 1-2 lower encapsulation inorganic layer LIL12_I and the 2-2 lower encapsulation inorganic layer LIL22_I.

[0219] Fig. 9B The 1-2nd and 2-2nd lower encapsulation inorganic patterns LIL12 and LIL22 are illustratively illustrated to have inclined side surfaces, but embodiments of the present disclosure are not limited thereto. For example, side surfaces of the 1-2nd and 2-2nd lower encapsulation inorganic patterns LIL12 and LIL22 may be vertically aligned.

[0220] Afterwards, refer to Fig. 9C The method for manufacturing a display panel according to the present disclosure may include removing the second dummy layer DMP2-I (see Fig. 9B ) and the operation of forming the second light emitting pattern EP2 and the second cathode CE2 inside the first partition wall opening OP1-P.

[0221] In the operation of removing the second dummy layer DMP2-I and the second light emitting pattern EP2 and the second cathode CE2 formed inside the first partition wall opening OP1-P, the second dummy layer DMP2-I and the second light emitting pattern EP2 and the second cathode CE2 formed inside the first partition wall opening OP1-P may be removed by wet etching.

[0222] The portion of the first lower organic layer BOL1 exposed to the etchant during the process may include a material changed by a chemical reaction. That is, the first lower organic layer BOL1 may be divided into an inner portion IP and a boundary portion BP. The inner portion IP of the first lower organic layer BOL1 may be defined as a third portion P3 (see FIG. 1 ) located at the lower encapsulation inorganic patterns LIL11 and LIL21. Figure 5 ) and the partition wall PW, and the boundary portion BP of the first lower organic layer BOL1 may be defined as a portion including a material exposed to the etchant and changed by a chemical reaction. The boundary portion BP may be formed by surrounding the inner portion IP on a plane (or in a plan view).

[0223] Afterwards, refer to Fig.9D The method of manufacturing a display panel according to the present disclosure may include an operation of forming a second lower organic layer BOL2 between the second partition wall layer L2 and the 1-2 lower encapsulation inorganic pattern LIL12 and the 2-2 lower encapsulation inorganic pattern LIL22. The operation of forming the second lower organic layer BOL2 may be the same as Figure 8M and Figure 8N The operation of forming the first lower organic layer BOL1 described in is substantially the same.

[0224] refer to Fig.9E , the method for manufacturing a display panel according to the present disclosure may include completing the operation of the display panel DP by forming an encapsulation organic film OL and an upper encapsulation inorganic film UIL. The encapsulation organic film OL may be formed by applying an organic material by an inkjet method, but the embodiments according to the present disclosure are not limited thereto. The encapsulation organic film OL provides a flat upper surface. Thereafter, the upper encapsulation inorganic film UIL may be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0225] The operation of forming the second lower organic layer BOL2 and the operation of completing the display panel DP may be further performed in the partition wall PW and the pixel definition film PDL to form the light emission areas (eg, the third light emission areas PXA-B (see FIG. 1 ) of different colors. Figure 4 )) corresponding to the third partition wall opening OP3-P (see Figure 7 ) and the third light emitting opening OP3-E (see Figure 7 ) operation, forming a third light emitting element ED3 (see Figure 7 ) operation, forming the lower encapsulation inorganic patterns LIL13 and LIL23 covering the third light emitting pattern EP3 (see Figure 7 ) and forming a third lower organic layer BOL3 (see Figure 7 ) operation. Therefore, it can be formed as follows Figure 7 The illustrated embodiment includes first to third light emitting elements ED1, ED2, and ED3 corresponding to a plurality of light emitting regions PXA-R, PXA-G, and PXA-B, and lower package inorganic patterns LIL1 and LIL2 corresponding to the first to third light emitting elements ED1, ED2, and ED3 (see FIG. Figure 7 ) and the third lower organic layer BOL3 (see Figure 7 ) display panel DP.

[0226] As described above, the display panel includes a lower organic layer between the partition wall and the lower encapsulation inorganic pattern, and thus the phenomenon of foreign matter being introduced between the partition wall and the lower encapsulation inorganic pattern can be relatively reduced or eliminated. Therefore, pixel defects (dark spots or pixel shrinkage, etc.) of the display panel caused by foreign matter can be relatively reduced or eliminated.

[0227] Although the above has been described with reference to aspects of some embodiments of the present disclosure, it is to be understood that those skilled in the art or those with ordinary knowledge in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the claims and their equivalents. Therefore, the technical scope of the embodiments of the present disclosure is not limited to the detailed description of the specification, but should be defined by the claims and their equivalents.

Claims

1. A display panel, comprising: Basal layer; a pixel defining film on the base layer, wherein a light emitting opening is defined in the pixel defining film; a partition wall on the pixel definition film, wherein a partition wall opening overlapping with the light emitting opening is defined in the partition wall; a light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall and located in the partition wall opening; a lower encapsulation inorganic pattern, comprising a first portion in the partition wall opening, a second portion extending from the first portion in the thickness direction of the base layer, and a third portion extending from the second portion in a direction away from the partition wall opening and spaced apart from the partition wall in cross section; as well as A lower organic layer is between the third portion of the lower encapsulation inorganic pattern and the partition wall.

2. The display panel according to claim 1, further comprising: an encapsulation organic film, on the lower encapsulation inorganic pattern, Wherein, the lower organic layer contacts the encapsulation organic film.

3. The display panel according to claim 2, wherein: The lower organic layer includes an inner portion and a boundary portion formed by surrounding the inner portion in a plan view, and The boundary portion and the encapsulating organic film are in contact with each other.

4. The display panel according to any one of claims 1 to 3, wherein: The lower encapsulation inorganic pattern includes a first lower encapsulation inorganic pattern on the cathode and a second lower encapsulation inorganic pattern on the first lower encapsulation inorganic pattern, and The first lower encapsulation inorganic pattern includes a plurality of inorganic patterns that are repeatedly laminated.

5. The display panel according to claim 4, wherein: A thickness of one of the plurality of inorganic patterns is in a range of 175 nanometers to 200 nanometers.

6. The display panel according to claim 4, wherein: The plurality of inorganic patterns reflect light having a wavelength of 350 nanometers to 400 nanometers.

7. The display panel according to claim 4, wherein: The plurality of inorganic patterns have equal thicknesses.

8. The display panel according to claim 4, wherein: Each of the plurality of inorganic patterns includes silicon nitride.

9. The display panel according to claim 4, wherein: Each of the plurality of inorganic patterns includes a first sub-pattern and a second sub-pattern, and the first sub-pattern and the second sub-pattern are sequentially and repeatedly laminated.

10. The display panel according to claim 9, wherein: The first sub-pattern is richer in silicon than the second sub-pattern, and the second sub-pattern is richer in nitrogen than the first sub-pattern.

11. The display panel according to claim 9, wherein: The thickness of the first sub-pattern is equal to the thickness of the second sub-pattern.

12. A display panel, comprising: Basal layer; a pixel defining film on the base layer, wherein a light emitting opening is defined in the pixel defining film; a partition wall on the pixel definition film, wherein a partition wall opening overlapping with the light emitting opening is defined in the partition wall; a light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall and located in the partition wall opening; a first lower encapsulation inorganic pattern on the cathode and configured to reflect light having an ultraviolet wavelength region; a second lower package inorganic pattern, on the first lower package inorganic pattern; as well as A lower organic layer is provided between the first lower encapsulation inorganic pattern and the partition wall.

13. The display panel according to claim 12, further comprising: encapsulating an organic film, on the second lower encapsulating inorganic pattern, The lower organic layer includes an inner portion and a boundary portion in contact with the encapsulation organic film.

14. The display panel according to claim 12, wherein: The first lower encapsulation inorganic pattern includes a plurality of inorganic patterns that are repeatedly laminated.

15. The display panel according to claim 14, wherein: The thicknesses of the plurality of inorganic patterns are equal, and a thickness of one inorganic pattern among the plurality of inorganic patterns is in a range of 175 nanometers to 200 nanometers.

16. The display panel according to claim 14, wherein: Each of the plurality of inorganic patterns includes a first sub-pattern and a second sub-pattern which are sequentially and repeatedly laminated, and The first sub-pattern includes silicon nitride that is richer in silicon than the second sub-pattern, and the second sub-pattern includes silicon nitride that is richer in nitrogen than the first sub-pattern.

17. A method for manufacturing a display panel, the method comprising: Providing a preliminary display panel, the preliminary display panel comprising a base layer, a pixel defining film on the base layer, a first preliminary partition wall layer on the pixel defining film, and a second preliminary partition wall layer on the first preliminary partition wall layer; etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a first partition wall layer and a second partition wall layer, wherein a partition wall opening is defined in the first partition wall layer and the second partition wall layer; forming a light emitting pattern and a cathode in the partition wall opening; forming a lower encapsulation inorganic pattern on the cathode; as well as A lower organic layer is formed between the second partition wall layer and the lower encapsulation inorganic pattern.

18. The method according to claim 17, wherein: The forming of the lower organic layer comprises: depositing a preliminary lower organic layer on the second partition wall layer and the lower encapsulation inorganic pattern; irradiating the prepared lower organic layer with light; and The remaining portion of the preliminary lower organic layer except for a portion of the preliminary lower organic layer formed under the lower encapsulation inorganic pattern is removed.

19. The method according to claim 18, wherein: The forming of the lower package inorganic pattern includes: depositing a 1-1 sublayer on the cathode; and depositing a 2-1 sub-layer on the 1-1 sub-layer, wherein the 1-1 sublayer and the 2-1 sublayer form a first inorganic layer, and The thickness of the first inorganic layer is half the wavelength of the light.

20. The method according to claim 19, wherein: The depositing of the 1-1 sub-layer on the cathode comprises: inputting silicon-containing gas and argon gas; and A nitrogen-containing gas and the argon gas are input.

21. The method according to claim 19, wherein: The depositing of the 2-1 sub-layer on the 1-1 sub-layer includes: inputting silicon-containing gas, nitrogen-containing gas, and argon gas; and The nitrogen-containing gas and the argon gas are input.

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