An active layer, artificial synapse transistor and a preparation method and application thereof

Abstract

The application belongs to the technical field of electronic devices, and particularly relates to an active layer, an artificial synapse transistor and a preparation method and application thereof. The application innovatively prepares an active layer for a synapse transistor, which is characterized in that ethanol is added to a PDPP-TT solution, which facilitates the formation of a unique trap structure at the active layer interface, that is, high-density shallow traps and low-density deep traps coexist, and is accompanied by the generation of interface discrete trap centers. The trap distribution significantly optimizes the ion mobility of the active layer, which not only greatly widens the simulation dynamic range of the device, but also effectively enhances the charge accumulation effect, thereby realizing the significant improvement of the post-synaptic current response degree. On the basis of the active layer, an artificial synapse transistor is further prepared. The transistor not only exhibits excellent short-range plasticity, but also has excellent synaptic plasticity and high current response characteristics, which provides strong support for its application in a wider field.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic devices. More particularly, it relates to an active layer, an artificial synapse transistor and a preparation method and application thereof. BACKGROUND

[0002] As a core technology for simulating the working mode of the human brain, the artificial synapse transistor plays a pivotal role in promoting the development of brain-like computing systems and neuromorphic computing technology. This innovative technology is not only expected to break through the limitations of the traditional binary computing system based on the von Neumann architecture, but also can significantly reduce the delay and energy consumption of data transmission by integrating storage and processing functions. More importantly, the artificial synapse transistor, by precisely simulating the function of biological synapses, exhibits a high degree of plasticity similar to biological synapses, enabling the addition of received electrical pulse signals and conduction, thereby opening up a promising application prospect.

[0003] When the gate of the artificial synapse transistor is stimulated by a negative pulse, anions will migrate to the active layer interface, forming a charge / ion double-layer interface and inducing the migration of hole carriers in the channel, thereby outputting an excitatory postsynaptic current. When the pulse stimulus is removed, the anions accumulated at the double-layer interface will quickly return to their original positions, causing the decay of the excitatory postsynaptic current and achieving the reset function of the system. However, although the conventional poly[3,3'-dihexyl-2,2'-bithiophene]-thieno[3,4-b]pyrrol-2,5-dione (PDPP-TT) thin film as an active layer for the artificial synapse transistor has a weak ion capture ability due to the few deep traps in the constructed double layer, thereby achieving ultra-fast reset after pulse removal and exhibiting excellent short-term memory characteristics, the limited number of carriers in the active layer results in a less sensitive change in the amplitude of the output postsynaptic current to the number and frequency of stimuli, i.e., the change in the amplitude of the postsynaptic current is not obvious, thereby resulting in a low synaptic plasticity. This defect directly limits the analog dynamic range of the device, thereby affecting its performance in time-frequency signal processing applications, making it difficult to efficiently simulate the learning and memory functions of synapses in the biological nervous system.

[0004] Therefore, there is an urgent need in the art to develop an artificial synapse transistor with excellent short-term memory characteristics and high synaptic plasticity. SUMMARY

[0005] The technical problem to be solved by the present application is to overcome the defects and deficiencies in the prior art, i.e., the limited number of carriers in the artificial synapse transistor prepared by using a PDPP-TT thin film as an active layer, resulting in a less obvious change in the amplitude of the postsynaptic current, thereby causing a low synaptic plasticity of the device, and to provide a preparation method of an active layer for an artificial synapse transistor.

[0006] Another object of the present application is to provide an active layer prepared by the above preparation method.

[0007] Another object of the present application is to provide the application of the active layer as described above in the preparation of a synaptic transistor.

[0008] Another object of the present application is to provide an artificial synaptic transistor.

[0009] Another object of the present application is to provide a preparation method of the artificial synaptic transistor as described above.

[0010] Still another object of the present application is to provide the application of the active layer as described above or the artificial synaptic transistor as described above in the preparation of a biomimetic perception device, a neuromorphic memory or a brain-like computing chip.

[0011] The above objects of the present application are achieved by the following technical solutions:

[0012] The present application protects a preparation method of an active layer for an artificial synaptic transistor, comprising the following steps:

[0013] Ethanol is added to a polydithiophene-pyrrolopyrrolodiketone (PDPP-TT) solution, mixed, to obtain a PDPP-TT-ethanol suspension, the obtained suspension is uniformly coated on a substrate, and the coated substrate is subjected to annealing treatment, to obtain an active layer.

[0014] The present application ingeniously introduces ethanol as an anti-solvent into the PDPP-TT solution, significantly reduces the solubility of PDPP-TT in the original solvent, increases the solute supersaturation in the PDPP-TT-ethanol suspension, and greatly promotes the nucleation and growth of PDPP-TT crystals. Secondly, in the mixing step, the interaction between ethanol and the solvation shell of PDPP-TT effectively replaces the original solvent molecules, further accelerating the growth of the crystals. Due to Brownian motion or due to the small particle density of the precipitated crystals being similar to that of the suspension, these small crystals will not deposit at the bottom of the container, but will be uniformly dispersed in the entire suspension. These chemical and physical effects not only greatly improve the crystalline quality of PDPP-TT, but also optimize its surface roughness, reduce the deep trap concentration, and thus improve the overall performance and stability of the device. In addition, this method ensures that the device maintains good hydrophilicity and polarity characteristics, which is crucial for the application of the device in different environments.

[0015] Further, the preparation method of the PDPP-TT solution comprises the following steps:

[0016] The PDPP-TT powder is dispersed into a solvent and fully dissolved to obtain a PDPP-TT solution.

[0017] Further, the solvent comprises one or more of chlorobenzene, chloroform and dichlorobenzene.

[0018] Preferably, the dissolution time is 10-20 h.

[0019] Further, the volume ratio of the ethanol and the PDPP-TT solution is 1:(7-13). In this volume ratio range, the addition of ethanol can effectively promote the nucleation and growth of PDPP-TT crystals.

[0020] Preferably, the volume ratio of the ethanol and the PDPP-TT solution is 1:(8-11).

[0021] More preferably, the volume ratio of the ethanol and the PDPP-TT solution is 1:9. In this ratio, the effect of ethanol on promoting the nucleation of PDPP-TT crystals is better, further improving the quality of the crystals.

[0022] Preferably, the mixing time is 15-60 min.

[0023] Further, the mixing further includes a standing step.

[0024] Preferably, the standing time is 8-12 h. Standing can further promote the uniform dispersion of each component in the suspension, allowing the precipitation reaction to proceed fully, thereby improving the stability of the PDPP-TT solution; moreover, since a small amount of solution is required for each spin-coated film, long-term standing can also ensure that the taken suspension is relatively uniform, thereby making the solute of the spin-coated film relatively uniform, effectively reducing problems such as uneven film thickness caused by unstable solution during the spin-coating process.

[0025] Further, the use of the substrate includes a pretreatment.

[0026] Further, as a preferred method, the pretreatment includes the following steps:

[0027] The substrate is sequentially cleaned with water, acetone, and isopropanol solutions under ultrasonic cleaning, and then dried with nitrogen, and treated with ozone for 15-20 min; the purpose of the ozone treatment is to hydroxylate the surface of the substrate and enhance wettability.

[0028] Preferably, the coating rotation speed is 1000-3000 rpm.

[0029] Preferably, the coating time is 30-60 s.

[0030] Further, the annealing temperature is 180-220°C.

[0031] Further, the annealing temperature is 190-210°C.

[0032] Preferably, the annealing temperature is 200°C.

[0033] Preferably, the annealing time is 10-20 min.

[0034] Preferably, the thickness of the active layer is 10-30 nm. In this range, the active layer has relatively fewer defects and better performance.

[0035] More preferably, the thickness of the active layer is 15-25 nm. In this thickness range, the active layer can further reduce defects, thereby more effectively improving the overall performance of the device.

[0036] The application protects the active layer prepared by the above preparation method.

[0037] The application protects the application of the above active layer in the preparation of a synaptic transistor.

[0038] The application protects an artificial synaptic transistor, which comprises a substrate, an active layer, a gate dielectric layer, and source and drain electrodes arranged on both sides of the gate dielectric layer, which are sequentially stacked.

[0039] The active layer is the aforementioned active layer.

[0040] The artificial synaptic transistor of the application integrates a substrate, an active layer, a gate dielectric layer, and source and drain electrodes, thereby constructing a stable and reliable device structure. The active layer prepared by the anti-solvent method significantly improves the ion mobility, not only broadening the dynamic range of the device simulation, but also greatly enhancing the charge accumulation effect, thereby significantly improving the responsivity of the post-synaptic current. This innovative breakthrough solves the problem of limited number of carriers when using PDPP-TT thin film as the active layer in traditional artificial synaptic transistors, making the device output post-synaptic current more sensitive to the number and frequency of stimuli, and significantly improving synaptic plasticity. The gate dielectric layer provides a solid guarantee for the efficient and stable operation of the device, and the cooperation of the source electrode and the drain electrode ensures the accurate transmission of signals. In summary, by skillfully combining the above structures, the artificial synaptic transistor of the application exhibits excellent synaptic plasticity and high current response characteristics.

[0041] Specifically, in the artificial synaptic transistor of the application, the gate dielectric layer is designed to cover only the area between the source electrode and the drain electrode. This design aims to refine the control of the gate, by more directly regulating the charge carriers between the source electrode and the drain electrode, significantly improving the response speed and switching performance of the transistor. At the same time, this design can also effectively avoid introducing unnecessary charge storage on the source electrode and the drain electrode, thereby reducing parasitic effects and improving the overall performance of the device.

[0042] Further, the substrate comprises any one of silicon dioxide, polyethylene terephthalate (PET), and a glass substrate.

[0043] Preferably, the thickness of the substrate is 290-310 nm. The substrate in this range has better mechanical stability and processing feasibility, thus ensuring that the device can be reliably carried without directly affecting the performance of the device.

[0044] Further, the source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are gold, silver or copper.

[0045] Preferably, the thickness of the source electrode and the drain electrode is 30-60 nm. The source electrode and the drain electrode in this thickness range can be more firmly attached to the substrate, significantly reducing the risk of falling off, while ensuring excellent electrical contact performance.

[0046] More preferably, the thickness of the source electrode and the drain electrode is 35-45 nm.

[0047] Further, the gate dielectric layer is an ionic gel.

[0048] Further, the ionic gel includes any one of [PVDF-HFP][EMIM-TFSI] ionic gel, polyethylene oxide-sodium ionic gel, and polyethylene oxide-lithium ionic gel. These ionic gel materials are rich in mobile anions and cations inside, thus being able to meet the requirements of artificial synapse transistors in the present application.

[0049] Preferably, the gate dielectric layer is [PVDF-HFP][EMIM-TFSI] ionic gel. [PVDF-HFP][EMIM-TFSI] ionic gel has higher ionic conductivity, wider working voltage range, and better mechanical strength and flexibility, and can exhibit better performance in the artificial synapse transistors in the present application.

[0050] Further, the preparation method of the [PVDF-HFP][EMIM-TFSI] ionic gel includes the following steps:

[0051] The polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) solution and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl) imide (EMIM-TFSI) ionic liquid are mixed uniformly, and after solidification, [PVDF-HFP][EMIM-TFSI] ionic gel is obtained.

[0052] Further, the specific preparation method of the PVDF-HFP solution includes the following steps:

[0053] The PVDF-HDP powder is fully dissolved in a solvent to obtain a PVDF-HDP solution.

[0054] Further, the solvent includes one or more of acetone, N-methyl pyrrolidone, and dimethylformamide.

[0055] Preferably, the temperature of the dissolving is 40-80℃.

[0056] Preferably, the time of the dissolving is 5-20min.

[0057] Further, the mass ratio of the PVDF-HFP and EMIM-TFSI is 1:(1-6). Within the mass ratio range, the synergistic effect of the PVDF-HFP and EMIM-TFSI can significantly improve the performance of the material.

[0058] Further, the mass ratio of the PVDF-HFP and EMIM-TFSI is 1:(2-4).

[0059] Preferably, the mass ratio of the PVDF-HFP and EMIM-TFSI is 1:3. Within the ratio, the synergistic effect of the PVDF-HFP and EMIM-TFSI is more optimal, further improving the performance of the material.

[0060] Preferably, the temperature of the mixing is 40-80℃.

[0061] Preferably, the time of the mixing is 6-24h.

[0062] Further, as a preferred way, the solidification is using a mold for solidification.

[0063] Specifically, the solidification is uniformly pouring the obtained mixed and uniform solution in a mold, and drying and solidifying at 80-85℃.

[0064] Preferably, the time of the drying is 1-5h.

[0065] Preferably, the thickness of the gate dielectric layer is 5-20μm. Within the thickness range of the gate dielectric layer, the ion conductive performance is more optimal, which can effectively reduce the leakage current, thereby improving the reliability and overall performance of the device.

[0066] The present application protects the preparation method of the artificial synapse transistor, comprising the following steps:

[0067] S1. Preparing a substrate covered with an active layer;

[0068] S2. Pasting a mask plate on the surface of the active layer obtained in step S1, and then evaporating a source electrode and a drain electrode;

[0069] S3. Preparing a gate dielectric layer;

[0070] S4. Removing the mask plate in step S2, and pasting the gate dielectric layer obtained in step S3, to obtain the artificial synapse transistor.

[0071] The application provides a preparation method of an artificial synapse transistor. In the preparation process, the inventor skillfully uses ethanol as an anti-solvent, effectively improves the crystallinity of the active layer, and significantly optimizes the charge transport performance of the transistor. At the same time, in order to ensure the stable operation of the device, the interface roughness is also controlled to avoid the increase of interface roughness caused by the increase of crystallinity. In addition, the hydrophilicity and polarity of the material are fully considered in the preparation process, in which the good hydrophilicity guarantees the ion transport, and the appropriate polarity promotes the efficient transport of charges. Through the comprehensive regulation of these factors, the preparation method successfully realizes the precise balance of crystallinity, interface roughness, hydrophilicity and polarity, thereby significantly improving the performance of the artificial synapse transistor.

[0072] Preferably, in step S2, the evaporation rate of the evaporation is 0.1-0.5 A / s.

[0073] Further, as a preferred manner, in step S3, the ionic glue is [PVDF-HFP][EMIM-TFSI] ionic glue.

[0074] The application protects the application of the above active layer or the above artificial synapse transistor in the preparation of a biomimetic sensing device, a neuromorphic memory or a brain-like computing chip.

[0075] Compared with the prior art, the application has the following beneficial effects:

[0076] The application innovatively prepares an active layer for a synapse transistor, characterized in that ethanol is added to a PDPP-TT solution, which promotes the formation of a unique trap structure at the interface of the active layer, that is, the coexistence of high-density shallow traps and low-density deep traps, accompanied by the generation of discrete trap centers at the interface. This trap distribution significantly optimizes the ion mobility of the active layer, not only greatly widens the analog dynamic range of the device, but also effectively enhances the charge accumulation effect, thereby significantly improving the post-synaptic current response. On this basis, an artificial synapse transistor is further prepared. The transistor not only exhibits excellent short-range plasticity, but also has excellent synaptic plasticity and high current response characteristics, providing strong support for its application in a wider field. BRIEF DESCRIPTION OF DRAWINGS

[0077] Figure 1 FIG. 1 is a structural schematic diagram of the artificial synapse transistor in Example 1; the schematic diagram mainly focuses on expressing the structural relationship, rather than accurately reflecting the actual thickness of each layer.

[0078] Figure 2 FIG. 4 is an excitatory post-synaptic current diagram of the artificial synapse transistor in Example 1 under 5 groups of pulse stimuli.

[0079] Figure 3The excitatory postsynaptic current graph of the artificial synapse transistor in Example 1 under 5 groups of pulse stimuli.

[0080] Figure 4 The spike number-dependent plasticity index graph of the artificial synapse transistor in Example 1 and Comparative Example 1.

[0081] Figure 5 The excitatory postsynaptic current graph of the artificial synapse transistor in Example 1 under different frequency pulse stimuli.

[0082] Figure 6 The excitatory postsynaptic current graph of the artificial synapse transistor in Comparative Example 1 under different frequency pulse stimuli. DETAILED DESCRIPTION

[0083] The present application will be further described in conjunction with the accompanying drawings and specific examples, but the examples do not limit the present application in any form. Unless otherwise specified, the reagents, methods and equipment used in the present application are conventional reagents, methods and equipment in the technical field.

[0084] Unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0085] Example 1 An artificial synapse transistor and a preparation method thereof

[0086] 1. An artificial synapse transistor (a structural schematic diagram is shown as Figure 1 ), comprising a substrate-SiO2, an active layer-PDPP-TT-ethanol thin film, a gate dielectric layer-[PVDF-HFP][EMIM-TFSI] ionic gel, and a source electrode-Au and a drain electrode-Au on both sides of the gate dielectric layer, which are sequentially stacked.

[0087] 2. A preparation method of the artificial synapse transistor described above, comprising the following steps:

[0088] S1. Pretreatment of the substrate:

[0089] The SiO2 thin film substrate was sequentially placed in deionized water, an acetone solution, and isopropyl alcohol, and was ultrasonically cleaned for 30 min, and then was blown dry with nitrogen and was ozone treated in a UV ozone cleaning machine for 20 min, to obtain a pretreated SiO2 thin film substrate with a thickness of 300 nm.

[0090] S2. Preparation of the active layer:

[0091] S2-1. Poly[3,4-(2,2-dihydroxy-5,5-dimethyl-1,4-phenylene)propane-1,2-dithiolate-2,5- diyl]pyrrol (PDPP-TT) powder was added to a chlorobenzene solution to prepare a 5 mg / mL solution, which was heated to 60°C and stirred for 15 h, and the solute was completely dissolved to be orange red, to obtain a PDPP-TT solution;

[0092] S2-2. The PDPP-TT solution obtained in step S2-1 was mixed with ethanol at a volume ratio of 1:9, stirred for 30 min, and then left to stand for 12 h to obtain a PDPP-TT-ethanol suspension.

[0093] S2-3. The PDPP-TT-ethanol suspension obtained in step S2-2 was uniformly dropped onto the pretreated SiO2 film substrate obtained in step S1 using a pipette, spin-coated at a speed of 2000 rpm / s for 50 s, and then placed on a hot plate to be annealed at 200°C for 15 min to obtain a substrate covered with an active layer having a thickness of 19 nm.

[0094] S3. Evaporation of electrodes:

[0095] A custom-made mask plate was attached to the surface of the active layer prepared in step S2, and then placed in an evaporation machine to evaporate 5 nm of Ag at an evaporation rate of 0.1 A / s, and then to evaporate 30 nm of Ag at an evaporation rate of 0.3 A / s, so that a 35-nm-thick Au layer was obtained on both sides of the active layer as source and drain electrodes.

[0096] S4. Preparation of gate dielectric layer:

[0097] S4-1. Polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) was mixed with acetone at a mass ratio of 1:4, stirred at 60°C for 10 min until completely dissolved to obtain a PVDF-HFP solution;

[0098] S4-2. The PVDF-HFP solution obtained in step S4-1 was mixed with 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt (EMIM-TFSI) at a mass ratio of 1:3, stirred at 60°C for 12 h until the solution was clear and transparent and free of bubbles to obtain a [PVDF-HFP][EMIM-TFSI] ionic gel solution;

[0099] S4-3. The [PVDF-HFP][EMIM-TFSI] ionic gel solution obtained in step S4-2 was uniformly poured into a mold, and then transferred into a 80°C drying oven to dry for 2 h to obtain a peelable [PVDF-HFP][EMIM-TFSI] ionic gel.

[0100] S4-4. The mask plate in step S3 was removed, and the peeled [PVDF-HFP][EMIM-TFSI] ionic gel film obtained in step S4-3 was attached to the channel region as a gate dielectric layer, and the thickness of the gate dielectric layer was 10 μm. The obtained device was an artificial synapse transistor.

[0101] Example 2: An artificial synapse transistor and a preparation method thereof

[0102] ​​The difference from Example 1 is that in step S2-2 in the preparation method of the artificial synapse transistor, the volume ratio of ethanol and PDPP-TT solution is replaced from 1:9 to 1:13.

[0103] The other steps and conditions are the same as in Example 1.

[0104] Example 3 An artificial synapse transistor and a preparation method thereof

[0105] The difference from Example 1 is that in step S2-2 in the preparation method of the artificial synapse transistor, the volume ratio of ethanol and PDPP-TT solution is replaced from 1:9 to 1:8.

[0106] The other steps and conditions are the same as in Example 1.

[0107] Comparative Example 1 An artificial synapse transistor and a preparation method thereof

[0108] The difference from Example 1 is that in step S2-2 in the preparation method of the artificial synapse transistor, no ethanol is added in the preparation of the active layer.

[0109] 1. An artificial synapse transistor comprising, in sequence, a substrate-SiO2, an active layer-PDPP-TT thin film gate dielectric layer-[PVDF-HFP][EMIM-TFSI] ionic gel, and source electrode-Au and drain electrode-Au on both sides of the gate dielectric layer.

[0110] 2. A preparation method of the artificial synapse transistor as described above, comprising the following steps:

[0111] S1. Pretreatment of the substrate:

[0112] The SiO2 thin film substrate is sequentially placed in deionized water, acetone solution, and isopropyl alcohol, and ultrasonically cleaned for 30 min each time, then dried with nitrogen, and placed in a UV ozone cleaning machine for ozone treatment for 20 min, to obtain a pretreated SiO2 thin film substrate with a thickness of 300 nm.

[0113] S2. Preparation of the active layer:

[0114] S2-1. Poly[2,6'-9,9'-bis(2-ethylhexyl)-5,5'-dimethyl-4H-cyclopropa[2,2:5',2']thieno[3,2-b]dithiophene-6,7'-cyclopenta[2,1-b]dithiophene-2,6'-dione (PDPP-TT) powder is added to a chlorobenzene solution to prepare a 5 mg / mL solution, heated to 60°C, and stirred for 15 h, and the solute is completely dissolved to form an orange red solution, to obtain a PDPP-TT solution;

[0115] S2-2. The PDPP-TT solution obtained in step S2-1 was uniformly dropped on the pretreated SiO2 thin film substrate obtained in step S1 using a pipette, and spin-coated at a rotation speed of 2000 rpm / s for 50 s, and then placed on a hot plate for annealing at 200°C for 15 min to obtain a substrate covered with an active layer with a thickness of 19 nm.

[0116] S3. Evaporation of electrodes:

[0117] A customized mask plate was attached to the surface of the active layer prepared in step S2, and then placed in a film coating machine to evaporate 5 nm of Ag at an evaporation rate of 0.1 nm / s, and then the evaporation rate was increased to 0.3 nm / s to evaporate 30 nm of Ag, and finally 35 nm of Au was evaporated on both sides of the active layer as source and drain electrodes.

[0118] S4. Preparation of gate dielectric layer:

[0119] S4-1. Polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) was mixed with acetone at a mass ratio of 1:4, stirred at 60°C for 10 min until completely dissolved to obtain a PVDF-HFP solution;

[0120] S4-2. The PVDF-HFP solution obtained in step S4-1 was thoroughly mixed with 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide salt (EMIM-TFSI) at a mass ratio of 1:3, and stirred at 60°C for 12 h until the solution was clear and transparent and free of bubbles to obtain a [PVDF-HFP][EMIM-TFSI] ionic gel solution;

[0121] S4-3. The [PVDF-HFP][EMIM-TFSI] ionic gel solution obtained in step S4-2 was uniformly poured into a mold, and then transferred into a 80°C drying oven for drying for 2 h to obtain a peelable [PVDF-HFP][EMIM-TFSI] ionic gel;

[0122] S4-4. The mask plate in step S3 was removed, and the peeled [PVDF-HFP][EMIM-TFSI] ionic gel film obtained in step S4-3 was attached to the channel region as a gate dielectric layer, and the thickness of the gate dielectric layer was 10 μm, and the obtained device was an artificial synapse transistor.

[0123] Experimental Example 1 Excitatory postsynaptic current performance test of artificial synapse transistor under 5 groups of pulse stimulation

[0124] 1. Experimental method

[0125] ​​The artificial synaptic transistors prepared in Example 1 and Comparative Example 1 were used as test samples and tested using a Keithley 4200-SCS semiconductor characterization analyzer. Test procedure: The probe of electrode SUM1 was connected to the source electrode, the probe of electrode SUM2 was connected to the drain electrode, and the probe of electrode SUM3 was connected to the gate dielectric ionomer as the top electrode. A readout voltage of -1V was continuously applied to electrode SUM2, and five pulse sequences were applied to electrode SUM3. The pulse sequences contained 1, 2, 3, 4, and 5 negative pulses, with each pulse lasting 0.05s, respectively, as presynaptic spikes. The excitatory postsynaptic current maps of the obtained artificial synaptic transistors under stimulation with five different numbers of negative pulses were measured.

[0126] 2. Experimental Results

[0127] Depend on Figure 2 It can be seen that as the number of spikes increases, the concentration of negative charge accumulated at the interface between the PDPP-TT-ethanol suspension and the ionomer cement conductor film in Example 1 gradually increases, leading to a corresponding increase in postsynaptic current. Specifically, when the number of spikes is 1, 2, 3, 4, and 5, the corresponding maximum postsynaptic currents are 16.8 μA, 50.78 μA, 686.67 μA, 1281.41 μA, and 1575.44 μA, respectively. In comparison, Figure 3 Comparative Example 1 (i.e., the PDPP-TT system without ethanol) showed significantly lower maximum postsynaptic currents with the same number of spikes, at 14.17 μA, 39.94 μA, 92.38 μA, 104.93 μA, and 122.1 μA, respectively. This significant difference is attributed to the fact that the addition of ethanol significantly enhanced the charge accumulation effect, thereby increasing the responsiveness of postsynaptic currents in the PDPP-TT-ethanol system. In contrast, Comparative Example 1 without ethanol showed relatively weaker charge accumulation and conduction, resulting in a lower responsiveness to spike stimuli.

[0128] Furthermore, Figure 4It is intuitively shown that there is a significant difference between the spike number-dependent plasticity index (SNDP index, calculated as ΔAn / ΔAi x 100%) of the artificial synapse transistor prepared based on PDPP-TT (Comparative Example 1) and the artificial synapse transistor prepared based on PDPP-TT-ethanol suspension (Example 1). Specifically, when the artificial synapse transistor is prepared only by using the PDPP-TT solution, as the input spike number increases from 1 to 5, the SNDP index increases to 100.00%, 281.86%, 651.94%, 740.51% and 861.67%, respectively. However, under the same condition of increasing spike number, the SNDP index of the artificial synapse transistor prepared by using the PDPP-TT-ethanol suspension is significantly improved to 100.00%, 302.26%, 4087.32%, 7627.44% and 9377.62%, which is about 10 times of the former. This data clearly shows that by introducing ethanol as an anti-solvent into the PDPP-TT solution, the artificial synapse transistor prepared based on PDPP-TT-ethanol suspension exhibits an increasingly enhanced post-synaptic current response intensity as the spike number increases. This phenomenon directly reflects the significant improvement of the device in spike number-dependent plasticity, further emphasizing the high flexibility and adaptability of the device in processing information.

[0129] Experimental Example 2 Excitatory post-synaptic current performance test of the artificial synapse transistor under different frequency pulse stimuli

[0130] 1. Experimental method

[0131] The artificial synapse transistors prepared in Example 1 and Comparative Example 1 were used as test samples, and were tested by using a Keithley 4200-SCS semiconductor characteristic analyzer. The test process was as follows: the probe of electrode SUM1 was connected to the source electrode, the probe of electrode SUM2 was connected to the drain electrode, and the probe of electrode SUM3 was connected to the gate dielectric layer ion colloid as the top electrode. A reading voltage of -1 V was continuously applied to electrode SUM2, and a series of different frequency pulse sequences were applied to electrode SUM3 as pre-synaptic spikes. Each sequence contained 10 pulse spikes with an amplitude of -3.5 V and a duration of 0.05 s, and different time intervals between adjacent pulses were set to produce different frequencies: 0.1 s interval to produce 10 Hz frequency, 0.2 s interval to produce 5 Hz frequency, 0.4 s interval to produce 2.5 Hz frequency, 0.8 s interval to produce 1.25 Hz frequency, and 1.6 s interval to produce 0.625 Hz frequency. The excitatory post-synaptic current diagram of the artificial synapse transistor under negative pulse stimuli of different frequencies (5 frequencies) was obtained by testing.

[0132] 2. Experimental results

[0133] From the above experimental results, it can be seen that the artificial synapse transistor prepared by using the PDPP-TT-ethanol suspension has a significantly improved excitatory post-synaptic current performance under different frequency pulse stimuli, and the excitatory post-synaptic current performance of the artificial synapse transistor prepared by using the PDPP-TT-ethanol suspension is about 10 times of that of the artificial synapse transistor prepared by using the PDPP-TT solution. This data clearly shows that by introducing ethanol as an anti-solvent into the PDPP-TT solution, the artificial synapse transistor prepared based on PDPP-TT-ethanol suspension exhibits an increasingly enhanced post-synaptic current response intensity as the spike number increases. This phenomenon directly reflects the significant improvement of the device in spike number-dependent plasticity, further emphasizing the high flexibility and adaptability of the device in processing information. Figure 5As shown, in Example 1, when the frequency of the stimulation spike increased from 0.625 Hz to 10 Hz, the post-synaptic current of the artificial synapse transistor increased significantly from 23.24 μA to 1069.42 μA, with a modulation range of up to 1046.2 μA. This result clearly demonstrates the excellent current modulation ability of the device under the driving of different frequency stimulation, and exhibits excellent stimulation frequency synaptic plasticity. Importantly, after the stimulation was removed, the post-synaptic current could quickly recover to the initial value, which reflects its excellent short-term memory. In contrast, in Comparative Example 1 Figure 6 ), within the same frequency range (from 0.625 Hz to 10 Hz), although the post-synaptic current of the artificial synapse transistor also increased from 26.79 μA to 353.18 μA, its modulation range was only 326.39 μA. Specifically, the post-synaptic current modulation range exhibited by the synaptic transistor in Example 1 was 3.2 times that of Comparative Example 1.

[0134] In summary, the synaptic transistor prepared in Example 1 using the PDPP-TT-ethanol suspension exhibits more excellent performance in stimulation frequency-dependent synaptic plasticity while maintaining excellent short-term memory. Examples 2-3, by changing only the volume ratio of PDPP-TT and ethanol solution, experimentally verified that the performance of the synaptic transistor prepared thereby is basically the same as that of Example 1, and therefore will not be described here.

[0135] The above examples are preferred embodiments of the present application, but the embodiments of the present application are not limited by the above examples, and any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present application are equivalent replacement methods and are included within the scope of protection of the present application.

Claims

1. A method for fabricating an active layer for a synaptic transistor, characterized in that, The method comprises the following steps: ethanol is added to the polybenzodithiophene-diketopyrrolopyrrole solution as an anti-solvent, mixed, to obtain a polybenzodithiophene-diketopyrrolopyrrole-ethanol suspension, the obtained suspension is uniformly coated on a substrate, and the coated substrate is subjected to annealing treatment, to obtain an active layer; The volume ratio of the ethanol and the PDPP-TT solution is 1: (7-13).

2. The active layer prepared by the preparation method of claim 1.

3. The active layer of claim 2 is used in the preparation of a synaptic transistor.

4. An artificial synapse transistor, comprising: The substrate, the active layer, the gate dielectric layer, the source electrode and the drain electrode are sequentially stacked. The active layer is the active layer of claim 2.

5. The artificial synapse transistor of claim 4, wherein, The gate dielectric layer is an ionic gel.

6. The artificial synapse transistor of claim 5, wherein, The ionic gel includes any one of [PVDF-HFP][EMIM-TFSI] ionic gel, polyethylene oxide-sodium ionic gel, and polyethylene oxide-lithium ionic gel.

7. The artificial synapse transistor of claim 4, wherein, The source electrode and the drain electrode are made of the same material, and the source electrode and the drain electrode are made of gold, silver or copper.

8. A method of fabricating the artificial synapse transistor according to any one of claims 4 to 7, characterized by, The method comprises the following steps: S1. Preparing a substrate covered with an active layer; S2. Adhering a mask plate to the surface of the active layer obtained in step S1, and then evaporating a source electrode and a drain electrode; S3. Preparing a gate dielectric layer; S4. Removing the mask plate in step S2, and then adhering the gate dielectric layer obtained in step S3, to obtain an artificial synaptic transistor.

9. The active layer of claim 2 or the artificial synaptic transistor of any one of claims 4-7 is used in the preparation of a bionic sensing device, a neuromorphic memory or a brain-like computing chip.

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