SSD content preloading via broadcast system

Abstract

In a storage system having multiple solid state drives (SSDs), a dedicated high speed data channel in which data and commands associated with the data are sent from an upstream SSD to a downstream SSD may be used to improve the performance of propagating data from a primary device to each secondary device. The data is also sent to the downstream SSD after a minimum amount of data has been programmed to the upstream SSD. The downstream SSD begins to program the data to its own memory device after receiving the data. Each SSD that programs data to the storage system may be parallel and at least partially concurrent with each other. Data, commands, and control messages may be sent to the upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel such that the downstream data path and the upstream data path are different.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire disclosure of U.S. Non - Provisional Patent Application No. 18 / 218,874, filed on July 6, 2023, entitled "SSD Content Preload Via Broadcasting System", which is hereby incorporated by reference in its entirety for all purposes, and which claims the priority of U.S. Provisional Patent Application No. 63 / 521,307, filed on June 15, 2023. Background Art Technical Field

[0003] Embodiments of the present disclosure generally relate to a storage system having a plurality of data storage devices such as a plurality of solid - state drives (SSDs), in which data is broadcast from a master device to the plurality of data storage devices.

[0004] Description of the Related Art

[0005] In the field of communications, there are broadcast - based solutions capable of broadcasting data from a master device to multiple devices. However, in a storage system utilizing data storage devices, broadcast - based solutions may be incompatible with data storage device standards such as Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI) (PCIe), etc., which are based on a handshake protocol between a host device and a data storage device. In the automotive industry, for example, pre - loaded content (images) or content being rolled out may be stored in multiple data storage devices, which may require a large amount of memory space. To store the pre - loaded content or the content being rolled out, data must be burned onto each drive. Therefore, it may take a significant amount of time to store data on each of the multiple storage devices. Additionally, during production, data is pre - loaded serially through the host on each data storage device. In other words, since data is stored sequentially on each data storage device, the amount of time to store data on multiple data storage devices may cause a bottleneck in the overall performance of the storage system.

[0006] Accordingly, there is a need in the art for an improved broadcast - based solution for a storage system having a plurality of data storage devices. Summary of the Invention

[0007] The present disclosure generally relates to a storage system having a plurality of data storage devices such as a plurality of solid state drives (SSDs), in which data is broadcast from a master device to the plurality of data storage devices. In a storage system having a plurality of SSDs, dedicated high-speed data channels may be used to improve the performance of propagating data from the master device to each slave device, in which data and commands associated with the data are sent from an upstream SSD to a downstream SSD. After a minimum amount of data has been programmed into the upstream SSD, the data is also sent to the downstream SSD. The downstream SSD begins programming the data into its own memory device after receiving the data. Programming the data into each SSD of the storage system may occur in parallel and at least partially simultaneously with each other. Data, commands, and control messages may be sent to the upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel such that the downstream data path and the upstream data path are not the same.

[0008] In one embodiment, a storage system includes a plurality of data storage devices. Each data storage device of the plurality of data storage devices is coupled to another data storage device of the plurality of data storage devices. Each data storage device includes an endpoint (EP) PCIe interface, a serial bus (SMB), and a high-speed serial trace port (HSSTP) interface. The HSSTP interface includes a PCIe transmitter (TX), a universal asynchronous receiver-transmitter (UART) receiver (RX), and a UART TX. A first data storage device is configured to send data to an EP PCIe interface of a second data storage device via a PCIe TX of the first data storage device. The first data storage device is coupled to the second data storage device. The sending occurs after a predetermined amount of data less than all of the data has been programmed into the first data storage device.

[0009] In another embodiment, a storage system includes a first data storage device and a second data storage device, the second data storage device being coupled to the first data storage device. The first data storage device is configured to program data into a non-volatile memory (NVM) device of the first data storage device, generate a write command for programming data into an NVM device of the second data storage device, and, after a predetermined amount of data has been programmed into the NVM device of the first data storage device, send the data to the second data storage device via a high-speed data path that couples the first data storage device to the second data storage device. The high-speed data path is different from a low-speed data path. The data transfer speed of the low-speed data path is lower than that of the high-speed data path. The high-speed data path is used to transfer write data. The low-speed data path is used to transfer read data. The second data storage device is configured to receive data from the first data storage device and program the data into the NVM device of the second data storage device. Programming the data into the NVM device of the second data storage device occurs partially simultaneously with programming the data into the NVM device of the first data storage device.

[0010] In another embodiment, a storage system includes a first data storage device, a second data storage device coupled to the first data storage device, means for transferring write data from the first data storage device to the second data storage device, and means for transferring read data and control data between the first data storage device and the second data storage device. The means for transferring write data is different from the means for transferring read data and control data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Accordingly, by referring to the embodiments, the above features of the present disclosure can be understood in detail, and the present disclosure briefly outlined above can be described more specifically, some of the embodiments being illustrated in the drawings. However, it should be noted that the drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope, as the present disclosure may admit other equally effective embodiments.

[0012] Figure 1 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device can be used as a storage device for a host device.

[0013] Figure 2 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a plurality of SSDs are connected together in a daisy chain.

[0014] Figure 3 is an exemplary graph illustrating the time for serially programming data into a plurality of SSDs according to certain embodiments.

[0015] Figure 4 is an exemplary chart illustrating the time for programming data in parallel to multiple SSDs according to certain embodiments.

[0016] Figure 5 is a flowchart illustrating a method for broadcasting data to multiple SSDs in a storage system, in which the multiple SSDs are connected together in a daisy chain.

[0017] Figure 6 is a flowchart illustrating a method for reading data from a data storage device among multiple data storage devices in a storage system, in which the multiple data storage devices are connected together in a daisy chain.

[0018] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment can be advantageously utilized in other embodiments without specific recitation. DETAILED DESCRIPTION

[0019] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements (whether or not they relate to different embodiments) is contemplated for implementing and practicing the present disclosure. Moreover, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment is not a limitation of the present disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, reference to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly recited in the claims.

[0020] The present disclosure generally relates to a storage system having a plurality of data storage devices such as a plurality of solid state drives (SSDs), in which data is broadcast from a host device to the plurality of data storage devices. In a storage system having a plurality of SSDs, a dedicated high-speed data channel can be used to improve the performance of propagating data from the host device to each auxiliary device, in which data and commands associated with the data are sent from an upstream SSD to a downstream SSD. After a minimum amount of data has been programmed into the upstream SSD, the data is also sent to the downstream SSD. The downstream SSD begins programming the data into its own memory device after receiving the data. Programming the data into each SSD of the storage system can occur in parallel and at least partially simultaneously with each other. Data, commands, and control messages can be sent to the upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel such that the downstream data path and the upstream data path are different.

[0021] Figure 1 FIG. 4 is a schematic block diagram illustrating a storage system 100 having a data storage device 106, which can be used as a storage device for a host device 104. For example, the host device 104 can utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host DRAM 138. In some examples, the storage system 100 can include a plurality of storage devices that can operate as a storage array, such as the data storage device 106. For example, the storage system 100 can include a plurality of data storage devices 106 that are configured to collectively operate as a redundant array of inexpensive / independent disks (RAID) for the mass storage device of the host device 104.

[0022] The host device 104 can store data to and / or retrieve data from one or more storage devices such as the data storage device 106. As Figure 1 illustrated, the host device 104 can communicate with the data storage device 106 via an interface 114. The host device 104 can include any one of a wide range of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebooks (i.e., laptops) computers, tablet computers, set-top boxes, cellular phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending data to or receiving data from the data storage device.

[0023] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated for exclusive use by the controller 108 of the data storage device 106 for data storage device 106. For example, the controller 108 may store mapping data, buffer commands, logical-to-physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the controller 108 may use the HMB 150 to store data that would typically be stored in the volatile memory 112, buffer 116, internal memory of the controller 108 (such as static random access memory (SRAM)), etc. In an example where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.

[0024] The data storage device 106 includes a controller 108, NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components (not shown in Figure 1 for clarity). For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5" data storage devices (e.g., HDD or SSD), 2.5" data storage devices, 1.8" data storage devices, Peripheral Component Interconnect (PCI), PCI Extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, PCIe x4, PCIe x8, PCIe x16, PCIe mini card, mini PCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of the host device 104.

[0025] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface eXtensions (CCIX), Open Channel SSD (OCSSD), etc. The PCIe TX interface 218 and the EP PCIe interface 212 may operate according to different protocols other than PCIe.

[0026] Each PCIe TX interface 218 is coupled to the EP PCIe interface 212 of an adjacent downstream (i.e., downstream of host device 202 or first SSD 1 210a) SSD. For example, the PCIe TX interface 218 of the first SSD 1 210a is coupled to the EP PCIe interface 212 of the second SSD 2210b, where data may be transferred from the first SSD 2 210a to the second SSD 2210b via a high-speed bus 226 between the PCIe TX interface 218 of the first SSD 1 210a and the EP PCIe interface 212 of the second SSD 2210b. In addition, it should be understood that the PCIe TX interface 218 may be any applicable interface port interface. For example, the PCIe TX interface 218 may be a dual-port or multi-port interface. In addition, the RC PCIe interface 204 is coupled to the EP PCIe interface 212 of the first SSD 1 210a via a first bus 224. The data transfer speed of the high-speed bus 226 may be faster than that of the low-speed bus 230. It should be understood that the term "bus" may refer to a data path through which data may be transferred.

[0027] In storage system 200, high-speed bus 226 can be used to stream data, commands, and SSD status between SSDs from an upstream source to a downstream source. The high-speed bus 226 can be a unidirectional data path or a bidirectional data path. In the unidirectional data path, the data transfer direction of the high-speed bus 226 can be static. In the bidirectional data path, in-band (PCIe) control messages are used or the data transfer direction of the high-speed bus 226 is managed by using a sideband interface such as low-speed bus 230 or SMB bus 228. It should be understood that the bidirectional data path can be referred to as a half-duplex data channel herein. For example, data can be transferred from downstream EP PCIe interface 212 to upstream PCIe TX interface 218, or from upstream PCIe TX interface 218 to downstream EP PCIe interface 212, based on the data transfer direction of the high-speed bus 226.

[0028] Since storage system 200 requires a bidirectional control path to expose data storage device status, program status, adjust the data rate according to the slowest SSD (e.g., programming speed) in the daisy chain, propagate an uplink data transfer termination in the event of a program failure, etc., a backward channel function is required. In storage system 200, SMB bus 228 and low-speed bus 230 can be used as backward channels to transfer data, status, fault messages, etc. from downstream SSDs to upstream SSDs. In some cases, when PCIe TX interface 218 is a dual-port interface or a multi-port interface, one or more (but less than all) of the ports can be used as uplink interfaces, and the remaining ports can be used as downlink interfaces. Therefore, the uplink interface can be used to propagate data and commands downstream, and the downlink interface can be used to transfer data, commands, and control data back to the upstream device.

[0029] In storage system 200, multiple SSDs 210a to 210n can support programming the same data propagated through each SSD simultaneously. For example, when host device 202 sends data to be programmed to the first SSD 1 210a, the first SSD 1 210a can start programming the data into its own memory device such as Figure 1 NVM 110, and generate write commands for each of the other SSDs among the multiple SSDs 210a to 210n. The first SSD 2 210a can generate ECC for the data programmed into its own memory device. After a predetermined amount of data has been programmed into the first SSD 1 210a, the first SSD 1 210a sends the data and commands to the second SSD 2 210b via the high-speed bus 226. The second SSD 2 210b starts programming the data into its own memory device (e.g., Figure 1NVM 110). The second SSD 2 210b can generate ECC for the data programmed to its own memory device, where the generated ECC can be the same as or different from the ECC generated for the first SSD 1 210a. When a predetermined amount of data has been programmed to the second SSD 2 210b, the second SSD 1 210a sends data and commands to the second SSD 2 210b via the high-speed bus 226.

[0030] Thus, the data sent by the host device 202 is propagated through and stored in each of the multiple SSDs 210a to 210n. It should be understood that the predetermined amount of data can be a percentage of the data that has been programmed to the memory device. For example, the percentage of the data that has been programmed to the memory device in the total amount of data in the data packet can be between about 5% and about 50%, where "about" can refer to a range of plus or minus 5%. In some examples, the predetermined amount of data can be set based on the requirements of the SSDs in the daisy chain, such that the predetermined amount of data for one SSD can be the same as that for another SSD, or the predetermined amount of data for one SSD can be different from that for another SSD.

[0031] During the operation of each of the multiple SSDs 210a to 210n, each SSD can perform its own data management operations, such as garbage collection, read verification, wear leveling, etc. When an SSD determines that the data in its memory device is corrupted, the SSD can request data from the upstream SSD or the downstream SSD, or in some examples, request ECC from the upstream SSD or the downstream SSD. For example, if the second SSD 2 210b has corrupted data, the second SSD 2 210b can send a request for the relevant data to the first SSD 1 210a through the UART TX 220 of the second SSD 2210b or the SMB 214 of the second SSD 2 210b, or send a request to the adjacent downstream SSD (e.g., the third SSD 3) from the SMB 214 or the high-speed bus 226 of the second SSD 2 210b. Thus, since multiple copies of the same data are stored in multiple SSDs, data integrity can be maintained.

[0032] Figure 3 is an exemplary diagram 300 illustrating the time for serially programming data to multiple data storage devices (such as Figure 2 multiple SSDs 210a to 210n). The exemplary diagram 300 shows the total time for continuously programming data to three SSDs. In other words, after the data has been programmed to the current SSD, the data is only programmed to the next SSD. As Figure 3As shown, it takes 4 times the time increment to transfer the host data stream 302 to SSD 1. It takes an additional 4 times the time increment to program the host data stream into SSD 1 304. It takes an additional 4 times the time increment to program the host data stream into SSD 2 306. It takes an additional 4 times the time increment to program the host data stream into SSD 1 308. Therefore, the total delay between the time when SSD 1 first receives data from the host device and the time when the data is fully programmed into all SSDs is 12 times the time increment. The time increments shown and mentioned are not intended to be limiting, but rather provide examples of possible implementations.

[0033] Figure 4 is an exemplary graph 400 illustrating the time for parallel programming of data to multiple data storage devices (such as Figure 2 multiple SSDs 210a to 210n). For the purpose of simplicity, the time increments shown on the exemplary graph 400 are the same as those shown on the Figure 3 exemplary graph 300. The exemplary graph 400 may illustrate a storage system such as Figure 2 storage system 200, in which after a predetermined amount of data has been programmed into the current SSD, data is sent to the adjacent downstream SSD in the storage system via a high-speed bus such as high-speed bus 226. Since the data is being sent and programmed into each SSD before the previous SSD has finished programming the data into its own memory device, the programming of data into each SSD can occur partially simultaneously or in parallel. For example, as shown in the exemplary graph 400, the programming of data into SSD 1, SSD2, and SSD3 occurs in parallel. It takes 4 times the time increment to transfer the host data stream 402 to SSD 1. It takes an additional 4 times the time increment to program the host data stream into SSD 1 404. It takes an additional 4 times the time increment to program the host data stream into SSD 2 406. It takes an additional 4 times the time increment to program the host data stream into SSD 1 408. However, the programming of data into each SSD occurs before the complete transfer or programming of data from the previous source. Therefore, the total delay is reduced from 16 times the time increment to 3 times the time increment. The time increments shown and mentioned are not intended to be limiting, but rather provide examples of possible implementations.

[0034] Figure 5 is a flowchart of a method 500 for broadcasting data to multiple data storage devices (such as Figure 2 multiple SSDs 210a to 210n) in a storage system, in which the multiple data storage devices are connected together in a daisy chain. The method 500 may be performed by a storage system such as Figure 2is performed by the storage system 200, where the host device 202 or the first SSD 210a acts as the master device. For exemplary purposes, aspects of the storage system 200 may be referred to herein Figure 2 throughout.

[0035] At block 502, the first SSD 1 210a receives data from the host device 202. At block 504, the first SSD 1 210a begins to program the received data in its own memory device (e.g., Figure 1 the NVM 110). At block 506, the first SSD 1 210a generates a command to program the data into the memory device of the second SSD 2 210b (and any other SSDs in the storage system). At block 508, the first SSD 1 210a passes the data and the command to the second SSD 2 210b via a high-speed data path (e.g., the high-speed bus 226). The data and the command may be passed in response to a minimum amount of data (e.g., a predetermined amount of data) in the total data packet received from the host device 202 being programmed into the first SSD 1 210a. At block 510, the second SSD 2 210b receives the data and the command from the first SSD 1 210a. At block 512, the second SSD 2 210b begins to program the data into its own memory device (e.g., Figure 1 the NVM 110), where programming the data into the second SSD 2 210b occurs simultaneously or in parallel with programming the data into the first SSD 1 210a.

[0036] Figure 6 is a flowchart illustrating a method 600 of reading data from a data storage device among multiple data storage devices (such as Figure 2 the multiple SSDs 210a to 210n) in a storage system, where the multiple data storage devices are connected together in a daisy-chain manner. The method 600 may be performed by a storage system such as Figure 2 the storage system 200, where the host device 202 or the first SSD 210a acts as the master device. For exemplary purposes, aspects of the storage system 200 may be referred to herein Figure 2 throughout.

[0037] At block 602, the first SSD 1 210a requests data from the second SSD 2 210b. For example, in response to the first SSD 1 210a determining that in its own memory device (e.g., Figure 1The corresponding data in the NVM 110) has been corrupted and data is requested. At block 604, the second SSD 1210b determines whether the high-speed bus 226 supports a half-duplex data channel. If, at block 604, the high-speed bus 226 does not support a half-duplex data channel, then at block 606, the second SSD 2 210b sends the data to the first SSD 1 210a via a low-speed data path (e.g., the SMB bus 228 or the low-speed bus 230). However, if, at block 604, a half-duplex data channel is supported, then at block 608, the second SSD 2 210b determines whether the high-speed data path transmission direction is correct (i.e., in the correct transmission direction). If, at block 608, the high-speed data path transmission direction is incorrect, then at block 610, the second SSD 210b sends a command to change the transmission direction of the high-speed data transmission path via an in-band control message or an out-of-band control message. If, at block 608, the high-speed data path transmission direction is correct, or at block 610, once the direction of the high-speed data path has been changed to the correct direction, then at block 612, the second SSD 2 210b sends the requested data to the first SSD 1 via the high-speed bus 226.

[0038] By using the high-speed data path to broadcast data to multiple data storage devices, the total time required to broadcast and program data to multiple data storage devices can be reduced, and the overall storage system performance can be improved.

[0039] In one embodiment, a storage system includes a plurality of data storage devices. Each data storage device of the plurality of data storage devices is coupled to another data storage device of the plurality of data storage devices. Each data storage device includes an endpoint (EP) PCIe interface, a serial bus (SMB), and a high-speed serial trace port (HSSTP) interface. The HSSTP interface includes a PCIe transmitter (TX), a universal asynchronous receiver-transmitter (UART) receiver (RX), and a UART TX. The first data storage device is configured to send data to the EP PCIe interface of the second data storage device via the PCIe TX of the first data storage device. The first data storage device is coupled to the second data storage device. This sending occurs after a predetermined amount of data less than all of the data has been programmed into the first data storage device.

[0040] Data is sent from the PCIe TX of a first data storage device to the EP PCIe interface of a second data storage device via a high-speed data path. The high-speed data path is unidirectional. The high-speed data path is a TX path. The high-speed data path is bidirectional. The high-speed data path is configured to switch from the TX path to the RX path and from the RX path to the TX path. Control messages for controlling the switching are transmitted via the high-speed data path. Control messages for controlling the switching are transmitted via the UART RX and UART TX of an adjacent data storage device. Control information for controlling the switching is transmitted via the SMB of an adjacent data storage device. The second data storage device is configured to send data back to the first data storage device via a low-speed data path that couples the UART TX of the second data storage device to the UART RX of the first data storage device. The data transfer speed of the low-speed data path is slower than that of the high-speed data path. The first data storage device is coupled to a host device. The first data storage device is further configured to receive data from the host device via a data path that couples the root complex (RC) PCIe interface of the host device to the EP PCIe interface of the first data storage device, and cause the data to be transmitted to each other data storage device among a plurality of data storage devices for programming. The data is programmed into two or more data storage devices among the plurality of data storage devices simultaneously. The first data storage device is further coupled to at least one other data storage device in addition to the second data storage device. Each data storage device among the plurality of data storage devices is configured to communicate with each other data storage device among the plurality of data storage devices via the SMB. At least one data storage device among the plurality of data storage devices includes a second EP PCIe interface.

[0041] In another embodiment, a storage system includes a first data storage device and a second data storage device, the second data storage device being coupled to the first data storage device. The first data storage device is configured to program data into a non-volatile memory (NVM) device of the first data storage device, generate a write command for programming data into an NVM device of the second data storage device, and after a predetermined amount of data has been programmed into the NVM device of the first data storage device, send data to the second data storage device via a high-speed data path that couples the first data storage device to the second data storage device. The high-speed data path is different from the low-speed data path. The data transfer speed of the low-speed data path is lower than that of the high-speed data path. The high-speed data path is used to transfer write data. The low-speed data path is used to transfer read data. The second data storage device is configured to receive data from the first data storage device and program the data into the NVM device of the second data storage device. Programming the data into the NVM device of the second data storage device occurs partially simultaneously with programming the data into the NVM device of the first data storage device.

[0042] A first data storage device generates a first error correction code (ECC) for data that is programmed into the NVM device of the first data storage device and that is programmed into the NVM device of the first data storage device. A second data storage device generates a second ECC for data that is programmed into the NVM device of the second data storage device and that is programmed into the NVM device of the second data storage device. The second data storage device is configured to request the first ECC from the first data storage device to correct data programmed into the NVM device of the second data storage device. The first data storage device is configured to request data programmed into the NVM device of the second data storage device in response to determining that data programmed into the NVM of the first data storage device is corrupted. A low-speed data path is also used to transfer control data.

[0043] In another embodiment, a storage system includes a first data storage device, a second data storage device coupled to the first data storage device, means for transferring write data from the first data storage device to the second data storage device, and means for transferring read data and control data between the first data storage device and the second data storage device. The means for transferring write data is different from the means for transferring read data and control data.

[0044] The first data storage device is configured to receive data from a host device for programming into the memory device of the first data storage device, program the data into the memory device of the first data storage device, generate a command for programming the data into the memory device of the second data storage device for the second data storage device, and send the data and the generated command to the second data storage device. The second data storage device is configured to program the data into the memory device of the second data storage device. Programming the data into the memory device of the second data storage device occurs partially concurrently with programming the data into the memory device of the first data storage device.

[0045] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be conceived without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A storage system, comprising: A plurality of data storage devices, wherein: Each data storage device of the plurality of data storage devices is coupled to another data storage device of the plurality of data storage devices; Each data storage device includes: Endpoint (EP) Peripheral Component Interconnect Express (PCI) (PCIe) interface; Serial Bus (SMB); and A high speed serial trace port (HSSTP) interface, wherein the HSSTP interface comprises: PCIe transmitter (TX); Universal Asynchronous Receiver-Transmitter (UART) receiver (RX); and UART TX; and A first data storage device, the first data storage device being configured to send data to the EP PCIe interface of a second data storage device via the PCIe TX of the first data storage device, wherein: The first data storage device is coupled to the second data storage device; and The transmitting occurs after a predetermined amount of data less than all of the data has been programmed to the first data storage device.

2. The storage system according to claim 1, wherein: Data is sent to the EP PCIe interface of the second data storage device via the PCIe TX of the first data storage device through a high-speed data path.

3. The storage system according to claim 2, wherein: The high-speed data path is unidirectional, and wherein the high-speed data path is a TX path.

4. The storage system according to claim 2, wherein: The high-speed data path is bidirectional, wherein the high-speed data path is configured to switch from a TX path to an RX path and from the RX path to the TX path.

5. The storage system according to claim 4, wherein: A control message for controlling the switching is transmitted via the high-speed data path.

6. The storage system according to claim 4, wherein: A control message for controlling the switching is transmitted through the UART RX and the UART TX of the adjacent data storage device.

7. The storage system according to claim 4, wherein: The switching control The control information of the switching is transmitted through the SMB of the adjacent data storage device.

8. The storage system according to claim 2, wherein: The second data storage device is configured to send data back to the first data storage device via a low-speed data path that couples the UART TX of the second data storage device to the UART RX of the first data storage device, and wherein the data transmission speed of the low-speed data path is slower than that of the high-speed data path.

9. The storage system according to claim 1, wherein: The first data storage device is coupled to a host device, and wherein the first data storage device is further configured to: receiving the data from the host device via a data path coupling a root complex (RC) PCIe interface of the host device to the EP PCIe interface of the first data storage device; and The data is caused to be transferred to each other data storage device of the plurality of data storage devices for programming.

10. The storage system according to claim 1, wherein: The data is simultaneously programmed to two or more data storage devices of the plurality of data storage devices.

11. The storage system according to claim 1, wherein: The first data storage device is also coupled to at least one other data storage device other than the second data storage device.

12. The storage system according to claim 1, wherein: Each data storage device of the plurality of data storage devices is configured to communicate with each other data storage device of the plurality of data storage devices via the SMB.

13. The storage system according to claim 1, wherein: At least one data storage device of the plurality of data storage devices includes a second EP PCIe interface.

14. A storage system, comprising: a first data storage device; and a second data storage device, the second data storage device being coupled to the first data storage device, wherein the first data storage device is configured to: programming data into a non-volatile memory (NVM) device of said first data storage device; generating a write command for the second data storage device to program the data into a NVM device of the second data storage device; and sending the data to the second data storage device via a high-speed data path coupling the first data storage device to the second data storage device after a predetermined amount of the data has been programmed to the NVM device of the first data storage device, wherein: The high-speed data path is different from the low-speed data path; The data transmission speed of the low-speed data path is lower than that of the high-speed data path; The high-speed data path is used to transmit write data; and The low-speed data path is used to transmit read data; and Wherein, the second data storage device is configured as: receiving said data from said first data storage device; and Programming the data to the NVM device of the second data storage device, wherein programming the data to the NVM device of the second data storage device occurs partially simultaneously with programming the data to the NVM device of the first data storage device.

15. The storage system according to claim 14, wherein: generating, by the first data storage device, a first error correction code (ECC) for the data, the data being programmed to the NVM device of the first data storage device and being programmed to the NVM device of the first data storage device; as well as A second ECC is generated by the second data storage device for the data, the data is programmed to the NVM device of the second data storage device and is programmed to the NVM device of the second data storage device.

16. The storage system according to claim 15, wherein: The second data storage device is configured to request the first ECC from the first data storage device to correct the data programmed to the NVM device of the second data storage device.

17. The storage system according to claim 15, wherein: The first data storage device is configured to request the data programmed to the NVM device of the second data storage device in response to determining that the data programmed to the NVM of the first data storage device is damaged.

18. The storage system according to claim 14, wherein: The low-speed data path is also used to transmit control data.

19. A storage system, comprising: a first data storage device; a second data storage device coupled to the first data storage device; means for transferring write data from said first data storage device to said second data storage device; and Means for transmitting read data and control data between the first data storage device and the second data storage device, wherein the means for transmitting write data is different from the means for transmitting read data and control data.

20. The storage system of claim 19, wherein: The first data storage device is configured as: receiving data from a host device for programming into a memory device of said first data storage device; programming said data into said memory device of said first data storage device; generating a command for the second data storage device to program the data into a memory device of the second data storage device; as well as sending the data and the generated command to the second data storage device; and The second data storage device is configured as: Programming the data to the memory device of the second data storage device, wherein programming the data to the memory device of the second data storage device occurs partially simultaneously with programming the data to the memory device of the first data storage device.

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