Semiconductor device and method of manufacturing the same

Abstract

The semiconductor chip (2) is flip-chip mounted on the substrate (1). A metal cover (4) having a top plate in which an opening (6) is formed above the semiconductor chip (2) is bonded to the substrate (1) so as to cover the semiconductor chip (2). The metal bonding material (7) bonds the top plate of the metal lid (4) and the back surface electrode (8) of the semiconductor chip (2), and blocks the opening (6).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices having a backside cooling structure and electromagnetic shielding performance have been proposed. In an existing semiconductor device, a heat sink is bonded to the back surface of an MMIC mounted on a package substrate in a flip-chip mounting manner. After resin sealing, back grinding is performed to expose the heat sink from the back surface of the package. Heat of the MMIC is released to a heat dissipation mechanism such as a module via the heat sink. The outer surface of the resin is covered with a metal shielding film, and has shielding properties against external interference (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Patent No. 7031004

[0004] In an existing semiconductor device, it is necessary to bond a heat sink to the back surface of the MMIC. In addition, special processes such as back grinding and formation of a shielding film are required. Therefore, there are problems such as an increase in manufacturing cost and a lengthening of the manufacturing period. Summary of the Invention

[0005] The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device and a method for manufacturing the same that can reduce the manufacturing cost and shorten the manufacturing period without impairing the backside cooling structure and electromagnetic shielding performance.

[0006] The semiconductor device according to the present disclosure is characterized by including: a substrate; a semiconductor chip mounted on the substrate in a flip-chip mounting manner; a metal lid bonded to the substrate so as to cover the semiconductor chip, and having a top plate in which an opening is formed above the semiconductor chip; and a metal bonding material that bonds the top plate of the metal lid to a backside electrode of the semiconductor chip and closes the opening.

[0007] The method for manufacturing a semiconductor device according to the present disclosure is characterized by including the following steps: mounting a semiconductor chip on a substrate in a flip-chip mounting manner; bonding the metal lid to the substrate so that an opening formed in a top plate of the metal lid is disposed above the semiconductor chip to cover the semiconductor chip; and introducing a metal bonding material into the opening, melting the metal bonding material to bond the top plate of the metal lid to a backside electrode of the semiconductor chip, and closing the opening with the metal bonding material.

[0008] In the present disclosure, heat can be dissipated from the back surface of the package via a metal bonding material and a metal lid. Since electromagnetic shielding performance can be ensured by the metal lid, there is no need to form a shielding film on the outer surface of the package. In addition, since resin sealing is not required, back grinding of the resin is also not required. Therefore, the manufacturing cost can be reduced and the manufacturing period can be shortened without compromising the back cooling structure and electromagnetic shielding performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1.

[0010] Figure 2 is a top view showing the inside of a semiconductor device according to Embodiment 1.

[0011] Figure 3 is a flowchart of the manufacturing process of a semiconductor device according to Embodiment 1.

[0012] Figure 4 is a cross-sectional view showing the manufacturing process of a semiconductor device according to Embodiment 1.

[0013] Figure 5 is a cross-sectional view showing a semiconductor device according to Embodiment 2.

[0014] Figure 6 is a cross-sectional view showing the manufacturing process of a semiconductor device according to Embodiment 2.

[0015] Figure 7 is a cross-sectional view showing a semiconductor device according to Embodiment 3.

[0016] Figure 8 is a cross-sectional view showing the manufacturing process of a semiconductor device according to Embodiment 3.

[0017] Figure 9 is a cross-sectional view showing a semiconductor device according to Embodiment 4.

[0018] Figure 10 is a cross-sectional view showing a semiconductor device according to Embodiment 5.

[0019] Figure 11 is a cross-sectional view showing a semiconductor device according to the comparative example.

[0020] Figure 12 is a cross-sectional view showing a semiconductor device according to Embodiment 6.

[0021] Figure 13 is a top view showing the back surface of a semiconductor chip according to Embodiment 6.

[0022] Figure 14This is a cross-sectional view of the semiconductor device according to Embodiment 7.

[0023] Figure 15 This is a cross-sectional view of the manufacturing process of the semiconductor device according to Embodiment 8.

[0024] Figure 16 This is a cross-sectional view of the semiconductor device according to Embodiment 9. Detailed Embodiments

[0025] With reference to the accompanying drawings, the semiconductor device and its manufacturing method according to the embodiments will be described. For the same or corresponding components, the same reference numerals may be used, and repeated descriptions may be omitted.

[0026] Embodiment 1

[0027] Figure 1 This is a cross-sectional view of the semiconductor device according to Embodiment 1. Figure 2 This is a top view of the inside of the semiconductor device according to Embodiment 1. This semiconductor device is a high-frequency semiconductor device having a backside cooling structure and electromagnetic shielding performance.

[0028] A plurality of semiconductor chips 2 are mounted on the upper surface of the multilayer organic substrate 1 in a flip-chip mounting manner. The surface electrodes of the semiconductor chips 2 are solder-bonded to the upper surface electrodes of the multilayer organic substrate 1. Surface-mounted components 3 such as capacitors are also mounted on the upper surface of the multilayer organic substrate 1. The metal lid 4 is joined to the upper surface of the multilayer organic substrate 1 by solder 5 so as to cover the semiconductor chips 2 and the surface-mounted components 3. An opening 6 is formed in the top plate of the metal lid 4 above the central portion of the semiconductor chips 2. The welding material 7 joins the lower surface of the top plate of the metal lid 4 to the back electrodes 8 of the semiconductor chips 2, thereby closing the opening 6. The metal lid 4 is connected to the GND of the multilayer organic substrate 1.

[0029] Next, the manufacturing method of the above semiconductor device will be described. Figure 3 This is a flowchart of the manufacturing process of the semiconductor device according to Embodiment 1. Figure 4 This is a cross-sectional view of the manufacturing process of the semiconductor device according to Embodiment 1.

[0030] First, solder paste is printed on the upper surface of the multilayer organic substrate 1 (step S1). The semiconductor chips 2 and the surface-mounted components 3 are mounted on the solder paste (step S2). The solder paste is melted by reflow, and the semiconductor chips 2 are mounted on the multilayer organic substrate 1 in a flip-chip mounting manner (step S3). The surface-mounted components 3 are also mounted on the multilayer organic substrate 1. The multilayer organic substrate 1 is cleaned after reflow.

[0031] Next, the metal lid 4 is bonded to the multilayer organic substrate 1 in such a manner that the opening 6 formed in the top plate of the metal lid 4 is disposed above the semiconductor chip 2 to cover the semiconductor chip 2. Next, a solder tablet 9 is inserted into the opening 6 (step S4). Solder balls may be used instead of the solder tablet 9. The solder tablet 9 is melted by reflow to bond the top plate of the metal lid 4 and the back electrode 8 of the semiconductor chip 2, thereby closing the opening 6 (step S5). The solder tablet 9 after reflow is the welding material 7. The multilayer organic substrate 1 is cleaned after reflow. Finally, the wafer is diced (step S6).

[0032] As described above, in the present embodiment, the heat of the semiconductor chip 2 can be released from the back surface of the package via the welding material 7 and the metal lid 4. Since the electromagnetic shielding performance against external interference can be ensured by the metal lid 4, it is not necessary to form a shielding film on the outer surface of the package. In addition, since resin sealing is not required, back grinding of the resin is not required either. Therefore, the manufacturing cost can be reduced and the manufacturing period can be shortened without impairing the back surface cooling structure and the electromagnetic shielding performance. In addition, since individual chip heat sinks are not required, further downsizing can be achieved.

[0033] In addition, openings 6 are formed in the top plate of the metal lid 4 above the central portions of the respective semiconductor chips 2 of the plurality of semiconductor chips 2. The solder tablets 9 are inserted into the respective openings 6 and reflowed. Each welding material 7 bonds the top plate of the metal lid 4 and the back electrode 8 of each chip, thereby closing the openings 6 located above each chip. Since the height deviation after mounting of the plurality of semiconductor chips 2 is absorbed by the welding material 7 on the back surface of the chips, the plurality of semiconductor chips 2 can be mounted in the same package. In addition, the worst value of the predicted tolerance is predicted, the amount of the welding material 7 to be inserted is adjusted, and the excess solder is discharged from the opening 6. Thereby, the manufacturing yield can be improved.

[0034] In addition, in the present embodiment, the welding material 7 is used as the metal bonding material for bonding the metal lid 4 and the semiconductor chip 2 to close the opening 6, but it is not limited thereto, and a metal bonding material having good thermal conductivity and electrical conductivity can be used.

[0035] Embodiment 2

[0036] Figure 5FIG. 0 is a cross-sectional view showing a semiconductor device according to Embodiment 2. In the present embodiment, as a metal bonding material for bonding the metal lid 4 to the back surface of the semiconductor chip 2 to seal the opening 6, a mixture of a solder material 7 and metal balls 10 made of Cu is used. The thermal conductivity of the solder material 7 also depends on the type and ratio of the alloy, but is about 30 to 60 W / m·K. The thermal conductivity of Cu is 398 W / m·K. That is, the thermal conductivity of the metal balls 10 is higher than that of the solder material 7. Therefore, compared with Embodiment 1 in which only the solder material 7 is used to fill the space between the back surface of the semiconductor chip 2 and the metal lid 4, the heat dissipation property of the present embodiment is more excellent. In addition, since the metal balls 10 occupy most of the space, large voids that affect the thermal resistance are not easily generated. In addition, the material of the metal balls 10 is not limited to Cu as long as it is a metal having a thermal conductivity higher than that of the solder material 7. For example, it may also be Ag. However, Au is expensive and Al is difficult to use.

[0037] Protrusions 11 extending to the side portions of the respective semiconductor chips 2 are provided on the lower surface of the top plate of the metal lid 4. For example, the diameter of the metal balls 10 is set to 300 μm, the height h of the protrusions 11 is set to 350 μm, and the lateral interval Δs between the side surface of the semiconductor chip 2 and the side surface of the protrusions 11 is set to 140 μm. By making the interval Δs smaller than the diameter of the metal balls 10, it is possible to prevent the metal balls 10 from falling off the back surface of the semiconductor chip 2.

[0038] Figure 6 FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device according to Embodiment 2. Cu core balls 12 are put into the opening 6 and filled into the space between the metal lid 4 and the back surface of the semiconductor chip 2. The Cu core balls 12 are obtained by covering the surface of the Cu metal balls 10 with the solder material 7. By performing reflow to melt the solder material 7 of the Cu core balls 12, the metal lid 4 and the back surface of the semiconductor chip 2 are solder-bonded. Since the space between the metal lid 4 and the semiconductor chip 2 cannot be filled only with the solder material 7 of the Cu core balls 12, after the Cu core balls 12 are put into the opening 6, the solder sheet 9 is further put into the opening 6. The width of the opening 6 of the metal lid 4 is designed to be, for example, 50% larger than the outer shapes of the Cu core balls 12 and the solder sheet 9. Other structures and effects are the same as those in Embodiment 1.

[0039] Embodiment 3

[0040] Figure 7 FIG. 14 is a cross-sectional view showing a semiconductor device according to Embodiment 3. As a metal bonding material, a solder paste 13 mixed with metal balls 10 made of Cu is used. In addition, as a metal bonding material, a resin paste mixed with Ag fillers or Ag nanoparticles can also be used. However, the thermal conductivity of the solder is higher than that of the resin paste mixed with Ag fillers.

[0041] Figure 8 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 3. Solder paste 13 is injected from nozzle 14 of a dispenser, which is a solder coating device, into opening 6 of metal lid 4. Since the viscosity of solder paste 13 is high, metal balls 10 do not roll and fall off from the back surface of the chip. The diameter of metal balls 10 is smaller than that of Figure 6 Cu core balls 12 of , and it has no effect on the height deviation. Other structures and effects are the same as those of Embodiment 2.

[0042] Embodiment 4

[0043] Figure 9 This is a cross-sectional view showing the semiconductor device according to Embodiment 4. Heat-generating parts 15 such as transistors are formed on the surface of semiconductor chip 2. Heat generally diffuses at a gradient of 45 degrees with respect to the heat-generating surface. Therefore, no opening 6 with a low thermal conductivity is formed within the 45-degree heat diffusion region from heat-generating part 15 toward the top plate of metal lid 4. Thus, opening 6 does not interfere with the heat diffusion from heat-generating part 15, and the thermal resistance of the device can be reduced. Other structures and effects are the same as those of Embodiment 1 and the like.

[0044] Embodiment 5

[0045] Figure 10 This is a cross-sectional view showing the semiconductor device according to Embodiment 5. Opening 6 has a first opening 6a and a second opening 6b formed at a position above the first opening 6a and having a width wider than that of the first opening 6a.

[0046] The effects of this embodiment will be described by comparison with a comparative example. Figure 11 This is a cross-sectional view showing the semiconductor device according to the comparative example. In the comparative example, the width of opening 6 is uniform. For example, when the interval between metal lid 4 and semiconductor chip 2 becomes smaller due to the height deviation of semiconductor chip 2, after reflow, excess solder material 7 overflows from opening 6 to a position above the top plate of metal lid 4. As a result, it is difficult to obtain the flatness of the top plate of metal lid 4, and it is difficult to make surface contact with components such as heat sinks.

[0047] In contrast, in this embodiment, even when the amount of solder is excessive, the excess solder material 7 flows into the second opening 6b with a wider width. Therefore, the occurrence of the bulge of the solder material 7 overflowing to a position above the top plate of metal lid 4 can be suppressed. Other structures and effects are the same as those of Embodiment 1 and the like.

[0048] Embodiment 6

[0049] Figure 12FIG. 0 is a cross-sectional view showing a semiconductor device according to Embodiment 6. The back electrode 8 has a first metal plating layer 8a and a second metal plating layer 8b formed on the first metal plating layer 8a. The first metal plating layer 8a is a metal with poor solder wettability, such as Ni. The second metal plating layer 8b is a metal with good solder wettability, such as Au. That is, the second metal plating layer 8b has better wettability with respect to the welding material 7 than the first metal plating layer 8a.

[0050] Figure 13 FIG. 4 is a top view showing the back surface of the semiconductor chip according to Embodiment 6. In the bonding region where the opening 6 and the heat generating portion 15 are located when viewed from above, the second metal plating layer 8b is formed and the first metal plating layer 8a is not exposed. In the exposed region surrounding the bonding region when viewed from above, an opening is formed in the second metal plating layer 8b and the first metal plating layer 8a is exposed from the second metal plating layer 8b. In the outer peripheral region of the semiconductor chip 2 outside the exposed region, the second metal plating layer 8b is formed and the first metal plating layer 8a is not exposed.

[0051] The first metal plating layer 8a with poor wettability is exposed in a ring shape so as to surround the periphery of the opening 6 and the heat generating portion 15 when viewed from above. The welding material 7 bonds the second metal plating layer 8b and the metal lid 4 in the bonding region and does not leak to the exposed region where the first metal plating layer 8a with poor wettability is exposed. Therefore, it is possible to reduce defects such as solder leakage to unnecessary regions and solder creeping out from the back surface of the chip. Other structures and effects are the same as those of Embodiment 1 and the like.

[0052] Embodiment 7

[0053] Figure 14 FIG. 14 is a cross-sectional view showing a semiconductor device according to Embodiment 7. The back electrode 8 is formed at the central portion of the back surface of the semiconductor chip 2, and the semiconductor of the semiconductor chip 2 is exposed at the outer peripheral portion of the back surface of the semiconductor chip 2. GaAs and SiC have poor metal wettability, and Si also has poor wettability depending on the metal. Therefore, it is possible to reduce defects such as solder leakage to unnecessary regions and solder creeping out from the back surface of the chip. Other structures and effects are the same as those of Embodiment 1 and the like.

[0054] Embodiment 8

[0055] Figure 15 FIG. 21 is a cross-sectional view showing a manufacturing process of a semiconductor device according to Embodiment 8. A metal plating layer 16 having better wettability with respect to the welding material 7 than the back electrode 8 and the metal lid 4 is formed on the lower surface of the metal lid 4 and the back electrode 8. The metal plating layer 16 is the same material as the welding material 7, such as a medium-temperature solder of the Sn - Ag - Cu system.

[0056] When there is a distance between the heat-generating part 15 and the opening 6 of the metal lid 4, even if the welding material 7 is introduced from the opening 6, there is a possibility that the welding material 7 cannot wet the area above the heat-generating part 15. Therefore, in the present embodiment, a metal plating 16 is applied in advance to the area where the welding material 7 is to be filled. As a result, during reflow, the welding material 7 easily flows inside, and the thermal resistance can be reduced. Other structures and effects are the same as those of Embodiment 1 and the like.

[0057] Embodiment 9

[0058] Figure 16 FIG. is a cross-sectional view showing a semiconductor device according to Embodiment 9. A recess 17 is formed in the central portion of the back surface of the semiconductor chip 2. A back electrode 8 is formed on the bottom surface of the recess 17. The back electrode 8 is not formed on the outer peripheral portion of the back surface of the semiconductor chip 2, but the semiconductor is exposed.

[0059] The outer peripheral portion of the back surface of the semiconductor chip 2 protrudes more than the central portion and has no back electrode 8, resulting in poor wettability of the solder. Therefore, even when the amount of solder is excessive, it is possible to prevent the welding material 7 from overflowing to the outer peripheral portion of the back surface and leaking to the side of the chip. Other structures and effects are the same as those of Embodiment 1 and the like.

[0060] Description of Reference Numerals

[0061] 1... Multi-layer organic substrate (substrate); 2... Semiconductor chip; 4... Metal lid; 6... Opening; 6a... First opening; 6b... Second opening; 7... Welding material (metal bonding material); 8... Back electrode; 8a... First metal plating; 8b... Second metal plating; 9... Solder sheet (metal bonding material); 10... Metal ball (metal bonding material); 11... Protrusion; 13... Solder paste (metal bonding material); 15... Heat-generating part; 16... Metal plating; 17... Recess.

Claims

1. A semiconductor device, characterized in that, comprising: a substrate; a semiconductor chip mounted on the substrate in a flip-chip mounting manner; a metal lid joined to the substrate so as to cover the semiconductor chip, and having a top plate with an opening formed above the semiconductor chip; and a metal bonding material that bonds the top plate of the metal lid to the back electrode of the semiconductor chip to block the opening.

2. The semiconductor device according to claim 1, characterized in that, the semiconductor chip has a plurality of chips, above each chip, the opening is formed in the top plate of the metal lid, the metal bonding material bonds the top plate of the metal lid to the back electrode of each chip to block the opening located above each chip.

3. The semiconductor device according to claim 1 or 2, characterized in that, the metal bonding material is a mixture of a welding material and metal balls having a thermal conductivity higher than that of the welding material.

4. The semiconductor device according to claim 3, characterized in that, protrusions extending to the side portion of the semiconductor chip are provided on the lower surface of the top plate of the metal lid, the distance between the side surface of the semiconductor chip and the side surface of the protrusion is smaller than the diameter of the metal ball.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, a heat generating portion is formed on the surface of the semiconductor chip, the opening is not formed in a 45-degree heat diffusion region from the heat generating portion toward the top plate of the metal lid.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, the opening has a first opening and a second opening formed at a position above the first opening and having a width wider than that of the first opening.

7. The semiconductor device according to claim 5, characterized in that, the back electrode has a first metal plating layer and a second metal plating layer formed on the first metal plating layer and having better wettability of the metal bonding material than the first metal plating layer, the second metal plating layer is formed in a bonding region where the opening and the heat generating portion are located in a top view, in an exposed region surrounding the bonding region in a top view, the first metal plating layer is exposed from the second metal plating layer.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that, the back electrode is formed at the central portion of the back surface of the semiconductor chip, and the semiconductor of the semiconductor chip is exposed at the outer peripheral portion of the back surface of the semiconductor chip.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, a metal plating layer having better wettability of the metal bonding material than the back electrode and the metal lid is formed on the lower surface of the metal lid and the back electrode.

10. The semiconductor device according to any one of claims 1 to 6, characterized in that, a concave portion is formed at the central portion of the back surface of the semiconductor chip, and the back electrode is formed on the bottom surface of the concave portion and not on the outer peripheral portion of the back surface of the semiconductor chip.

11. A manufacturing method of a semiconductor device, characterized in that, it comprises the following steps: mounting a semiconductor chip on a substrate in a flip-chip mounting manner; bonding the metal lid to the substrate in such a way that an opening formed in a top plate of the metal lid is disposed above the semiconductor chip to cover the semiconductor chip; and introducing a metal bonding material into the opening, melting the metal bonding material to bond the top plate of the metal lid and a back electrode of the semiconductor chip, and using the metal bonding material to seal the opening.

12. The manufacturing method of a semiconductor device according to claim 11, characterized in that, a material obtained by covering the surface of a metal ball with a soldering material is introduced into the opening as the metal bonding material.

13. The manufacturing method of a semiconductor device according to claim 11, characterized in that, a solder paste mixed with metal balls, a resin paste mixed with Ag fillers, or Ag nanoparticles is injected into the opening as the metal bonding material.

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