Communication system for power noise reduction

Abstract

A method and apparatus for transmitting a data signal, comprising: receiving a digital data signal through a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal through a first inverted data input of the transmitter multiplexer; counting the clock signals through a first counter; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first select signal to a first select signal input of the transmitter multiplexer; and alternately transmitting the digital data signal and the inverted digital data signal as a transmitter output signal to a receiver in response to the first select signal and through a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output being operably coupled to the data link.

Description

Background Art

[0001] The present invention relates to data transfer technology, and more particularly, to data transfer technology on one or more data links.

[0002] A data link is an interconnection between agents, where in a given data transaction, one agent is the "transmitter" and the other agent is the "receiver". Among other examples, an example data link can be arranged between a processor and a disk drive, between processors on separate boards in a computer system, and / or between processors on the same board or package. For two agents to communicate, the two agents agree on the timing of sending and receiving data. Such an agreement is commonly referred to as a clocking scheme in link design.

[0003] For example, in a "common clock" scheme, all components in the interconnection share a single clock when sending and receiving data. In a "source synchronous" clock scheme, the clock signal is sent together with the data signal. An "embedded" clock scheme embeds the clock signal in the data transfer, but not without drawbacks including the need for clock data recovery circuitry and bandwidth limitations. Within a given clock scheme, the transmission protocol defines when the transmitter sends data and when the receiver samples the transmitted data.

[0004] The transmission protocol may include techniques for idling agents that may have no data to transmit or are in an idle state, but such idling introduces various delays, data overheads, and complexities. Summary of the Invention

[0005] According to a first embodiment of the present invention, a method includes: receiving a digital data signal through a first input of a multiplexer operably coupled to a transmitter of a data link; transmitting the digital data signal to a receiver operably coupled to the data link through a digital data signal output of the multiplexer; receiving a first selection signal indicating an idle mode for the transmitter through a selection signal input of the multiplexer; receiving a patterned data signal through a second input of the multiplexer; and transmitting the patterned data signal to the receiver through the digital data signal output and in response to the first selection signal.

[0006] In a first aspect of the first embodiment, the method further includes intermittently passing the patterned data signal to the second input, thereby reducing the switching rate of the patterned data signal received through the second input of the multiplexer.

[0007] In a second aspect, in combination with the first embodiment and / or aspects thereof, the method further includes receiving, via a selection signal input of a multiplexer, a second selection signal indicative of a data signal transmission mode for a transmitter, and the step of transmitting a digital data signal includes transmitting the digital data signal to a receiver in response to the second selection signal.

[0008] In a third aspect, in combination with the first embodiment and / or aspects thereof, the method further includes selecting an idle mode for the transmitter based on the digital data signal. In a fourth aspect, the selecting step includes selecting an idle mode for the transmitter based on a switching activity value of the digital data signal. In a fifth aspect, the selecting step includes detecting at least one of an idle flow control unit / digit (flit) of the digital data signal and an idle physical digit (phit) of the digital data signal, and selecting an idle mode for the transmitter based on at least one of the idle flit and the idle phit.

[0009] In a sixth aspect, in combination with the first embodiment and / or aspects thereof, a first processor includes a transmitter and a second processor includes a receiver.

[0010] According to a second embodiment of the present invention, a method includes: receiving a digital data signal via a first data input of a transmitter multiplexer; inverting the digital data signal via a first inverter to provide an inverted digital data signal; receiving the inverted digital data signal via a first inverted data input of the transmitter multiplexer; counting a clock signal via a first counter; transmitting, via the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting the digital data signal and the inverted digital data signal to a receiver as a transmitter output signal in response to the first selection signal and via a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output being operably coupled to a data link.

[0011] In a first aspect of the second embodiment, the receiver includes a second counter and a receiver multiplexer arranged to receive the transmitter output signal, and the method further includes receiving the transmitter output signal via a second data input of the receiver multiplexer; inverting the transmitter output signal via a second inverter to provide an inverted transmitter output signal; receiving the inverted digital data signal via a second inverted data input of the receiver multiplexer; counting the clock signal via the second counter; transmitting, via the second counter and in response to the second counter counting a threshold number of clock cycles, a second selection signal to a second selection signal input of the receiver multiplexer; and alternately providing the transmitter output signal and the inverted transmitter output signal in response to the selection signal and via a second digital data signal output of the receiver multiplexer.

[0012] In a second aspect of the second embodiment, the counting step by the first counter includes counting each occurrence of a clock cycle that counts a threshold number by the first counter, and providing a first selection signal in response to each occurrence of the clock cycle that counts the threshold number, and the counting step by the second counter includes counting each occurrence of a clock cycle that counts a threshold number by the second counter, and providing a second selection signal in response to each occurrence of the clock cycle that counts the threshold number.

[0013] In a third aspect of the second embodiment, in combination with the second embodiment and / or aspects thereof, the method further includes synchronizing the first counter and the second counter. In a fourth aspect, in combination with the second embodiment and / or aspects thereof, the first processor includes a transmitter multiplexer, and the second processor includes a receiver multiplexer.

[0014] As described herein, the first and second embodiments and aspects thereof may be combined in additional embodiments.

[0015] According to a third embodiment of the present invention, a system includes a data link; a receiver operatively coupled to the data link; a memory that stores data for generating a stylized data signal; and a transmitter operatively coupled to the data link and the memory, the transmitter being arranged to transmit a digital data signal and including a multiplexer, the multiplexer including a first input arranged to receive a digital data signal, a second input arranged to receive a stylized data signal, a selection signal input arranged to receive a mode selection signal, and a digital data signal output arranged to transmit a multiplexer output signal to the data link, the multiplexer being adapted to selectively output the digital data signal and the stylized data signal as the multiplexer output signal in response to receiving the mode selection signal, the mode selection signal indicating an idle mode of the transmitter and a data signal transmission mode of the transmitter.

[0016] In a first aspect of the third embodiment, the system further includes a switch arranged between the memory and the stylized data signal input for intermittently passing the stylized data signal to the stylized data signal input.

[0017] In a second aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the processor includes at least one of the memory and the transmitter. In a third aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the memory includes a processor register that stores data for generating a stylized data signal.

[0018] In a fourth aspect of the third embodiment, the system further includes a serializer operatively coupled to the processor register and the second input, the serializer being adapted to serialize data to generate a styled data signal. In a fifth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the multiplexer includes a 1-of-2 multiplexer.

[0019] In a sixth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the system further includes a mode selection controller adapted to provide a mode selection signal based on a digital data signal. In a seventh aspect of the third embodiment, the mode selection controller is adapted to provide a mode selection signal in response to a digital data signal including a flow control message indicating an idle mode. In an eighth aspect of the third embodiment, the mode selection controller is adapted to provide a mode selection signal in response to a digital data signal including a flow control message indicating a data signal transmission mode.

[0020] In a ninth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the transmitter is arranged to transmit a clockless data signal as the digital data signal. In a tenth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the memory includes a programmable memory arranged to receive data for generating the styled data signal.

[0021] According to a fourth embodiment of the present invention, a system includes a first inverter arranged to receive a digital data signal, a clock, a first counter operatively coupled to the clock, and a transmitter multiplexer including: a first input arranged to receive the digital data signal, a first inverted data input operatively coupled to the first inverter and arranged to receive the inverted digital data signal, a first selection signal input operatively coupled to the first counter and arranged to receive a first selection signal, and a first output arranged to transmit a transmitter multiplexer output signal, the first counter being adapted to provide the first selection signal in response to a threshold number of counted clock cycles such that the transmitter multiplexer alternately transmits the digital data signal and the inverted digital data signal as the transmitter multiplexer output signal.

[0022] In a first aspect of the fourth embodiment, the system further includes a second inverter, a second counter, a receiver multiplexer, and a data link operably coupled to the transmitter multiplexer and the receiver multiplexer, the receiver multiplexer including a second input arranged to receive the transmitter multiplexer output signal, a second inverted data input operably coupled to the second inverter and arranged to receive the inverted transmitter multiplexer output signal, a second select signal input operably coupled to the second counter and arranged to receive a second select signal, and a second output arranged to provide a receiver multiplexer output signal, the second counter being adapted to provide the second select signal in response to a threshold number of clock cycles of counted clock cycles, such that the receiver multiplexer alternately provides the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal as the receiver multiplexer output signal.

[0023] In a second aspect of the fourth embodiment, in combination with the fourth embodiment and / or aspects thereof, the system further includes a processor operably coupled to a computer-readable storage medium having computer-readable program code embodied therein, the computer-readable program code being executable by the processor to synchronize the first counter and the second counter.

[0024] In a third aspect of the fourth embodiment, in combination with the fourth embodiment and / or aspects thereof, the first processor includes a transmitter multiplexer, and the second processor includes a receiver multiplexer.

[0025] In a fourth aspect of the fourth embodiment, in combination with the fourth embodiment and / or aspects thereof, the first counter is a programmable counter adapted to change the programmable counter in response to a threshold number of clock cycles of counted clock cycles to provide a first select signal. In a fifth aspect of the fourth embodiment, in combination with the fourth embodiment and / or aspects thereof, the first counter is a first programmable counter adapted to change the first programmable counter in response to a threshold number of clock cycles of counted clock cycles to provide a first select signal, and the second counter is a second programmable counter adapted to change the second programmable counter in response to a threshold number of clock cycles of counted clock cycles to provide a second select signal.

[0026] As described herein, the third and fourth embodiments and aspects thereof may be combined in additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 An example of a communication system is depicted.

[0028] Figure 2 An example of a transmitter agent is described.

[0029] Figure 3 Describes an example of a transmitter agent.

[0030] Figure 4 Depicts an example of a communication system.

[0031] Figure 5 Depicts an example method for data communication.

[0032] Figure 6 Depicts an example method for data communication.

[0033] Figure 7 Depicts an example method for data communication.

[0034] Figure 8 Describes an example of a transmitter agent.

[0035] Figure 9 Depicts an example computing environment. Detailed Description

[0036] Aspects of the present disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or in a manner that at least partially overlaps in time.

[0037] A computer program product embodiment (“CPP embodiment” or “CPP”) is a term used in this disclosure to describe any collection of one or more storage media (also referred to as “media”) collectively included in a set of one or more storage devices, the set of one or more storage devices collectively including machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device that can hold and store instructions used by a computer processor. By way of non-limiting example, computer-readable storage media can be electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded devices such as punched cards or pits / lands formed in the main surface of a disk, or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, should not be construed to store in the form of transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, optical pulses propagating through a fiber optic cable, electrical signals communicated over a line, and / or other transmission media. As will be understood by those skilled in the art, data is typically moved at certain incidental points in time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not cause the storage device to be construed as transitory because the data is not transitory when it is stored.

[0038] An idle agent (e.g., a processor) operates with a minimal power budget. This causes a large change in the current on the I / O power supply when transitioning from an idle state to an active state. Due to package inductance, this change in current translates into large voltage noise. This voltage noise will cause a performance degradation of the noisy I / O or other I / O operably coupled to the same power supply. In one aspect, some embodiments can effectively provide a data link noise ceiling by ensuring minimal switching activity occurs on the data link.

[0039] The power consumption of a digital circuit can be characterized from the switching activity of digital signals (e.g., digital data signals or clock signals). The switching activity can be characterized as an activity factor of the digital signal (e.g., a switching activity value), which has the probability of a power consumption transition per clock cycle of the digital signal. The clock signal has an activity factor expressed as 100% in percentage, in contrast to the digital data signal with an activity factor between 5% and 15%, which means the digital data signal will include a power consumption transition during 5% to 15% of the clock cycles.

[0040] Now referring to Figure 1 , in an embodiment, the communication system 100 includes a circuit board 101 having agents 102a and 102b and an optional agent 102c. Agent 102a includes a transmitter 106a and a receiver 122a. Agent 102b includes a transmitter 106b and a receiver 122b, and the optional agent 102c includes a transmitter 106c and a receiver 122c. Transmitters 106a and 106b and receivers 122a and 122b can communicate via respective data links 120a and 120b. In one aspect, data links 120a and 120b can be clockless data links (e.g., data links that do not carry data with an embedded clock signal).

[0041] Transmitter 106a and receiver 122a can be included in a processor occupying a computer motherboard, where data link 26 is a bus interconnecting the processors. Alternatively, transmitter 106a and receiver 122a can be arranged within separate chips located on respective circuit boards. Transmitter 106a and receiver 122a can be in close proximity to each other or farther apart, such as having a signal trace of 100 inches or longer. In one aspect, transmitter 106a and receiver 122a can reside on a multi-chip package. In one aspect, data links 120a and 120b include one or more physical interconnects (e.g., point-to-point physical interconnects), thereby defining a physical link at the physical layer of system 100.

[0042] In one embodiment, multiplexer 108 includes a digital data input 110, a data pattern input 112, a mode selection input 114, and a digital data output 118. Digital data output 118 can be operably coupled to Tx circuit 116. In one aspect, input 110 can receive a digital data signal for transmission via data link 120a. In one aspect, mode selection input 114 can receive a signal indicating that transmitter 106a is in an idle mode.

[0043] Any one of several criteria can be used to initiate the idle mode. Example embodiments include trigger conditions for initiating the idle mode, such as detecting an idle flit, an output signal below a switching activity threshold, and an empty transaction queue for the transmission agent, or if the queue reaches a non-zero minimum threshold. Additionally or alternatively, the trigger condition can reflect a software-triggered event, an event triggered by a higher protocol layer, and / or a power management event.

[0044] When the idle mode select signal is received at input 114, multiplexer 108 transmits the data pattern received via data pattern input 112. In one aspect, the data pattern is based on predetermined data for ensuring a minimum switching activity on data link 120a. Thus, the data pattern does not include actual data for processing, but rather includes data for ensuring a maximum noise level or noise ceiling for data link 120a and the operatively coupled agent. In one aspect, the transmitted data pattern is not processed by the receiving agent.

[0045] When the select signal indicating the data signal transmission mode of transmitter 106a is received at input 114, multiplexer 108 transmits the digital data signal received via digital data input 110 to at least agent 102b. In some embodiments, multiplexer 108 is a 2-to-1 multiplexer.

[0046] Figure 2 Agent 202 in an embodiment includes a processor 204, an optional switch controller 224, and a mode select controller 228. In one embodiment, processor 204 includes switch controller 224 and mode select controller 228.

[0047] In an embodiment, processor 204 includes a multiplexer 108 having the above-described digital data input 110, data pattern input 112, mode select input 114, and digital data output 118. In one embodiment, processor 204 may further include a clock 216 and an internal memory 218. The internal memory 218 may include data for generating a patterned data signal. In some embodiments, the internal memory 218 includes programmable memory, thereby allowing the patterned signal data to be changed and / or supplemented.

[0048] For example, the processor 204 can be included in a wide variety of different computing systems and subsystems, each having a different noise ceiling threshold for not corrupting the transmitted data via voltage noise. For different computing systems / subsystems, different stylized signal data can be provided to the memory 218 such that different noise ceiling thresholds can be accommodated. In some embodiments, the different stylized signal data represents stylized data signals having different activity factors. In a programmable memory embodiment of the internal memory 218, a programmable communication protocol is implemented by programmably defining the stylized signal data.

[0049] In one embodiment, the internal memory 218 can be relatively small (e.g., Figure 3 as shown in the embodiment), and accommodate a small range of data values having a relatively high activity factor for the idle mode. For example, the stylized data signal can have an activity factor of no less than 6%. In one embodiment, the switch 220 switches the application of the stylized data signal to the input 112, thereby reducing the activity factor. In one aspect, the switch 220 reduces the activity factor by approximately half such that a signal having a 6% activity factor has an activity factor of approximately 3.25%.

[0050] In one embodiment, the switch controller 224 is adapted to control the application and / or switching rate of the switch 220. The variable switching rate can also provide stylized data input signals having different activity factors to the input 112. For example, in some embodiments, the switch controller 224 can increase or decrease the switching speed of the switch 220 to intermittently provide the stylized data signal. In one embodiment, at least one of the switch 220 and the switch controller 224 is programmable, thereby allowing at least one instruction for defining the switching rate, as well as other possible instructions.

[0051] In one embodiment, the mode selection controller 228 can detect a flit or phit 230. "FLIT" stands for "flow control unit / digital", while "PHIT" stands for "physical digital". The smallest unit of information transmitted to / from the link layer is referred to as a "flit". The smallest data unit transmitted from one agent to another at the physical layer is referred to as a "phit".

[0052] During the idle mode, not sending any data across the data link may result in any voltage (e.g., noise) on the data link. Instead, in one embodiment, the flit / phit 230 may include one of an idle flit and an idle phit. In some embodiments, the mode selection controller 228 may detect the idle flit and / or idle phit indicating the idle mode of the transmitter 206 and / or the processor 204, and in response, provide an idle mode selection signal, such that the multiplexer 108 transmits a stylized data signal.

[0053] In one embodiment, the mode selection controller 228 may monitor the transaction queue 210 and / or the data therein. In one embodiment, the controller 228 provides an idle mode selection signal in response to an empty and / or nearly empty transaction queue 210.

[0054] Figure 3 An agent 302 including a processor 304 having a transmitter 206, a clock 216, a receiver 306, a serializer 308, and an internal memory 218 is shown in an embodiment. In one embodiment, the internal memory 218 includes processor registers 318 for accommodating (or storing) data 320 for generating a stylized data signal. In one embodiment, the processor registers 318 may include 16-bit data, shown in Figure 3 hexadecimal format, and in one aspect, storing the data 320 in the processor registers 318 is a particularly efficient implementation in terms of memory utilization, computing resources, and messaging efficiency for providing a stylized data signal during the idle mode.

[0055] The optional serializer 308 may receive the data 320 in parallel via one or more inputs 310 and serialize the data 320 into a stylized data signal for the input 112. That is, the serializer 308 may include a parallel input serial output (PISO) block structure. In one aspect, the serializer 308 may be a component of a SerDes (i.e., serializer / deserializer). Alternatively, the data 320 may be output directly from the memory 218 to the input 112 in a serial manner.

[0056] In an embodiment, even when the transmitter 206 is in the idle mode, the processor 304 may still receive and process data received from the data output 340. That is, in some embodiments, the transmitter 206 and the receiver 306 may be idled independently.

[0057] Figure 4Illustrates an example of a communication system 400 which, in an embodiment, includes processors 404a and 404b, a data link 420, and a clock link 444. In one embodiment, the data link 420 and / or the clock link 444 includes one or more physical interconnections (e.g., point-to-point physical interconnections) to define a physical link at the physical layer of the system 400.

[0058] In Figure 4 it, the system 400 depicts an embodiment of a "source synchronous" clock scheme, but other embodiments may include embodiments of a "common clock" scheme. For example, the clock 416a may reside external to the processor 404a, where the clock 416a provides a clock signal to the processors 404a and 404b.

[0059] In an embodiment, the processor 404a includes a transmitter 406 and a clock 416a. In an embodiment, the transmitter 406 includes an inverter 403a, a multiplexer 408a, a counter 414a, and a Tx circuit 416. The multiplexer 408a (e.g., transmitter multiplexer) includes a digital data input 110, an inverted data input 410, a select signal input 412a, and a data output 418.

[0060] In an embodiment, the processor 404b includes a receiver 422 and an optional clock 416b. In one embodiment, the clock 416b receives a clock signal to generate a further clock signal. In one embodiment, the processor 404b does not include the clock 416b and utilizes an external clock signal.

[0061] In an embodiment, the receiver 422 includes an inverter 403b, a multiplexer 408b, a counter 414b, and an Rx circuit 424. The multiplexer 408b (e.g., receiver multiplexer) includes a digital data input 426, an inverted data input 428, a select signal input 412b, and a data output 440. In some embodiments, the multiplexers 408a and 408b are 2-to-1 multiplexers.

[0062] In one embodiment, counters 414a and 414b are synchronized and transmit selection signals to corresponding multiplexers 408a and 408b after at least a threshold number of clock cycles of clock 416a. In one aspect, multiplexers 408a and 408b switch synchronously from output data or inverted data. For example, in one embodiment mode, the data input 110 of the data provided to transmitter 406 will be provided via data link 420, received via data input 426, and provided via data output 440. In another embodiment mode, counters 414a and 414b synchronously provide (e.g., transmit) selection signals to corresponding selection signal inputs 412a and 412b such that multiplexers 408a and 408b switch synchronously to output inverted data signals provided on corresponding inverted data inputs 410 and 428.

[0063] In an inverted mode embodiment, the original data signal is inverted twice (e.g., first inverted by inverter 403a and then by 403b), thereby providing an accurate data signal via output 440. In an advantageous aspect, since the data signal or the inverted data signal is provided independent of the data content, a minimum activity factor (and thus a noise ceiling) can be established. For example, the actual data can include long strings of 0s or 1s, and the actual data can bias the circuit or otherwise introduce noise. However, in some embodiments, at least a portion of the long strings of 0s or 1s can be inverted, thereby increasing the activity factor of the data signal.

[0064] In another advantageous aspect, switching between the data signal and the inverted data signal can maintain circuit health. For example, by ensuring a minimum switching amount for each threshold number of clock cycles, circuit components are more likely to remain within design tolerances with minimum power consumption, especially in embodiments with extended periods of minimal to no data transmission (e.g., a processor with an extended period of an empty transaction queue).

[0065] In one embodiment, counters 414a and 414b are programmable. For example, in an embodiment, counters 414a and 414b can be adapted to change the threshold number of clock cycles that trigger the counting of the selection signal via an instruction. An example threshold can be thirty-two thousand clock cycles, and in a programmable embodiment, this threshold can be updated to a different clock cycle value. In a programmable embodiment of counters 414a and 414b, a programmable communication protocol is achieved by programmably defining the number of clock cycles that trigger counters 414a and 414b to synchronously transmit their respective selection signals.

[0066] System 400 can be included in a wide variety of different computing systems and subsystems, each having a different noise ceiling threshold for transmitting data without being corrupted by voltage noise. For different computing systems / subsystems, different trigger clock period values can be provided to clocks 416a and 416b such that different noise ceiling thresholds can be accommodated.

[0067] Figure 5 An example method 500 for data communication is depicted and includes the steps shown in embodiments. In some embodiments, method 500 can correspond to Figure 1 agent 102a of Figure 2 agent 202 of Figure 3 agent 302 of

[0068] Step 502 includes receiving a data link signal through a first input of a multiplexer of a transmitter operably coupled to a data link. Step 504 includes transmitting a digital data signal to a receiver operably coupled to the data link through a digital data signal output of the multiplexer.

[0069] Step 506 includes receiving a first selection signal indicating an idle mode for the transmitter through a selection signal input of the multiplexer. In some embodiments, the idle mode can be selected based on the digital data signal (such as a switching activity value of the digital data signal and / or detecting at least one of an idle flit and an idle phit).

[0070] Optional step 508 includes intermittently delivering a patterned data signal to a second signal input. As explained with reference to Figure 2 a switch can intermittently couple or otherwise deliver a patterned data signal. In some embodiments, step 508 modifies the switching activity of the patterned data signal, including reducing an activity factor of the patterned data signal.

[0071] Step 510 includes receiving a patterned data signal through a second input of the multiplexer. Step 512 includes transmitting the patterned data signal to the receiver through the digital data signal output and in response to the first selection signal. Optional step 514 includes receiving a second selection signal indicating a data signal transmission mode for the transmitter through a selection signal input of the multiplexer. In an embodiment, method 500 can then return to step 504, which is associated with the data signal transmission mode.

[0072] Figure 6Depicts an example method 600 for data communication and includes the steps shown in the embodiments. In some embodiments, method 600 may correspond to communication system 400. Optional step 602 includes synchronizing at least a receiver counter and a transmitter counter. For example, a memory may include computer program instructions executable by a processor for synchronizing two or more counters. In some embodiments, the counters may already be synchronized such that the method of the embodiment may be at step 604.

[0073] Step 604 includes receiving a digital data signal through a first input of a transmitter multiplexer. Step 606 includes receiving an inverted digital data signal through a second input of the transmitter multiplexer. Step 608 includes counting a threshold number of clock cycles by a transmitter counter and, in response to the transmitter counter, transmitting a first selection signal to a selection signal input of the transmitter multiplexer. In some embodiments, the counting includes counting each occurrence of the threshold number of counted clock cycles and providing the selection signal of step 608 in response to each occurrence of the threshold number of counted clock cycles.

[0074] Step 610 includes alternately transmitting the digital data signal and the inverted digital data signal to a receiver in response to the first selection signal and through a digital data signal output of the transmitter multiplexer. As described above, some embodiment communication systems (e.g., system 400) may switch between transmitting data and transmitting inverted data independent of an idle mode or a data signal transmission mode.

[0075] Figure 7 Depicts an example method 700 for data communication and includes the steps shown in the embodiments. In some embodiments, method 700 may correspond to communication system 400. Method 700 may include step 610. Step 702 includes alternately receiving a digital data signal and an inverted digital data signal from a transmitter through a first input of a receiver multiplexer. Step 704 includes receiving an inverted version of the digital data signal received in step 702 or an inverted signal of the digital data signal through a second input of the receiver multiplexer.

[0076] Step 706 includes counting a threshold number of clock cycles by a receiver counter and, in response to the receiver counter, transmitting a second selection signal to a selection signal input of the receiver multiplexer. In some embodiments, step 706 may occur synchronously with step 608 of method 600 such that the transmitter and the receiver alternately process a data input signal or an inverted data input signal. In some embodiments, the counting includes counting each occurrence of the threshold number of counted clock cycles and providing the selection signal of step 706 in response to each occurrence of the threshold number of counted clock cycles.

[0077] Step 708 includes providing a digital data signal in response to a second selection signal and via a digital data signal output of a multiplexer. In one aspect, given that a receive and transmit counter are synchronized, the digital data signal of step 604 is faithfully reproduced as the digital data signal of step 708.

[0078] Now referring Figure 8 , in an embodiment, agent 802 includes a processor 804 and a transmitter 806. In an embodiment, transmitter 806 includes a multiplexer 108 that is operably coupled to Figure 4 multiplexer 408a of Figure 1 . In such an embodiment, as described above, digital data output 118 provides an (actual) data signal or a stylized data signal as the received digital data signal to digital data input 810 and inverted data input 410 of multiplexer 408a based on an idle mode or a data signal transmission mode. As described above, multiplexer 408a alternately provides the received digital data signal or the inverted digital data signal to digital data output 418 based on counter 414a counting a threshold number of clock cycles. Thus, in some embodiments, agent 902 combines Figure 1 and 4 features and advantages thereof.

[0079] Computing environment 900 includes an example of an environment for executing at least some of the computer code involved in performing the methods of the present invention, such as programmable communication protocol code block 1000. In addition to block 1000, computing environment 900 includes, for example, a computer 901, a wide area network (WAN) 902, an end user device (EUD) 903, a remote server 904, a public cloud 905, and a private cloud 906. In this embodiment, computer 901 includes a processor group 910 (including processing circuitry 920 and cache 921), a communication fabric 911, volatile memory 912, a persistent storage device 913 (including operating system 922 and block 1000 as described above), a peripheral device group 914 (including a user interface (UI) device group 923, a storage device 924, and an Internet of Things (IoT) sensor group 925), and a network module 915. Remote server 904 includes a remote database 930. Public cloud 905 includes a gateway 940, a cloud orchestration module 941, a host physical machine group 942, a virtual machine group 943, and a container group 944.

[0080] The computer 901 can take the form of a desktop computer, a laptop computer, a tablet computer, a smart phone, a smart watch or other wearable computer, a mainframe computer, a quantum computer or any other form of computer or mobile device now known or to be developed in the future that is capable of running programs, accessing networks or querying databases such as the remote database 930. As is well known in the computer technology field and depending on the technology, the execution of computer-implemented methods can be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of the computing environment 900, the discussion focuses in detail on a single computer, particularly the computer 901, to keep the presentation as simple as possible. The computer 901 can be located in the cloud, even though it is not shown in the cloud in Figure 9 , on the other hand, the computer 901 does not need to be in the cloud, unless to any extent that can be definitely indicated.

[0081] The processor group 910 includes one or more computer processors of any type now known or to be developed in the future. The processing circuitry 920 can be distributed over multiple packages, such as multiple cooperative integrated circuit chips. The processing circuitry 920 can implement multiple processor threads and / or multiple processor cores. The cache 921 is a memory located in the (one or more) processor chip packages and is generally used for data or code that should be available for quick access by the threads or cores running on the processor group 910. The cache memory is generally organized into multiple levels according to its relative proximity to the processing circuitry. Alternatively, some or all of the caches in the cache of the processor group can be located "off-chip". In some computing environments, the processor group 910 can be designed to work with qubits and perform quantum computing.

[0082] Computer-readable program instructions are generally loaded onto the computer 901 so that the processor group 910 of the computer 901 executes a series of operation steps, thereby implementing the computer-implemented method, such that the instructions so executed will instantiate the method specified in the flowchart and / or the narrative description of the computer-implemented method included in this document (collectively referred to as "the method of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as the cache 921 and other storage media discussed below. The program instructions and the associated data are accessed by the processor group 910 to control and guide the execution of the method of the present invention. In the computing environment 900, at least some of the instructions for executing the method of the present invention can be stored in block 1000 in the persistent storage 913.

[0083] The communication structure 911 is a signal conduction path that allows various components of the computer 901 to communicate with each other. Generally, this structure consists of switches and conductive paths, such as those that make up a bus, a bridge, a physical input / output port, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0084] The volatile memory 912 is any type of volatile memory known now or developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Generally, the volatile memory 912 is characterized by random access, but this is not required unless expressly stated. In the computer 901, the volatile memory 912 is located in a single package and inside the computer 901. However, alternatively or additionally, the volatile memory can be distributed across multiple packages and / or be located external to the computer 901.

[0085] The persistent storage device 913 is any form of non-volatile storage for a computer known now or developed in the future. The non-volatility of this storage device means that the stored data is retained regardless of whether power is supplied to the computer 901 and / or directly to the persistent storage device 913. The persistent storage device 913 can be read-only memory (ROM), but generally at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some common forms of persistent storage devices include magnetic disks and solid-state storage devices. The operating system 922 can take several forms, such as various known proprietary operating systems or operating systems of the open-source portable operating system interface type that employ a kernel. The code included in block 1000 generally includes at least some of the computer code involved in performing the method of the present invention.

[0086] The peripheral device group 914 includes a collection of the peripheral devices of the computer 901. The data communication connections between the peripheral devices and other components of the computer 901 can be implemented in various ways, such as Bluetooth connections, near-field communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), plug-in connections (e.g., secure digital (SD) cards), connections made through local communication networks, and even connections made through wide area networks such as the Internet. In various embodiments, the UI device group 923 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and tactile devices. The storage device 924 is an external memory, such as an external hard disk drive, or a pluggable memory, such as an SD card. The storage device 924 can be persistent and / or volatile. In some embodiments, the storage device 924 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where the computer 901 needs to have a large amount of storage (e.g., in the case where the computer 901 locally stores and manages a large database), the storage can be provided by a peripheral storage device (such as a storage area network (SAN) shared by multiple geographically distributed computers) designed to store a very large amount of data. The IoT sensor group 925 consists of sensors that can be used in Internet of Things applications. For example, one sensor can be a thermometer, and another sensor can be a motion detector.

[0087] The network module 915 is a collection of computer software, hardware, and firmware that allows the computer 901 to communicate with other computers via the WAN 902. The network module 915 may include hardware such as a modem or a Wi-Fi signal transceiver, software for packetizing and / or depacketizing data transmitted over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 915 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control function and the forwarding function of the network module 915 are executed on physically separate devices, such that the control function manages several different network hardware devices. The computer-readable program instructions for performing the methods of the present invention can generally be downloaded to the computer 901 from an external computer or an external storage device through a network adapter card or a network interface included in the network module 915.

[0088] The WAN 902 is any wide area network (e.g., the Internet) capable of transferring computer data over non-local distances by any technology known now or developed in the future for transferring computer data. In some embodiments, the WAN 902 may be replaced and / or supplemented by a local area network (LAN) designed to transfer data between devices located in a local area such as a Wi-Fi network. The WAN and / or LAN typically includes computer hardware such as copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0089] The end user device (EUD) 903 is any computer system used and controlled by an end user (e.g., a customer of an enterprise operating the computer 901) and may take any form discussed above in connection with the computer 901. The EUD 903 typically receives useful and beneficial data from the operation of the computer 901. For example, in the hypothetical case where the computer 901 is designed to provide recommendations to an end user, the recommendation will typically be transferred from the network module 915 of the computer 901 through the WAN 902 to the EUD 903. In this way, the EUD 903 can display or otherwise present the recommendation to the end user. In some embodiments, the EUD 903 may be a client device such as a thin client, a fat client, a mainframe computer, a desktop computer, etc.

[0090] The remote server 904 is any computer system that provides at least some data and / or functions to the computer 901. The remote server 904 may be controlled and used by the same entity operating the computer 901. The remote server 904 represents a machine that collects and stores useful and beneficial data used by other computers such as the computer 901. For example, in the hypothetical case where the computer 901 is designed and programmed to provide recommendations based on historical data, the historical data may be provided to the computer 901 from the remote database 930 of the remote server 904.

[0091] A public cloud 905 is any computer system that can be used by multiple entities, which provides on-demand availability of computer system resources and / or other computing capabilities (especially data storage (cloud storage) and computing power) without the user's direct active management. Cloud computing typically utilizes the sharing of resources to achieve scale consistency and economy. The direct and active management of the computing resources of the public cloud 905 is performed by the computer hardware and / or software of the cloud orchestration module 941. The computing resources provided by the public cloud 905 are typically implemented by virtual computing environments running on various computers that make up the host physical machine group 942, which is the complete set of physical computers in and / or available for the public cloud 905. The virtual computing environment (VCE) typically takes the form of virtual machines from the virtual machine group 943 and / or containers from the container group 944. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after the instantiation of the VCE. The cloud coordination module 941 manages the transfer and storage of images, deploys new instantiations of the VCE, and manages the active instantiations of the VCE deployment. The gateway 940 is a collection of computer software, hardware, and firmware that allows the public cloud 905 to communicate via the WAN 902.

[0092] Some further explanations of the virtualized computing environment (VCE) will now be provided. The VCE can be stored as an "image". New active instances of the VCE can be instantiated from this image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows the existence of multiple isolated user space instances, called containers. From the perspective of the programs running within them, these isolated user space instances typically appear as actual computers. A computer program running on a normal operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU capabilities, and quantifiable hardware capabilities. However, a program running within a container can only use the contents of the container and the devices allocated to the container, which is a feature known as containerization.

[0093] A private cloud 906 is similar to a public cloud 905, except that the computing resources are only available for use by a single enterprise. Although the private cloud 906 is depicted as communicating with the WAN 902, in other embodiments, the private cloud can be completely disconnected from the Internet and only accessible through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types) that are typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, both the public cloud 905 and the private cloud 906 are part of the larger hybrid cloud.

[0094] A description of various embodiments of the invention has been presented for purposes of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0095] In the foregoing, reference has been made to embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. On the contrary, any combination of features and elements, whether or not related to different embodiments, is contemplated for implementing and practicing the contemplated embodiments. Moreover, although the embodiments disclosed herein may achieve advantages over other possible solutions or the prior art, whether a given embodiment achieves a particular advantage does not limit the scope of this disclosure. Accordingly, the aspects, features, embodiments, and advantages discussed herein are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly stated in one or more of the claims. Similarly, references to "the invention" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly recited in one or more of the claims.

[0096] Aspects of the invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may be collectively referred to herein as "circuitry," "module," or "system."

[0097] While the foregoing relates to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is determined by the appended claims.

Claims

1. A method, comprising: receiving a digital data signal through a first data input of a transmitter multiplexer; inverting the digital data signal through a first inverter to provide an inverted digital data signal; receiving the inverted digital data signal through a first inverted data input of the transmitter multiplexer; counting a clock signal by a first counter; transmitting a first selection signal to a first selection signal input of the transmitter multiplexer through the first counter and in response to the first counter counting a threshold number of clock cycles; and alternately transmitting the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver in response to the first selection signal and through a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output being operably coupled to a data link.

2. The method according to claim 1, wherein the receiver comprises a second counter and a receiver multiplexer, the receiver multiplexer being arranged to receive the transmitter output signal, and the method further comprising: receiving the transmitter output signal through a second data input of the receiver multiplexer; inverting the transmitter output signal through a second inverter to provide an inverted transmitter output signal; receiving the inverted digital data signal through a second inverted data input of the receiver multiplexer; counting the clock signal by a second counter; transmitting a second selection signal to a second selection signal input of the receiver multiplexer through the second counter and in response to the second counter counting the threshold number of clock cycles; and alternately providing the transmitter output signal and the inverted transmitter output signal in response to the selection signal and through a second digital data signal output of the receiver multiplexer.

3. The method according to claim 1, wherein the counting step by the first counter comprises counting each occurrence of the threshold number of counted clock cycles by the first counter and providing the first selection signal in response to each occurrence of the threshold number of counted clock cycles.

4. The method according to claim 2, wherein the counting step by the first counter comprises counting each occurrence of the threshold number of counted clock cycles by the first counter and providing the first selection signal in response to each occurrence of the threshold number of counted clock cycles, and the counting step by the second counter comprises counting each occurrence of the threshold number of counted clock cycles by the second counter and providing the second selection signal in response to each occurrence of the threshold number of counted clock cycles.

5. The method according to claim 2, further comprising synchronizing the first counter and the second counter.

6. The method according to claim 1, wherein a first processor comprises the transmitter multiplexer.

7. The method according to claim 2, wherein the first processor includes the transmitter multiplexer, and the second processor includes the receiver multiplexer.

8. The method according to claim 1, further comprising: receiving the digital data signal through a first input of the multiplexer; transmitting the digital data signal to the transmitter multiplexer through an output of the multiplexer; receiving a first selection signal indicating an idle mode through a selection signal input of the multiplexer; receiving a styled data signal through a second input of the multiplexer; and in response to the first selection signal, transmitting the styled data signal as the digital data signal and through the output of the multiplexer to the transmitter multiplexer.

9. A system, comprising: a first inverter arranged to receive a digital data signal, a clock, a first counter operably coupled to the clock, and a transmitter multiplexer, the transmitter multiplexer including: a first input arranged to receive a digital data signal, a first inverted data input operably coupled to the first inverter and arranged to receive an inverted digital data signal, a first selection signal input operably coupled to the first counter and arranged to receive a first selection signal, and a first output arranged to transmit a transmitter multiplexer output signal, the first counter adapted to provide the first selection signal in response to a threshold number of clock cycles of counting, such that the transmitter multiplexer alternately transmits the digital data signal and the inverted digital data signal as the transmitter multiplexer output signal.

10. The system according to claim 9, further comprising a second inverter arranged to receive the transmitter multiplexer output signal, a second counter, a receiver multiplexer, and a data link operably coupled to the transmitter multiplexer and the receiver multiplexer, the receiver multiplexer including: a second input arranged to receive the transmitter multiplexer output signal, a second inverted data input operably coupled to the second inverter and arranged to receive an inverted transmitter multiplexer output signal, a second selection signal input operably coupled to the second counter and arranged to receive a second selection signal, and a second output arranged to provide a receiver multiplexer output signal, the second counter adapted to provide the second selection signal in response to the threshold number of clock cycles of counting, such that the receiver multiplexer alternately provides the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal as the receiver multiplexer output signal.

11. The system according to claim 10 further includes a processor operably coupled to a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code being executable by the processor to synchronize the first counter and the second counter.

12. The system according to claim 9, wherein the first processor includes the transmitter multiplexer.

13. The system according to claim 10, wherein the first processor includes the transmitter multiplexer and the second processor includes the receiver multiplexer.

14. The system according to claim 12, wherein the first processor further includes the first inverter, the clock, and the first counter.

15. The system according to claim 13, wherein the first processor further includes the first inverter, the clock, and the first counter, and the second processor further includes the second inverter and the second counter.

16. The system according to claim 9, wherein the first counter is a programmable counter adapted to change a threshold number of clock cycles of the programmable counter in response to a count to provide the first selection signal.

17. The system according to claim 10, wherein the first counter is a first programmable counter adapted to change a threshold number of clock cycles of the first programmable counter in response to a count to provide the first selection signal, and the second counter is a second programmable counter adapted to change a threshold number of clock cycles of the second programmable counter in response to a count to provide the second selection signal.

18. The system according to claim 9, further comprising: a memory that houses data for generating a stylized data signal; and a first multiplexer that includes: a data signal input arranged to receive a digital data signal, a stylized data signal input arranged to receive a stylized data signal, a selection signal input arranged to receive a mode selection signal, and a digital data signal output arranged to transmit a first multiplexer output signal to the first input of the transmitter multiplexer and the first inverted data input, the first multiplexer being adapted to selectively output the digital data signal and the stylized data signal as the multiplexer output signal in response to receiving the mode selection signal, the mode selection signal indicating an idle mode and a data signal transmission mode.

19. The system according to claim 18, wherein the processor includes the transmitter multiplexer, the first multiplexer, and the memory.

20. The system according to claim 19, wherein the memory includes processor registers that hold data for generating the stylized data signal.

21. A computer program comprising program code adapted to perform the method steps of any one of claims 1 to 8 when the program is run on a computer.

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