Semiconductor device and memory device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device includes a first insulator on a substrate, an oxide semiconductor covering the first insulator, a first conductor and a second conductor on the oxide semiconductor, and a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor. A third insulator disposed in the opening and on the oxide semiconductor; and a third conductor disposed in the opening and on the third insulator. The height of the first insulator is greater than the width of the first insulator.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor layer. Another aspect of the present invention relates to a method for manufacturing the semiconductor device described above.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods of the above devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, or storage devices are also one aspect of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor integrated circuits (including at least transistors and memories) formed by processing a semiconductor wafer to form a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on a circuit board (e.g., a printed wiring board) and used as one of the components of various electronic devices.

[0006] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have received attention.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely small leakage current in a non-conductive state. For example, Patent Document 1 has disclosed a low-power CPU etc. that utilize the characteristic of small leakage current of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device etc. that can achieve long-term retention of stored content by utilizing the characteristic of small leakage current of a transistor using an oxide semiconductor.

[0008] In recent years, with the miniaturization and lightening of electronic devices, the demand for further high-density integration of integrated circuits has increased. In addition, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which a plurality of memory cells are arranged overlappingly by laminating a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. Further, for example, as shown in Patent Document 4, a technique for achieving high-density integration of an integrated circuit by arranging the channels of transistors using an oxide semiconductor film in the longitudinal direction is also disclosed. [Prior Art Documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-Patent Documents]

[0010] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech.Dig., 2019, pp.50-53 Summary of the Invention Technical Problem to be Solved by the Invention

[0011] In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device in which the electrical characteristics of transistors are unevenly small. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. In addition, one of the objects of one embodiment of the present invention is to provide a manufacturing method of a novel semiconductor device.

[0012] In addition, one of the objects of one embodiment of the present invention is to provide a storage device that can be miniaturized or highly integrated. In addition, one of the objects of one embodiment of the present invention is to provide a storage device with a large storage capacity. In addition, one of the objects of one embodiment of the present invention is to provide a storage device with a high operating speed. In addition, one of the objects of one embodiment of the present invention is to provide a storage device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a novel storage device.

[0013] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of the above objects. Objects other than the above can be extracted from the description of the specification, drawings, and claims. Means for Solving the Technical Problem

[0014] One embodiment of the present invention is a semiconductor device including a first insulator on a substrate, an oxide semiconductor covering the first insulator, a first conductor and a second conductor on the oxide semiconductor, a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a third insulator disposed in the opening and on the oxide semiconductor, and a third conductor disposed in the opening and on the third insulator. When viewed in a cross-section in the channel width direction, the height of the first insulator is longer than the width of the first insulator.

[0015] In the above structure, when viewed from above, the side surface of the opening of the second insulator preferably aligns or substantially aligns with the side surfaces of the first conductor and the second conductor.

[0016] In addition, in the above structure, when viewed in a cross-section along the channel width direction, the height of the first insulator is preferably more than 2 times and less than 20 times the width of the first insulator.

[0017] In addition, in the above structure, preferably, the first conductor is used as one of the source electrode and the drain electrode of the transistor, the second conductor is used as the other of the source electrode and the drain electrode of the transistor, and the third conductor is used as the gate electrode of the transistor.

[0018] In addition, in the above semiconductor device, preferably, when viewed in a cross-section along the channel width direction, the oxide semiconductor and the third conductor face each other with the third insulator interposed therebetween on one side surface of the first insulator, and the oxide semiconductor and the third conductor face each other with the third insulator interposed therebetween on the other side surface of the first insulator.

[0019] In addition, in the above semiconductor device, preferably, when viewed in a cross-section along the channel width direction, the first conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator, and the second conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator.

[0020] In addition, in the above structure, preferably, the oxide semiconductor contains one or more selected from In, Ga, and Zn.

[0021] Another aspect of the present invention is a storage device including the above semiconductor device and a capacitor, and one electrode of the capacitor is electrically connected to the first conductor of the semiconductor device.

[0022] In addition, in the above structure, preferably, the capacitor is disposed on the third conductor, and at least a part of the capacitor overlaps with the oxide semiconductor and the third conductor. Advantages of the Invention

[0023] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device in which the electrical characteristics of transistors are unevenly small can be provided. In addition, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0024] In addition, according to one aspect of the present invention, a storage device that can be miniaturized or highly integrated can be provided. In addition, according to one aspect of the present invention, a storage device with a large storage capacity can be provided. In addition, according to one aspect of the present invention, a storage device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a storage device with low power consumption can be provided. In addition, according to one aspect of the present invention, a novel storage device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not need to have all of the above effects. In addition, effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A is a top view showing an example of the semiconductor device, Figures 1B to 1D is a cross-sectional view showing an example of the semiconductor device. Figure 2A and Figure 2B is a cross-sectional view showing an example of the semiconductor device. Figures 3A to 3C is a cross-sectional view showing an example of the semiconductor device. Figures 4A to 4C is a cross-sectional view showing an example of the semiconductor device. Figure 5A is a top view showing an example of the semiconductor device. Figures 5B to 5D is a cross-sectional view showing an example of the semiconductor device. Figure 6A is a top view showing an example of the semiconductor device. Figures 6B to 6DIt is a cross-sectional view showing an example of a semiconductor device. Figure 7A It is a top view showing an example of a semiconductor device. Figures 7B to 7D It is a cross-sectional view showing an example of a semiconductor device. Figure 8 It is a cross-sectional view showing an example of a semiconductor device. Figure 9A It is a top view showing an example of a semiconductor device. Figures 9B to 9D It is a cross-sectional view showing an example of a semiconductor device. Figure 10A and Figure 10B It is a cross-sectional view showing an example of a semiconductor device. Figure 11A It is a top view showing an example of a semiconductor device. Figures 11B to 11D It is a cross-sectional view showing an example of a semiconductor device. Figure 12A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 12B to 12D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 13A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 13B to 13D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 14A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 14B to 14D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 15A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 15B to 15D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 16A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 16B to 16D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 17A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 17B to 17D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 18A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 18B to 18D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 19A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 19B to 19DIt is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 20A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 20B to 20D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 21A It is a top view showing an example of a manufacturing method of a semiconductor device. Figures 21B to 21D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 22 It is a block diagram showing an example of a storage device. Figure 23A And Figure 23B It is a schematic diagram and a circuit diagram showing an example of a storage device. Figure 24A And Figure 24B It is a schematic diagram showing an example of a storage device. Figure 25 It is a circuit diagram showing an example of a storage device. Figure 26A And Figure 26B It is a cross-sectional view showing an example of a storage device. Figure 27A And Figure 27B It is a cross-sectional view showing an example of a storage device. Figure 28 It is a cross-sectional view showing an example of a storage device. Figure 29A And Figure 29B It is a diagram showing an example of a semiconductor device. Figure 30A And Figure 30B It is a diagram showing an example of an electronic component. Figure 31A And Figure 31B It is a diagram showing an example of an electronic device. Figures 31C to 31E It is a diagram showing an example of a mainframe computer. Figure 32 It is a diagram showing an example of a space device. Figure 33 It is a diagram showing an example of a storage system that can be used in a data center. Detailed implementation

[0027] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understandable to those of ordinary skill in the art that its modes and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments shown below.

[0028] Note that in the invention structure described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same functions, and repeated descriptions are omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching reference numerals.

[0029] In addition, for ease of understanding, the positions, sizes, ranges, etc. of the respective constituent elements shown in the drawings do not represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, dimensions, ranges, etc. disclosed in the drawings.

[0030] In addition, particularly in the top view (also referred to as the "plan view") or the perspective view, etc., for ease of understanding of the invention, the description of some constituent elements is sometimes omitted. In addition, the description of some hidden lines is sometimes omitted.

[0031] Note that in this specification, etc., for convenience, ordinal numbers such as "first" and "second" are added, and they do not limit the number of constituent elements or the order of constituent elements (for example, the process order or the stacking order). In addition, the ordinal numbers added to a constituent element in a certain part of this specification may sometimes be inconsistent with the ordinal numbers added to the same constituent element in other parts of this specification or in the claims.

[0032] In addition, depending on the situation or circumstances, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be changed to "conductive film". In addition, "insulating film" can be changed to "insulating layer". In addition, depending on the situation or circumstances, "conductor" can be interchanged with "conductive layer" or "conductive film". In addition, depending on the situation or circumstances, "insulator" can be interchanged with "insulating layer" or "insulating film".

[0033] In this specification, etc., "parallel" means a state in which the angle formed by two straight lines is -10 degrees or more and 10 degrees or less. Therefore, it also includes a state in which the angle is -5 degrees or more and 5 degrees or less. "Substantially parallel" means a state in which the angle formed by two straight lines is -30 degrees or more and 30 degrees or less. In addition, "perpendicular" means a state in which the angle between two straight lines is 80 degrees or more and 100 degrees or less. Therefore, it also includes a state in which the angle is 85 degrees or more and 95 degrees or less. "Substantially perpendicular" means a state in which the angle formed by two straight lines is 60 degrees or more and 120 degrees or less.

[0034] The opening includes, for example, a groove, a slit, etc. In addition, sometimes the region where the opening is formed is referred to as an opening portion.

[0035] In addition, in the drawings used in the embodiments of this specification, the side walls in the opening portion of the insulator are shown to be perpendicular or substantially perpendicular to the substrate surface or the formation surface, but the side walls can also be in a tapered shape.

[0036] Note that in this specification and the like, the tapered shape means a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface or the formation surface. For example, it means a shape having a region where the angle (hereinafter, sometimes also referred to as the taper angle) formed by the inclined side surface and the substrate surface or the formation surface is less than 90°. Note that the side surface of the component and the substrate surface do not necessarily have to be completely flat, and may be in an approximately planar shape with a minute curvature or an approximately planar shape with fine unevenness.

[0037] In addition, in this specification and the like, "being of the same height or substantially the same height" means a structure having the same height from a reference plane (for example, a flat surface such as the substrate surface) in a cross-sectional view. For example, in the manufacturing process of a storage device, sometimes due to a planarization process (typically a CMP process), the surfaces of a single layer or multiple layers are exposed. At this time, the surface to be processed in the CMP process has a structure having the same height from the reference plane. However, depending on the processing device, processing method, or material of the surface to be processed used in the CMP process, the heights of multiple layers may sometimes be different. In this specification and the like, this situation is also regarded as "being of the same height or substantially the same height". For example, the following situation is also referred to as "being of the same height or substantially the same height": including two layers (here, the first layer and the second layer) having different heights from the reference plane, and the difference between the top surface height of the first layer and the top surface height of the second layer is 20 nm or less.

[0038] In this specification and the like, "side end portions being aligned or substantially aligned" means that at least a part of the contour of each layer in the stack overlaps in a top view. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, strictly speaking, sometimes the contours do not overlap and the contour of the upper layer is located inside the contour of the lower layer or the contour of the upper layer is located outside the contour of the lower layer, and these situations are also referred to as "side end portions being aligned or substantially aligned".

[0039] (Embodiment 1) In this embodiment, a semiconductor device including an oxide semiconductor layer and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1 to 21.

[0040] <Structural example of semiconductor device> A structural example of the semiconductor device will be described with reference to FIGS. 1 to 10. Figures 1A to 1DIt is a plan view and a cross-sectional view of a semiconductor device including transistor 200a and transistor 200b on a substrate (not shown). Note that transistor 200b has the same structure as transistor 200a, so the components are attached with the same hatching as transistor 200a without attaching symbols. Hereinafter, transistor 200a and transistor 200b may sometimes be collectively referred to as transistor 200. By providing a capacitor electrically connected to transistor 200a and a capacitor electrically connected to transistor 200b in the semiconductor device shown in this embodiment, it can be used as two 1T (transistor) 1C (capacitor) type memory cells and used in a memory device.

[0041] Figure 1A It is a plan view of the above semiconductor device. In addition, Figures 1B to 1D It is a cross-sectional view of this semiconductor device. Here, Figure 1B It is a cross-sectional view of the portion along the dash-dotted line A1 - A2 in Figure 1A , and it is also a cross-sectional view in the channel length direction of transistor 200a. In addition, Figure 1C It is a cross-sectional view of the portion along the dash-dotted line A3 - A4 in Figure 1A , and it is also a cross-sectional view in the channel width direction of transistor 200a and transistor 200b. In addition, Figure 1D It is a cross-sectional view of the portion along the dash-dotted line A5 - A6 in Figure 1A , and it is also a cross-sectional view in the channel width direction of transistor 200a and transistor 200b. Here, the dash-dotted line A1 - A2 is orthogonal to the dash-dotted line A3 - A4 and the dash-dotted line A5 - A6, and the dash-dotted line A3 - A4 and the dash-dotted line A5 - A6 are parallel to each other. Note that in the plan view of Figure 1A , some components are omitted for clarity. In addition, Figure 2A It shows an enlarged view near the conductor 260 of Figure 1B . In addition, Figure 2B It shows an enlarged view near the insulator 225 of Figure 1C . In addition, Figure 4A It shows an enlarged view near the conductor 242a of Figure 1B . In addition, Figure 4B It shows an enlarged view near the insulator 225 of Figure 1D .

[0042] The semiconductor device according to the present embodiment includes conductors 205 (conductor 205a and conductor 205b) provided in an insulator 216 embedded in a substrate (not shown), the insulator 216, an insulator 221 on the conductors 205, an insulator 222 on the insulator 221, an insulator 225 on the insulator 222, oxides 230 (oxide 230a and oxide 230b) on the insulator 225 and the insulator 222, conductors 242a and 242b on the oxides 230, an insulator 250 on the oxides 230, and conductors 260 (conductor 260a and conductor 260b) on the insulator 250. Hereinafter, the conductors 242a and 242b may be collectively referred to as conductor 242.

[0043] An insulator 275 is provided on the conductor 242, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductors 260 are disposed inside an opening provided in the insulator 280 and the insulator 275. In addition, an insulator 282 is provided on the insulator 280 and the conductors 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 215 is provided under the insulator 216 and the conductors 205.

[0044] An insulator 241a is provided in contact with the inner wall of the opening in the insulator 280 or the like, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The bottom surface of the conductor 240a is in contact with the top surface of the conductor 242a. An insulator 241b is provided in contact with the inner wall of the opening in the insulator 280 or the like, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The bottom surface of the conductor 240b is in contact with the top surface of the conductor 242b. Hereinafter, the conductors 240a and 240b may be collectively referred to as conductor 240. In addition, the insulators 241a and 241b may be collectively referred to as insulator 241.

[0045] The oxide 230 has a region serving as a channel formation region of the transistor 200. In addition, the conductor 260 has a region serving as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region serving as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region serving as a second gate electrode (lower gate electrode) of the transistor 200. Both the insulator 222 and the insulator 221 have a region serving as a second gate insulator of the transistor 200.

[0046] The conductor 242a has a region that serves as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a is used as a plug connected to the conductor 242a. The conductor 242b has a region that serves as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b is used as a plug connected to the conductor 242b.

[0047] The oxide 230 preferably includes an oxide 230a covering the insulator 225 and an oxide 230b on the oxide 230a. Here, the oxide 230a contacts the top surface and the side surfaces of the insulator 225 and the top surface of the insulator 222. As Figure 2B shown, the oxide 230a and the oxide 230b are arranged to cover the insulator 225 having a high aspect ratio. Therefore, the oxide 230a and the oxide 230b are preferably deposited by a deposition method with high coverage such as the ALD method. Here, as Figure 2B shown, in a cross-section in the channel width direction, the oxide 230a and the oxide 230b are formed in a folded state with the insulator 225 sandwiched therebetween. By adopting such a structure, the channel formation region of the transistor 200 can be formed on the top, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225, so that the channel width per unit area can be increased.

[0048] By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed under the oxide 230a into the oxide 230b can be suppressed.

[0049] This embodiment shows an example in which the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but is not limited thereto. The oxide 230 may have, for example, a single-layer structure of the oxide 230b, or may have a stacked structure of three or more layers.

[0050] A channel formation region of the transistor 200 and a source region and a drain region arranged to sandwich the channel formation region are formed in the oxide 230b. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0051] Since it has fewer oxygen vacancies or a lower impurity concentration than the source region and the drain region, the channel formation region is a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0052] In addition, the source region and the drain region have a large number of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements, and thus are low-resistance regions with a high carrier concentration. That is to say, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0053] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 or less, lower than 1×10 17 cm -3 or less, lower than 1×10 16 cm -3 or less, lower than 1×10 15 cm -3 or less, lower than 1×10 14 cm -3 or less, lower than 1×10 13 cm -3 or less, lower than 1×10 12 cm -3 or less, lower than 1×10 11 cm -3 or lower than 1×10 10 cm -3 . Note that there is no particular limitation on the lower limit value of the carrier concentration in the channel formation region. For example, it can be 1×10 -9 cm -3 .

[0054] In the case of aiming to reduce the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b can be reduced to reduce the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0055] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. To reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230b refer to elements other than the main components constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0056] In addition, the channel formation region, the source region, and the drain region can be formed not only in the oxide 230b but also in the oxide 230a.

[0057] In the oxide 230, it is sometimes difficult to clearly observe the boundaries of the respective regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in the respective regions do not need to change stepwise for each region, and may also change continuously in the respective regions. That is, the closer to the channel formation region, the lower the concentrations of the metal elements and impurity elements such as hydrogen and nitrogen can be.

[0058] Preferably, a metal oxide used as a semiconductor (hereinafter also referred to as an oxide semiconductor) is used for the oxide 230 (oxide 230a and oxide 230b).

[0059] The bandgap of the metal oxide used as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. A transistor including a metal oxide in the channel formation region is referred to as an OS transistor. Since the OS transistor has a small off-state current, the power consumption of the semiconductor device can be sufficiently reduced. In addition, since the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0060] The oxide 230 preferably contains a metal oxide (oxide semiconductor). Examples of the metal oxide that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three selected from indium, element M, and zinc. In addition, element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification and the like sometimes include metalloid elements.

[0061] The oxide 230 can be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0062] By increasing the atomic number ratio of indium to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0063] In addition, the metal oxide can also replace indium or contain one or more metal elements with a large period number in addition to indium. The greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by containing metal elements with a large period number, the field-effect mobility of the transistor can sometimes be increased. Examples of metal elements with a large period number include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, as the metal element, examples include: yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0064] In addition, the metal oxide can also contain one or more non-metal elements. When the metal oxide contains non-metal elements, the field-effect mobility of the transistor can sometimes be increased. Examples of non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0065] In addition, by increasing the atomic number ratio of zinc to the total number of atoms of all metal elements contained in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation in the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0066] In addition, by increasing the atomic ratio of element M to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be achieved. In addition, the variation in the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0067] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide for the oxide 230. Therefore, by making the composition of the metal oxide different corresponding to the required electrical characteristics and reliability of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be achieved.

[0068] The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions. For example, the atomic ratio of element M to the metal element as the main component in the metal oxide for the oxide 230a is preferably greater than the atomic ratio of element M to the metal element as the main component in the metal oxide for the oxide 230b. In addition, the atomic ratio of element M to In in the metal oxide for the oxide 230a is preferably greater than the atomic ratio of element M to In in the metal oxide for the oxide 230b. By adopting this structure, the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b can be suppressed.

[0069] In addition, preferably, the atomic ratio of In to element M in the metal oxide for the oxide 230b is greater than the atomic ratio of In to element M in the metal oxide for the oxide 230a. By adopting this structure, the transistor 200 can obtain a large on-state current and high-frequency characteristics.

[0070] In addition, when the oxide 230a and the oxide 230b contain a common element as the main component in addition to oxygen, the density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. The density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction becomes smaller, and thus the transistor 200 can obtain a large on-state current and high-frequency characteristics.

[0071] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or near it, a composition of In:M:Zn = 1:3:4 [atomic ratio] or near it, a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or near it can be used. In addition, as the oxide 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it, a composition of In:M:Zn = 1:1:1.2 [atomic ratio] or near it, a composition of In:M:Zn = 1:1:2 [atomic ratio] or near it, a composition of In:M:Zn = 4:2:3 [atomic ratio] or near it, or a composition of In:Zn = 4:1 [atomic ratio] or near it without containing the element M can be used. Note that the near composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M. In addition, when a single layer of the oxide 230b is provided as the oxide 230, a metal oxide that can be used for the oxide 230a can also be applied as the oxide 230b. In addition, the composition of the metal oxide that can be used for the oxide 230a and the oxide 230b is not limited to this. For example, the composition of the metal oxide that can be used for the oxide 230a can also be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b can also be applied to the oxide 230a. As either one or both of the oxide 230a and the oxide 230b, a metal oxide having the above composition can also be laminated.

[0072] In addition, when depositing a metal oxide by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but can also be the atomic ratio of the sputtering target used for the deposition of the metal oxide.

[0073] The oxide 230b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide 230b.

[0074] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (for example, oxygen vacancies). In particular, by performing heat treatment at a temperature at which the metal oxide is not polycrystallized (for example, 400 °C or higher and 600 °C or lower) after forming the metal oxide, CAAC-OS can have a denser structure with higher crystallinity. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0075] In addition, distinct grain boundaries are not easily observable in CAAC-OS, so a decrease in electron mobility due to grain boundaries is not likely to occur. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Accordingly, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0076] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Therefore, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is also stable with respect to a high temperature (so-called thermal budget) in the manufacturing process.

[0077] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in the channel-forming region of the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may sometimes decrease. In addition, hydrogen near an oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H), and electrons that become carriers may be generated. Therefore, when an oxygen vacancy is included in the channel-forming region of the oxide semiconductor, the transistor has a normally-on characteristic (a characteristic in which a channel exists and current flows through the transistor even when a voltage is not applied to the gate electrode). Thus, in the channel-forming region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration in the channel-forming region of the oxide semiconductor is decreased and the region is i-type (intrinsic) or substantially i-type.

[0078] In contrast, by performing heat treatment with an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) disposed near the oxide semiconductor, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that when too much oxygen is supplied to the source region or the drain region, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 may occur. Also, when the amount of oxygen supplied to the source region or the drain region is non-uniform within the substrate surface, the characteristics of the semiconductor device including the transistor become non-uniform. In addition, when oxygen supplied from the insulator to the oxide semiconductor diffuses to conductors such as the gate electrode, the source electrode, and the drain electrode, sometimes the conductor is oxidized, which results in a loss of conductivity and thus has a negative impact on the electrical characteristics and reliability of the transistor.

[0079] Therefore, preferably, in the oxide semiconductor, the carrier concentration in the channel formation region is reduced and is i - type or substantially i - type. On the other hand, preferably, the carrier concentrations in the source region and the drain region are high and are n - type. In other words, it is preferable to reduce the oxygen vacancies and V O H in the channel formation region of the oxide semiconductor. In addition, preferably, the source region and the drain region are not supplied with too much oxygen and the amount of V O H in the source region and the drain region is not excessively reduced. In addition, preferably, there is a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, etc. For example, preferably, there is a structure that suppresses the oxidation of the conductor 260, the conductor 242a, the conductor 242b, etc. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce the amount of V O H, it is necessary to reduce the hydrogen concentration.

[0080] Then, the semiconductor device in this embodiment has the following structure: reducing the hydrogen concentration in the channel formation region; suppressing the oxidation of the conductor 242a, the conductor 242b, and the conductor 260; and suppressing a decrease in the hydrogen concentration in the source region and the drain region.

[0081] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing or fixing hydrogen. Thereby, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, V O H in the channel formation region can be reduced to make the channel formation region i - type or substantially i - type.

[0082] Here, as Figure 2A shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. At this time, the insulator 250a and the insulator 250c preferably have a function of capturing or fixing hydrogen.

[0083] As the insulator having a function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a and the insulator 250c, for example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. The above - mentioned metal oxide having an amorphous structure sometimes has the following property: an oxygen atom has a dangling bond and captures or fixes hydrogen by this dangling bond. That is to say, it can be said that the ability of the metal oxide having an amorphous structure to capture or fix hydrogen is high.

[0084] In addition, the insulators 250a and 250c are preferably made of a high-dielectric constant (high-k) material. As an example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. When the high-k material is used as the insulators 250a and 250c, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0085] As the insulators 250a and 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0086] In the present embodiment, an aluminum oxide film is used as the insulator 250a. In addition, the aluminum oxide preferably has an amorphous structure. Here, by disposing the insulator 250a in contact with the oxide 230b, hydrogen contained in the oxide 230b or the like can be captured and fixed more effectively.

[0087] In the present embodiment, hafnium oxide is used as the insulator 250c. Here, by disposing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b or the like can be captured and fixed more effectively.

[0088] Next, as the insulator 250b, a thermally stable insulator such as silicon oxide or silicon oxynitride is preferably used. Note that in this specification and the like, "oxynitride" refers to a material in which the oxygen content is more than the nitrogen content in its composition, and "nitroxide" refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as "silicon oxynitride", it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as "silicon nitroxide", it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0089] In order to suppress the oxidation of the conductors 242a, 242b, and 260, an oxygen barrier insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in the present embodiment, this insulator is, for example, the insulators 250a, 250d, 250c, and 275.

[0090] Note that in this specification and the like, a barrier insulator refers to an insulator having a barrier property. In this specification and the like, having a barrier property means having a property of hindering the permeation of the corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that the corresponding substance does not easily diffuse into the insulator. For example, an insulator having a barrier property has a function of capturing or fixing (also referred to as gettering) the corresponding substance inside the insulator.

[0091] As the oxygen barrier insulator, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as the oxides containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate) can be cited. For example, the insulator 250a, the insulator 250c, the insulator 250d, and the insulator 275 preferably adopt a single-layer structure or a laminated structure of the above-mentioned oxygen barrier insulator.

[0092] The insulator 250a preferably has oxygen barrier properties. The insulator 250a is preferably at least less likely to allow oxygen to pass through than the insulator 280. The insulator 250a has regions in contact with the sides of the conductor 242a and the sides of the conductor 242b. When the insulator 250a has oxygen barrier properties, oxidation of the sides of the conductor 242a and the conductor 242b can be suppressed, and an oxide film can be prevented from forming on these sides. Therefore, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0093] The insulator 250a is provided so as to be in contact with the top surface and the side surface of the oxide 230b, the side surface of the oxide 230a, and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, detachment of oxygen from the channel formation region of the oxide 230b during heat treatment or the like can be suppressed. Therefore, the formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.

[0094] In addition, by providing the insulator 250a, excessive oxygen supply from the insulator 280 to the oxide 230a and the oxide 230b can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide 230a and the oxide 230b. Therefore, over-oxidation of the source region and the drain region can be prevented, and a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0095] Since the oxides containing one or both of aluminum and hafnium have oxygen barrier properties, they can be suitably used as the insulator 250a.

[0096] The insulator 250d preferably has oxygen barrier properties as well. The insulator 250d is disposed between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. By adopting this structure, oxygen diffusion from the channel formation region of the oxide 230 into the conductor 260 can be suppressed, and oxygen vacancies can be prevented from forming in the channel formation region of the oxide 230. In addition, oxygen diffusion from the oxide 230 and the insulator 280 into the conductor 260, which may cause oxidation of the conductor 260, can be suppressed. The insulator 250d is preferably less permeable to oxygen than the insulator 280 at least. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0097] In addition, the insulator 250d preferably has hydrogen barrier properties. Thereby, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.

[0098] The insulator 275 preferably has oxygen barrier properties as well. The insulator 275 is disposed between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. The insulator 275 is disposed in contact with the side surfaces of the conductor 242, the side surfaces of the oxide 230, and the top surface of the insulator 222. By adopting this structure, oxygen diffusion from the insulator 280 into the conductor 242 can be suppressed. Therefore, an increase in resistivity due to oxidation of the conductor 242 caused by oxygen contained in the insulator 280 can be suppressed. The insulator 275 is preferably less permeable to oxygen than the insulator 280 at least. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0099] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region of the oxide 230, a hydrogen barrier insulator is preferably provided near the source region and near the drain region. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, the insulator 275.

[0100] Examples of the hydrogen barrier insulator include oxides such as alumina, hafnium oxide, tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above hydrogen barrier insulator.

[0101] By providing the above insulator 275, hydrogen diffusion from the source region and the drain region to the outside can be reduced, and thus a decrease in the hydrogen concentration in the source region and the drain region can be suppressed. Therefore, the source region and the drain region can be n-type.

[0102] By adopting the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and the drain region can be made n-type, thereby providing a semiconductor device with good electrical characteristics. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can still have good electrical characteristics. In addition, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0103] The insulators 250a to 250d are used as part of the gate insulator. The insulators 250a to 250d and the conductor 260 are disposed in an opening formed in the insulator 280. In order to miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are all preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, still further preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. In addition, at least a part of the insulators 250a to 250d may include a region having the above-described thickness.

[0104] In order to reduce the thicknesses of the insulators 250a to 250d as described above, it is preferable to perform deposition by the atomic layer deposition (ALD: Atomic Layer Deposition) method. In addition, in order to dispose the insulators 250a to 250d in the opening of the insulator 280 or the like, it is preferable to perform deposition by the ALD method. The ALD method includes a thermal ALD (Thermal ALD) method in which only heat energy is used to react the precursor and the reactant, a PEALD (Plasma-Enhanced ALD) method in which a reactant excited by plasma is used, and the like. In the PEALD method, since deposition can be performed at a lower temperature by using plasma, it is sometimes preferable.

[0105] The ALD method can deposit atoms layer by layer, and thus has effects such as being able to deposit an extremely thin film, being able to deposit on a structure with a high aspect ratio, being able to deposit with few defects such as pinholes, being able to perform deposition with high coverage, and being able to perform deposition at a low temperature. Therefore, the insulator 250 can be deposited with the above-described small thickness and high coverage on the side surface of the opening formed in the insulator 280 and the side end portions of the conductors 242a and 242b.

[0106] Precursors used in ALD sometimes contain carbon or the like. Therefore, the film formed by ALD sometimes contains more impurities such as carbon compared to the film formed by other deposition methods. In addition, the quantification of impurities can be carried out using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0107] Note that in the above, it is described that the insulator 250 has a four-layer structure of insulator 250a to insulator 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of insulator 250a to insulator 250d. By forming the insulator 250 from one, two, or three layers of insulator 250a to insulator 250d, the manufacturing process of the semiconductor device can be simplified, and thus the productivity can be improved.

[0108] For example, as Figure 3A shown, the insulator 250 may also have a two-layer structure. At this time, the insulator 250 preferably has a stacked structure of the insulator 250a and the insulator 250d on the insulator 250a. A high-k material can be used for at least one of the insulator 250a and the insulator 250d. Thereby, the equivalent oxide thickness (EOT) can be reduced while maintaining the thickness of the insulator 250a and the insulator 250d at a level that suppresses leakage current.

[0109] For example, as Figure 3B shown, the insulator 250 may also have a three-layer structure. At this time, the insulator 250 preferably has a stacked structure of the insulator 250a, the insulator 250b on the insulator 250a, and the insulator 250d on the insulator 250b. That is, it has a structure in which the insulator 250b is further provided to the structure Figure 3A shown.

[0110] In this embodiment, preferably, the semiconductor device has a structure for suppressing hydrogen from mixing into the transistor 200 or the like in addition to the above structure. For example, preferably, an insulator having a function of suppressing hydrogen diffusion is provided so as to cover one or both of the upper and lower sides of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, insulator 283, insulator 282, insulator 222, insulator 221, etc. In addition, the insulator 215 provided under the transistor 200 may have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a laminated structure of the insulator 282 and the insulator 283, and may adopt a structure in which the insulator 282 is located below and the insulator 283 is located above, or a structure in which the insulator 282 is located above and the insulator 283 is located below.

[0111] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 are preferably used as a barrier insulator for suppressing the diffusion of impurities such as water and hydrogen from the substrate side or above the transistor 200 or the like to the transistor 200 or the like. Therefore, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably contain an insulating material having a function of suppressing the diffusion of impurity atoms such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. (not easily permeable to the above impurities). In addition, it preferably includes an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not easily permeable to the above oxygen).

[0112] The insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably all include an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. For example, alumina, magnesia, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc. can be used. For example, the insulator 283 and the insulator 221 preferably use silicon nitride or the like with higher hydrogen barrier properties. In addition, for example, the insulator 282 preferably uses alumina or the like with high hydrogen trapping or fixing ability. In addition, for example, the insulator 222 preferably uses hafnium oxide or the like with high hydrogen trapping or fixing ability and being a high dielectric constant (high-k) material.

[0113] By adopting such a structure, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 200 or the like. In addition, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed below the insulator 221 to the transistor 200 or the like. In addition, hydrogen in the insulator 280, the insulator 250, etc. can be captured or fixed to the insulator 282 or the insulator 222. In addition, by providing the insulator 282 and the insulator 283, it is possible to suppress the diffusion of oxygen in the insulator 280 or the like above the transistor 200 or the like. In addition, by providing the insulator 222 and the insulator 221, it is possible to suppress the diffusion of oxygen in the oxide 230 or the like below the transistor 200 or the like. Thus, by adopting a structure in which the transistor 200 is surrounded by insulators having functions of suppressing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be reduced. Thereby, improvement in the electrical characteristics and reliability of the semiconductor device can be achieved.

[0114] Moreover, the insulator 275 and the insulator 250d are preferably made of silicon nitride or the like having higher hydrogen barrier properties. In addition, the insulator 250a is preferably made of alumina or the like having a high ability to capture or fix hydrogen. In addition, the insulator 250c is preferably made of hafnium oxide or the like having a high ability to capture or fix hydrogen.

[0115] The insulator 225 is formed on the insulator 222 in contact therewith. As Figure 2B and Figure 4B shown, when viewed in cross section in the channel width direction, the insulator 225 has a shape with a high aspect ratio. Here, the aspect ratio of the insulator 225 when viewed in cross section in the channel width direction refers to the ratio of the length L in the A3 - A4 direction of the insulator 225 (which can also be referred to as the width L of the insulator 225) to the length H in the direction perpendicular to the formation surface of the insulator 225 (for example, the insulator 222) (which can also be referred to as the height H of the insulator 225). In the insulator 225, the height H of the insulator 225 is at least larger than the width L of the insulator 225. The height H of the insulator 225 can be more than 1 times the width L of the insulator 225, preferably 2 times or more, more preferably 5 times or more, and further preferably 10 times or more. In addition, it is preferable that the height H of the insulator 225 is 20 times or less the width L of the insulator 225.

[0116] An oxide 230a, an oxide 230b, and a conductor 242 are provided to cover the insulator 225 having the high aspect ratio. In the transistor 200, as Figure 2BAs shown, oxide 230a and oxide 230b are arranged in a folded state sandwiching insulator 225, and insulator 250 and conductor 260 are provided covering oxide 230b. Thus, when viewed in cross-section in the channel width direction, on the top of insulator 225, the side surface on the A3 side, and the side surface on the A4 side, oxide 230 and conductor 260 face each other with insulator 250 in between. That is to say, the top of insulator 225, the side surface on the A3 side, and the side surface on the A4 side all serve as channel formation regions. Therefore, the channel width of transistor 200 is larger than the case where insulator 225 is not provided by the portions of the side surfaces on the A3 side and the A4 side of insulator 225.

[0117] As described above, by increasing the channel width, the on-state current, field-effect mobility, frequency characteristics, etc. of transistor 200 can be improved. Thereby, a semiconductor device with a high operating speed can be provided. In addition, the operating speed of a storage device using this semiconductor device can be increased. Further, in the above structure, by providing insulator 225, the channel width can be increased without increasing the occupied area of transistor 200. Thereby, miniaturization or high integration of the semiconductor device can be achieved. Additionally, the storage capacity of a storage device using this semiconductor device can be increased.

[0118] Insulator 225 can use an insulating material that can be used for insulator 222, insulator 280, insulator 250, etc. Since insulator 225 has a shape with a high aspect ratio, it is preferably formed in a sidewall shape on the side surface of a sacrificial layer (insulator 223 described later). Therefore, insulator 225 is preferably formed by ALD method with high coverage. For example, insulator 225 can use hafnium oxide deposited by thermal ALD method, etc.

[0119] In this way, by forming sidewall-shaped insulator 225 in contact with the side surface of the sacrificial layer, as Figure 1A shown, etc., insulator 225 of transistor 200a and insulator 225 of transistor 200b can be formed simultaneously. By forming two insulators 225 in this way, the distance between the two insulators 225 can be set according to the size of the sacrificial layer. Therefore, the distance between insulators 225 can be reduced to reduce the occupied area of transistor 200a and transistor 200b, and thereby high integration of the semiconductor device can be achieved.

[0120] Note that insulator 225 is not strictly limited to an insulating material. For example, relatively highly insulating metal oxides, etc. can also be used. For example, the metal oxides that can be used for oxide 230a described above can also be used.

[0121] In addition, the top of the insulator 225 may also have a curved shape. When having such a curved shape, it is possible to prevent defects such as voids from forming in the oxide 230a, the oxide 230b, and the conductor 242 near the top of the insulator 225. Note that in Figure 2B and Figure 4B etc., both the A3 side (A5 side) and the A4 side (A6 side) of the top of the insulator 225 are set to have a curved shape. Although a symmetric structure is adopted, the present invention is not limited thereto. For example, there may be an asymmetric structure in which only the A3 side (A5 side) of the top of the insulator 225 is set to have a curved shape.

[0122] In addition, although Figure 1A etc. show a structure in which the insulator 225 extends in the A1 - A2 direction, the present invention is not limited thereto. For example, the insulator 225 may also be arranged in a circumferential shape (it can also be said to be a frame shape or a closed curve shape) as shown in Figures 5A to 5D . Figure 5A is a plan view of the above semiconductor device. In addition, Figures 5B to 5D is a cross-sectional view of the semiconductor device. Here, Figure 5B is a cross-sectional view of the part shown by the dotted line A1 - A2 in Figure 5A . In addition, Figure 5C is a cross-sectional view of the part shown by the dotted line A3 - A4 in Figure 5A . In addition, Figure 5D is a cross-sectional view of the part shown by the dotted line A7 - A8 in Figure 5A . Note that in the plan view of Figure 5A , some components are omitted for easy understanding.

[0123] As shown in the cross-section of A7 - A8 in Figure 5D , the insulator 225 is integrated between the transistor 200a and the transistor 200b. Therefore, between the transistor 200a and the transistor 200b, the insulator 275 contacts the top surface of the insulator 225. As described above, the insulator 225 is preferably formed in a sidewall shape so as to contact the side surface of the sacrificial layer. In the semiconductor device shown in Figures 5A to 5D , the insulator 225 is formed by providing a sacrificial layer in the region surrounded by the insulator 225.

[0124] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided in such a way as to be embedded in the opening formed in the insulator 216. In addition, as shown in Figure 1A and Figure 1C , the conductor 205 is preferably extended in the channel width direction. By adopting such a structure, the conductor 205 is used as a wiring when a plurality of transistors are provided.

[0125] As Figure 1B and Figure 1C shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is disposed in contact with the bottom surface and the side wall of the above-mentioned opening portion. The conductor 205b is disposed so as to be embedded in the concave portion of the conductor 205a formed along the above-mentioned opening portion. Here, the height of the top surface of the conductor 205 is the same as or substantially the same as the height of the top surface of the insulator 216.

[0126] Here, as the conductor 205a, it is preferably composed of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. Or, it is preferably composed of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0127] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 through the insulator 216 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion as the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide can be cited. The conductor 205a may have a single-layer structure or a laminated structure of the above-mentioned conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0128] In addition, the conductor 205b preferably uses a conductive material mainly composed of tungsten, copper or aluminum. For example, the conductor 205b preferably contains tungsten.

[0129] The conductor 205 can be used as a second gate electrode. In this case, by independently changing the potential applied to the conductor 205 without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where no negative potential is applied to the conductor 205, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0130] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205 as described above, and the thickness of the conductor 205 is set according to this resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferable to reduce the thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of the impurities into the oxide 230 can be suppressed.

[0131] Note that, in the above structure, a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 205 has a three-layer stacked structure, the above-described stacked structure of the conductor 205a and the conductor 205b may be employed and a conductor containing the same material as the conductor 205a may be provided on the conductor 205b. At this time, the above-described conductor may also be formed in such a manner as to be embedded in a recess formed by the conductor 205a and the conductor 205b, and the recess is formed in such a manner that the top surface of the conductor 205b is lower than the uppermost portion of the conductor 205a.

[0132] In addition, the semiconductor device of the present embodiment may also be as Figures 6A to 6D shown and adopt a structure in which the conductor 205 is not provided. Here, as Figure 2B shown, in the transistor 200, the oxide 230 has a structure in which it is folded in half with the insulator 225 interposed therebetween. Thus, the conductor 260 facing the oxide 230 with the insulator 225 interposed therebetween sometimes has the same function as the above-described conductor 205. Therefore, even if the conductor 205 is not provided as Figures 6A to 6D shown, a part of the conductor 260 may sometimes be used as the second gate electrode.

[0133] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. As such a conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thereby, a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed. When a conductive material containing a metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least a metal and nitrogen.

[0134] The conductor 242a and the conductor 242b are provided separately from each other and are provided in contact with the oxide 230b. As Figure 4A and Figure 4BAs shown in etc., the conductor 242 is provided so as to cover the insulator 225 having a high aspect ratio. Therefore, the conductor 242 is preferably deposited by a deposition method with high coverage such as the ALD method or the CVD method.

[0135] Here, as Figure 4B shown, near the source or drain of the transistor 200a, the oxides 230a, 230b and the conductor 242a are provided in a folded state with the insulator 225 interposed therebetween. Thus, when viewed in cross-section in the channel width direction, the conductor 242a is in contact with the oxide 230b on the top, the side surface on the A5 side and the side surface on the A6 side of the insulator 225. Therefore, the contact area between the conductor 242a and the oxide 230b is larger than the case where the insulator 225 is not provided by the portions of the side surfaces on the A5 side and the A6 side of the insulator 225. Note that Figure 4B shows near the conductor 242a, but the same applies to the conductor 242b. That is, similarly to the above-described conductor 242a and oxide 230b, the contact area between the conductor 242b and the oxide 230b increases.

[0136] As described above, when the contact area between the conductor 242 and the oxide 230b increases, the on-state current, frequency characteristics, etc. of the transistor 200 can be improved without increasing the occupied area of the transistor 200. Thereby, a semiconductor device with a high operating speed can be provided. In addition, the operating speed of a storage device using the semiconductor device can be increased. Thereby, miniaturization or high integration of the semiconductor device can be achieved. Further, the storage capacity of a storage device using the semiconductor device can be increased.

[0137] Since the conductor 242a and the conductor 242b are in contact with the oxide 230b, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. Thereby, a decrease in the conductivity of the conductors 242a and 242b can be suppressed. In addition, extraction of oxygen from the oxide 230b to form excessive oxygen vacancies can be suppressed. Further, by using a material that easily absorbs (extracts) hydrogen as the conductors 242a and 242b, the hydrogen concentration in the oxide 230 can be reduced, which is preferable.

[0138] As the conductor 242, a metal nitride is preferably used. For example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, a nitride containing tantalum is particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable.

[0139] Note that sometimes hydrogen contained in the oxide 230b or the like diffuses into the conductor 242a or the conductor 242b. In particular, when nitrides containing tantalum are used as the conductor 242a and the conductor 242b, sometimes hydrogen contained in the oxide 230b or the like easily diffuses into the conductor 242a or the conductor 242b, and sometimes the diffused hydrogen bonds with nitrogen contained in the conductor 242a or the conductor 242b. That is to say, sometimes hydrogen contained in the oxide 230b or the like is absorbed by the conductor 242a or the conductor 242b.

[0140] In addition, in order to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b. In particular, a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin is preferably used. When CAAC-OS is used, oxygen extraction from the oxide 230b by the conductor 242a or the conductor 242b can be suppressed. In addition, a decrease in the conductivity of the conductor 242a and the conductor 242b can be suppressed.

[0141] As Figure 3C shown, the conductors 242a and 242b may also have a two-layer structure. The conductor 242a may be a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b may be a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. At this time, as the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion as described above is preferably used. Thereby, a decrease in the conductivity of the conductors 242a and 242b can be suppressed. In addition, oxygen extraction from the oxide 230b to form excessive oxygen vacancies can be suppressed. Further, by using a material that easily absorbs (extracts) hydrogen as the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), the hydrogen concentration of the oxide 230 can be reduced, which is therefore preferable.

[0142] The conductivity of the conductor 242a2 and the conductor 242b2 is preferably higher than that of the conductor 242a1 and the conductor 242b1. For example, the thickness of the conductor 242a2 and the conductor 242b2 is preferably larger than the thickness of the conductor 242a1 and the conductor 242b1. The conductors that can be used for the conductor 205b as described above can be used as the conductor 242a2 and the conductor 242b2. By adopting the above structure, the resistance of the conductor 242a2 and the conductor 242b2 can be reduced. Thereby, the on-state current of the transistor 200 can be increased to improve the operating speed of the semiconductor device according to the present embodiment.

[0143] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0144] As Figure 3C shown, it is preferable to provide an insulator 255 between the conductors 242a2, 242b2, insulators 275 and 280 and the insulator 250. The insulator 255 is disposed in an opening formed in the insulator 280 or the like, and contacts the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1 and the top surface of the conductor 242b1. In other words, the insulator 255 is formed so as to contact the side wall of the opening formed in the insulator 280 or the like. That is to say, the insulator 255 can be referred to as a side wall insulating film.

[0145] The insulator 255 is formed so as to contact the side surfaces of the conductors 242a2 and 242b2, and is an inorganic insulator that protects the conductors 242a2 and 242b2. Since it is exposed to an oxidizing atmosphere, the insulator 255 is preferably an inorganic insulator that is not easily oxidized. In addition, since the insulator 255 contacts the conductors 242a2 and 242b2, it is preferably an inorganic insulator that does not easily oxidize the conductors 242a2 and 242b2. Therefore, it is preferable to use an insulating material that can be used for the insulator 250d having an oxygen barrier property for the insulator 255. For example, silicon nitride can be used as the insulator 255.

[0146] By using such an insulator 255, even when heat treatment is performed in an oxygen-containing atmosphere after the conductor is divided into the conductors 242a1 and 242b1 and before the insulator 250 is deposited, the conductors 242a2 and 242b2 can be prevented from being excessively oxidized.

[0147] Note that Figure 3C a structure in which the upper end of the insulator 255 is substantially aligned with the top surface of the insulator 280, the upper end of the insulator 250, and the upper end of the conductor 260 is shown, but the present embodiment is not limited thereto. The insulator 255 only needs to have a structure that covers the side surfaces of the conductors 242a2 and 242b2. For example, a structure in which the position of the upper end of the insulator 255 is lower than the top surface of the insulator 280 and higher than the top surface of the insulator 275 can also be adopted.

[0148] As Figure 3CAs shown, when viewed in a cross-section along the channel length direction of the transistor 200, the distance between the conductors 242a1 and 242b1 is smaller than the distance between the conductors 242a2 and 242b2. Specifically, the difference in the above distances is equal to or approximately equal to twice the thickness of the insulator 255. Here, the thickness of the insulator 255 refers to the thickness in the A1 - A2 direction of at least a part of the insulator 255. By adopting such a structure, the distance between the source and the drain can be further shortened and accordingly the channel length can be reduced. Therefore, the frequency characteristics of the transistor 200 can be improved. Thus, by realizing miniaturization of the semiconductor device, a semiconductor device with an increased operating speed can be provided.

[0149] As Figure 1B and Figure 1C shown, the conductor 260 is disposed in an opening formed in the insulators 280, 275, the conductors 242a and 242b. In this opening, the conductor 260 is disposed so as to cover the top surface of the insulator 222, the side surfaces of the oxides 230a and 230b, and the top surface of the oxide 230b with the insulator 250 interposed therebetween. In addition, the top surface of the conductor 260 is disposed to be equal to or approximately equal to the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0150] In the above opening in which the conductor 260 and the insulator 250 are disposed, the side wall of the opening may be perpendicular or substantially perpendicular to the top surface of the insulator 222, or may have a tapered shape. By having a tapered shape of the side wall, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 can be improved, and thus defects such as voids can be reduced.

[0151] The conductor 260 is used as the first gate electrode of the transistor 200. Here, as Figure 1A and Figure 1C shown, the conductor 260 is preferably extended in the channel width direction. By adopting such a structure, the conductor 260 is used as a wiring when a plurality of transistors are provided.

[0152] In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification and the like is different from a Fin type structure and a planar type structure. On the other hand, the S-channel structure disclosed in this specification and the like can be regarded as a kind of Fin type structure. In addition, in this specification and the like, the Fin type structure refers to a structure in which gate electrodes are arranged so as to surround at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, four surfaces, etc.). By adopting the Fin type structure and the S-channel structure, the tolerance to the short channel effect can be improved, in other words, a transistor in which the short channel effect is not likely to occur can be realized.

[0153] By adopting the above S-channel structure as the transistor 200, the channel formation region can be electrically surrounded. Since the S-channel structure is a structure that electrically surrounds the channel formation region, it can also be said that this structure is substantially the same as a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be regarded as the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the on-state current of the transistor or the field effect mobility of the transistor can be expected.

[0154] In Figure 1B and the like, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, it is preferable to arrange the conductor 260a so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is preferably used.

[0155] As the conductor 260a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably used.

[0156] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280 or the like. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0157] In addition, the conductor 260b is preferably a conductor having high conductivity. For example, as the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. In addition, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0158] In addition, in the transistor 200, the conductor 260 is formed self-aligned so as to fill an opening formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the above opening is aligned or substantially aligned with the side surfaces of the conductor 242a and the conductor 242b. Therefore, the conductor 260 can be arranged so as to overlap the region between the conductor 242a and the conductor 242b without performing alignment.

[0159] The dielectric constants of the insulator 216 and the insulator 280 are preferably lower than that of the insulator 222. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0160] For example, the insulator 216 and the insulator 280 preferably contain one or more of silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores.

[0161] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating.

[0162] In addition, the top surfaces of the insulator 216 and the insulator 280 can also be planarized.

[0163] The concentrations of impurities such as water and hydrogen in the insulator 280 are preferably reduced. For example, as the insulator 280, a silicon-containing oxide such as silicon oxide or silicon oxynitride is preferably used.

[0164] Both the conductor 240a and the conductor 240b are formed in the openings of the insulator 275, the insulator 280, the insulator 282, and the insulator 283. The bottom surface of the conductor 240a is in contact with the top surface of the conductor 242a, and the bottom surface of the conductor 240b is in contact with the top surface of the conductor 242b. Here, the height of the top surface of the conductor 240 is substantially the same as the height of the top surface of the insulator 283.

[0165] The conductor 240 preferably uses a conductive material mainly composed of tungsten, copper or aluminum. Additionally, the conductor 240 may also adopt a laminated structure in which the first conductor is arranged to contact the side surface of the insulator 241 and the second conductor is arranged inside thereof. In this case, the above-mentioned conductive material can be used as the second conductor.

[0166] Furthermore, when the laminated structure is adopted for the conductor 240, as the first conductor disposed near the insulators 283, 282, 280 and 275, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. Additionally, a single layer or a laminate of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen can also be used. By adopting such a structure, impurities such as water and hydrogen contained in the layer above the insulator 283 can be prevented from mixing into the oxide 230 through the conductors 240a and 240b.

[0167] Both the insulators 241a and 241b are formed in such a way as to contact the inner walls of the openings of the insulators 275, 280, 282 and 283. The inner side surface of the insulator 241a contacts the conductor 240a, and the inner side surface of the insulator 241b contacts the conductor 240b.

[0168] As the insulator 241, a barrier insulating film that can be used for the insulator 275 etc. can be used. For example, as the insulator 241, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride can be used. By providing the insulator 241, impurities such as water and hydrogen contained in the insulator 280 etc. can be prevented from mixing into the oxide 230 through the conductors 240a and 240b. In particular, silicon nitride is preferred because of its high barrier property against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0169] When the insulator 241 has a laminated structure as shown in Figure 1B it is preferable to use an oxygen barrier insulating film and a hydrogen barrier insulating film in combination as the first insulator that contacts the inner wall of the opening of the insulator 280 etc. and the second insulator inside thereof.

[0170] For example, alumina deposited by thermal ALD method can be used as the first insulator, and silicon nitride deposited by PEALD method can be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and hydrogen entering the conductor 240 can be reduced.

[0171] Note that, although the above example shows a stacked structure of two layers for the insulator 241, the present invention is not limited thereto. For example, the insulator 241 may also have a single-layer structure or a stacked structure of three or more layers. Additionally, although the above example shows a stacked structure of two layers for the conductor 240, the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer or a stacked structure of three or more layers.

[0172] In addition, Figure 4B etc. show a structure in which the conductor 240a is in contact with the conductor 242a only above the upper end portion of the insulator 225, but the present invention is not limited thereto. For example, as Figure 4C shown, it may also have a structure in which the conductor 240a covers the insulator 225 and the oxides 230a, 230b and the conductor 242a that are in a folded state with the insulator 225 interposed therebetween. Thus, when viewed in cross-section in the channel width direction, the conductor 240a is in contact with the conductor 242a at the top, the side surface on the A5 side and the side surface on the A6 side of the insulator 225. Therefore, the contact area between the conductor 240a and the conductor 242a is larger than the case where the insulator 225 is not provided by the portions of the side surfaces on the A5 side and the A6 side of the insulator 225. Note that, Figure 4C shows the vicinity of the conductor 240a and the conductor 242a, but the same applies to the conductor 240b and the conductor 242b. That is, similar to the above-mentioned conductor 240a and conductor 242a, the contact area between the conductor 240b and the conductor 242b increases.

[0173] As described above, when the contact area between the conductor 240 and the conductor 242 increases, the on-state current, frequency characteristics, etc. of the transistor 200 can be improved without significantly increasing the occupied area of the transistor 200. Thereby, a semiconductor device with a high operating speed can be provided. In addition, the operating speed of a storage device using this semiconductor device can be increased. Thereby, miniaturization or high integration of the semiconductor device can be achieved. Additionally, the storage capacity of a storage device using this semiconductor device can be increased.

[0174] In addition, in the above structure, as Figure 1C etc. shown, the oxides 230a and 230b cover the insulator 225 near the channel of the transistor 200, but the present invention is not limited thereto. For example, as Figures 7A to 7D and Figure 8 shown, the top surface of the insulator 225 near the channel of the transistor 200 may also be exposed from the oxides 230a and 230b. Figure 7A is a plan view of the above semiconductor device. Additionally, Figures 7B to 7D and Figure 8 are cross-sectional views of this semiconductor device. Here, Figure 7B is alongFigure 7A The cross-sectional view of the portion indicated by the dash-dotted line A1 - A2 in Figure 7C is the cross-sectional view of the portion indicated by the dash-dotted line A3 - A4 along Figure 7A in Figure 7D is the cross-sectional view of the portion indicated by the dash-dotted line A5 - A6 along Figure 7A in Figure 8 is the cross-sectional view of the portion indicated by the dash-dotted line B1 - B2 along Figure 7A in Figure 7A Note that in the plan view of

[0175] As shown in Figure 7A , Figure 7B , Figure 7C , Figure 8 etc., the following structure can be adopted: In the region not overlapping with the conductor 242 etc. (which can also be said to be the region sandwiched between the conductor 242a and the conductor 242b), the oxide 230a contacts the side surface of the insulator 225, the oxide 230b contacts the side surface of the oxide 230a, and the oxide 230a and the oxide 230b do not contact at least a part of the top surface of the insulator 225. Here, the oxide 230a contacts the side surface of the insulator 225, the side surface and the bottom surface of the oxide 230b, and the top surface of the insulator 222. As shown in Figure 7B , Figure 7C etc., the top surface of the insulator 225 contacts the bottom surface of the insulator 250. In addition, as shown in Figure 7A , Figure 7D etc., the oxide 230a and the oxide 230b cover the insulator 225 in the same way as the structure shown in Figure 1D in the region overlapping with the conductor 242 etc.

[0176] In Figure 7B , although it seems that the oxide 230a and the oxide 230b are not formed between the conductor 242a and the conductor 242b, as shown in Figure 8 , the oxide 230a and the oxide 230b are formed near the side surface of the insulator 225. In other words, both the oxide 230a and the oxide 230b have the following shape: The portion on the A5 side and the portion on the A6 side are formed integrally in a folded manner sandwiching the insulator 225 in the region overlapping with the conductor 242; the portion on the A3 side and the portion on the A4 side are separated by the insulator 225 in the region between the conductor 242a and the conductor 242b. In other words, the insulator 225 is almost covered by the oxide 230, but in the region between the conductor 242a and the conductor 242b, an opening is formed in the oxide 230, and in this region, the insulator 225 is exposed from the oxide 230.

[0177] As described above, in the region between the conductors 242a and 242b, the side oxides 230a and 230b of the insulator 225 with a high aspect ratio are provided in a sidewall shape. By adopting such a structure, channel formation regions of the transistor 200 can be formed on the side surface of the A3 side and the side surface of the A4 side of the insulator 225, whereby the channel width per unit area can be increased. By increasing the channel width, the on-state current, field effect mobility, and frequency characteristics of the transistor 200 can be improved. Therefore, by using the semiconductor device of the present embodiment as a storage device, the operating speed can be increased.

[0178] In the above structure, as Figure 7D shown, etc., the oxides 230a, 230b, the conductor 242a, and the conductor 242b sandwich the insulator 225 and are in a folded state near the source or drain of the transistor 200, but the present invention is not limited thereto. For example, as Figures 9A to 9D , Figure 10A and Figure 10B shown, a structure in which the oxides 230a, 230b, the conductor 242a, and the conductor 242b are divided into a part on the A3 side and a part on the A4 side with the dotted line A1 - A2 as the boundary can also be adopted. Figure 9A is a plan view of the above semiconductor device. In addition, Figures 9B to 9D and Figure 10A and Figure 10B are cross-sectional views of the semiconductor device. Here, Figure 9B is a cross-sectional view along the part shown by the dotted line D1 - D2 in Figure 9A . In addition, Figure 9C is a cross-sectional view along the part shown by the dotted line A3 - A4 in Figure 9A . In addition, Figure 9D is a cross-sectional view along the part shown by the dotted line A5 - A6 in Figure 9A . Figure 10A is a cross-sectional view along the part shown by the dotted line E1 - E2 in Figure 9A . Figure 10B is a cross-sectional view along the part shown by the dotted line A1 - A2 in Figure 9A . Note that, in the plan view of Figure 9A , some components are omitted for easy understanding.

[0179] Figures 9A to 9D , Figure 10A and Figure 10B shown, the semiconductor device includes a transistor 200aD on the A3 side and a transistor 200aE on the A4 side with the dotted line A1 - A2 (insulator 225) as the boundary. That is, in Figures 7A to 7D and Figure 8In the semiconductor device shown, the transistor 200a is divided into a transistor 200aD and a transistor 200aE without significantly increasing the occupied area. Note that in Figures 9A to 9D , Figure 10A and Figure 10B In the semiconductor device shown, the components corresponding to the transistor 200b of Figures 7A to 7D and Figure 8 are not shown, but the components corresponding to the transistor 200b can also be provided in the same manner as in the semiconductor device of Figures 7A to 7D and Figure 8 .

[0180] Therefore, the components of the semiconductor device of Figures 7A to 7D and Figure 8 are appended with "D" or "E" and shown as the components of the semiconductor device of Figures 9A to 9D , Figure 10A and Figure 10B . That is, the components included in the transistor 200aD on the A3 side are the oxide 230D (oxide 230aD and oxide 230bD), the conductor 242aD, the conductor 242bD, the conductor 240aD, the conductor 240bD, the insulator 241aD, and the insulator 241bD. In addition, the components included in the transistor 200aE on the A4 side are the oxide 230E (oxide 230aE and oxide 230bE), the conductor 242aE, the conductor 242bE, the conductor 240aE, the conductor 240bE, the insulator 241aE, and the insulator 241bE. The details of these components can be referred to the above description.

[0181] As shown in Figure 9B and Figure 9C , the oxide 230aD, the oxide 230bD, and the conductor 242aD (conductor 242bD) are provided separately from the oxide 230aE, the oxide 230bE, and the conductor 242aE (conductor 242bE) on the insulator 225. Therefore, as shown in Figure 10B , the oxide 230aD, the oxide 230bD, the conductor 242aD, the conductor 242bD, the oxide 230aE, the oxide 230bE, the conductor 242aE, and the conductor 242bE are not formed above at least a part of the insulator 225.

[0182] In addition, as shown in Figure 9B , the oxide 230D (oxide 230aD and oxide 230bD) is formed in contact with the side surface of the A3 side of the insulator 225, and a channel formation region is provided in the oxide 230bD. Similarly, as shown in Figure 10AAs shown, an oxide 230E (oxide 230aE and oxide 230bE) is formed in contact with the side surface of the A4 side of the insulator 225, and a channel formation region is provided in the oxide 230bE.

[0183] By adopting Figures 9A to 9D , Figure 10A and Figure 10B the structure shown, memory cells can be formed in a quantity twice as large without significantly increasing the occupied area. Therefore, miniaturization or high integration of the semiconductor device can be achieved. In addition, the storage capacity of a storage device using the semiconductor device can be increased.

[0184] <Constituent Materials of Semiconductor Device> Hereinafter, constituent materials that can be used for a semiconductor device will be described. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked structure.

[0185] <<Substrate>> As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. Also, a semiconductor substrate having an insulator region inside the above semiconductor substrate can be cited, for example, an SOI (Silicon On Insulator) substrate, etc. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator can be cited. Or, a substrate having one or more elements provided thereon can also be used. As an element provided on the substrate, for example, a capacitor, a resistor, a switching element, a light-emitting element, and a memory element can be cited.

[0186] <<Insulator>> As an insulator, for example, oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrides having insulating properties can be cited.

[0187] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator film. By using a high-k material as the insulator for the gate insulator, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. On the other hand, by using a material with a relatively low relative dielectric constant as the insulator for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0188] As insulators with a relatively high relative dielectric constant, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium can be cited.

[0189] As insulators with a relatively low relative dielectric constant, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resin can be cited.

[0190] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, a single layer or a laminate of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0191] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that can be removed by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that can be removed by heating contacts the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0192] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be cited. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable. In addition, a semiconductor with high conductivity represented by polysilicon containing impurity elements such as phosphorus or a silicide such as nickel silicide can also be used.

[0193] In the case of using a laminated conductor structure, for example, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen, a laminated structure combining a material containing the above metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can also be adopted.

[0194] In addition, when an oxide is used for the channel formation region of the transistor, as the conductor used as the gate electrode, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen is preferably adopted. In this case, it is preferable to dispose the conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, the oxygen released from the conductive material is easily supplied to the channel formation region.

[0195] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. For example, a nitrogen-containing conductive material such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, it is sometimes possible to capture the hydrogen contained in the metal oxide forming the channel. Or, sometimes it is possible to capture the hydrogen mixed in from an external insulator or the like.

[0196] <<Metal Oxide>> As the oxide 230, a metal oxide (oxide semiconductor) used as a semiconductor is preferably used. Hereinafter, the metal oxide of the oxide 230 that can be used in one aspect of the present invention will be described.

[0197] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition, in addition to this, it is preferably further contains aluminum, gallium, yttrium, tin, antimony, etc. In addition, it may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt, etc.

[0198] Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or antimony. As other elements that can be applied to element M, there are boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. Note that as element M, sometimes multiple of the above elements may be combined. In particular, element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0199] In addition, in this specification, etc., a metal oxide containing nitrogen may sometimes also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride.

[0200] Hereinafter, In-Ga-Zn oxide will be described as an example of the metal oxide.

[0201] As the crystal structure of the oxide semiconductor, examples include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal, etc.

[0202] In addition, when focusing on the structure of the oxide semiconductor, sometimes the classification of the oxide semiconductor is different from the above. For example, the oxide semiconductor can be classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than this. As the non-single crystal oxide semiconductor, for example, the above CAAC-OS and nc-OS can be cited. In addition, among the non-single crystal oxide semiconductors, there are polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0203] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0204] [CAAC-OS] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, and the c-axes of the plurality of crystalline regions are oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Further, as Figure 2B shown, etc., in the region where the oxide 230 contacts the insulator 225, the c-axis is preferably oriented along the normal direction of the surface of the insulator 225 film. In addition, a crystalline region is a region having periodicity in atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region where the lattice arrangements are consistent. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the a-b plane direction, and sometimes this region has distortion. In addition, the distortion refers to the portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are consistent and another region where the lattice arrangements are consistent in the region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0205] In addition, each of the above-mentioned plurality of crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one microcrystal, the maximum diameter of the crystalline region is less than 10 nm. In addition, when a crystalline region is composed of a plurality of microcrystals, sometimes the maximum diameter of the crystalline region is about several tens of nm.

[0206] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries confirmed. Therefore, it can be said that in CAAC-OS, a reduction in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor sometimes decreases due to the incorporation of impurities or the generation of defects, etc., so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor containing CAAC-OS are stable. Therefore, the oxide semiconductor containing CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable against high temperatures (so-called heat accumulation) in the manufacturing process. Thus, by using CAAC-OS in an OS transistor, the degree of freedom in the manufacturing process can be expanded.

[0207] [nc-OS] In nc-OS, the atomic arrangement in a minute region (e.g., a region of more than 1 nm and less than 10 nm, particularly a region of more than 1 nm and less than 3 nm) has periodicity. In other words, nc-OS has minute crystals. Further, for example, the size of the minute crystal is more than 1 nm and less than 10 nm, particularly more than 1 nm and less than 3 nm, and this minute crystal is called a nanocrystal. Further, in nc-OS, no regularity in crystal orientation is observed among different nanocrystals. Therefore, no orientation is observed in the whole film. Thus, sometimes nc-OS shows no difference from a-like OS or an amorphous oxide semiconductor in some analysis methods.

[0208] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS contains voids or low-density regions. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. Further, the hydrogen concentration in the film of a-like OS is higher than the hydrogen concentration in the films of nc-OS and CAAC-OS.

[0209] Next, the details of the above-mentioned CAC-OS will be described. Further, CAC-OS is related to the material composition.

[0210] [CAC-OS] CAC-OS refers to, for example, a composition in which elements contained in a metal oxide are unevenly distributed, and the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less or an approximate size. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic state or a patch state, and the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less or an approximate size.

[0211] Furthermore, CAC-OS refers to a structure in which its material is separated into a first region and a second region to form a mosaic state and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0212] Further, CAC-OS in In-Ga-Zn oxide refers to the following composition: in a material composition containing In, Ga, Zn, and O, regions (first regions) mainly composed of In and regions (second regions) mainly composed of Ga exist irregularly in a mosaic state. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.

[0213] The CAC-OS can be formed, for example, by sputtering under the condition of not heating the substrate. In the case of forming the CAC-OS by sputtering, as the deposition gas, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas can be used. In addition, the lower the flow ratio of oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow ratio of oxygen gas in the total flow rate of the deposition gas during deposition is set to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0214] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, it exhibits the conductivity of a metal oxide. Therefore, when the first region is distributed in a cloud shape in the metal oxide, high field-effect mobility (μ) can be achieved.

[0215] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0216] Thus, in the case of using the CAC-OS for a transistor, through the complementary action due to the conductivity of the first region and the insulation of the second region, the CAC-OS can have a switching function (a function of controlling on / off). In other words, it has a conductive function in a part of the material of the CAC-OS and an insulating function in another part, and has a semiconductor function in the whole material. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using the CAC-OS for a transistor, a large on-state current (I on )、high field-effect mobility (μ), and good switching operation can be achieved.

[0217] In addition, a transistor using the CAC-OS has high reliability. Therefore, the CAC-OS is most suitable for various semiconductor devices such as display devices.

[0218] Oxide semiconductors have various structures and various properties. The oxide semiconductor of one aspect of the present invention may also include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0219] <<Other semiconductor materials>> As the semiconductor layer of the transistor, a semiconductor material having a bandgap (a semiconductor material that is not a zero-bandgap semiconductor) can also be used. For example, a single-element semiconductor such as silicon or a compound semiconductor such as gallium arsenide can also be used.

[0220] In addition, as the semiconductor layer of the transistor, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide for the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ), etc. By using the above transition metal chalcogenides for the semiconductor layer of the transistor, a semiconductor device with a large on-state current can be provided.

[0221] <Example of manufacturing method of semiconductor device> Use Figures 11A to 21D An example of a manufacturing method of a semiconductor device according to one aspect of the present invention will be described. Here, the case of manufacturing the semiconductor device shown in Figures 1A to 1D will be described as an example.

[0222] In each drawing, A is a plan view. In addition, B in each drawing is a cross-sectional view of a portion along the dotted line A1 - A2 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. C in each drawing is a cross-sectional view of a portion along the dotted line A3 - A4 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. In addition, D in each drawing is a cross-sectional view of a portion along the dotted line A5 - A6 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. For clarity, some constituent elements are omitted in the plan view of A in each drawing.

[0223] Hereinafter, as the insulating material for forming an insulator, the conductive material for forming a conductor, or the semiconductor material for forming a semiconductor, a deposition method such as sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), or ALD method can be appropriately used.

[0224] As the sputtering method, there can be mentioned an RF sputtering method using a high-frequency power source as a sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides by a reactive sputtering method.

[0225] Note that the CVD method can be classified into a plasma-enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0226] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since no plasma is used, the thermal CVD method is a deposition method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0227] As the ALD method, there are adopted a thermal ALD method in which only heat energy is used to react a precursor and a reactant, a PEALD method using a reactant excited by plasma, etc.

[0228] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material, etc. are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have high step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, etc. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferably used in combination with other deposition methods such as the CVD method with a high deposition rate.

[0229] In addition, when using the CVD method, a film of any composition can be deposited by adjusting the flow rate ratio of the source gases. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gases during deposition. When depositing while changing the flow rate ratio of the source gases, since the time required for transferring or adjusting the pressure is not needed, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, sometimes the productivity of the semiconductor device can be improved.

[0230] When using the ALD method, a film of any composition can be deposited by simultaneously introducing different types of precursors. Alternatively, when introducing different types of precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0231] First, a substrate (not shown) is prepared, and an insulator 215 (see Figures 11A to 11D ) is deposited on the substrate. As described above, the insulator 215 can use the same insulator as the stacked film of any one or more of the insulator 282 and the insulator 283. For example, the insulator 215 can be deposited by sputtering, CVD, MBE, PLD, or ALD methods. By using the sputtering method that does not require using a molecule containing hydrogen as the deposition gas, the hydrogen concentration in the insulator 215 can be reduced, so it is preferred.

[0232] Next, an insulator 216 is deposited on the insulator 215. The insulator 216 is preferably deposited by sputtering. By using the sputtering method that does not require using a molecule containing hydrogen as the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, the CVD method, MBE method, PLD method, or ALD method can also be appropriately used. In the present embodiment, silicon oxide is deposited as the insulator 216 by sputtering.

[0233] The insulator 215 and the insulator 216 are preferably continuously deposited without being exposed to the atmosphere. For example, a deposition apparatus using a multi-chamber method can be used. Thereby, the hydrogen in the film can be reduced to deposit the insulator 215 and the insulator 216, and the hydrogen mixing into the film between the respective deposition processes can be reduced.

[0234] Next, an opening reaching the insulator 215 is formed in the insulator 216. When forming the opening, wet etching can be used, but dry etching is preferred for microfabrication. As the insulator 215, an insulator that is preferably used as an etch stop film when etching the insulator 216 to form a groove is selected. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, the insulator 215 is preferably silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0235] After forming the opening, a conductive film that will become the conductor 205a is deposited. The conductive film that will become the conductor 205a preferably includes a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used for the conductive film. In addition, a laminated film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy can be used for the conductive film. The conductive film that will become the conductor 205a can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0236] In the present embodiment, titanium nitride is deposited as the conductive film that will become the conductor 205a. By using the above metal nitride as the lower layer of the conductor 205b, oxidation of the conductor 205b such as the insulator 216 can be suppressed. In addition, even if a metal such as copper that easily diffuses is used as the conductor 205b, outward diffusion of the metal from the conductor 205a can be prevented.

[0237] Next, a conductive film that will become the conductor 205b is deposited. As the conductive film that will become the conductor 205b, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc. can be used. The conductive film can be deposited, for example, by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, etc. In the present embodiment, tungsten is deposited as the conductive film that will become the conductor 205b.

[0238] Next, by performing a CMP process, a part of the conductive film that will become the conductor 205a and the conductive film that will become the conductor 205b is removed to expose the insulator 216 (refer to Figures 11A to 11D ). As a result, only the conductor 205a and the conductor 205b remain in the opening. Note that sometimes a part of the insulator 216 is removed due to this CMP process.

[0239] Next, an insulator 221 is deposited on the insulator 216 and the conductor 205 (refer to Figures 12A to 12D ).

[0240] The insulator 221 may be an insulator having a barrier property against oxygen, hydrogen, and water. The insulator 221 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, etc. In the present embodiment, silicon nitride is deposited as the insulator 221 by the PEALD method.

[0241] Next, an insulator 222 is deposited on the insulator 221 (refer to Figures 12A to 12D ).

[0242] As the insulator 222, an insulator containing one or both of aluminum and hafnium oxides is preferably deposited. As the insulator containing one or both of aluminum and hafnium oxides, for example, alumina, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), etc. is preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing one or both of aluminum and hafnium oxides has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, it is possible to suppress hydrogen and water contained in the structure around the transistor from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0243] The insulator 222 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, hafnium oxide is deposited as the insulator 222 by the ALD method.

[0244] Next, an insulating film is deposited on the insulator 222 and the insulating film is etched to form an insulator 223 (see Figures 12A to 12D ). The insulator 223 is used as a sacrificial layer for forming the insulator 225. As the insulator 223, for example, an insulator that can be used for the insulator 216 can be used.

[0245] The insulator 223 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, silicon oxide is deposited as the insulator 223 by the sputtering method.

[0246] The insulator 223 can be processed into an island shape by photolithography. This processing can be performed by a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0247] As Figure 12C and Figure 12D shown, a structure in which the side surface of the insulator 223 is perpendicular or substantially perpendicular to the top surface of the insulator 222 can also be adopted. By adopting this structure, miniaturization and high density can be achieved when multiple transistors are provided.

[0248] In addition, heat treatment can also be performed before depositing the insulator 223. This heat treatment can also be performed under reduced pressure, and the insulator 223 is continuously deposited in a manner not exposed to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration of the insulator 222 can be reduced. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 due to this heat treatment. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is set to 250°C.

[0249] Next, an insulating film 225f that will become the insulator 225 is deposited so as to cover the insulator 223 (see Figures 13A to 13D ). The insulating film 225f is an insulating film that will become the insulator 225 in a later process, and the above-mentioned insulator can be used. The insulating film 225f can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD methods.

[0250] Since the insulating film 225f is deposited along the insulator 223, high coverage is preferred. Therefore, the insulating film 225f is preferably deposited by an ALD method or the like having high coverage. In addition, since the insulator 225 preferably has a high aspect ratio, it is preferable that the thickness of the insulating film 225f is small. Therefore, it is preferable to use the ALD method capable of adjusting the thickness to a smaller value to deposit the insulating film 225f. For example, as the insulating film 225f, hafnium oxide is preferably deposited by thermal ALD. By depositing the insulating film 225f in this way, the insulating film 225f is formed so as to contact the top surface and the side surface of the insulator 223.

[0251] Next, a part of the insulating film 225f is removed by anisotropic etching, and then the insulator 223 is removed (see Figures 14A to 14D ). Thereby, an insulator 225 having a high aspect ratio can be formed. By using the insulator 225, the channel width of the transistor 200 can be increased without increasing the occupied area, and thus the on-state current, field-effect mobility, and frequency characteristics of the transistor 200 can be improved. In addition, the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupied area, thereby improving the on-state current, field-effect mobility, and frequency characteristics of the transistor 200.

[0252] As shown in Figures 14A to 14D , by forming two insulators 225, the distance between the two insulators 225 can be set according to the size of the insulator 223. Thereby, the distance between the insulators 225 can be shortened, the occupied area of the transistors 200a and 200b can be reduced, and thus high integration of the semiconductor device and the memory device can be achieved. Thereby, the storage capacity of the memory device can be increased.

[0253] The anisotropic etching of the insulating film 225f preferably uses a dry etching method.

[0254] As the etching gas for dry etching treatment, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. As the etching gas, for example, C 4 F 6 gas, C 5 F 6 gas, C 4 F 8 gas, CF4 Gas, SF 6 Gas, CHF 3 Gas, CH 2 F 2 Gas, Cl 2 Gas, BCl 3 Gas, SiCl 4 and BBr 3 One or more mixed gases among gases such as these. Additionally, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas, etc. can be appropriately added to the above etching gases. Additionally, depending on the object to be dry-etched, a gas that does not contain halogen gas but contains hydrocarbon gas or hydrogen gas can also be used as the etching gas. As the hydrocarbon used for the etching gas, methane (CH 4 )), ethane (C 2 H 6 ), propane (C 3 H 8 ), butane (C 4 H 10 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), acetylene (C 2 H 2 ), and propyne (C 3 H 4 ) can be used, one or more of them. The etching conditions can be appropriately set according to the etching object.

[0255] As a dry-etching device, for example, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. A capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Or, a structure in which different multiple high-frequency voltages are applied to one of the parallel plate electrodes can also be adopted. Or, a structure in which high-frequency voltages with the same frequency are applied to each of the parallel plate electrodes can also be adopted. Or, a structure in which high-frequency voltages with different frequencies are applied to each of the parallel plate electrodes can also be adopted. Or, a dry-etching device having a high-density plasma source can be used. For example, as a dry-etching device having a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device, etc. can be used. The etching device can be appropriately set according to the etching object.

[0256] For example, when hafnium oxide is used for the insulating film 225f, C 4 F8 , a mixed gas of H 2 and Ar.

[0257] In addition, in the above processing, the insulator 223 can be removed by a dry etching method or a wet etching method. For example, the insulator 223 can be removed by a wet etching method.

[0258] In addition, when the insulator 225 is formed by anisotropic etching, it is formed in a sidewall shape in contact with the side surface of the insulator 223. That is, a circumferential insulator 225 is formed around the insulator 223. When manufacturing a semiconductor device while maintaining the circumferential shape of the insulator 225, as Figures 5A to 5D shown, the insulator 225 is integrated between the transistor 200a and the transistor 200b.

[0259] Here, in the structure shown in FIG. 14, the unnecessary part of the semiconductor device structure in the sidewall-shaped insulator is removed, thereby forming the insulator 225. When forming such an insulator 225, the unnecessary part of the insulator 225 can also be etched before anisotropically etching the insulating film 225f.

[0260] Next, an oxide film 230af is deposited on the insulator 222 and the insulator 225, and an oxide film 230bf is deposited on the oxide film 230af (see Figures 15A to 15D ). As the oxide film 230af, a metal oxide corresponding to the above-mentioned oxide 230a can be used, and as the oxide film 230bf, a metal oxide corresponding to the above-mentioned oxide 230b can be used. It is preferable to continuously deposit the oxide film 230af and the oxide film 230bf without being exposed to the atmospheric environment. By depositing without being exposed to the atmosphere, since impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230af and the oxide film 230bf, the interface or the vicinity of the interface between the oxide film 230af and the oxide film 230bf can be kept clean.

[0261] The oxide film 230af and the oxide film 230bf can each be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0262] The deposition of the oxide film 230af and the oxide film 230bf is preferably carried out by the ALD method with high coverage. By using the ALD method, the oxide film 230af and the oxide film 230bf can be deposited on the side surfaces of the insulator 225 with high coverage. Thus, in the transistor 200, channel formation regions can also be provided on the side surfaces of the A3 side and the A4 side of the insulator 225, thereby increasing the channel width of the transistor 200. As a result, the field-effect mobility, on-state current, and frequency characteristics of the transistor 200 can be improved.

[0263] Here, in the ALD method, the composition of the resulting film can be controlled according to the introduction amount of the source gas. For example, in the ALD method, by adjusting the introduction amount of the source gas, the number of introductions (also referred to as the number of pulses), and the time required for one pulse (also referred to as the pulse time), etc., oxide films 230af and 230bf with arbitrary compositions can be deposited. Further, for example, when using the ALD method, oxide films 230af and 230bf with continuously varying compositions can be deposited by changing the source gas while performing the deposition. When depositing while changing the source gas, since the time required for transferring and adjusting the pressure is not needed, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, sometimes the productivity of the semiconductor device can be improved.

[0264] As the oxide film 230af, a metal oxide layer with In:Ga:Zn = 1:3:2 [atomic ratio], a metal oxide layer with In:Ga:Zn = 1:3:4 [atomic ratio], or a metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio] can be deposited using the ALD method. Additionally, as the oxide film 230bf, a metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio] or a metal oxide layer with In:Zn = 4:1 [atomic ratio] can be deposited using the ALD method. Further, the oxide films 230af and 230bf can also have a laminated structure of the above metal oxide layers. For example, the oxide film 230bf can also be a laminated film in which a metal oxide layer with In:Zn = 4:1 [atomic ratio] and a metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio] are laminated in sequence. Additionally, in the above oxide film 230bf, a metal oxide layer with In:Ga:Zn = 1:3:2 [atomic ratio] or a metal oxide layer with In:Ga:Zn = 1:3:4 [atomic ratio] can be used instead of the metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio].

[0265] When depositing the oxide films 230af and 230bf, the sputtering method can also be used. For example, when depositing the oxide films 230af and 230bf using the sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Further, when depositing the above oxide films using the sputtering method, an In-M-Zn oxide target, etc., can be used.

[0266] In the case of forming the oxide film 230bf by sputtering, an oxygen-excess type oxide semiconductor can be formed by performing deposition under the condition that the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less. Using the oxygen-excess type oxide semiconductor for the transistor in the channel formation region can obtain relatively high reliability. Note that one aspect of the present invention is not limited to this. In the case of forming the oxide film 230bf by sputtering, when the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor is formed. Using the oxygen-deficient type oxide semiconductor for the transistor in the channel formation region can have a high field-effect mobility. In addition, by performing deposition while heating the substrate, the crystallinity of the oxide film can be improved.

[0267] In the present embodiment, the oxide film 230af is deposited by sputtering using an oxide target of In:Ga:Zn = 1:3:2 [atomic ratio], an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1 [atomic ratio], or an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio]. In addition, the oxide film 230bf is deposited by sputtering using an oxide target of In:Ga:Zn = 1:1:1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio], an oxide target of In:Ga:Zn = 4:2:4.1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:2 [atomic ratio], or an oxide target of In:Zn = 4:1 [atomic ratio]. Each oxide film is preferably formed by appropriately selecting the deposition conditions and the atomic ratio according to the required characteristics of the oxides 230a and 230b.

[0268] In addition, for example, the oxide film 230af can also be deposited by sputtering, and the oxide film 230bf can also be deposited by ALD. Here, one or both of the oxide film 230af and the oxide film 230bf may adopt a stacked structure. For example, the oxide film 230af can be deposited by sputtering using any one of an oxide target of In:Ga:Zn = 1:1:1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio], an oxide target of In:Ga:Zn = 1:3:2 [atomic ratio], or an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio].

[0269] In addition, as the oxide film 230bf, the above-described metal oxide layer deposited by ALD method can be used. For example, as the oxide film 230bf, a stacked film in which a metal oxide layer with In:Zn = 4:1 [atomic ratio] and a metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio] are sequentially stacked can be deposited.

[0270] The crystallinity can be improved by depositing the oxide film 230af by sputtering method. For example, by first improving the crystallinity of the oxide film 230af and then depositing the oxide film 230bf on the oxide film 230af, part or all of the oxide film 230bf can be crystallized. That is to say, by improving the crystallinity of the oxide film 230af, the crystallinity of the oxide film 230bf can also be improved. For example, when the oxide film 230af is an oxide semiconductor film with CAAC structure, an oxide semiconductor with CAAC structure can also be used as the oxide film 230bf formed on the oxide film 230af.

[0271] In addition, by depositing the oxide film 230bf by ALD method, a thinner film can be deposited with high controllability. Thereby, the oxide film 230bf can have a smaller thickness according to the design. By using the above-described oxide film 230af and oxide film 230bf, the electrical characteristics and reliability of the transistor 200 can be improved.

[0272] Note that it is preferable to deposit the oxide film 230af and oxide film 230bf in a manner not exposed to the atmosphere. For example, it is preferable to use a deposition apparatus with a multi-chamber method. Thereby, the hydrogen mixing into the oxide film 230af and oxide film 230bf during each deposition process can be reduced.

[0273] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which polycrystallization does not occur in the oxide film 230af and oxide film 230bf. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher and 650°C or lower, 600°C or lower, or 550°C or lower.

[0274] The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Or, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere first, and then in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to replenish the oxygen that has escaped.

[0275] In addition, the gas used in the above heat treatment is preferably purified to a high purity. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and still more preferably 0.05 ppb or less. By performing the heat treatment using the purified gas, it is possible to prevent moisture and the like from being absorbed by the oxide film 230af, the oxide film 230bf, and the like as much as possible.

[0276] In the present embodiment, as the heat treatment, a treatment is performed for 1 hour under the conditions of a flow rate ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 450°C. By such a heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide film 230af and the oxide film 230bf is improved, and a denser structure with a higher density can be achieved. Therefore, the crystalline region in the oxide film 230af and the oxide film 230bf can be increased, and the in-plane non-uniformity of the crystalline region in the oxide film 230af and the oxide film 230bf can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0277] In addition, by performing the heat treatment, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf is absorbed by the insulator 225 and the insulator 222. In other words, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 225 and the insulator 222. Therefore, although the hydrogen concentration in the insulator 225 and the insulator 222 increases, the hydrogen concentration in the insulator 216, the oxide film 230af, and the oxide film 230bf all decreases. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 due to this heat treatment.

[0278] In particular, the oxide film 230af and the oxide film 230bf (the subsequent oxide 230a and oxide 230b) are used as the channel formation region of the transistor 200. The transistor 200 formed using the oxide film 230af and the oxide film 230bf with a reduced hydrogen concentration has excellent reliability, and thus is preferred.

[0279] Next, a conductive film 242f is deposited on the oxide film 230bf (refer to Figures 15A to 15D)。It is sufficient to use a conductor corresponding to the above-mentioned conductors 242a and 242b as the conductive film 242f. After depositing the oxide film 230bf, the conductive film 242f is deposited on the oxide film 230bf in contact therewith without an etching process or the like, whereby the top surface of the oxide film 230bf can be protected by the conductive film 242f. Thus, since the diffusion of impurities into the oxide 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0280] The conductive film 242f can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using the ALD method, the conductive film 242f can be deposited on the side surface of the insulator 225 with high coverage. For example, tantalum nitride can be deposited as the conductive film 242f by the ALD method. Thus, by depositing the conductive film 242f with high coverage, the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupied area. Thereby, the on-state current and frequency characteristics of the transistor 200 can be improved.

[0281] Next, the oxide film 230af, the oxide film 230bf, and the conductive film 242f are processed into an island shape by a photolithography method, thereby forming the oxide 230a, the oxide 230b, and the conductor 242A (refer to Figures 16A to 16D ).

[0282] Thereby, the oxide 230a, the oxide 230b, and the conductor 242A forming the transistor 200a are separated from the oxide 230a, the oxide 230b, and the conductor 242A forming the transistor 200b. At this time, it is preferable that the oxide 230a, the oxide 230b, and the conductor 242A are formed so as to cover the insulator 225 forming the transistor 200a and the insulator 225 forming the transistor 200b, respectively.

[0283] The above processing can be performed by a dry etching method or a wet etching method. The processing using the dry etching method is suitable for microfabrication. The conditions of the dry etching method and the dry etching apparatus can be referred to the previous description. In addition, the oxide film 230af, the oxide film 230bf, and the conductive film 242f can be processed under different conditions.

[0284] Here, it is preferable to process the oxide 230a, the oxide 230b, and the conductor 242A into an island shape all at once. Here, the side end portions of two or more of the oxide 230a, the oxide 230b, and the conductor 242A are aligned or substantially aligned with each other. By adopting this structure, the number of processes of the semiconductor device according to one aspect of the present invention can be reduced. Thereby, a manufacturing method of a semiconductor device with high productivity can be provided.

[0285] At least a portion of the oxide 230a, the oxide 230b, and the conductor 242A is formed to overlap with the conductor 205. In a region where the insulator 222 does not overlap with the oxide 230a, the oxide 230b, and the conductor 242A, the insulator 222 is exposed.

[0286] like Figure 16B As shown, a structure may be adopted in which the side surfaces of the oxide 230a, the oxide 230b, and the conductor 242A are perpendicular or substantially perpendicular to the top surface of the insulator 222. By adopting such a structure, it is possible to realize a reduction in area and a high density when arranging a plurality of transistors.

[0287] However, the structure is not limited to the above, and the side surfaces of the oxide 230a, the oxide 230b, and the conductor 242A may also have a tapered shape. The taper angle of the side surfaces of the oxide 230a, the oxide 230b, and the conductor 242A may be, for example, 60° or more and less than 90°. In this way, by having the side surfaces have a tapered shape, the coverage of the insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0288] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. In addition, when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0289] The resist mask that is unnecessary after processing can be removed by dry etching treatment such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0290] Furthermore, a hard mask made of an insulator or a conductor can also be used under the resist mask. When using a hard mask, an insulating film or a conductive film that becomes the hard mask material can be formed on the conductive film 242f, and a resist mask can be formed thereon. Then, the hard mask material is etched to form a hard mask with a desired shape. The etching of the conductive film 242f or the like can be performed after removing the resist mask, or can be performed without removing the resist mask. In the latter case, the resist mask sometimes disappears during etching. The hard mask can be removed by etching after the etching of the oxide film 230bf or the like. On the other hand, when the hard mask material does not affect the subsequent processes or can be used in the subsequent processes, it is not necessarily required to remove the hard mask.

[0291] In addition, an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film can also be deposited between the workpiece and the resist mask. By using the SOC film and the SOG film as masks, the adhesion between the workpiece and the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, lithography can be performed by sequentially depositing an SOC film, an SOG film, and a resist mask on the workpiece.

[0292] In addition, in Figures 16A to 16D the process shown, the conductive film 242f can also be divided into a conductor 242a and a conductor 242b, and the oxide films 230af and 230bf are anisotropically etched using the mask used when dividing the conductor 242a and the conductor 242b. By adopting such a structure, as Figures 7A to 7D and Figure 8 shown, the oxides 230a and 230b can be formed in a sidewall shape for the insulator 225 in a region that does not overlap with the conductor 242a and the conductor 242b.

[0293] Next, an insulator 275 is deposited to cover the oxides 230a, 230b, and the conductor 242A, and an insulator 280 is deposited on the insulator 275 (see Figures 17A to 17D ). As the insulator 275 and the insulator 280, the above-mentioned insulators can be used.

[0294] Here, the insulator 275 preferably contacts the top surface of the insulator 222.

[0295] As the insulator 280, it is preferable to form an insulating film that will become the insulator 280 and perform a CMP process on the insulating film to form an insulator with a flat top surface. In addition, silicon nitride can be deposited on the insulator 280 by, for example, sputtering until it reaches the insulator 280, and the silicon nitride is subjected to a CMP process.

[0296] The insulator 275 and the insulator 280 can each be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD methods.

[0297] The insulator 275 is preferably an insulator having a function of suppressing oxygen permeation. For example, silicon nitride is preferably deposited on the insulator 275 by the PEALD method. In addition, aluminum oxide is preferably deposited on the insulator 275 by sputtering and silicon nitride is deposited thereon by the PEALD method. When the insulator 275 has the above structure, the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0298] In this way, the oxide 230a, the oxide 230b, and the conductor 242A can be covered by the insulator 275 having the function of suppressing oxygen diffusion. Thereby, the direct diffusion of oxygen from the insulator 280 or the like into the oxide 230a, the oxide 230b, and the conductor 242A in the subsequent process can be reduced.

[0299] In addition, silicon oxide is preferably deposited on the insulator 280 by sputtering. By depositing the insulating film that will become the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require a hydrogen-containing molecule as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, heat treatment can also be performed before depositing the insulating film. This heat treatment can also be performed under reduced pressure, and the insulating film can be continuously deposited in a manner not exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 or the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. This heat treatment can adopt the conditions of the above heat treatment.

[0300] Next, the conductor 242A, the insulator 275, and the insulator 280 are processed by photolithography to form openings reaching the oxide 230b and the insulator 222 (see Figures 18A to 18D ). Here, the conductor 242A is divided to form the conductor 242a and the conductor 242b. The above openings are formed in the region where the oxide 230b overlaps with the conductor 205.

[0301] In photolithography, the above method can be appropriately used. In order to process the opening of the insulator 280 into a fine size, a photolithography method using light or an electron beam with a short wavelength such as EUV light is preferably adopted.

[0302] The above processing is preferably performed by a dry etching method. In the dry etching method, anisotropic etching can be performed, so the dry etching method is suitable for forming an opening with a high aspect ratio. Note that the dry etching method conditions and the dry etching apparatus can refer to the above content.

[0303] After the processing of the conductor 242A, ashing treatment using oxygen plasma can also be performed. By performing such oxygen plasma treatment, impurities generated in the above-described etching treatment and diffused into the oxide 230 or the like can be removed. Examples of such impurities include impurities resulting from components in the workpiece due to the above-described etching treatment and impurities resulting from components in the gas used in the etching or the like. For example, chlorine, fluorine, tantalum, silicon, hafnium, etc. can be cited. In particular, as shown in the above-described etching treatment, when chlorine gas is used in the processing of the conductor 242A, the oxide 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine attached to the oxide 230. By removing the impurities attached to the oxide 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0304] In order to remove impurities and the like attached to the surface of the oxide 230b in the above-described etching step, a washing treatment can also be performed. As the washing method, there are wet washing using a washing liquid or the like (which can also be called wet etching treatment), plasma treatment using plasma, washing using heat treatment, etc., and the above-described washing can be appropriately combined. Note that the above-described groove portion may become deeper by performing this washing treatment.

[0305] As the wet washing, an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, pure water, carbonated water, or the like can be used. Alternatively, ultrasonic washing can be performed using the above-described aqueous solution, pure water, or carbonated water. In addition, the above-described washing can be appropriately combined.

[0306] Note that in this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of this aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, more preferably 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01 ppm or more and 100 ppm or less, more preferably 0.1 ppm or more and 10 ppm or less.

[0307] In addition, as the ultrasonic washing, a frequency of 200 kHz or more is preferably used, more preferably 900 kHz or more. By using this frequency, the damage to the oxide 230b or the like can be reduced.

[0308] In addition, the above-described washing treatment can be performed multiple times, and the washing liquid can be changed for each washing treatment. For example, as the first washing treatment, a treatment using dilute hydrofluoric acid or dilute ammonia water can be performed, and as the second washing treatment, a treatment using pure water or carbonated water can be performed.

[0309] As the above-described washing treatment, in the present embodiment, wet washing is performed using dilute ammonia water. By performing this washing treatment, impurities adhering to the surfaces of the oxides 230a, 230b, etc. or diffused into their interiors can be removed. Also, the crystallinity of the oxides 230a, 230b, etc. can be improved.

[0310] Heat treatment is preferably performed after the above-described etching or the above-described washing. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas, inert gas, or an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more. It is preferable to perform this heat treatment in an oxygen-containing atmosphere. For example, it is preferable to perform a treatment at a temperature of 350°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. Thereby, oxygen is supplied to the oxides 230a and 230b, and thus oxygen vacancies can be reduced. In addition, by performing the above-described heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the hydrogen remaining in the oxides 230a and 230b reacts with the supplied oxygen, and the hydrogen can be removed in the form of H 2 O (dehydration). Thereby, the recombination of the hydrogen remaining in the oxides 230a and 230b with the oxygen vacancies to form V O H can be suppressed. Thereby, the electrical characteristics of the transistor provided with the oxide 230 can be improved and the reliability can be enhanced. In addition, the non-uniformity of the electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed. The above-described heat treatment can also be performed in a reduced-pressure state. Alternatively, heat treatment can be performed in an oxygen atmosphere and then heat treatment can be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.

[0311] When heat treatment is performed in a state where the conductors 242a and 242b are in contact with the oxide 230b, the sheet resistance of the regions of the oxide 230b overlapping with the conductor 242a and the regions of the oxide 230b overlapping with the conductor 242b sometimes decreases. Also, sometimes the carrier concentration increases. Therefore, the regions of the oxide 230b overlapping with the conductor 242a and the regions of the oxide 230b overlapping with the conductor 242b can be self-aligned to have a low resistance.

[0312] Next, an insulating film 250A that will become the insulator 250 is deposited so as to fill an opening formed in the insulator 280, etc. (see Figures 19A to 19D ). Here, the insulating film 250A is in contact with the insulator 280, the insulator 275, the conductors 242a, 242b, the insulator 222, the oxides 230a, and 230b.

[0313] The insulating film 250A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably deposited by the ALD method. Similar to the above-described insulator 250, the insulating film 250A is preferably formed thin, and it is necessary to suppress thickness non-uniformity to a small value. In this regard, the ALD method is a deposition method in which a precursor and a reactant (for example, an oxidizing agent, etc.) are alternately introduced, and since the thickness can be adjusted according to the number of times of repeating this cycle, the thickness can be precisely adjusted. In addition, the insulating film 250A needs to be deposited on the bottom surface and the side surface of the above opening with high coverage. By using the ALD method, atomic layers of each layer can be deposited on the bottom surface and the side surface of the above opening, so that the insulating film 250A can be formed with high coverage in the opening.

[0314] In addition, when depositing the insulating film 250A by the ALD method, ozone (O 3 ), oxygen (O 2 ), water (H 2 O), etc. can be used as the oxidizing agent. By using ozone (O 3 ) or oxygen (O 2 ) that does not contain hydrogen as the oxidizing agent, the hydrogen diffusing into the oxide 230b can be reduced.

[0315] The insulator 250 can adopt a stacked structure as shown in FIG. 2 etc. For example, as Figure 2A shown, the insulator 250 can adopt a stacked structure of insulator 250a to insulator 250d. In this case, aluminum oxide can be deposited by thermal ALD method as the insulator 250a, silicon oxide can be deposited by PEALD method as the insulator 250b, hafnium oxide can be deposited by thermal ALD method as the insulator 250c, and silicon nitride can be deposited by PEALD method as the insulator 250d.

[0316] In addition, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after depositing the insulating film 250A or after depositing any insulator constituting the insulating film 250A. Here, the microwave treatment is, for example, a treatment using a device including a power source that generates high-density plasma with microwaves. In addition, in this specification etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0317] Microwave treatment preferably uses, for example, a microwave treatment apparatus including a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment apparatus is preferably set to 300 MHz or higher and 300 GHz or lower, more preferably 2.4 GHz or higher and 2.5 GHz or lower, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source for applying microwaves in the microwave treatment apparatus is preferably 1000 W or higher and 10000 W or lower, more preferably 2000 W or higher and 5000 W or lower. In addition, the microwave treatment apparatus may also include a power source for applying RF to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated from the high-density plasma can be efficiently introduced into the oxide 230b.

[0318] In addition, the above microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or higher and 1000 Pa or lower, more preferably 300 Pa or higher and 700 Pa or lower. In addition, the treatment temperature is preferably 750 °C or lower, more preferably 500 °C or lower, and can be, for example, about 250 °C. In addition, heat treatment can also be continuously performed in a manner that does not expose to external air after oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100 °C or higher and 750 °C or lower, more preferably 300 °C or higher and 500 °C or lower.

[0319] In addition, for example, the above microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O 2 / (O 2 +Ar)) is greater than 0% and 100% or less. Preferably, the oxygen flow ratio (O 2 / (O 2 +Ar)) is greater than 0% and 50% or less. More preferably, the oxygen flow ratio (O 2 / (O 2 +Ar)) is 10% or higher and 40% or less. Further preferably, the oxygen flow ratio (O 2 / (O 2 +Ar)) is 10% or higher and 30% or less. Thus, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide 230b can be reduced. In addition, by preventing excessive introduction of oxygen into the processing chamber during microwave treatment, excessive reduction of the carrier concentration in the oxide 230b can be prevented.

[0320] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using high frequencies such as microwaves or RF, and the oxygen plasma can act on the region between the conductor 242a and the conductor 242b of the oxide 230b. Through the action of plasma, microwaves, etc., the V O H in this region can be separated into oxygen vacancies and hydrogen, and hydrogen can be removed from this region. Here, whenFigure 2A When the structure shown in etc. is used, as the insulator 250a, an insulating film having a function of capturing or fixing hydrogen (for example, alumina, etc.) is preferably used. By adopting the above structure, the insulator 250a can capture or fix hydrogen generated by microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thereby, the oxygen vacancies and V in the channel formation region can be reduced. O H to reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and thereby the carrier concentration can be reduced.

[0321] As the oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0322] In addition, impurities such as carbon in the oxide 230b can be removed by microwave treatment. By removing the carbon of the impurities in the oxide 230b, the crystallinity of the oxide 230b can be improved. Thereby, the oxide 230b can be formed into CAAC-OS. In particular, when the oxide 230b is deposited by the ALD method, the carbon contained in the precursor sometimes enters the oxide 230b, so it is preferable to remove the carbon by microwave treatment.

[0323] On the other hand, the oxide 230b has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as a shielding film for protecting against the action of high frequencies such as microwaves and RF or oxygen plasma in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0324] The conductors 242a and 242b shield the action of high frequencies such as microwaves or RF and oxygen plasma, so they do not act on the region of the oxide 230b overlapping with any one of the conductors 242a and 242b. Thereby, a decrease in V and an excessive supply of oxygen do not occur in the source region and the drain region by microwave treatment, so a decrease in the carrier concentration can be prevented. O H and an excessive supply of oxygen, so a decrease in the carrier concentration can be prevented.

[0325] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor.O By H, the channel formation region becomes an i-type or substantially an i-type. Moreover, it is possible to suppress an excessive supply of oxygen to a region serving as a source region or a drain region and maintain the conductivity (state of a low-resistance region) before the microwave treatment. Thereby, it is possible to suppress variations in electrical characteristics of the transistor and suppress non-uniformity in electrical characteristics of transistors within the substrate surface.

[0326] In addition, in the microwave treatment, sometimes thermal energy is directly transferred to the oxide 230b due to the electromagnetic interaction between microwaves and molecules in the oxide 230b. Sometimes the oxide 230b is heated by this thermal energy. Sometimes this heat treatment is called microwave annealing. By performing the microwave treatment in an oxygen-containing atmosphere, sometimes an effect equivalent to oxygen annealing can be obtained. In addition, it is considered that when the oxide 230b contains hydrogen, the above thermal energy is transferred to the hydrogen in the oxide 230b and the activated hydrogen is released from the oxide 230b.

[0327] Furthermore, by performing the microwave treatment, the film quality of the insulator 250 can be modified, and diffusion of hydrogen, water, impurities, etc. can be suppressed. Thereby, it is possible to suppress diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 due to post-processes such as deposition of a conductive film that will become the conductor 260 or post-treatments such as heat treatment. Thus, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0328] In addition, heat treatment can also be performed while maintaining a reduced-pressure state after the microwave treatment. By performing such treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. In addition, a part of the hydrogen is sometimes gettered by the conductors 242a and 242b. In addition, the step of performing heat treatment while maintaining a reduced-pressure state after the microwave treatment can also be repeated. By repeating the heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be further efficiently removed. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. The above microwave treatment, i.e., microwave annealing, can also serve as this heat treatment. When the oxide 230b etc. are sufficiently heated by microwave annealing, this heat treatment may not be performed.

[0329] When the insulator 250 has a stacked structure of the insulators 250a to 250d, it is preferable to perform the microwave treatment after depositing the insulator 250b. Furthermore, the microwave treatment can also be performed again after depositing the insulator 250c. Thus, the microwave treatment in an oxygen-containing atmosphere can also be performed multiple times (at least two or more times).

[0330] Next, a conductive film 260A that will become the conductor 260a and a conductive film 260B that will become the conductor 260b are sequentially deposited (refer to Figures 20A to 20D)。The conductive films 260A and 260B can be deposited, for example, by sputtering, CVD, MBE, PLD, electroplating, or ALD methods. In the present embodiment, titanium nitride is deposited as the conductive film 260A by ALD, and tungsten is deposited as the conductive film 260B by CVD.

[0331] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP processing until the insulator 280 is exposed. That is, a part of the insulating film 250A, the conductive film 260A, and the conductive film 260B that is exposed from the above opening is removed. Thereby, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see Figures 21A to 21D ).

[0332] Thereby, the insulator 250 is disposed so as to be in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the oxide 230b, the oxide 230a, and the insulator 222 in the above opening. In addition, the conductor 260 is disposed so as to be embedded in the above opening with the insulator 250 interposed therebetween. Thereby, the transistor 200 is formed.

[0333] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD methods. The insulator 282 is preferably deposited by sputtering. By using a sputtering method that does not require a hydrogen-containing molecule as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0334] In addition, by depositing the insulator 282 in an oxygen-containing atmosphere by sputtering, oxygen can be added to the insulator 280 while deposition is being performed. Thereby, the insulator 280 can contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate. By depositing the insulator 282 in this way, oxygen can be diffused from the insulator 280 through the insulator 250 into the oxide 230b, and thereby an appropriate amount of oxygen can be supplied to the oxide 230b. In addition, by providing the insulator 250a in the insulator 250, excessive oxygen supply to the insulator 250 can be prevented, and the vicinity of the conductors 242a and 242b in the insulator 250 can be prevented from being over-oxidized.

[0335] In the present embodiment, alumina is deposited by sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 282. The amount of oxygen injected into the lower layer of the insulator 282 can be controlled according to the magnitude of the RF power applied to the substrate in the sputtering method. For example, the smaller the RF power, the less the amount of oxygen injected into the lower layer of the insulator 282, and this amount of oxygen is likely to saturate even when the thickness of the insulator 282 is small. In addition, the larger the RF power, the more the amount of oxygen injected into the lower layer of the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Alternatively, the insulator 282 having a two-layer stacked structure may be deposited. At this time, for example, the lower layer of the insulator 282 is deposited without applying RF power to the substrate, and the upper layer of the insulator 282 is deposited by applying RF power to the substrate.

[0336] In addition, the frequency of the RF is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the frequency of the RF, the more the damage to the substrate can be reduced.

[0337] Furthermore, heat treatment may be performed before depositing the insulator 282. This heat treatment may also be performed under reduced pressure, and the insulator 282 is continuously deposited in a manner not exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed, and the moisture concentration and hydrogen concentration in the insulator 280 can be reduced. The temperature of the heat treatment is preferably 100 °C or more and 400 °C or less. In the present embodiment, the temperature of the heat treatment is set to 250 °C.

[0338] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited, for example, by sputtering, CVD method, MBE method, PLD method, or ALD method. The insulator 283 is preferably deposited by sputtering. By using the sputtering method that does not require molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In the present embodiment, silicon nitride is deposited as the insulator 283 by sputtering.

[0339] Here, it is preferable to continuously deposit the insulator 282 and the insulator 283 without being exposed to the atmospheric environment. By depositing without being exposed to the atmosphere, since impurities or moisture from the atmospheric environment can be prevented from adhering to the insulator 282 and the insulator 283, the interface between the insulator 282 and the insulator 283 or the vicinity of the interface can be kept clean.

[0340] In addition, heat treatment may be performed after depositing the insulator 283. The temperature of this heat treatment is preferably 100°C or higher and 400°C or lower. By performing the heat treatment, hydrogen in the insulator 280, the insulator 250, and the oxide 230 is absorbed by the insulator 282. In other words, hydrogen in the insulator 280, the insulator 250, and the oxide 230 diffuses into the insulator 282. Therefore, although the hydrogen concentration of the insulator 282 becomes high, the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide 230 all become low. In addition, when the insulator 283 is provided in contact with the top surface of the insulator 282, it is possible to prevent impurities such as moisture or hydrogen from entering from above the insulator 283 during this heat treatment. In addition, by performing the heat treatment, hydrogen in the oxide 230 is absorbed by the insulator 222. In other words, hydrogen in the oxide 230 diffuses into the insulator 222. Therefore, although the hydrogen concentration of the insulator 222 becomes high, the hydrogen concentration of the oxide 230 becomes low. By providing the insulator 221 in contact with the bottom surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 during this heat treatment.

[0341] Next, openings reaching the conductor 242a and openings reaching the conductor 242b are formed in the insulator 275, the insulator 280, the insulator 282, and the insulator 283 (see Figures 1A to 1D ). The formation of these openings can be carried out by photolithography. In addition, although Figure 1A the shape of the opening is circular in plan view, it is not limited to this. For example, in plan view, the opening may also have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are rounded.

[0342] Next, an insulating film that will become the insulator 241 is deposited, and this insulating film is anisotropically etched to form the insulator 241a in the opening reaching the conductor 242a and the insulator 241b in the opening reaching the conductor 242b (see Figures 1A to 1D ). The insulating film that will become the insulator 241 can be deposited by sputtering, CVD, MBE, PLD, or ALD. As the insulating film that will become the insulator 241, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, it is preferable to deposit aluminum oxide by ALD and deposit silicon nitride thereon by PEALD. Silicon nitride has a high barrier property against hydrogen, so it is preferable.

[0343] In addition, as the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method or the like can be employed, for example. By providing the insulator 241 on the sidewall portion of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. In addition, diffusion of impurities such as water and hydrogen in the insulator 280 or the like into the conductor 240a and the conductor 240b can be prevented.

[0344] Next, a conductive film that will become the conductor 240a and the conductor 240b is deposited. The conductive film that will become the conductor 240a and the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, it can be a stack of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The conductive film that will become the conductor 240a and the conductor 240b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0345] Next, by performing a CMP process, a part of the conductive film that will become the conductor 240a and the conductor 240b is removed to expose the top surface of the insulator 283. As a result, only the conductive film remains in the opening, and thus the conductor 240a and the conductor 240b with a flat top surface can be formed (see Figures 1A to 1D ). Note that sometimes a part of the top surface of the insulator 283 is removed by this CMP process.

[0346] As described above, by providing the conductor 240a in contact with the conductor 242a, the conductor 240a that serves as one of the source and drain of the transistor 200 can be electrically connected to the wiring. In addition, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b that serves as the other of the source and drain of the transistor 200 can be electrically connected to the wiring.

[0347] In addition, a conductive film serving as wiring or a conductive film serving as a plug can be formed on the conductor 240a and the conductor 240b.

[0348] Through the above processes, the semiconductor device shown in FIG. 1 can be manufactured.

[0349] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0350] (Embodiment 2) In this embodiment, a comparison between the OS transistor shown in the above embodiment and a transistor including silicon in the channel formation region (also referred to as a Si transistor) will be described.

[0351] [OS Transistor] Preferably, an oxide semiconductor with a low carrier concentration is used for the OS transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm -3 or less, preferably less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , further preferably less than 1×10 13 cm -3 , still further preferably less than 1×10 10 cm -3 , and 1×10 -9 cm -3 or more. When aiming to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to lower the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0352] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a low density of defect states, it sometimes has a low density of trap states. In addition, it takes a long time for the charge trapped in the trap states of the oxide semiconductor to disappear, and it sometimes behaves like a fixed charge. Therefore, the electrical characteristics of a transistor formed in an oxide semiconductor with a high density of trap states are sometimes unstable.

[0353] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, etc. Note that impurities in the oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0354] In the OS transistor, when impurities and oxygen vacancies exist in the channel formation region of the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may decrease. In addition, in the OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), and electrons that can become carriers may be generated. In addition, when V OAt time H, sometimes the donor concentration in the channel formation region increases. As the donor concentration in the channel formation region increases, sometimes the threshold voltage becomes non-uniform. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor has normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows in the transistor). Thus, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0355] In addition, the bandgap of the oxide semiconductor is preferably larger than the bandgap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a larger bandgap than silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0356] For example, in Si transistors, as the miniaturization of transistors progresses, the short channel effect (Short Channel Effect: also referred to as SCE) appears. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the appearance of the short channel effect can be cited as the relatively small bandgap of silicon. On the other hand, in OS transistors, an oxide semiconductor which is a semiconductor material having a large bandgap is used, so the short channel effect can be suppressed. In other words, OS transistors are transistors having no short channel effect or having very little short channel effect.

[0357] The short channel effect refers to the deterioration of electrical characteristics that occurs as transistors are miniaturized (reduction of the channel length). As specific examples of the short channel effect, there are a decrease in the threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), an increase in the leakage current, etc. Here, the S value refers to the change in the gate voltage in the subthreshold region where the value of the drain current changes by one digit with a fixed drain voltage.

[0358] As an index of the tolerance to the short channel effect, the characteristic length is widely used. The characteristic length is an index of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist the short channel effect is high.

[0359] OS transistors are accumulation-mode transistors, and Si transistors are inversion-mode transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are small. Therefore, the ability of OS transistors to resist the short channel effect is higher than that of Si transistors. That is, when wanting to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0360] Even when the carrier concentration of the oxide semiconductor is reduced to a state where the channel formation region is i-type or substantially i-type, in a short-channel transistor, due to the Conduction-Band-Lowering (CBL) effect, the conduction band bottom of the channel formation region also becomes lower. Therefore, the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having an n + / n - / n + accumulation-type junctionless transistor structure or an n + / n - / n + accumulation-type non-junction transistor structure, where the channel formation region is an n - type region, and the source region and the drain region are n + type regions.

[0361] When the above structure is adopted as the OS transistor, good electrical characteristics can be achieved even when the semiconductor device is miniaturized or highly integrated. For example, even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of 20 nm or less or 15 nm or less because of the short-channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during the operation of the transistor, and is the width of the bottom surface of the gate electrode in the top view of the transistor.

[0362] In addition, by miniaturizing the OS transistor, the frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0363] As described above, the OS transistor has excellent effects compared with Si transistors, such as a small off-state current and the ability to manufacture transistors with a small channel length.

[0364] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0365] (Embodiment 3) In this embodiment, with reference to Figures 22 to 28A memory device including a transistor using one mode of the present invention.

[0366] In this embodiment, a structural example of a memory device including memory cells using the transistor described in the above embodiment will be described. In this embodiment, a structural example of a memory device is described, in which a layer including stacked memory cells and a layer including a functional circuit having a function of amplifying and holding a data potential held in the memory cells and outputting the same are provided.

[0367] [Structural example of memory device] Figure 22 It is a block diagram showing a memory device according to one mode of the present invention.

[0368] Figure 22 The shown memory device 300 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0369] Figure 22 An example is shown in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix configuration of m rows and n columns (m and n are integers of 2 or more). In addition, Figure 22 An example is shown in which a functional circuit 51 is provided for each wiring BL serving as a bit line, and an example is also shown in which the functional layer 50 includes n functional circuits 51 provided corresponding to n wirings BL.

[0370] In Figure 22 the first row and first column memory cell 10 is represented as memory cell 10[1, 1], and the m-th row and n-th column memory cell 10 is represented as memory cell 10[m, n]. In addition, in this embodiment and the like, an arbitrary row may be denoted as "the i-th row". In addition, an arbitrary column may be denoted as "the j-th column". Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. In addition, in this embodiment and the like, the i-th row and j-th column memory cell 10 is represented as memory cell 10[i, j]. Note that in this embodiment and the like, when expressed as "i + α" (α is a positive integer or a negative integer), "i + α" is not less than 1 and not greater than m. Similarly, when expressed as "j + α", "j + α" is not less than 1 and not greater than n.

[0371] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the wiring WL provided in the first (first row) is denoted as wiring WL[1], and the wiring WL provided in the m-th (m-th row) is denoted as wiring WL[m]. Similarly, the wiring PL provided in the first (first row) is denoted as wiring PL[1], and the wiring PL provided in the m-th (m-th row) is denoted as wiring PL[m]. Similarly, the wiring BL provided in the first (first column) is denoted as wiring BL[1], and the wiring BL provided in the n-th (n-th column) is denoted as wiring BL[n].

[0372] The plurality of memory cells 10 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0373] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. The OS transistor has an extremely small leakage current flowing between the source and the drain in the off state. In DOSRAM, by turning off the access transistor (rendering it non-conductive), the charge based on the data held in the capacitor can be maintained for a long time. Therefore, compared with a DRAM constituted by a transistor (Si transistor) including silicon in the channel formation region, the frequency of the refresh operation of DOSRAM can be lower. As a result, power consumption can be reduced. In addition, since the frequency characteristics of the OS transistor are high, reading and writing of a high-speed storage device can be performed. Thus, a storage device with a high operating speed can be provided.

[0374] For example, in Figure 22 the memory array 20 shown, a plurality of memory arrays 20[1] to 20[m] can be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided, the storage density of the memory cells 10 can be increased.

[0375] The wiring BL is used as a bit line for writing and reading data. The wiring WL is used as a word line for controlling the on or off state (conductive state or non-conductive state) of an access transistor that serves as a switch. The wiring PL is used as a constant potential line connected to a capacitor. In addition, as a wiring for transmitting a back gate potential to the back gate of the OS transistor of the access transistor, a wiring CL (not shown) may be provided separately. Alternatively, a structure in which the wiring PL also serves as a transmission line for the back gate potential may be employed.

[0376] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be significantly reduced, power consumption and signal delay can be reduced. In addition, the memory device can operate even if the capacitance of the capacitor included in the memory cell 10 is reduced.

[0377] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through a wiring GBL (not shown) described later. By adopting this structure, a minute potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, power consumption and signal delay can be reduced.

[0378] In addition, the wiring BL is arranged in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is arranged in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that serves as a source or a drain. Alternatively, the wiring BL is arranged in contact with a conductor that contacts a region of the semiconductor layer of the transistor included in the memory cell 10 that serves as a source or a drain. That is to say, the wiring BL can be said to be a wiring that electrically connects, in the vertical direction, one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51.

[0379] The memory array 20 can be overlapped and disposed on the driving circuit 21. By overlapping the driving circuit 21 and the memory array 20, the signal transmission distance between the driving circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the driving circuit 21 and the memory array 20 are reduced, and reduction in power consumption and signal delay can be achieved. In addition, miniaturization of the storage device 300 can be realized.

[0380] By using the OS transistor in the same manner as the transistor included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on the circuit using the Si transistor in the same manner as the memory arrays 20[1] to 20[m], and thus integration can be easily performed. By adopting a structure in which the functional circuit 51 amplifies the signal, circuits such as the sense amplifier 46 of the subsequent-stage circuit can be miniaturized, and thus miniaturization of the storage device 300 can be realized.

[0381] The driving circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0382] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or discarded as needed. Alternatively, other circuits or other signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0383] In addition, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 can also be generated in the control circuit 32.

[0384] The control circuit 32 is a logic circuit having a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the storage device 300 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0385] The voltage generation circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a signal of H level is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0386] The peripheral circuit 41 is a circuit for writing data to and reading data from the memory cell 10. In addition, the peripheral circuit 41 is a circuit that outputs various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0387] The row decoder 42 and the column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has a function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0388] The input circuit 47 has a function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300. The data output from the output circuit 48 is the signal RDA.

[0389] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the storage device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. In Figure 22 In, the number of power supply domains supplied with VDD in the peripheral circuit 31 is 1, but it can also be multiple. At this time, a power switch can be set for each power supply domain.

[0390] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50, and a plurality of layers of memory arrays 20 can be overlapped and provided on the drive circuit 21. By overlapping and providing a plurality of layers of memory arrays 20, the storage density of the storage cells 10 can be increased. Figure 23A FIG. 2 is a perspective view of a storage device 300 in which a functional layer 50 and five layers (m = 5) of memory arrays 20[1] to 20[5] are overlapped and provided on the drive circuit 21.

[0391] In Figure 23A FIG. 2, the memory array 20 provided in the first layer is denoted as the memory array 20[1], the memory array 20 provided in the second layer is denoted as the memory array 20[2], and the memory array 20 provided in the fifth layer is denoted as the memory array 20[5]. In addition, Figure 23A FIG. 2 shows a wiring WL, a wiring PL, and a wiring CL extending in the X direction and a wiring BL extending in the Z direction (a direction perpendicular to the surface of the substrate on which the drive circuit is provided). Note that, in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the memory arrays 20 is not shown.

[0392] Figure 23B FIG. 2 shows Figure 23A a schematic diagram for explaining a structural example of a functional circuit 51 connected to the wiring BL and storage cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL shown in FIG. 2. In addition, Figure 23B FIG. 2 shows a wiring GBL provided between the functional circuit 51 and the drive circuit 21. In addition, a structure in which one wiring BL is electrically connected to a plurality of storage cells (storage cells 10) is also referred to as a "memory string". Note that, in the drawings, in order to improve visibility, the wiring GBL is sometimes shown by a thick line.

[0393] Figure 23B FIG. 2 shows an example of the circuit structure of the storage cell 10 connected to the wiring BL. The storage cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitor 12, and each wiring (wiring BL, wiring WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL, the wiring WL, etc. Here, the transistor 11 corresponds to the transistor 200 shown in Embodiment 1.

[0394] In the storage cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL. The back gate of the transistor 11 is connected to the wiring CL.

[0395] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 12. The wiring CL is a wiring for supplying a constant potential for controlling the threshold voltage of the transistor 11. The wiring PL and the wiring CL may also be at the same potential. At this time, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0396] Figure 23B The wiring GBL shown is provided so as to electrically connect the drive circuit 21 and the functional layer 50. Figure 24A FIG. shows a schematic diagram of a storage device 300 having functional circuits 51 and memory arrays 20[1] to 20[m] as repeating units 70. Although Figure 24A one wiring GBL is shown in, the wiring GBL can also be appropriately provided according to the number of functional circuits 51 in the functional layer 50.

[0397] In addition, the wiring GBL is provided so as to contact the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided so as to contact the region of the semiconductor layer of the transistor included in the functional circuit 51 that serves as a source or a drain. Alternatively, the wiring GBL is provided so as to contact a conductor that contacts the region of the semiconductor layer of the transistor included in the functional circuit 51 that serves as a source or a drain. That is to say, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 and the drive circuit 21 in the vertical direction.

[0398] In addition, a structure in which repeating units 70 including functional circuits 51 and memory arrays 20[1] to 20[m] are stacked may also be provided. A storage device 300A according to one aspect of the present invention can include repeating units 70[1] to 70[p] (p is an integer of 2 or more) as shown in Figure 24B The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL can be appropriately provided according to the number of functional circuits 51.

[0399] In one aspect of the present invention, while the OS transistor is stacked, the wiring serving as the bit line is arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided. By arranging the wiring serving as the bit line extending from the memory array 20 in the vertical direction of the substrate surface, the length of the wiring between the memory array 20 and the drive circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0400] In addition, one aspect of the present invention includes a functional layer 50 in the layer provided with the memory array 20. The functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting the same. By adopting this structure, a minute potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the drive circuit 21. Since circuits such as the sense amplifier can be miniaturized, miniaturization of the storage device 300 can be achieved. In addition, even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced, the storage device 300 can operate.

[0401] Note that the above description includes the storage device of the memory arrays 20[1] to 20[m], but the semiconductor device according to the present invention can also be used for a single-layer storage device including only the memory array 20[1].

[0402] [Structural examples of the memory array 20 and the functional circuit 51] Refer to Figure 25 Description Figure 22 to the structural examples of the functional circuit 51 illustrated in FIGS. 24 and the structural examples of the sense amplifier 46 included in the memory array 20 and the drive circuit 21. Figure 25 The drive circuit 21 is shown. The drive circuit 21 is connected to the wirings GBL (wiring GBL_A, wiring GBL_B). The wirings GBL are connected to the functional circuits 51 (functional circuit 51_A, functional circuit 51_B), and the functional circuits 51 are connected to the memory cells 10 (memory cell 10_A, memory cell 10_B) connected to different wirings BL (wiring BL_A, wiring BL_B). As Figure 25 the shown drive circuit 21, in addition to the sense amplifier 46, a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 are shown.

[0403] As the functional circuits 51_A and 51_B, transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown. Figure 25 The shown transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are OS transistors in the same manner as the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked and provided on the drive circuit 21 in the same manner as the memory arrays 20[1] to 20[m].

[0404] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the source and drain of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the source and drain of the transistors 53_b and 54_b. Similarly to the wirings BL_A and BL_B, the wirings GBL_A and GBL_B are provided in the vertical direction and connected to the transistors included in the drive circuit 21. As Figure 25 shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with the selection signal MUX, the control signal WE, or the control signal RE.

[0405] constitute Figure 25 The transistors 81_1 to 81_6 and 82_1 to 82_4 that constitute the read amplifier 46, the precharge circuit 71_A, and the precharge circuit 71_B shown are made of Si transistors. The switches 83_A to 83_D that constitute the switch circuit 72_A and the switch circuit 72_B may also be made of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistor or switch that constitutes the precharge circuit 71_A, the precharge circuit 71_B, the read amplifier 46, and the switch circuit 72_A.

[0406] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit that precharges the wirings BL_A and BL_B to an intermediate potential VPC equivalent to the potential VDD / 2 between the high power supply potential (VDD) and the low power supply potential (VSS) according to the precharge signal supplied to the precharge line PCL1.

[0407] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit that precharges the wirings GBL_A and GBL_B to an intermediate potential VPC equivalent to the potential VDD / 2 between VDD and VSS according to the precharge signal supplied to the precharge line PCL2.

[0408] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. According to the potential changes of the pre-charged wiring BL_A and wiring BL_B by selecting the memory cells 10_A and 10_B, the potentials of the wiring GBL_A and wiring GBL_B are set to VDD or VSS. The potentials of the wiring GBL_A and wiring GBL_B can be output to the outside through the switches 83_C and 83_D and the write / read circuit 73. The wiring BL_A and wiring BL_B and the wiring GBL_A and wiring GBL_B correspond to bit line pairs. The writing of the data signal to the write / read circuit 73 is controlled according to the signal EN_data.

[0409] The switch circuit 72_A is a circuit that controls the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B. The switch circuit 72_A can be switched between on and off by controlling the switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, it is turned on when the switching signal CSEL1 is at a high level and turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit that controls the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched between on and off by controlling the switching signal CSEL2. The switches 83_C and 83_D can operate in the same manner as the switches 83_A and 83_B.

[0410] As Figure 25 shown, the storage device 300 can have a structure in which the memory cells 10, the functional circuit 51, and the sense amplifier 46 are connected by the wiring BL and the wiring GBL provided in the vertical direction of the shortest distance. Although the functional layer 50 including the transistors constituting the functional circuit 51 increases, since the load of the wiring BL is reduced, the write time can be shortened and the data can be easily read.

[0411] In addition, as Figure 25 shown, each transistor included in the functional circuits 51_A and 51_B is controlled by the control signals WE, RE, and the selection signal MUX. Each transistor can output the potential of the wiring BL to the drive circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A and 51_B can be used as sense amplifiers constituted by OS transistors. By adopting this structure, a minute potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0412] <Structural Example of Memory Cell> Use Figure 26A To describe an example of the structure of the memory cell 10 for the above-described storage device.

[0413] Note that in Figure 26A X direction is parallel to the channel width direction of the transistor, Y direction is perpendicular to the X direction, and Z direction is perpendicular to the X direction and the Y direction.

[0414] As Figure 26A shown, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided on the transistor 11 and an insulator 284 is provided on the insulator 285. The insulator 285 and the insulator 284 can use the insulator that can be used as the insulator 216. In addition, the transistor 11 has the same structure as the transistor 200 shown in the above-described embodiment, and the same reference numerals are attached to the same components. For the details of the transistor 200, reference can be made to the above-described embodiment. In addition, a conductor 240b is provided in contact with one of the source and drain of the transistor 11 (conductor 242b). The conductor 240b extends in the Z direction and is used as a wiring BL.

[0415] The capacitor 12 includes a conductor 153 on a conductor 242a, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0416] At least a part of each of the conductor 153, the insulator 154, and the conductor 160 is disposed inside an opening provided in the insulators 275, 280, 282, 283, and 285. At least an end portion of each of the conductor 153, the insulator 154, and the conductor 160 is located on the insulator 282, preferably on the insulator 285. The insulator 154 is provided so as to cover the end portion of the conductor 153. Thereby, the conductor 153 can be electrically insulated from the conductor 160.

[0417] The deeper the depth of the opening provided in the insulators 275, 280, 282, 283, and 285 (that is, the greater the thickness of one or more of the insulators 275, 280, 282, 283, and 285), the larger the capacitance of the capacitor 12 can be. By increasing the capacitance per unit area of the capacitor 12, miniaturization or high integration of the storage device can be achieved.

[0418] The conductor 153 has a region that serves as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region that serves as the dielectric of the capacitor 12. The conductor 160 has a region that serves as the other electrode (upper electrode) of the capacitor 12. Further, the top of the conductor 260 can be extended and used as Figure 23A and Figure 23B the wiring PL shown. The capacitor 12 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0419] The conductor 242a provided on the oxide 230 so as to overlap with the oxide 230 is used as an electrode electrically connected to the conductor 153 of the capacitor 12.

[0420] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260, respectively. The conductor 153 and the conductor 160 are preferably deposited using a deposition method with high coverage such as the ALD method or the CVD method. For example, titanium nitride or tantalum nitride deposited using the ALD method or the CVD method can be used as the conductor 153.

[0421] The bottom surface of the conductor 153 is in contact with the top surface of the conductor 242a. Here, by using a conductive material with good conductivity as the conductor 242a, the contact resistance between the conductor 153 and the conductor 242a can be reduced.

[0422] Further, titanium nitride deposited using the ALD method or the CVD method can be used as the conductor 160a, and tungsten deposited using the CVD method can be used as the conductor 160b. Here, when the adhesion of tungsten to the insulator 154 is sufficiently high, a single-layer structure of tungsten deposited using the CVD method can also be used as the conductor 160.

[0423] The insulator 154 in the capacitor 12 preferably uses a high dielectric constant (high-k) material (a material with a relatively high relative dielectric constant). The insulator 154 is preferably deposited using a deposition method with high coverage such as the ALD method or the CVD method.

[0424] Examples of the insulator as a high dielectric constant (high-k) material include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, gallium, etc. Further, the above oxides, oxynitrides, oxynitrides, or nitrides may also contain silicon. Further, insulators made of the above materials can also be used in a stacked manner.

[0425] For example, as an insulator of a high dielectric constant (high-k) material, alumina, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, and an oxynitride containing hafnium and zirconium can be cited. By using such a high-k material, the insulator 154 can be thickened to an extent that can suppress leakage current, and the capacitance of the capacitor 12 can also be sufficiently ensured.

[0426] In addition, it is preferable to use the insulator composed of the above materials in a stacked manner, and a stacked structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material is preferably used. For example, as the insulator 154, an insulator stacked in the order of zirconium oxide, alumina, and zirconium oxide can be used. In addition, for example, an insulator stacked in the order of zirconium oxide, alumina, zirconium oxide, and alumina can be used. In addition, for example, an insulating film stacked in the order of hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina can be used. By using an insulator with a relatively high dielectric strength such as alumina in a stacked manner, the dielectric strength is increased, and thus electrostatic breakdown of the capacitor 12 can be suppressed.

[0427] In addition, as the insulator 154, a material that can have ferroelectricity can also be used. As a material that can have ferroelectricity, metal oxides such as hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) can be cited. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide can be cited. Here, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be appropriately set. For example, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide can be cited, etc. In addition, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be appropriately set. For example, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc., which are piezoelectric ceramics having a perovskite structure, can also be used.

[0428] In addition, as materials that can have ferroelectricity, metal nitrides containing element M1, element M2, and nitrogen can be cited. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic ratio of element M1 to element M2 can be appropriately set. In addition, metal oxides containing element M1 and nitrogen sometimes have ferroelectricity even if they do not contain element M2. In addition, as materials that can have ferroelectricity, materials obtained by adding element M3 to the above metal nitrides can be cited. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set.

[0429] In addition, as materials that can have ferroelectricity, SrTaO 2 N, BaTaO 2 N and other perovskite-type oxynitrides, GaFeO of κ-type alumina 3 etc.

[0430] Note that in the above description, although examples of metal oxides and metal nitrides are shown, it is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitroxides obtained by adding oxygen to the above metal nitrides can also be used.

[0431] In addition, as materials that can have ferroelectricity, for example, mixtures or compounds composed of multiple materials selected from the above materials can be used. In addition, the insulator 154 can have a laminated structure composed of multiple materials selected from the above materials. Note that the crystal structures (properties) of the materials and the like listed above may change not only according to the deposition conditions but also according to various processes and the like. Therefore, in this specification and the like, materials that exhibit ferroelectricity are not only called ferroelectrics but also called materials that can have ferroelectricity.

[0432] A ferroelectric is an insulator that has the property of polarizing internally when an electric field is applied from the outside and maintaining the polarization even when the electric field is 0. Therefore, by using a capacitor that uses this material as a dielectric (hereinafter, sometimes called a ferroelectric capacitor), a non-volatile storage element can be formed. A non-volatile storage element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor 12, the storage device shown in this embodiment is used as a ferroelectric memory.

[0433] The deeper the depth of the openings provided in insulators 275, 280, 282, 283, and 285 (that is, by increasing the thickness of one or more of insulators 275, 280, 282, 283, and 285), the larger the capacitance of capacitor 12 can be. Here, since insulators 275, 282, and 283 are used as barrier insulators, it is preferable to set the thickness according to the barrier properties required for the semiconductor device. In addition, since the thickness of conductor 260 used as the gate electrode is determined by the thickness of insulator 280, the thickness of insulator 280 is preferably set according to the thickness of conductor 260 required for the semiconductor device.

[0434] Therefore, it is preferable to set the capacitance of capacitor 12 by adjusting the thickness of insulator 285. For example, by setting the thickness of insulator 285 in the range of 50 nm or more and 250 nm or less, the depth of the above-mentioned opening can be about 150 nm or more and 350 nm or less. By forming capacitor 12 within the above range, capacitor 12 has sufficient capacitance, and in a semiconductor device in which multiple memory cell layers are stacked, the height of one layer does not increase excessively. In each of the multiple memory cell layers, the capacitance of the capacitors provided in each memory cell can be different. When adopting this structure, for example, it is only necessary to make the thickness of insulator 285 provided in each memory cell layer different.

[0435] In the opening provided in insulator 285 etc. where capacitor 12 is disposed, the sidewall of this opening can be perpendicular or substantially perpendicular to the top surface of insulator 222, or can have a tapered shape. By having a tapered sidewall shape, the coverage of conductor 153 etc. provided in the opening of insulator 285 etc. can be improved, and thus defects such as voids can be reduced.

[0436] Conductor 242b provided on oxide 230 so as to overlap with oxide 230 is used as a wiring electrically connected to conductor 240b. For example, in Figure 26A , the top surface and side ends of conductor 242b are electrically connected to conductor 240b extending in the Z direction. In particular, in Figure 26A , the top surface and side ends of conductor 242b are in contact with conductor 240b.

[0437] When the conductor 240b is in direct contact with at least one of the top surface and the side end of the conductor 242b, there is no need to separately provide an electrode for connection, so the occupied area of the memory array can be reduced. In addition, the integration degree of the memory cells is improved, and the storage capacity of the storage device can be increased. Further, the conductor 240b preferably contacts a part of the top surface and the side end of the conductor 242b. By contacting the conductor 240b with multiple surfaces of the conductor 242b, the contact resistance between the conductor 240b and the conductor 242b can be reduced.

[0438] The conductor 240b is disposed in an opening formed in the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284.

[0439] In addition, as Figure 26A shown, the insulator 241b is preferably disposed in contact with the side surface of the conductor 240b. Specifically, the insulator 241b is disposed in contact with the inner walls of the openings of the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284. Further, the insulator 241 is also formed on the side surface of the oxide 230 protruding in the opening. Here, at least a part of the conductor 242b is exposed from the insulator 241b and contacts the conductor 240b. That is, the conductor 240b is disposed in such a manner that it is embedded in the interior of the above opening with the insulator 241b interposed therebetween.

[0440] As Figure 26A shown, the uppermost part of the insulator 241b formed below the conductor 242b is preferably located below the top surface of the conductor 242b. By adopting this structure, the conductor 240b can contact at least a part of the side end of the conductor 242b. Further, the insulator 241b formed below the conductor 242b preferably includes a region in contact with the side surface of the oxide 230. By adopting this structure, it is possible to prevent impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 230 through the conductor 240b.

[0441] In the opening portion where the conductor 240b and the insulator 241b are disposed, the side wall of the opening portion may be perpendicular or substantially perpendicular to the top surface of the insulator 222, or may have a tapered shape. By having a tapered shape of the side wall, the covering property of the insulator 241b and the like disposed in the opening portion is improved.

[0442] In addition, in Figure 26A the memory cell 10 shown, the conductor 153 of the capacitor 12 contacts the conductor 242a of the transistor 11, but the present invention is not limited thereto. For example, asFigure 26B As shown, a conductor 240a may also be provided in the transistor 11, and a capacitor 12 may be provided thereon.

[0443] In Figure 26B In the memory cell 10 shown, an insulator 286 may be provided on the insulator 283, an insulator 287 may be provided on the insulator 286, and an insulator 288 may be provided on the insulator 287. Insulators that can be used for the insulator 284 may be used as the insulator 286, the insulator 287, and the insulator 288. In addition, the conductor 246a and the conductor 246b are provided in a manner of being embedded in the insulator 286. The conductor 246a and the conductor 246b are used as wirings or electrodes, and conductors that can be used for the conductor 205 may be used. In addition, the capacitor 12 is provided in a manner of being embedded in the insulator 287 and the insulator 288. Figure 26B The capacitor 12 shown has the same structure as Figure 26A In addition, similar to the transistor 200 shown in Figure 1B etc., Figure 26B The transistor 11 shown includes the conductor 240a, the conductor 240b, the insulator 241a, and the insulator 241b embedded in the insulator 280 or the like.

[0444] As Figure 26B shown, the conductor 240a is in contact with the conductor 242a, the conductor 246a is in contact with the conductor 240a, and the conductor 153 is in contact with the conductor 246a. Therefore, the conductor 153, which is the lower electrode of the capacitor 12, is electrically connected to the conductor 242a, which is one of the source and drain of the transistor 11, through the conductor 246a and the conductor 240a.

[0445] In addition, as Figure 26B shown, the conductor 240b is in contact with the conductor 242b, and the conductor 246b is in contact with the conductor 240b. Here, by extending and providing the conductor 246b in the same layer, it can be used as the wiring BL. At this time, Figure 26B The memory cell 10 shown is arranged in a row and column shape in the same layer to form a memory array. In addition, without being limited thereto, similar to the conductor 240b shown in Figure 26A it may also be extended and provided in the Z direction.

[0446] In addition, in Figure 26B the memory cell 10 shown, the conductor 246a and the conductor 246b are formed in the same layer, but the present invention is not limited thereto. For example, as Figure 27A shown, the conductor 246a may also be provided in a layer above the conductor 246b.

[0447] In Figure 27AIn the memory cell 10 shown, an insulator 289 may be provided on the insulator 286, and an insulator 290 may be provided on the insulator 289. As the insulator 289, an insulator that can be used for the insulator 283 may be used, and as the insulator 290, an insulator that can be used for the insulator 284 may be used. In addition, a conductor 246a is provided in such a manner as to be embedded in the insulator 290.

[0448] By adopting the above structure, the conductor 246a can be overlapped and arranged on the transistor 11 without affecting the conductor 246b. Therefore, the capacitor 12 provided on the conductor 246a can be overlapped and arranged on the transistor 11. Here, it is preferable that at least a part of the capacitor 12, for example, the part where the conductor 153, the insulator 154, and the conductor 160 overlap, overlaps with the oxide 230 and the conductor 260. By adopting such a structure, the memory cell 10 including the transistor 11 and the capacitor 12 can be provided without significantly increasing the occupied area. Thereby, the storage capacity per unit area of the storage device can be increased.

[0449] Note that the insulator 289 is preferably used as an etch stop layer when forming the conductor 246a. By adopting such a structure, even if a part of the conductor 246a overlaps with the conductor 246b, it is possible to prevent a part of the conductor 246a from contacting the conductor 246b.

[0450] In addition, in Figure 26A the memory cell 10 shown, the capacitor 12 is provided on the transistor 11, but the present invention is not limited thereto. For example, as shown in Figure 27B the capacitor 12 may also be provided under the transistor 11.

[0451] In Figure 27B the memory cell 10 shown, similar to Figure 1B an insulator 215 may be provided under the insulator 216, an insulator 291 may be provided under the insulator 215, an insulator 292 may be provided under the insulator 291, and an insulator 293 may be provided under the insulator 292. As the insulator 291, the insulator 292, and the insulator 293, an insulator that can be used for the insulator 284 may be used. In addition, a conductor 294 is provided in such a manner as to be embedded in the insulator 293. The conductor 294 is used as a wiring or an electrode, and a conductor that can be used for the conductor 205 may be used. In addition, the capacitor 12 is provided in such a manner as to be embedded in the insulator 291 and the insulator 292. Figure 27B The capacitor 12 shown has the same as Figure 26AThe same structure. In addition, the conductor 206 is disposed in such a way as to be embedded in the insulators 215 and 216. The conductor 206 can be formed by the same process as the conductor 205 using the dual damascene method. Further, the conductors 240c and the insulator 241c are disposed in such a way as to be embedded in the insulators 221, 222, 275, 280, 282, and 283. The conductor 240c can be formed by the same process as the conductors 240a and 240b, and the insulator 241c can be formed by the same process as the insulators 241a and 241b.

[0452] As Figure 27B shown, the conductor 240a is in contact with the conductor 242a, the conductor 246a is in contact with the conductor 240a, the conductor 240c is in contact with the conductor 246a, the conductor 206 is in contact with the conductor 240c, and the conductor 160 is in contact with the conductor 206. Accordingly, the conductor 160, which is the upper electrode of the capacitor 12, is electrically connected to the conductor 242a, which is one of the source and drain of the transistor 11, through the conductors 206, 240c, 246a, and 240a.

[0453] As Figure 27B shown, the conductor 294 is in contact with the conductor 153. Here, the conductor 153 can be used as the wiring PL.

[0454] By adopting the above structure, the capacitor 12 can be overlapped and disposed under the transistor 11. Here, it is preferable that at least a part of the capacitor 12, for example, the overlapping part of the conductor 153, the insulator 154, and the conductor 160, overlaps with the oxide 230 and the conductor 260. By adopting such a structure, the storage unit 10 including the transistor 11 and the capacitor 12 can be provided without significantly increasing the occupied area. Thereby, the storage capacity per unit area of the storage device can be increased.

[0455] <Structural Example of Storage Device 300> Use Figure 28 to illustrate the structural example of the above storage device 300.

[0456] The storage device 300 includes: a drive circuit 21 including a layer including transistors 310, etc.; a functional layer 50 including a layer including transistors 52, 53, 54, 55, etc. on the drive circuit 21; and memory arrays 20[1] to 20[m] on the functional layer 50. The transistor 52 corresponds to the above transistors 52_a and 52_b, the transistor 53 corresponds to the above transistors 53_a and 53_b, the transistor 54 corresponds to the above transistors 54_a and 54_b, and the transistor 55 corresponds to the above transistors 55_a and 55_b.

[0457] Figure 28 The transistor 310 included in the driving circuit 21 is shown. The transistor 310 is provided on a substrate 311 and includes a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and low-resistance regions 314a and 314b serving as a source region or a drain region. The transistor 310 can be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single-crystalline silicon substrate can be used.

[0458] Here, in Figure 28 the transistor 310 shown, the semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. Further, the conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. Further, a material for adjusting the work function can be used for the conductor 316. Because of the convex portion of the semiconductor substrate, such a transistor 310 is also called a Fin-type transistor. Further, an insulator of a mask for forming the convex portion may be provided in contact with the top of the convex portion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0459] Note that Figure 28 the structure of the transistor 310 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or the driving method.

[0460] A wiring layer including an interlayer film, wirings, plugs, etc. may be provided between the respective structural bodies. Further, the wiring layer may be provided in multiple layers according to the design. Further, in this specification, etc., a wiring and a plug electrically connected to the wiring may also be one constituent element. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

[0461] For example, on the transistor 310, insulators 320, 322, 324, and 326 are sequentially stacked as an interlayer film. Further, conductors 328, etc. are embedded in the insulators 320 and 322. Further, conductors 330, etc. are embedded in the insulators 324 and 326. Further, the conductors 328 and 330 are used as contact plugs or wirings.

[0462] In addition, the insulator used as the interlayer film can also be used as a planarization film covering the uneven shape below it. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by a planarization process such as chemical mechanical polishing (CMP: Chemical Mechanical Polishing).

[0463] In addition, Figure 28 Transistors 52, 53, and 55 in the functional layer 50 are shown. Transistors 52, 53, and 55 have the same structure as the transistor 11 in the memory cell 10. The sources and drains of transistors 52, 53, and 55 are connected in series with each other.

[0464] An insulator 208 is provided on transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Further, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Moreover, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A part of the conductor 240b provided in the memory array 20[1] is embedded in the openings formed in the insulator 212 and the insulator 214. Here, the insulator 208 and the insulator 210 can use the insulator that can be used as the insulator 216. In addition, the insulator 212 can use the insulator that can be used as the insulator 283. In addition, the insulator 214 can use the insulator that can be used as the insulator 282.

[0465] The bottom surface of the conductor 207 is provided in contact with the top surface of the conductor 260 of the transistor 52. In addition, the top surface of the conductor 207 is provided in contact with the bottom surface of the conductor 209. Further, the top surface of the conductor 209 contacts the bottom surface of the conductor 240b provided in the memory array 20[1]. By adopting this structure, the conductor 240b equivalent to the wiring BL can be electrically connected to the gate of the transistor 52.

[0466] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240b included in each memory cell 10 is electrically connected to the conductor 240b in the upper layer and the conductor 240b in the lower layer.

[0467] As Figure 28 shown, adjacent memory cells 10 share the conductor 240b. In addition, in adjacent memory cells 10, the structure on the right side and the structure on the left side of the conductor 240b are symmetrically arranged.

[0468] Here, the conductor 160 serving as the upper electrode of the capacitor 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 205 serving as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 in the lower layer and the conductor 205 of the transistor 11 in the upper layer are formed in such a manner as to be embedded in the openings in the same insulator 216. In addition, the conductor 205 of the transistor 11 in the upper layer can also be formed by processing the conductive film of the conductor 160 of the capacitor 12 in the lower layer. At this time, the conductor 205 of the transistor 11 in the upper layer contains the same material as the conductor 160 of the capacitor 12 in the lower layer.

[0469] As described above, by simultaneously forming the conductor 160 of the capacitor 12 in the lower layer and the conductor 205 of the transistor 11 in the upper layer, the manufacturing process of the storage device according to this embodiment can be reduced, thereby improving the productivity of the storage device.

[0470] In the above-mentioned memory array 20, a plurality of memory arrays 20[1] to 20[m] can be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, the storage density of the storage unit 10 can be increased. In addition, the memory array 20 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0471] This embodiment can be appropriately combined with other embodiments.

[0472] (Embodiment 4) In this embodiment, an example of a chip of a storage device in which one aspect of the present invention is mounted is described with reference to FIG. 29.

[0473] In Figure 29A and Figure 29B shown, a plurality of circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a System on Chip (SoC).

[0474] As Figure 29A shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0475] Bumps (not shown) are provided on the chip 1200, and the bumps are as Figure 29Bis connected to the first surface of the package substrate 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, and the bumps 1202 are connected to the mother board 1203.

[0476] In addition, a storage device such as a DRAM 1221 and a flash memory 1222 may be provided on the mother board 1203. For example, the DOSRAM shown in the above embodiment may be used for the DRAM 1221. Thereby, the DRAM 1221 can be made to have low power consumption, high speed, and large capacity.

[0477] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory shared by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above DOSRAM may be used for this memory. In addition, the GPU 1212 is suitable for parallel computing of a plurality of data, and it can be used for image processing or multiply-accumulate operation. By providing an image processing circuit or a multiply-accumulate operation circuit using the OS transistor shown in the above embodiment as the GPU 1212, image processing or multiply-accumulate operation can be performed with low power consumption.

[0478] In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the operation result from the GPU 1212 to the CPU 1211 after the operation in the GPU 1212 can be performed at high speed.

[0479] The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the above multiply-accumulate operation circuit may be provided in the analog operation unit 1213.

[0480] The memory controller 1214 has a circuit serving as a controller for the DRAM 1221 and a circuit serving as an interface for the flash memory 1222.

[0481] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a controller for a game machine, etc. As the above interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0482] The network circuit 1216 has a circuit for connecting to a network such as a LAN (Local Area Network). In addition, it may also have a circuit for network security.

[0483] The above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Thus, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0484] The mother board 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the flash memory 1222 can be referred to as the GPU module 1204.

[0485] The GPU module 1204 can reduce its size due to the chip 1200 using the SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smart phones, tablet terminals, laptop personal computers, and portable (portable) game machines due to its high image processing ability. In addition, by using the sum-of-products operation circuit using the GPU 1212, methods such as deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann machine (DBM), and deep belief network (DBN) can be executed. Thus, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0486] This embodiment can be appropriately combined with other embodiments.

[0487] (Embodiment 5) In this embodiment, the electronic components, electronic devices, mainframe computers, space devices, and data centers (also referred to as DC) of the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframe computers, space devices, and data centers using one aspect of the present invention are very effective for realizing high performance such as low power consumption.

[0488] [Electronic Components] Figure 30A A perspective view showing a substrate (circuit board 704) on which an electronic component 700 is mounted. Figure 30A The illustrated electronic component 700 includes a semiconductor device 710 within a mold 711. Figure 30A In, a part of the electronic component 700 is omitted from the description to show its interior. The electronic component 700 includes lands 712 outside the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 through leads 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining a plurality of such electronic components and electrically connecting them to the printed circuit board 702 respectively, the circuit board 704 is thus completed.

[0489] In addition, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the drive circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding can be dispensed with for connecting between the layers. When the drive circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0490] In addition, by adopting the on-chip memory structure, compared with technologies using through electrodes such as TSV, the size of connection wirings and the like can be reduced, and thus the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, and thereby the memory bandwidth (also referred to as memory bandwidth) can be improved.

[0491] In addition, preferably, a plurality of memory cell arrays in the storage layer 716 are formed using OS transistors and are stacked in a monolithic manner. When the plurality of memory cell arrays are stacked in a monolithic manner, either or both of the memory bandwidth and the memory access latency can be improved. The bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to achieve a monolithic stacked structure compared with OS transistors. Therefore, in the monolithic stacked structure, OS transistors are superior to Si transistors.

[0492] Alternatively, the semiconductor device 710 may be referred to as a die. In this specification and the like, a die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for a die include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.

[0493] Next, Figure 30B A perspective view of the electronic component 730 is shown. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0494] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can be used for integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0495] The package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0496] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different electrode pitch. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuits provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through this through electrode. In addition, in the case of using a silicon interposer, a TSV can also be used as the through electrode.

[0497] In HBM, in order to achieve a wide memory bandwidth, many wirings need to be connected. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer for mounting the HBM.

[0498] In addition, in SiP, MCM, etc. using a silicon interposer, it is not easy for the reliability to decrease due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer. In addition, since the surface flatness of the silicon interposer is high, it is not easy for a connection failure to occur between the integrated circuit provided on the silicon interposer and the silicon interposer. It is particularly preferable to use a silicon interposer for 2.5D packaging (2.5D mounting), in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0499] On the other hand, when electrically connecting a plurality of integrated circuits having different terminal pitches using a silicon interposer, TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the above-described terminal pitch becomes a problem, and it is sometimes difficult to provide a large number of wirings required to achieve a wide memory bandwidth. Thus, as described above, a monolithic stacked structure using an OS transistor is preferable. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner may also be employed.

[0500] In addition, a heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. In the case of providing a heat sink, it is preferable that the heights of the integrated circuits provided on the interposer 731 be the same. For example, in the electronic component 730 shown in the present embodiment, it is preferable that the heights of the semiconductor device 710 and the semiconductor device 735 be the same.

[0501] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 30B An example of forming the electrodes 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. In addition, the electrodes 733 may also be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0502] The electronic component 730 can be mounted on another substrate by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (LandGrid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0503] [Electronic device] Next, Figure 31A A perspective view of the electronic device 6500 is shown. Figure 31A The illustrated electronic device 6500 is a portable information terminal that can be used as a smart phone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, etc. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for the display unit 6502, the control device 6509, etc.

[0504] Figure 31B The illustrated electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using a semiconductor device according to one embodiment of the present invention for the above control device 6509 and control device 6616, power consumption can be reduced, so it is preferable.

[0505] [Mainframe computer] Next, Figure 31C A perspective view of the mainframe computer 5600 is shown. In Figure 31C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. In addition, the mainframe computer 5600 may also be referred to as a supercomputer.

[0506] The computer 5620 may, for example, have Figure 31D the structure of the perspective view shown. In Figure 31D the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals, etc. A personal computer card 5621 is inserted into the slot 5631. And the personal computer card 5621 includes connection terminals 5623, 5624, 5625, which are connected to the motherboard 5630.

[0507] Figure 31EThe personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes connection terminals 5623, connection terminals 5624, connection terminals 5625, semiconductor devices 5626, semiconductor devices 5627, semiconductor devices 5628, and connection terminals 5629. Note that Figure 31E Semiconductor devices other than the semiconductor devices 5626, 5627, and 5628 are shown. For the description of these semiconductor devices, refer to the description of the semiconductor devices 5626, 5627, and 5628 described below.

[0508] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the specifications of the connection terminal 5629 include PCIe, etc.

[0509] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the personal computer card 5621 or inputting signals, etc. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, etc. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA: Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), etc. In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of each specification include HDMI (registered trademark), etc.

[0510] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected.

[0511] The semiconductor device 5627 includes a plurality of terminals. For example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5627 and the board 5622 can be electrically connected. Examples of the semiconductor device 5627 include FPGA, GPU, CPU, etc. As the semiconductor device 5627, for example, the electronic component 730 can be used.

[0512] The semiconductor device 5628 includes a plurality of terminals. For example, by soldering the terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5628 and the board 5622 can be electrically connected. As the semiconductor device 5628, for example, a storage device or the like can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0513] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0514] [Space equipment] The semiconductor device according to one aspect of the present invention can be applied to space equipment such as devices for processing and storing information.

[0515] The semiconductor device according to one aspect of the present invention may include an OS transistor. The change in electrical characteristics of the OS transistor due to irradiation with radiation is small. In other words, since the resistance to radiation is high, it can be appropriately used even in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space.

[0516] In Figure 32 , as an example of space equipment, the artificial satellite 6800 is shown. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In addition, Figure 32 An example is shown in which there is a planet 6804 in outer space. Note that outer space generally refers to a height of 100 km or more, but the outer space shown in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0517] In addition, although Figure 32 is not shown in the figure, a battery management system (also referred to as BMS) or a battery control circuit can also be provided in the secondary battery 6805. When the OS transistor is used for the above battery management system or battery control circuit, the power consumption is low and high reliability can be achieved even in outer space, so it is preferable.

[0518] In addition, outer space is an environment where the radiation dose is 100 times or more that of the ground. As radiation, for example, electromagnetic waves (electromagnetic radiation) represented by X-rays and γ-rays; and particle radiation represented by α-rays, β-rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. can be cited.

[0519] When sunlight shines on the solar panel 6802, electricity required for the operation of the satellite 6800 is generated. However, for example, when sunlight does not shine on the solar panel or when the amount of sunlight shining on the solar panel is small, the amount of electricity generated decreases. Therefore, it is possible that the electricity required for the operation of the satellite 6800 is not generated. In order to operate the satellite 6800 even when the generated electricity is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. In addition, the solar panel is sometimes referred to as a solar cell module.

[0520] The satellite 6800 can generate a signal. This signal is transmitted through the antenna 6803 and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that receives the signal can be measured. Thus, the satellite 6800 can constitute a satellite positioning system.

[0521] In addition, the control device 6807 has a function of controlling the satellite 6800. The control device 6807 is constituted by, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use the semiconductor device of one aspect of the present invention as the control device 6807. Compared with Si transistors, the OS transistor has less change in electrical characteristics due to radiation exposure. That is, the OS transistor has high reliability even in an environment where radiation may enter and can be appropriately used.

[0522] In addition, the satellite 6800 may include sensors. For example, by including a visible light sensor, the satellite 6800 can have a function of detecting sunlight reflected by an object on the ground. Or, by including a thermal infrared sensor, the satellite 6800 can have a function of detecting thermal infrared rays released from the earth's surface. Thus, the satellite 6800 can be used, for example, as an earth observation satellite.

[0523] Note that in the present embodiment, a satellite is shown as an example of a space device, but it is not limited thereto. For example, the semiconductor device of one aspect of the present invention can be appropriately applied to space devices such as spacecraft, space capsules, and space probes.

[0524] As described above, compared with Si transistors, the OS transistor has excellent effects such as enabling a wider memory bandwidth and high radiation resistance.

[0525] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to ensure data immutability and perform long-term management of data. When performing long-term management of data, it is necessary to scale up the facilities, such as setting up storage and servers for storing a huge amount of data, ensuring a stable power supply to maintain the data, or ensuring cooling equipment required during data retention.

[0526] By using a semiconductor device according to one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, reduce the scale of the cooling equipment, etc. As a result, space savings in the data center can be achieved.

[0527] In addition, the power consumption of a semiconductor device according to one embodiment of the present invention is low, so the circuit heat generation can be reduced. As a result, the negative impacts on the circuit itself, peripheral circuits, and modules caused by this heat generation can be reduced. In addition, by using a semiconductor device according to one embodiment of the present invention, a data center that can operate stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0528] Figure 33 A storage system applicable to a data center is shown. Figure 33 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (illustrated as a main computer). In addition, a plurality of storage devices 7003md are included as storage 7003 (illustrated as storage). The form in which the host 7001 and the storage 7003 are connected through a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as a storage controller) is shown.

[0529] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 can also be connected to each other through a network.

[0530] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for storing and outputting data is shortened, but this time is much longer than the time required for DRAM that can be used as a cache memory in the storage 7003. In a storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage 7003 to shorten the time required for storing and outputting data.

[0531] The above cache memory is used in the storage control circuit 7002 and the storage 7003. The data exchanged between the host 7001 and the storage 7003 is output to the host 7001 or the storage 7003 after being stored in the cache memory in the storage control circuit 7002 and the storage 7003.

[0532] When an OS transistor is used as the transistor for storing the data of the above cache memory to hold the potential corresponding to the data, the refresh frequency can be reduced to lower the power consumption. In addition, miniaturization of the storage can be achieved by stacking the memory cell arrays.

[0533] Note that by using the semiconductor device according to one embodiment of the present invention for any one or more selected from electronic components, electronic devices, mainframe computers, space devices, and data centers, an effect of reducing power consumption can be expected. Therefore, although it is currently considered that the energy demand increases with the high performance or high integration of semiconductor devices, by using the semiconductor device according to one embodiment of the present invention, it is also possible to reduce the emissions of greenhouse gases represented by carbon dioxide (CO 2 ). In addition, the semiconductor device according to one embodiment of the present invention has low power consumption and is thus also effective as a measure against global warming.

[0534] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments, etc. [Symbol description]

[0535] ADDR: Signal, BL[1]: Wiring, BL[j]: Wiring, BL[n]: Wiring, BL_A: Wiring, BL_B: Wiring, BL: Wiring, BW: Signal, CE: Signal, CLK: Signal, EN_data: Signal, GBL_A: Wiring, GBL_B: Wiring, GBL: Wiring, GW: Signal, MUX: Select Signal, PL[1]: Wiring, PL[i]: Wiring, PL[m]: Wiring, PL: Wiring, RDA: Signal, RE: Control Signal, VHH: Wiring, VLL: Wiring, VPC: Intermediate Potential, WAKE: Signal, WDA: Signal, WE: Control Signal, WL[1]: Wiring, WL[i]: Wiring, WL[m]: Wiring, WL: Wiring, 10[1,1]: Memory Cell, 10[i,j]: Memory Cell, 10[m,n]: Memory Cell, 10_A: Memory Cell, 10_B: Memory Cell, 10: Memory Cell, 11: Transistor, 12: Capacitor, 20[1]: Memory Array, 20[2]: Memory Array, 20[5]: Memory Array, 20[m]: Memory Array, 20: Memory Array, 21: Driver Circuit, 22: PSW, 23: PSW, 31: Peripheral Circuit, 32: Control Circuit, 33: Voltage Generation Circuit, 41: Peripheral Circuit, 42: Row Decoder, 43: Row Driver, 44: Column Decoder, 45: Column Driver, 46: Sense Amplifier, 47: Input Circuit, 48: Output Circuit, 50: Functional Layer, 51_A: Functional Circuit, 51_B: Functional Circuit, 51: Functional Circuit, 52_a: Transistor, 52_b: Transistor, 52: Transistor, 53_a: Transistor, 53_b: Transistor, 53: Transistor, 54_a: Transistor, 54_b: Transistor, 54: Transistor, 55_a: Transistor, 55_b: Transistor, 55: Transistor, 70[1]: Repetition Unit, 70: Repetition Unit, 71_A: Precharge Circuit, 71_B: Precharge Circuit, 72_A: Switching Circuit, 72_B: Switching Circuit, 73: Write / Read Circuit, 81_1: Transistor, 81_3: Transistor, 81_4: Transistor, 81_6: Transistor, 82_1: Transistor, 82_2: Transistor, 82_3: Transistor, 82_4: Transistor, 83_A: Switch, 83_B: Switch, 83_C: Switch, 83_D: Switch, 153: Conductor, 154: Insulator, 160a: Conductor, 160b: Conductor, 160: Conductor, 200a: Transistor, 200aD: Transistor, 200aE: Transistor, 200b: Transistor, 200: Transistor, 205a: Conductor, 205b: Conductor, 205: Conductor, 206: Conductor, 207: Conductor, 208: Insulator, 209: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 215: Insulator, 216: Insulator,221: Insulator, 222: Insulator, 223: Insulator, 225f: Insulating film, 225: Insulator, 230a: Oxide, 230aD: Oxide, 230aE: Oxide, 230af: Oxide film, 230b: Oxide, 230bD: Oxide, 230bE: Oxide, 230bf: Oxide film, 230D: Oxide, 230E: Oxide, 230: Oxide, 240a: Conductor, 240aD: Conductor, 240aE: Conductor, 240b: Conductor, 240bD: Conductor, 240bE: Conductor, 240c: Conductor, 240: Conductor, 241a: Insulator, 241aD: Insulator, 241aE: Insulator, 241b: Insulator, 241bD: Insulator, 241bE: Insulator, 241c: Insulator, 241: Insulator, 242A: Conductor, 242a: Conductor, 242aD: Conductor, 242aE: Conductor, 242b: Conductor, 242bD: Conductor, 242bE: Conductor, 242f: Conductive film, 242: Conductor, 246a: Conductor, 246b: Conductor, 250a: Insulator, 250A: Insulating film, 250b: Insulator, 250c: Insulator, 250d: Insulator, 250: Insulator, 255: Insulator, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 260: Conductor, 275: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 284: Insulator, 285: Insulator, 286: Insulator, 287: Insulator, 288: Insulator, 289: Insulator, 290: Insulator, 291: Insulator, 292: Insulator, 293: Insulator, 294: Conductor, 300A: Storage device, 300: Storage device, 310: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 700: Electronic component, 702: Printed circuit board, 704: Circuit board, 710: Semiconductor device, 711: Die, 712: Pad, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 730: Electronic component, 731: Daughter board, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 1200: Chip, 1201: Package substrate, 1202: Bump, 1203: Mother board, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog operation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: Computer card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6600: Electronic device, 6611: Housing, 6612: Keyboard, 6613: Pointing device, 6614: External connection port, 6615: Display unit, 6616: Control device, 6800: Satellite, 6801: Main body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001sb: Server, 7001: Host, 7002: Storage control circuit, 7003md: Storage device, 7003: Storage.,

Claims

1. A semiconductor device, comprising: a first insulator on a substrate; an oxide semiconductor covering the first insulator; a first conductor and a second conductor on the oxide semiconductor; a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor; a third insulator disposed in the opening and on the oxide semiconductor; and a third conductor disposed in the opening and on the third insulator, wherein, when viewed in a cross-section in the channel width direction, a height of the first insulator is longer than a width of the first insulator.

2. The semiconductor device according to claim 1, wherein, when viewed from above, a side surface of the opening of the second insulator is aligned or substantially aligned with side surfaces of the first conductor and the second conductor.

3. The semiconductor device according to claim 1, wherein, when viewed in a cross-section in the channel width direction, the height of the first insulator is 2 times or more and 20 times or less the width of the first insulator.

4. The semiconductor device according to claim 1, wherein the first conductor is used as one of a source electrode and a drain electrode of a transistor, the second conductor is used as the other of the source electrode and the drain electrode of the transistor, and the third conductor is used as a gate electrode of the transistor.

5. The semiconductor device according to claim 4, wherein, when viewed in a cross-section in the channel width direction, the oxide semiconductor and the third conductor face each other with the third insulator interposed therebetween on one side surface of the first insulator, the oxide semiconductor and the third conductor face each other with the third insulator interposed therebetween on the other side surface of the first insulator.

6. The semiconductor device according to claim 4, wherein, when viewed in a cross-section in the channel width direction, the first conductor contacts the oxide semiconductor on one side and the other side of one side surface of the first insulator, the second conductor contacts the oxide semiconductor on one side and the other side of one side surface of the first insulator.

7. The semiconductor device according to any one of claims 1 to 6, wherein the oxide semiconductor contains any one or more selected from In, Ga, and Zn.

8. A storage device, comprising: the semiconductor device according to claim 7; and a capacitor, wherein one electrode of the capacitor is electrically connected to the first conductor of the semiconductor device.

9. The storage device according to claim 8, wherein the capacitor is disposed on the third conductor, and at least a part of the capacitor overlaps the oxide semiconductor and the third conductor.

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