Semiconductor device

Abstract

A semiconductor device includes: a plurality of signal lines extending in a first direction and arranged in a second direction crossing the first direction; a first inspection terminal electrically connected to one end of the signal line and providing an inspection signal to the signal line; a detection circuit electrically connected to the other end of the signal line and detecting a defect in the signal line; a second inspection terminal that provides a control signal that controls a detection operation of the detection circuit; and a protection element electrically connected to the second inspection terminal and absorbing the surge.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a semiconductor device constituting an imaging element. In the semiconductor device, a plurality of semiconductor substrates are bonded and stacked. One semiconductor substrate includes a pixel array in which a plurality of pixels each having a light receiving element is arranged in a matrix form, and a plurality of wirings are arranged for each pixel row and each pixel column. On the other semiconductor substrate, a circuit is formed that performs, for example, processing of a pixel signal read out from each pixel. In such semiconductor devices, the presence or absence of defects in any of the wirings affects the manufacturing yield, and therefore, in the manufacturing process of the semiconductor device, it is checked whether or not any of the wirings has defects before the semiconductor substrates are bonded. Citation list Patent Literature

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2021-103760 Summary of the invention

[0004] In the semiconductor device disclosed in Patent Document 1, it is necessary to take measures against electrostatic discharge (ESD) breakdown caused by the occurrence of surge in an inspection step during the manufacturing process.

[0005] A semiconductor device according to a first embodiment of the present disclosure includes a plurality of signal lines, a first inspection terminal, a detection circuit, a second inspection terminal, and a protection element. The plurality of signal lines extend along a first direction and are arranged in a second direction intersecting the first direction. The first inspection terminal is electrically connected to one end of each signal line and provides an inspection signal to each signal line. The detection circuit is electrically connected to the other end of each signal line and detects defects in any one signal line. The second inspection terminal provides a control signal for controlling the detection operation of the detection circuit. The protection element is electrically connected to the second inspection terminal and absorbs surges.

[0006] A semiconductor device according to a second embodiment of the present disclosure includes a semiconductor device according to the first embodiment, wherein a protection element is electrically connected between a second inspection terminal and a power supply line. In addition, a signal line, a first inspection terminal, a detection circuit, a second inspection terminal, and a protection element are arranged on a first surface side of a first substrate. In the first substrate, the first inspection terminal and the power supply line are electrically isolated from each other, and an inspection signal and a power supply are provided independently of each other.

[0007] A semiconductor device according to a third embodiment of the present disclosure includes the semiconductor device according to the second embodiment, wherein a second substrate is bonded to the first face side of the first substrate, and the second substrate includes a wiring electrically connecting the first check terminal and the power supply line to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] [ Figure 1 ] Figure 1 1 is a circuit block diagram showing a system of a solid-state imaging device mounted on a semiconductor device according to a first embodiment of the present disclosure. [ Figure 2 ] Figure 2 It is shown Figure 1 A circuit diagram of a pixel and a pixel circuit of a solid-state imaging device shown. [ Figure 3 ] Figure 3 It is shown Figure 1 FIG. 1 is a circuit block diagram of a system for inspecting a signal line (vertical signal line) of a solid-state imaging device shown in FIG. [ Figure 4 ] Figure 4 is Figure 1 The cross-sectional view of the main part of the substrate showing the step of inspecting the signal line in the manufacturing process of the solid-state imaging device shown. [ Figure 5 ] Figure 5 yes Figure 4 FIG. 1 is a schematic circuit diagram of an inspection system in which a signal line inspection step is shown. [ Figure 6 ] Figure 6 It is the final product after the manufacturing process is completed. Figure 1 The solid-state imaging device shown is Figure 4 The corresponding main part cross-sectional view. [ Figure 7 ] Figure 7 It is shown Figure 6 Schematic circuit diagram of, for example, a connection state of a check terminal, a signal line, a power supply line, and a protection element in the solid-state imaging device shown. [ Figure 8 ] Figure 8 is Figure 1 Schematic circuit diagram for explaining the first inspection method in the solid-state imaging device shown. [ Fig. 9 ] Fig. 9 is Figure 1 Schematic circuit diagram for explaining the second inspection method in the solid-state imaging device shown. [ Fig.10 ] Fig.10 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a second embodiment of the present disclosure. Figure 5 or Figure 7 The corresponding schematic circuit diagram. [ Fig.11 ] Fig.11 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a third embodiment of the present disclosure. Figure 5 or Figure 7 The corresponding schematic circuit diagram. [ Fig.12 ] Fig.12 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a fourth embodiment of the present disclosure. Figure 5 or Figure 7 The corresponding schematic circuit diagram. [ Fig.13 ] Fig.13 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a fifth embodiment of the present disclosure. Figure 5 or Figure 7 The corresponding schematic circuit diagram. [ Fig.14 ] Fig.14 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a sixth embodiment of the present disclosure. Figure 3 The corresponding circuit block diagram. [ Fig.15 ] Fig.15 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to a seventh embodiment of the present disclosure. Figure 3 The corresponding circuit block diagram. [ Fig.16 ] Fig.16 FIG. 1 is a diagram showing an inspection system of a solid-state imaging device mounted on a semiconductor device according to an eighth embodiment of the present disclosure. Figure 3 The corresponding circuit block diagram. DETAILED DESCRIPTION

[0009] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the description is carried out in the following order. 1. First Embodiment The first embodiment describes a first example in which the present technology is applied to a solid-state imaging device mounted on a semiconductor device. In the first embodiment, the following configurations will be described, which include, for example, a system configuration of the solid-state imaging device, a circuit configuration of pixels and pixel circuits, a configuration of an inspection system, and a cross-sectional configuration of the solid-state imaging device during and after an inspection step in a manufacturing process of the solid-state imaging device. In addition, the first embodiment describes the configuration of a protection element included in the inspection system. 2. Second Embodiment The second embodiment explains a first example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 3. Third embodiment The third embodiment explains a second example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 4. Fourth embodiment The fourth embodiment explains a third example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 5. Fifth embodiment The fifth embodiment explains a fourth example in which the configuration of the protection element is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 6. Sixth embodiment The sixth embodiment explains a fifth example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 7. Seventh embodiment The seventh embodiment explains a sixth example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 8. Eighth Embodiment The eighth embodiment explains a seventh example in which the configuration of the inspection system is changed in the solid-state imaging device mounted on the semiconductor device according to the first embodiment. 9. Other embodiments <1. First Embodiment>

[0010] refer to Figures 1 to 9 A semiconductor device 1 according to a first embodiment of the present disclosure will be described. Here, for convenience, the arrow X direction appropriately shown in the figure represents one plane direction of the semiconductor device 1 placed on the plane. The arrow Y direction represents another plane direction orthogonal to the arrow X direction. In addition, the arrow Z direction represents an upward direction orthogonal to the arrow X direction and the arrow Y direction. That is, the arrow X direction, the arrow Y direction, and the arrow Z direction just coincide with the X-axis direction, the Y-axis direction, and the Z-axis direction of the three-dimensional coordinate system, respectively. It should be noted that these directions are shown to aid in understanding the description and are not intended to limit the directions used in the present technology. [Structure of Semiconductor Device 1] (1) Overall Structure of Semiconductor Device 1 and Solid-State Image Capture Device 2

[0011] Figure 1 An example of a system configuration of the solid-state imaging device 2 mounted on the semiconductor device 1 according to the first embodiment is shown. like Figure 1 As shown, a back-illuminated solid-state imaging device 2 is mounted on the semiconductor device 1 according to the first embodiment. More specifically, the solid-state imaging device 2 is configured as a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor. The solid-state imaging device 2 includes a pixel region 3 and peripheral circuits. (2) Structure of the Pixel Region 3 of the Solid-State Image Capture Device 2

[0012] In the pixel region 3 , signal lines VL, signal lines HL, and pixels 30 are arranged. The signal line VL is used as a vertical signal line and extends, for example, in the arrow Y direction which is the column direction, and a plurality of signal lines VL are arranged at equal intervals in the arrow X direction which is the row direction. On the other hand, the signal line HL is used as a driving signal line. The signal line HL extends in the arrow X direction, for example, and a plurality of signal lines HL are arranged at equal intervals in the arrow Y direction. Here, the "first direction" according to the present technology corresponds to the arrow Y direction, and the "second direction" according to the present technology corresponds to the arrow X direction. It should be noted that in the present technology, the "first direction" and the "second direction" can be interchangeable, and the "first direction" can be the arrow X direction, and the "second direction" can be the arrow Y direction.

[0013] Each pixel 30 is arranged at an intersection of one of the signal lines VL and one of the signal lines HL. That is, a plurality of pixels 30 are arranged in the arrow X direction and the arrow Y direction, respectively. The pixels 30 each include a photoelectric conversion element. The photoelectric conversion element converts incident light into electric charges and accumulates the electric charges. It should be noted that the circuit configuration of each pixel 30 and the pixel circuit 5 will be described below. (3) Configuration of Peripheral Circuits of Solid-State Image Pickup Device 2

[0014] The peripheral circuit of the solid-state imaging device 2 includes, for example, a row selector 41 , a constant current source 42 , an analog-to-digital converter 43 , a horizontal transfer scanner 44 , a signal processor 45 , and a timing controller 46 .

[0015] The row selector 41 has a shift register, an address decoder, etc. The row selector 41 scans the signal lines HL arranged in the pixel area 3 in the direction of arrow Y, and selects pixels 30 by row. Although a detailed description of the configuration is omitted, the row selector 41 includes, for example, two scanning systems, namely, a readout scanning system and a clear scanning system.

[0016] The readout scanning system sequentially selects and scans the pixels 30 in units of rows in the pixel area 3, and reads out pixel signals accumulated in the pixels 30. The pixel signals read out from the pixels 30 include analog signals. The clean-out scanning system performs a clean-out scan row by row on pixels 30 to be read-out scanned by the read-out scanning system at a time earlier than the read-out scanning by the shutter speed. By the clearing scan performed by the clearing scanning system, unnecessary charges are cleared from the photoelectric conversion element of each pixel 30 to be read out, and the photoelectric conversion element is reset. By this resetting, the so-called electronic shutter operation is performed. Here, the electronic shutter operation includes an operation of discarding the charge of the photoelectric conversion element and restarting exposure. In other words, the electronic shutter operation includes an operation of starting to accumulate charge in the photoelectric conversion element.

[0017] The constant current source 42 is connected to each signal line VL and supplies bias current to the pixels 3 in rows selected by the row selector 41 through the corresponding signal line VL. The constant current source 42 includes a plurality of current sources, each of which includes, for example, an insulated-gate field-effect transistor (IGFET). Here, the use of IGFET includes at least metal-oxide-semiconductor field-effect transistor (MOSFET: metal-oxide-semiconductor field-effect transistor) and metal-insulator-semiconductor field-effect transistor (MISFET: metal-insulator-semiconductor field-effect transistor).

[0018] The AD converter 43 includes a plurality of AD converters arranged for respective pixel columns in the pixel region 3. The AD converter 43 is a column parallel type AD converter that converts an analog pixel signal output through a signal line VL for each pixel column into an N-bit digital signal. As the AD converter 43, for example, a single slope AD converter which is an example of a reference signal comparison AD converter can be used. Alternatively, as the AD converter 43, a successive approximation AD converter, a delta-sigma modulation type (ΔΣ modulation type) AD converter, etc. can be used.

[0019] The horizontal transfer scanner 44 includes a shift register, an address decoder, etc. The horizontal transfer scanner 44 controls the scanning of the pixel columns and the addresses of the pixel columns when the signals of the pixels 30 in the pixel region 3 are to be read out. Under the control of the horizontal transfer scanner 44, the pixel signals converted into digital signals by the analog-to-digital converter 43 are read out to the horizontal transfer lines HTL having a width of 2N bits in units of pixel columns.

[0020] The signal processor 45 performs predetermined signal processing on the digital pixel signal provided through the horizontal transmission line HTL to generate two-dimensional image data. For example, the signal processor 45 corrects vertical line defects, point defects, etc. on the pixel signal, or performs signal processing such as signal clamping. In addition, the signal processor 45 can perform signal processing on the pixel signal, and the signal processing includes, for example, parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processor 45 outputs the generated image data as an output signal of the solid-state image pickup device 2 to a subsequent device not shown.

[0021] The timing controller 46 generates various timing signals, clock signals, control signals, etc. The timing controller 46 drives and controls the row selector 41, the constant current source 42, the analog-to-digital converter 43, the horizontal transfer scanner 44, the signal processor 45, etc. based on the generated signals. (4) Structure of pixel 30 and pixel circuit 5

[0022] Figure 2 An example of the circuit configuration of the pixel 30 and the pixel circuit 5 is shown. The pixel 30 includes a photoelectric conversion element 31. The photoelectric conversion element 31 converts incident light into electric charges and accumulates the electric charges. Here, the photoelectric conversion element 31 includes a photodiode. It should be noted that the photoelectric conversion element 31 may include a plurality of photodiodes. Alternatively, the photoelectric conversion element 31 may include an organic photoelectric conversion layer. Furthermore, the photoelectric conversion element 31 may include a photodiode and an organic photoelectric conversion layer.

[0023] Here, the pixel circuit 5 includes a transfer transistor 51 , an amplification transistor 52 , a selection transistor 53 , and a reset transistor 54 .

[0024] One of the pair of main electrodes of the transfer transistor 51 is electrically connected to the cathode electrode of the photoelectric conversion element 31. The anode electrode of the photoelectric conversion element 31 is grounded. The ground is, for example, 0 [V]. The other of the pair of main electrodes of the transfer transistor 51 is electrically connected to the gate electrode of the amplifier transistor 52 through the floating diffusion portion FD. One of the pair of main electrodes of the amplifier transistor 52 is electrically connected to the power supply line V3 . The other of the pair of main electrodes of the amplifier transistor 52 is electrically connected to one of the pair of main electrodes of the selection transistor 53 . The other of the pair of main electrodes of the selection transistor 53 is electrically connected to a corresponding signal line (vertical signal line) VL. One of the pair of main electrodes of the reset transistor 54 is electrically connected to the floating diffusion FD. The other of the pair of main electrodes of the reset transistor 54 is electrically connected to the power supply line V4.

[0025] In the first embodiment, the same voltage is supplied to the power line V3 and the power line V4. The voltage supplied to the power line V3 and the power line V4 is, for example, 3 [V] or more and 5 [V] or less. (5) Check the structure of system 6

[0026] Figure 3 An example of a circuit configuration of the inspection system 6 of the signal line VL is shown. In the first embodiment, the inspection system 6 is arranged on the first surface 8A side of the first substrate 8 (see Figure 4 and Figure 6 ). The first substrate 8 is formed based on a semiconductor substrate such as a single crystal silicon substrate. The pixels 30 and the pixel circuit 5 are arranged on a second surface 8B of the first substrate 8 opposite to the first surface 8A (see Figure 4 and Figure 6 ). In addition, the second substrate 9 is bonded to the first surface 8A side of the first substrate 8. The above-mentioned peripheral circuit is arranged on the second substrate 9. Next, a specific configuration of the solid-state image pickup device 2 will be described.

[0027] The inspection system 6 includes, as main components, a signal line VL, an application circuit 61 , a first inspection terminal 62 , a first inspection terminal 63 , a detection circuit 65 , a second inspection terminal 66 , a second inspection terminal 67 , and a second inspection terminal 68 .

[0028] As described above, the signal line VL is a vertical signal line extending in the arrow Y direction in the pixel region 3, and a plurality of signal lines VL are arranged in the arrow X direction. At one end of each signal line VL in the extending direction, a node region N1 is arranged for each signal line VL. In addition, at the other end of each signal line VL in the extending direction, a node region N2 is arranged for each signal line VL. The node region N1 and the node region N2 are electrically connected to the peripheral circuit at a stage where the second substrate 9 and the first substrate 8 are bonded to each other.

[0029] The applying circuit 61 is electrically connected to one end of each signal line VL. The applying circuit 61 includes a plurality of IGFETs 611 as current sources, which are arranged for each corresponding signal line VL. One of a pair of main electrodes of each IGFET 611 is electrically connected to the corresponding signal line VL. The other of a pair of main electrodes of each IGFET 611 is electrically connected to a first inspection terminal 62 arranged adjacent to the applying circuit 61. The first inspection terminal 62 is shared by a plurality of IGFETs. An inspection signal is provided to the first inspection terminal 62. Furthermore, the gate electrode of each IGFET 611 is electrically connected to a first inspection terminal 63. The first inspection terminal 63 is arranged adjacent to the applying circuit 61 and is shared by a plurality of IGFETs 611. In the inspection step, a control signal for controlling the current supply operation of the applying circuit 61 is supplied to the first inspection terminal 63.

[0030] The detection circuit 65 is electrically connected to the other ends of the plurality of signal lines VL. The detection circuit 65 includes an IGFET 651 arranged for each signal line VL and an IGFET 652 arranged for each signal line VL. The detection circuit 65 is configured as an open-circuit type detection circuit that detects a disconnection defect of any signal line VL. One of the pair of main electrodes of each IGFET 651 is electrically connected to the corresponding signal line VL The other of the pair of main electrodes of each IGFET 651 is electrically connected to the gate electrode of the corresponding IGFET 652 . Furthermore, the gate electrode of each IGFET 651 is electrically connected to a second inspection terminal 68. The second inspection terminal 68 is arranged adjacent to the detection circuit 65 and is shared by a plurality of IGFETs 651. In the inspection step, a control signal for controlling the detection operation of the detection circuit 65 is supplied to the second inspection terminal 68.

[0031] One of the pair of main electrodes of each IGFET 652 is electrically connected to the other of the pair of main electrodes of another adjacent IGFET 652. The other of the pair of main electrodes of each IGFET 652 is electrically connected to one of the pair of main electrodes of another adjacent IGFET 652. That is, a plurality of IGFETs 652 arranged for each corresponding signal line VL are electrically connected in series. One of a pair of main electrodes of the IGFET 652 electrically connected in series at one end of the IGFET 652 is electrically connected to the second inspection terminal 66. The other of a pair of main electrodes of the IGFET 652 electrically connected in series at the other end of the IGFET 652 is electrically connected to the second inspection terminal 67. A detection signal for detecting whether the signal line VL is good or bad is supplied to the second inspection terminal 66 , while a detection result is output to the second inspection terminal 67 .

[0032] Furthermore, at least one of the first check terminal 62 and the first check terminal 63 may be arranged in a region assumed to be within the applying circuit 61 . Likewise, at least one of the second check terminal 66 , the second check terminal 67 , and the second check terminal 68 may be arranged in a region assumed to be within the detection circuit 65 . (6) Structure of protection element 7

[0033] The inspection system 6 is provided with a protection element 7, which will be described in detail below. In the first embodiment, the protection element 7 is electrically connected to the second check terminal 68. More specifically, the protection element 7 is inserted between the gate electrode of the IGFET 651 of the detection circuit 65 and the second check terminal 68.

[0034] The protection element 7 includes a first protection element 71 and a second protection element 72. The first protection element 71 has a protection diode. The anode electrode of the first protection element 71 is electrically connected to the second inspection terminal 68. The cathode electrode of the first protection element 71 is electrically connected to the first power supply line V1. That is, the first protection element 71 is electrically connected in parallel between the gate electrode of the IGFET 651 and the second inspection terminal 68.

[0035] The first power line V1 is electrically connected to the third inspection terminal 73. In the inspection step, the first power line V1 and the third inspection terminal 73 are arranged on the first substrate 8, and are electrically isolated from the first inspection terminal 62 because the second substrate 9 is not bonded. That is, the inspection signal supplied to the first inspection terminal 62 and the power supplied to the first power line V1 through the third inspection terminal 73 are respectively independently supplied. When the second substrate 9 is bonded to the first substrate 8 after the inspection step and the solid-state image pickup device 2 is completed as a final product, the first inspection terminal 62 and the first power supply line V1 are electrically connected to each other. The voltage supplied to the third inspection terminal 73 is, for example, 3 [V] or more and 5 [V] or less. The first protection element 71 defines an upper limit of a surge, and absorbs a surge exceeding the upper limit.

[0036] The second protection element 72 has a protection diode similar to the first protection element 71. The cathode electrode of the second protection element 72 is electrically connected to the second inspection terminal 68. The anode electrode of the second protection element 72 is electrically connected to the second power supply line V2. That is, the second protection element 72 is electrically connected in parallel between the gate electrode of the IGFET 651 and the second inspection terminal 68.

[0037] The second power line V2 is electrically connected to the third inspection terminal 74. In the inspection step, the second power line V2 and the third inspection terminal 74 may be independent of the power terminal (not shown) of the peripheral circuit similarly to the first power line V1 and the third inspection terminal 73. Alternatively, the second power line V2 and the third inspection terminal 74 may not be independent of the power terminal (not shown) of the peripheral circuit. The voltage supplied to the third check terminal 74 is, for example, 0 [V]. The second protection element 72 defines a lower limit of surges, and absorbs surges below the lower limit. (7) Longitudinal Sectional Structure of Solid-State Image Pickup Device 2 and Circuit Structure of Inspection System 6 in Inspection Step

[0038] Figure 4 An example of a main portion of the substrate 8 showing an inspection step of the signal line VL in the manufacturing process of the solid-state imaging device 2 is shown. Figure 5 An example of a schematic circuit configuration of the inspection system 6 in the inspection step of the signal line VL is shown.

[0039] In the inspection step of the solid-state imaging device 2, although Figure 4 6, but the applying circuit 61 and the detecting circuit 65 are arranged in the first substrate 8. The inspection step is a so-called probe inspection step. In the inspection step of the open circuit method, the disconnection defect of the signal line VL is detected.

[0040] A multilayer wiring 801 and a wiring 803 are arranged on the first face 8A side of the first substrate 8. The wiring 801 is formed by stacking a wiring 801A including, for example, copper (Cu) and a barrier metal film 801B arranged on the surface of the wiring 801A. As the barrier metal film 801B, for example, a metal material such as tungsten (W) or titanium tungsten (TiW) is used. The wiring 803 includes, for example, a wiring material such as copper (Cu). Further, the wiring 801 and the wiring 803 are electrically connected to each other through a plug wiring 802. The plug wiring 802 includes, for example, a metal material such as tungsten (W). The wiring 801, the plug wiring 802, and the wiring 803 are arranged in the insulator 805. The insulator 805 is actually formed by forming a silicon oxide (SiO 2 ) and silicon nitride (SiN) and other insulating films are stacked in multiple layers. The insulator 805 corresponds to the "first insulator" in this technology.

[0041] Figures 3 to 5The first inspection terminal 62, the first inspection terminal 63, the second inspection terminal 66, the second inspection terminal 67, the second inspection terminal 68, the third inspection terminal 73, and the third inspection terminal 74 of the inspection system 6 shown are formed using the wiring 801. Here, the expression "formed using the wiring 801" is used to mean that the first inspection terminal 62 and the like are formed in the same manufacturing process as the process of forming the wiring 801. Although Figure 4 Only the cross sections of the first check terminal 62 and the third check terminal 73 are shown, but the other first check terminals 63 and the like have similar cross-sectional configurations. Furthermore, the first check terminal 62 and the like are formed to have a wiring width wider than that of the wiring 801 and the like.

[0042] The surfaces of the first inspection terminal 62, the second inspection terminal 68, etc. are exposed through the corresponding inspection openings 805H formed in the insulator 805. In the inspection openings 805H, the barrier metal film 801B on the respective surfaces of the first inspection terminal 62, the second inspection terminal 68, etc. is removed.

[0043] like Figure 4 As shown, the probe 10 is brought into contact with the surfaces of the first inspection terminal 62, the second inspection terminal 68, etc., and the disconnection defect of the signal line VL is detected by the inspection step of the open circuit method. A specific inspection method will be described below.

[0044] In the inspection step, since the protection element 7 is arranged in the inspection system 6, when a surge occurs, the surge is absorbed by the protection element 7. This makes it possible to improve the electrostatic breakdown voltage in the inspection step, thereby improving the manufacturing yield of the solid-state imaging device 2.

[0045] Furthermore, in the inspection step, in particular, the first inspection terminal 62 located near the application circuit 61 and the first power line V1 (third inspection terminal 73) connected to the protection element 7 can be electrically separated from each other within the first substrate 8. Therefore, the first inspection terminal 62 and the first power line V1 (third inspection terminal 73) can independently supply the inspection signal and the power supply, respectively. This enables an inspection step of changing the inspection signal supplied to the first inspection terminal 62 (e.g., changing the voltage).

[0046] Furthermore, since the barrier metal film 801B is not formed on the surface of the first inspection terminal 62 and the like, the contact resistance between the surface of the first inspection terminal 62 and the like and the probe needle 10 can be reduced. In addition, probe marks caused by contact of the probe 10 remain on the surface of the first inspection terminal 60 and the like. (8) Longitudinal Section Structure of Solid-State Image Pickup Device 2 and Circuit Structure of Inspection System 6 as Final Products

[0047] Figure 6 An example of the main part of the solid-state image pickup device 2 as a final product is shown. Figure 7 Shows Figure 6 An example of a schematic circuit configuration of the inspection system 6 in the solid-state imaging device 2 is shown.

[0048] like Figure 6 As shown, the solid-state imaging device 2 is configured by bonding the second substrate 9 to the first surface 8A side of the first substrate 8 . Here, the pixel circuit 5 and the pixel 30 are sequentially arranged on the second surface 8B side of the first substrate 8. Each pixel 30 includes a photoelectric conversion element 31, a filter 35, and an optical lens 36 stacked in sequence. The color filter 35 includes, for example, a total of three color filters having different colors for each pixel 30. That is, the color filter 35 includes a red filter that transmits light in a red light band, a green filter that transmits light in a green light band, and a blue filter that transmits light in a blue light band. The color filter 35 includes, for example, a resin material containing a dye. The optical lens 36 is formed into a curved shape that curves toward the light incident side and condenses the incident light in the photoelectric conversion element 31. The optical lens 36 is formed as a so-called on-chip lens and is formed for each pixel 30 or integrally formed on a plurality of pixels 30. The optical lens 36 includes, for example, a transparent resin material.

[0049] As described above, the second substrate 9 includes a semiconductor substrate and a peripheral circuit (detailed description of the configuration thereof will be omitted), and also includes a wiring 901, a plug wiring 902, a wiring 903, etc. Each of the wiring 901, the plug wiring 902, and the wiring 903 includes, for example, the same material as each of the wiring 801, the plug wiring 802, and the wiring 803. In addition, the wiring 901, etc. are arranged in an insulator 905.

[0050] When the second substrate 9 is bonded, the inspection opening 805H of the first substrate 8 is filled with a buried insulator 806. The buried insulator 806 corresponds to the "second insulator" of the present technology. The uppermost wiring 803 of the first substrate 8 and the uppermost wiring 903 of the second substrate 9 are bonded to each other to bond the second substrate 9 to the first substrate 8. Thus, the solid-state imaging device 2 is constructed. The bonding includes, for example, Cu-Cu bonding. Here, if Figure 6 and Figure 7 As shown, when the second substrate 9 is bonded to the first substrate 8 , the first inspection terminal 62 of the inspection system 6 of the first substrate 8 and the first power line V1 are electrically connected to each other by the wiring 901 of the second substrate 9 . [Signal line VL inspection method]

[0051] Next, we will refer to Figure 8 and Fig. 9 The inspection method using the above-mentioned inspection system 6 is briefly described. (1) Inspection method of the first inspection method

[0052] Figure 8 An example of a schematic circuit configuration for explaining the first inspection mode is shown. exist Figure 8 In the first inspection mode shown, the detection circuit 65 of the inspection system 6 includes the above-mentioned circuit. That is, the detection circuit 65 includes an AND circuit.

[0053] First, a low-level signal (hereinafter referred to as “L signal”) as a check signal is supplied to the first check terminal 62. Subsequently, a high-level signal (hereinafter referred to as “H signal”) as a control signal is supplied to the first check terminal 63. This resets all signal lines VL to L signals. Thereafter, an H signal is supplied to the first check terminal 62, and an H signal is supplied to the first check terminal 63. This causes all the signal lines VL to become H signals.

[0054] In the detection circuit 65, an H signal as a control signal is supplied to the second check terminal 68. Subsequently, an H signal as a detection signal is supplied to the second check terminal 66. As a result, each IGFET 651 and each IGFET 652 are in an on state, and the detection signal supplied to the second check terminal 66 is detected at the second check terminal 67. When there is no disconnection defect in all the signal lines VL, the detection signal detected at the second check terminal 67 is equal to the detection signal supplied to the second check terminal 66.

[0055] Here, if Figure 8 As shown by the mark “×” in FIG. 1 , when a disconnection defect occurs in one of the signal lines VL, the IGFET 652 connected to the signal line VL is in the off state. Therefore, the detection signal supplied to the second inspection terminal 66 is not detected at the second inspection terminal 67 . (2) Inspection method of the second inspection method

[0056] Fig. 9 An example of a schematic circuit configuration for explaining the second inspection mode is shown. exist Fig. 9 In the second inspection mode shown, the detection circuit 65 of the inspection system 6 includes an OR circuit. That is, the IGFET 652 is electrically connected in parallel between the second inspection terminal 66 and the second inspection terminal 67.

[0057] First, an H signal as a check signal is supplied to the first check terminal 62, and an H signal as a control signal is supplied to the first check terminal 63. This resets all the signal lines VL to an H signal. Thereafter, an L signal is supplied to the first check terminal 63 , thereby disconnecting the first check terminal 62 from the signal line VL.

[0058] In the detection circuit 65, an H signal as a control signal is supplied to the second inspection terminal 68. Subsequently, an H signal as a detection signal is supplied to the second inspection terminal 66. As a result, the IGFET 651 is in an on state, and the IGFET 652 is in an off state. When there is no disconnection defect in all the signal lines VL, no detection signal is detected at the second inspection terminal 67.

[0059] Here, if Fig. 9 As shown by the mark “×” in FIG. 1 , when a disconnection defect occurs in one of the signal lines VL, the IGFET 652 connected to the signal line VL is turned on. Therefore, the detection signal supplied to the second inspection terminal 66 is detected at the second inspection terminal 67 . [Function and Effect]

[0060] like Figure 3 , Figure 5 and Figure 7 As shown, the semiconductor device 1 according to the first embodiment includes a signal line VL, an application circuit 61 , a first check terminal 62 , a detection circuit 65 , and a second check terminal 68 . A plurality of signal lines VL extend along a first direction and are arranged in a second direction intersecting the first direction. An application circuit 61 is electrically connected to one end of each signal line VL and provides an inspection signal to each signal line VL. A first inspection terminal 62 provides an inspection signal to the application circuit 61. A detection circuit 65 is electrically connected to the other end of each signal line VL and detects a defect in any one of the signal lines VL. A second inspection terminal 68 provides a control signal for controlling the detection operation of the detection circuit 65. Here, the semiconductor device 1 further includes a protection element 7. The protection element 7 is electrically connected to the second check terminal 68, and absorbs surge. Therefore, in the inspection step, surge is absorbed by the protection element 7, so that the semiconductor device 1 capable of improving the electrostatic breakdown voltage can be provided. In the first embodiment, the solid-state imaging device 2 is mounted on the semiconductor device 1, so the solid-state imaging device 2 capable of improving the electrostatic breakdown voltage can be provided. In other words, it is possible to provide the semiconductor device 1 or the solid-state imaging device 2 capable of reducing the manufacturing yield.

[0061] Specifically, the protection element 7 is electrically connected between the second inspection terminal 68 and the power supply line. More specifically, the detection circuit 65 includes an IGFET 651, each of which has one of a pair of main electrodes electrically connected to the other end of the corresponding signal line VL and a gate electrode electrically connected to the second inspection terminal 68. The protection element 7 is electrically connected in parallel between the second inspection terminal 68 and the gate electrode. The power line includes a first power line V1 and a second power line V2. The power supplied to the second power line V2 is lower than the power supplied to the first power line V1. The protection element 7 includes a first protection element 71 electrically connected between the second check terminal 68 and the first power line V1, and a second protection element 72 electrically connected between the second check terminal 68 and the second power line V2. The protection element 7 includes a protection diode. In the semiconductor device 1 configured as described above, in the inspection step, positive surge and negative surge can be reliably absorbed by the first protection element 71 and the second protection element 72 , and thus the electrostatic breakdown voltage can be further improved.

[0062] Furthermore, in the semiconductor device 1, as Figure 3 , Figure 4 and Figure 6 As shown, the signal line VL, the applying circuit 61, the first check terminal 62, the detecting circuit 65, the second check terminal 68 and the protection element 7 are arranged on the first surface 8A side of the first substrate 8. In the first substrate 8, the first check terminal 62 and the power line (first power line V1) are electrically isolated from each other, and the check signal and the power supply are independently provided. Therefore, in the inspection step, an inspection signal of a different level from the power supplied to the power line can be provided to the first inspection terminal 62. This makes it possible to increase the degree of freedom of inspection. Specifically, for the power supplied to the first power line V1, the inspection step can be performed using an inspection signal having the same voltage level, a low voltage level, or a high voltage level. <2. Second Embodiment>

[0063] Reference Fig.10 A semiconductor device 1 according to a second embodiment of the present disclosure will be described. Furthermore, in the second embodiment and the subsequent embodiments, the same reference numerals are used to denote components that are the same as or substantially the same as those of the semiconductor device 1 according to the first embodiment, and duplicate description thereof will be omitted. [Construction of inspection system 6]

[0064] Fig.10 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. In the inspection system 6 according to the second embodiment, the application circuit 61 in the inspection system 6 according to the first embodiment is omitted. Detailed description is given below.

[0065] As described above, the pixel circuit 5 is arranged on the first substrate 8. The pixel circuit 5 is provided with the power supply line V3 and the power supply line V4. In the second embodiment, the same power supply is supplied to the power supply line V3 and the power supply line V4. On the first surface 8A of the first substrate 8, although the arrangement position is not particularly limited, the power terminal 62A electrically connected to the power line V3 and the power line V4 is arranged in the peripheral portion. In the second embodiment, the power terminal 62A is used as the first inspection terminal 62 according to the first embodiment in the inspection step.

[0066] In a specific pixel circuit 5, the power supply line V3 is electrically connected to the corresponding signal line VL through the amplifier transistor 52 and the selection transistor 53 inserted therebetween. The power supply line V4 is electrically connected to the gate electrode of the amplifier transistor 52 through the reset transistor 54 inserted therebetween. That is, by controlling the amplifier transistor 52, the selection transistor 53, and the reset transistor 54 so that they are in an on state, the pixel circuit 5 can be used as an application circuit 61, and a check signal is supplied to the signal line VL.

[0067] The inspection system 6 constructed as described above allows the application circuit 61 to be omitted. After the inspection step, the second substrate 9 is bonded to the first substrate 8 so that the power supply terminal 62A and the first power supply line V1 of the protection element 7 are electrically connected to each other using the wiring 901 of the second substrate 9.

[0068] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to the first embodiment, description thereof will be omitted. [Function and Effect]

[0069] The semiconductor device 1 according to the second embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the first embodiment.

[0070] Furthermore, in the semiconductor device 1, as Fig.10 As shown, a specific pixel circuit 5 of the solid-state imaging device 2 can be used as the application circuit 61 according to the first embodiment. This makes it possible to effectively use the first substrate 8 by the portion corresponding to the application circuit 61 and improve the integration of the semiconductor device 1 and the solid-state imaging device 2. <3. Third embodiment>

[0071] Reference Fig.11 A semiconductor device 1 according to a third embodiment of the present disclosure will be described. [Construction of inspection system 6]

[0072] Fig.11 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. In the inspection system 6 according to the third embodiment, the application circuit 61 is omitted similarly to the inspection system 6 according to the second embodiment. This will be described in detail below.

[0073] As described above, the pixel circuit 5 is arranged on the first substrate 8. The pixel circuit 5 is provided with a power line V3 and a power line V4. In the third embodiment, the power line V3 and the power line V4 are electrically isolated from each other. That is, the power supplied to the power line V4 is supplied independently from the power supplied to the power line V3. On the first surface 8A of the first substrate 8, although the arrangement position is not particularly limited, the power terminal 62B electrically connected to the power line V3 is arranged in the peripheral portion, and the power terminal 62C electrically connected to the power line V4 is also arranged in the peripheral portion. In the third embodiment, for example, the power terminal 62B is used as the first inspection terminal 62 according to the first embodiment in the inspection step, and the power terminal 62C is used as the first inspection terminal 63 according to the first embodiment in the inspection step.

[0074] In a specific pixel circuit 5, the power supply line V3 is electrically connected to the corresponding signal line VL through the amplifier transistor 52 and the selection transistor 53 inserted therebetween. The power supply line V4 is electrically connected to the gate electrode of the amplifier transistor 52 through the reset transistor 54 inserted therebetween. That is, by controlling the amplifier transistor 52, the selection transistor 53, and the reset transistor 54 so that they are in an on state, the pixel circuit 5 can be used as an application circuit 61, and a check signal is supplied to the signal line VL.

[0075] The inspection system 6 constructed as described above enables the application circuit 61 to be omitted. After the inspection step, the second substrate 9 is bonded to the first substrate 8 so that the power terminals 62B and 62C are electrically connected to the first power lines V1 of the protection element 7 using the wirings 901 of the second substrate 9, respectively.

[0076] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to the second embodiment, description thereof will be omitted. [Function and Effect]

[0077] The semiconductor device 1 according to the third embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the second embodiment.

[0078] Furthermore, in the semiconductor device 1, as Fig.11As shown, in the inspection step, power can be supplied to each of the power supply terminal 62B and the power supply terminal 62C independently. Therefore, the timing of supplying the inspection signal to the signal line VL can be easily adjusted. <4. Fourth embodiment>

[0079] Reference Fig.12 A semiconductor device 1 according to a fourth embodiment of the present disclosure will be described. [Construction of inspection system 6]

[0080] Fig.12 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. The inspection system 6 according to the fourth embodiment is an application example of the inspection system 6 according to the second embodiment, and similarly the application circuit 61 is omitted. Detailed description is given below.

[0081] The pixel circuit 5 is arranged on the first substrate 8. The pixel circuit 5 is provided with a power supply line V3 and a power supply line V4. In the fourth embodiment, the same power supply is supplied to the power supply line V3 and the power supply line V4. On the first surface 8A of the first substrate 8, although the arrangement position is not particularly limited, the power supply terminal 62D electrically connected to the power supply line V3 and the power supply line V4 of the specific pixel circuit 5A is arranged in the peripheral portion. The pixel circuit 5A is arranged in a row unit and, for example, is arranged in the middle portion of the pixel region 3. Furthermore, a power supply terminal 62E electrically connected to the power supply line V3 and the power supply line V4 of another specific pixel circuit 5B is arranged. The pixel circuits 5B are arranged in a row unit in a region other than the row having the pixel circuits 5A. In the fourth embodiment, in the inspection step, the power supply terminal 62D and the power supply terminal 62E are used as the first inspection terminals 62 according to the first embodiment.

[0082] The inspection system 6 constructed as described above enables the application circuit 61 to be omitted. After the inspection step, the second substrate 9 is bonded to the first substrate 8 so that the power terminals 62D and 62E are electrically connected to the first power lines V1 of the protection element 7 using the wirings 901 of the second substrate 9, respectively.

[0083] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to the second embodiment, description thereof will be omitted. [Function and Effect]

[0084] The semiconductor device 1 according to the fourth embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the second embodiment.

[0085] Furthermore, in the semiconductor device 1, as Fig.12 As shown, power can be supplied to each of the power supply terminal 62D and the power supply terminal 62E independently in the inspection step. This makes it possible to independently perform at least one of the row-by-row inspection step including the pixel circuit 5A or the row-by-row inspection step including the pixel circuit 5B. As a result, the scope of the inspection method can be expanded. <5. Fifth embodiment>

[0086] Reference Fig.13 A semiconductor device 1 according to a fifth embodiment of the present disclosure will be described. [Construction of inspection system 6]

[0087] Fig.13 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. In the inspection system 6 according to the fifth embodiment, the configuration of the protection element 7 of the inspection system 6 according to the first embodiment is changed. This will be described in detail below.

[0088] The protection element 7 includes a first protection element 75 and a second protection element 76 . The first protection element 75 has a protection transistor. Specifically, the first protection element 75 has, for example, a GGMOS (Gate-Grounded Metal-Oxide Semiconductor). One of a pair of main electrodes of the first protection element 75 is electrically connected to the second inspection terminal 68, and the other of the pair of main electrodes is electrically connected to the first power line V1. Its gate electrode is electrically connected to the first power line V1. The second protection element 76 also has a protection transistor, for example, a GGMOS. One of a pair of main electrodes of the second protection element 76 is electrically connected to the second inspection terminal 68, and the other of the pair of main electrodes is electrically connected to the second power supply line V2. Its gate electrode is electrically connected to the second inspection terminal 68.

[0089] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to any one of the first to fourth embodiments, description thereof will be omitted. [Function and Effect]

[0090] The semiconductor device 1 according to the fifth embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of any one of the first to fourth embodiments.

[0091] Furthermore, in the semiconductor device 1, as Fig.13As shown, the protection element 7 of the inspection system 6 includes a protection transistor. The anti-static breakdown capability of the protection transistor is generally higher than the anti-static breakdown capability of the protection diode. Therefore, it is possible to provide the semiconductor device 1 and the solid-state imaging device 2 capable of further improving the electrostatic breakdown voltage. <6. Sixth embodiment>

[0092] Reference Fig.14 A semiconductor device 1 according to a sixth embodiment of the present disclosure will be described. [Construction of inspection system 6] Fig.14 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. In the inspection system 6 according to the sixth embodiment, both the application circuit 61 and the detection circuit 65 in the inspection system 6 according to the first embodiment adopt a dual-system circuit configuration.

[0093] In the application circuit 61, IGFETs 611A connected to one of the signal lines VL and IGFETs 611B connected to the signal line VL adjacent in the direction of arrow X (row direction) are repeatedly arranged in the direction of arrow X. The plurality of IGFETs 611A are electrically connected in parallel, and the plurality of IGFETs 611B are electrically connected in parallel. One of the main electrodes of each IGFET 611A is electrically connected to the first inspection terminal 62F. The gate electrodes of the plurality of IGFETs 611A are electrically connected to the first inspection terminal 63A. One of the main electrodes of each IGFET 611B is electrically connected to the first inspection terminal 62G. The gate electrodes of the plurality of IGFETs 611B are electrically connected to the first inspection terminal 63B.

[0094] In the detection circuit 65, IGFETs 652A connected to one of the signal lines VL and IGFETs 652B connected to the signal line VL adjacent in the direction of arrow X (row direction) are repeatedly arranged in the direction of arrow X. A plurality of IGFETs 652A are electrically connected in series, and a plurality of IGFETs 652B are electrically connected in series. One of the main electrodes of IGFET 652A arranged at one end of the plurality of IGFETs 652A is electrically connected to second inspection terminal 66. The other end of the main electrode of IGFET 652A arranged at the other end of the plurality of IGFETs 652A is electrically connected to second inspection terminal 67. One of the main electrodes of IGFET 652B arranged at one end of the plurality of IGFETs 652B is electrically connected to second inspection terminal 66. The other end of the main electrode of IGFET 652B arranged at the other end of the plurality of IGFETs 652B is electrically connected to second inspection terminal 67.

[0095] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to any one of the first to fifth embodiments, description thereof will be omitted. [Function and Effect]

[0096] The semiconductor device 1 according to the sixth embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the first embodiment or the fifth embodiment.

[0097] Furthermore, in the semiconductor device 1, as Fig.14 As shown, the application circuit 61 and the detection circuit 65 of the inspection system 6 have a dual system circuit configuration. Although the description of the specific inspection method is omitted, the detection circuit 65 is configured as an open circuit detection circuit for detecting a disconnection defect of any signal line VL, and is also configured as a short circuit detection circuit for detecting a short circuit defect between adjacent signal lines VL. This enables the scope of the inspection method to be expanded. <7. Seventh embodiment>

[0098] Reference Fig.15 A semiconductor device 1 according to a seventh embodiment of the present disclosure will be described. [Construction of inspection system 6]

[0099] Fig.15 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. The inspection system 6 according to the seventh embodiment includes the inspection system 6 according to the sixth embodiment, in which the circuit configurations of the applying circuit 61 and the detecting circuit 65 are changed. Detailed description will be given below.

[0100] In the application circuit 61, similarly to the application circuit 61 according to the sixth embodiment, IGFETs 611A and IGFETs 611B are repeatedly arranged in the direction of arrow X. A plurality of IGFETs 611A are electrically connected in parallel, and a plurality of IGFETs 611B are electrically connected in parallel. One of the main electrodes of each IGFET 611A and one of the main electrodes of each IGFET 611B are electrically connected to a common first inspection terminal 62F. The gate electrodes of the plurality of IGFETs 611A are electrically connected to the first inspection terminal 63A. The gate electrodes of the plurality of IGFETs 611B are electrically connected to the first inspection terminal 63B.

[0101] In the detection circuit 65, similarly to the detection circuit 65 according to the sixth embodiment, IGFETs 652A and IGFETs 652B are repeatedly arranged in the direction of arrow X. A plurality of IGFETs 652A are electrically connected in series, and a plurality of IGFETs 652B are electrically connected in series. One of the main electrodes of the IGFET 652A arranged at one end of the plurality of IGFETs 652A is electrically connected to the second inspection terminal 66. Another of the main electrodes of the IGFET 652A arranged at the other end of the plurality of IGFETs 652A is electrically connected to the second inspection terminal 67. One of the main electrodes of the IGFET 652B arranged at one end of the plurality of IGFETs 652B is electrically connected to the second inspection terminal 66. Another of the main electrodes of the IGFET 652B arranged at the other end of the plurality of IGFETs 652B is electrically connected to the second inspection terminal 67.

[0102] In the detection circuit 65, an IGFET 651A connected to one of the signal lines VL and an IGFET 651B connected to a signal line VL adjacent to the direction of arrow X (row direction) are also repeatedly arranged in the direction of arrow X. One of the main electrodes of each IGFET 651A is electrically connected to the corresponding signal line VL. One of the main electrodes of each IGFET 651B is electrically connected to the adjacent signal line VL. The other of the main electrodes of each IGFET 651A and the other of the main electrodes of each IGFET 651B are electrically connected to the second inspection terminal 69. The gate electrode of the IGFET 651A is electrically connected to the second inspection terminal 68A. The gate electrode of the IGFET 651B is electrically connected to the second inspection terminal 68B.

[0103] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to the sixth embodiment, description thereof will be omitted. [Function and Effect]

[0104] The semiconductor device 1 according to the seventh embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the sixth embodiment.

[0105] Furthermore, in the semiconductor device 1, as Fig.15 As shown, IGFET 611A and IGFET 611B are connected to first inspection terminal 62F in application circuit 61 of inspection system 6. In detection circuit 65, IGFET 651A and IGFET 651B are arranged on signal line VL, and IGFET 651A and IGFET 651B are connected to second inspection terminal 69. Therefore, a short-circuit defect between adjacent signal lines VL can be detected by measuring the current flowing through the first inspection terminal 62F or the second inspection terminal 69. As a result, the scope of the inspection method can be expanded. <8. Eighth Embodiment>

[0106] Reference Fig.16 A semiconductor device 1 according to an eighth embodiment of the present disclosure will be described. [Construction of inspection system 6]

[0107] Fig.16 An example of a schematic circuit configuration of an inspection system 6 of a solid-state imaging device 2 mounted on a semiconductor device 1 is shown. The inspection system 6 according to the eighth embodiment includes the inspection system 6 according to the seventh embodiment, in which the circuit configuration of the applying circuit 61 is changed. Detailed description will be given below.

[0108] The applying circuit 61 includes a plurality of switch decoders 612 arranged on the signal line VL. A first check terminal 62 for supplying a check signal and a first check terminal 64 for supplying a control signal for controlling the supply operation are electrically connected to the switch decoders 612, respectively.

[0109] Since components other than the above are the same or substantially the same as those of the semiconductor device 1 according to the seventh embodiment, description thereof will be omitted. [Function and Effect]

[0110] The semiconductor device 1 according to the eighth embodiment can obtain the same actions and effects as those obtained by the semiconductor device 1 of the seventh embodiment.

[0111] Furthermore, in the semiconductor device 1, as Fig.16 As shown, the application circuit 61 of the inspection system 6 includes a switch decoder 612. Therefore, a disconnection defect of any signal line VL can be detected in predetermined line units. As a result, the scope of the inspection method can be expanded. <9. Other embodiments>

[0112] The present technology is not limited to the above-described embodiments, and may be modified in various ways without departing from the gist thereof. For example, the semiconductor devices according to two or more embodiments may be combined in the semiconductor device according to the first to eighth embodiments described above.

[0113] Furthermore, the present technology can be applied to an inspection system for a drive signal line. In this case, the "first direction" according to the present technology is interpreted as the "second direction", and the "second direction" is interpreted as the "first direction". Furthermore, the present technology can be applied to a semiconductor device in which three or more substrates are bonded. Furthermore, the present technology is not limited to the solid-state imaging device but can be widely applied to a semiconductor device having a plurality of signal lines and having a signal line inspection system. In addition, the present technology can constitute a protection element of the inspection system by combining two or more selected from a protection diode, a protection transistor, a protection resistor, and a protection capacitor.

[0114] A semiconductor device according to a first embodiment of the present disclosure includes a plurality of signal lines, a first check terminal, a detection circuit, and a second check terminal. A plurality of signal lines extend along a first direction and are arranged in a second direction intersecting the first direction. A first inspection terminal is electrically connected to one end of each signal line and provides an inspection signal to each signal line. A detection circuit is electrically connected to the other end of each signal line and detects a defect in any one of the signal lines. A second inspection terminal provides a control signal for controlling a detection operation of the detection circuit. Here, the semiconductor device further includes a protection element. The protection element is electrically connected to the second inspection terminal and absorbs surge. Therefore, in the inspection step, surge is absorbed by the protection element, so that the semiconductor device 1 capable of improving the electrostatic breakdown voltage can be provided.

[0115] A semiconductor device according to a second embodiment of the present invention includes the semiconductor device according to the first embodiment, wherein the protection element is electrically connected between the second inspection terminal and the power supply line. Furthermore, the signal line, the first inspection terminal, the detection circuit, the second inspection terminal and the protection element are arranged on the first surface side of the first substrate. In the first substrate, the first inspection terminal and the power supply line are electrically isolated from each other, and the inspection signal and the power supply are independently provided. Therefore, in the inspection step, an inspection signal of a level different from the power supplied to the power supply line can be supplied to the first inspection terminal. This makes it possible to improve the degree of freedom of inspection.

[0116] A semiconductor device according to a third embodiment of the present invention includes the semiconductor device according to the second embodiment, wherein a second substrate is bonded to the first face side of the first substrate, and the second substrate includes a wiring electrically connecting the first check terminal and the power supply line to each other. Therefore, in the inspection step, an inspection signal of a level different from the power supplied to the power supply line can be supplied to the first inspection terminal. This makes it possible to improve the degree of freedom of inspection. <Structure of this technology>

[0117] The present technology has the following configuration. According to the present technology having the following configuration, a semiconductor device capable of improving an electrostatic breakdown voltage in an inspection step can be provided. (1) A semiconductor device comprising: a plurality of signal lines extending along a first direction and arranged in a second direction intersecting the first direction; a first inspection terminal electrically connected to one end of the signal line and providing an inspection signal to the signal line; a detection circuit electrically connected to the other end of the signal line and detecting a defect in the signal line; a second inspection terminal which provides a control signal for controlling a detection operation of the detection circuit; and A protection element is electrically connected to the second check terminal and absorbs surge. (2) The semiconductor device according to (1), wherein the protection element is electrically connected between the second inspection terminal and a power supply line. (3) The semiconductor device according to (2), wherein: The detection circuit includes an insulated gate field effect transistor having a pair of main electrodes and a gate electrode, wherein one of the main electrodes is electrically connected to the other end of the signal line and the gate electrode is electrically connected to the second inspection terminal, and The protection element is electrically connected in parallel between the second inspection terminal and the gate electrode. (4) The semiconductor device according to (2) or (3), wherein: The power line includes a first power line and a second power line, the power supplied to the second power line is lower than the power supplied to the first power line, and The protection element includes a first protection element and a second protection element, the first protection element is electrically connected between the second check terminal and the first power line, and the second protection element is electrically connected between the second check terminal and the second power line. (5) The semiconductor device according to any one of (2) to (4), wherein the protection element is a protection diode. (6) The semiconductor device according to any one of (2) to (4), wherein the protection element is a protection transistor. (7) The semiconductor device according to any one of (2) to (6), wherein the signal line, the first check terminal, the detection circuit, the second check terminal, and the protection element are arranged on the first surface side of the first substrate. (8) The semiconductor device according to (7), wherein, in the first substrate, the first inspection terminal and the power supply line are electrically isolated from each other, and the inspection signal and the power supply are independently supplied, respectively. (9) The semiconductor device according to (8), wherein: A first insulator is arranged on the first surface side of the first substrate, the first insulator covers the first inspection terminal and the second inspection terminal, and the first insulator has an inspection opening through which a surface of the first inspection terminal and a surface of the second inspection terminal are exposed, and The inspection openings are respectively filled with a second insulator. (10) The semiconductor device according to (8) or (9), wherein a second substrate is bonded to the first surface side of the first substrate, and the second substrate includes a wiring that electrically connects the first inspection terminal and the power supply line to each other. (11) The semiconductor device according to (10), wherein: A barrier metal film is arranged on a connection path between the wiring and the first inspection terminal and between the wiring and the power line, and The barrier metal film is not disposed on each of the first check terminal and the second check terminal. (12) The semiconductor device according to (10), comprising: A solid-state imaging device is provided, and the solid-state imaging device includes: a pixel disposed on a second surface side of the first substrate opposite to the first surface side, the pixel having a photoelectric conversion element that converts light into electric charge; and A pixel circuit is arranged on the second surface side and performs signal processing on the charge from the pixel. (13) The semiconductor device according to (12), wherein: The pixel circuit at least comprises: a transfer transistor electrically connected to the photoelectric conversion element and the floating diffusion; an amplifying transistor having a gate electrode and a pair of main electrodes, the gate electrode of the amplifying transistor being electrically connected to the floating diffusion, and one of the main electrodes of the amplifying transistor being electrically connected to a third power supply line; a reset transistor electrically connected to the floating diffusion and a fourth power supply line; and A selection transistor has a pair of main electrodes, one of the main electrodes of the selection transistor is electrically connected to the other of the pair of main electrodes of the amplification transistor, and the other main electrode of the selection transistor is electrically connected to the signal line. (14) The semiconductor device according to (13), wherein: In the first substrate, the first inspection terminal is electrically connected to the third power line and the fourth power line, and the first inspection terminal and the power lines are electrically isolated from each other, and The first inspection terminal and the power line are electrically connected to each other through the wiring of the second substrate, and the wiring of the second substrate is inserted between the first inspection terminal and the power line. (15) The semiconductor device according to (14), wherein, in the first substrate, the third power supply line and the fourth power supply line are electrically isolated from each other and independently supply power. (16) The semiconductor device according to (14), wherein: The pixel circuit includes a plurality of pixel circuits arranged along the first direction, and In the first substrate, the third power line and the fourth power line of a part of the pixel circuits among the plurality of pixel circuits are electrically isolated from the third power line and the fourth power line of another part of the pixel circuits among the plurality of pixel circuits. (17) The semiconductor device according to any one of (1) to (16), wherein a probe mark is formed on a surface of each of the first inspection terminal and the second inspection terminal. (18) A semiconductor device comprising: a plurality of signal lines extending along a second direction and arranged in a first direction intersecting the second direction; a first inspection terminal electrically connected to one end of the signal line and providing an inspection signal to the signal line; a detection circuit electrically connected to the other end of the signal line and detecting a defect in the signal line; a second inspection terminal which provides a control signal for controlling a detection operation of the detection circuit; and A protection element is electrically connected to the second check terminal and absorbs surge.

[0118] This application claims the benefit of Japanese Priority Patent Application JP2022-187913 filed in the Japan Patent Office on November 25, 2022, the entire contents of which are incorporated herein by reference.

[0119] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A semiconductor device, which comprises: a plurality of signal lines extending in a first direction and arranged in a second direction intersecting the first direction; a first inspection terminal electrically connected to one end of the signal line and supplying an inspection signal to the signal line; a detection circuit electrically connected to the other end of the signal line and detecting a defect in the signal line; a second inspection terminal supplying a control signal for controlling the detection operation of the detection circuit; and a protection element electrically connected to the second inspection terminal and absorbing a surge.

2. The semiconductor device according to claim 1, wherein the protection element is electrically connected between the second inspection terminal and a power supply line.

3. The semiconductor device according to claim 2, wherein the detection circuit includes an insulated gate field effect transistor having a pair of main electrodes and a gate electrode, one of the main electrodes being electrically connected to the other end of the signal line and the gate electrode being electrically connected to the second inspection terminal, and the protection element is electrically connected in parallel between the second inspection terminal and the gate electrode.

4. The semiconductor device according to claim 2, wherein the power supply line includes a first power supply line and a second power supply line, the power supplied to the second power supply line being lower than the power supplied to the first power supply line, and the protection element includes a first protection element and a second protection element, the first protection element being electrically connected between the second inspection terminal and the first power supply line, and the second protection element being electrically connected between the second inspection terminal and the second power supply line.

5. The semiconductor device according to claim 1, wherein the protection element has a protection diode.

6. The semiconductor device according to claim 1, wherein the protection element has a protection transistor.

7. The semiconductor device according to claim 2, wherein the signal line, the first inspection terminal, the detection circuit, the second inspection terminal, and the protection element are arranged on a first surface side of a first substrate.

8. The semiconductor device according to claim 7, wherein in the first substrate, the first inspection terminal and the power supply line are electrically isolated from each other and the inspection signal and the power supply are provided independently.

9. The semiconductor device according to claim 8, wherein a first insulator is arranged on the first surface side of the first substrate, the first insulator covers the first inspection terminal and the second inspection terminal, and the first insulator has inspection openings through which surfaces of the first inspection terminal and the second inspection terminal are exposed, and the inspection openings are filled with a second insulator respectively.

10. The semiconductor device according to claim 8, wherein a second substrate is bonded to the first surface side of the first substrate, and the second substrate includes wirings for electrically connecting the first inspection terminal and the power supply line to each other.

11. The semiconductor device according to claim 10, wherein A barrier metal film is disposed on a connection path between the wiring and the first inspection terminal and between the wiring and the power supply line, and the barrier metal film is not disposed on each of the first inspection terminal and the second inspection terminal.

12. The semiconductor device according to claim 10, wherein, a solid-state imaging device is configured, and the solid-state imaging device includes: Pixels disposed on a second surface side of the first substrate opposite to the first surface side, the pixels having a photoelectric conversion element that converts light into charge; and A pixel circuit disposed on the second surface side and performing signal processing on the charge from the pixels.

13. The semiconductor device according to claim 12, wherein, the pixel circuit at least includes: A transfer transistor electrically connected to the photoelectric conversion element and a floating diffusion portion; An amplification transistor having a gate electrode and a pair of main electrodes, the gate electrode of the amplification transistor being electrically connected to the floating diffusion portion, and one of the main electrodes of the amplification transistor being electrically connected to a third power supply line; A reset transistor electrically connected to the floating diffusion portion and a fourth power supply line; and A selection transistor having a pair of main electrodes, one of the main electrodes of the selection transistor being electrically connected to the other of the pair of main electrodes of the amplification transistor, and the other main electrode of the selection transistor being electrically connected to the signal line.

14. The semiconductor device according to claim 13, wherein, in the first substrate, the first inspection terminal is electrically connected to the third power supply line and the fourth power supply line, and the first inspection terminal and the power supply line are electrically isolated from each other, and the first inspection terminal and the power supply line are electrically connected to each other through the wiring of the second substrate, and the wiring of the second substrate is inserted between the first inspection terminal and the power supply line.

15. The semiconductor device according to claim 14, wherein, in the first substrate, the third power supply line and the fourth power supply line are electrically isolated from each other and independently supply power.

16. The semiconductor device according to claim 14, wherein, the pixel circuit includes a plurality of pixel circuits arranged along the first direction, and in the first substrate, the third power supply line and the fourth power supply line of a part of the plurality of pixel circuits are electrically isolated from the third power supply line and the fourth power supply line of another part of the plurality of pixel circuits.

17. The semiconductor device according to claim 1, wherein, pin marks are respectively formed on the surfaces of each of the first inspection terminal and the second inspection terminal.

18. A semiconductor device, which includes: A plurality of signal lines extending in a second direction and arranged in a first direction intersecting the second direction; A first inspection terminal electrically connected to one end of the signal line and supplying an inspection signal to the signal line; A detection circuit electrically connected to the other end of the signal line and detecting a defect in the signal line; A second inspection terminal that provides a control signal for controlling the inspection operation of the detection circuit; and A protection element that is electrically connected to the second inspection terminal and absorbs surges.

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