Method and system for electrocardiogram monitoring and disease analysis based on FPGA (Field Programmable Gate Array)

Abstract

The embodiment of the invention provides an electrocardiogram monitoring and disease analysis method and system based on an FPGA, and belongs to the technical field of computers. The system comprises a heart rhythm judgment algorithm module, a low-power-consumption Bluetooth module, a feature extraction module and a preprocessing module. The heart rhythm judgment algorithm module is used for carrying out heart rhythm abnormity detection through a logic branch judgment method based on the QRS wave width and the RR interval electrocardio characteristic parameters; the low-power-consumption Bluetooth module is used for synchronously receiving data through a baud rate and recovering original data; the feature extraction module is used for identifying and extracting electrocardiogram parameters of R waves and QRS complex waves from the electrocardiogram signals; the preprocessing module is used for removing noise in the electrocardiosignals. According to the method, condition judgment of the RR interval and the QRS width can be combined, and various arrhythmia conditions can be accurately recognized.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a method and system for electrocardiogram monitoring and disease analysis based on FPGA. Background Art

[0002] Currently, in the field of electrocardiogram monitoring and disease analysis technology, there are still certain technical challenges and problems. Especially in terms of the accuracy of heart rate detection and the accuracy of disease analysis, there are gaps in accuracy in the existing electrocardiogram monitoring technology for real-time detection and analysis of different types of arrhythmias. For example, some monitoring systems may not be able to accurately distinguish different types of arrhythmias, such as premature ventricular contractions, atrial fibrillation, etc., affecting the accuracy of clinical decisions. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to provide a method and system for electrocardiogram monitoring and disease analysis based on FPGA.

[0004] The technical solution adopted by the present invention is as follows:

[0005] On the one hand, the embodiments of the present invention provide a system for electrocardiogram monitoring and disease analysis based on FPGA. The system for electrocardiogram monitoring and disease analysis based on FPGA includes a heart rhythm judgment algorithm module, a low-power Bluetooth module, a feature extraction module, and a preprocessing module;

[0006] The heart rhythm judgment algorithm module is used to detect abnormal heart rhythms through a logical branch discrimination method based on electrocardiogram feature parameters such as QRS wave width and RR interval;

[0007] The low-power Bluetooth module is used to receive data synchronously through the baud rate and restore the original data;

[0008] The feature extraction module is used to identify and extract electrocardiogram parameters of R waves and QRS complexes from electrocardiogram signals;

[0009] The preprocessing module is used to remove noise from electrocardiogram signals.

[0010] Furthermore, the system for electrocardiogram monitoring and disease analysis based on FPGA further includes a data storage module;

[0011] The data storage module is used to select a specific ROM module for data reading according to the system state.

[0012] Furthermore, the system for electrocardiogram monitoring and disease analysis based on FPGA further includes an electrocardiogram display module;

[0013] The electrocardiogram display module includes a top-level sub-module, an LCD selection sub-module, a clock frequency division sub-module, an LCD display driving sub-module, an LCD display control sub-module, and an electrocardiogram signal data sub-module;

[0014] The top-level sub-module is responsible for calling and managing the LCD selection sub-module, the clock frequency division sub-module, the LCD display driving sub-module, the LCD display control sub-module, and the electrocardiogram signal data sub-module;

[0015] The LCD selection sub-module is used to determine the LCD display screen model according to the configuration requirements of the top-level sub-module;

[0016] The clock frequency division sub-module is used to divide the external high-frequency clock signal into low-frequency clock signals for LCD display driving and electrocardiogram data processing, and generate clock signals for other sub-modules to use;

[0017] The LCD display driving sub-module is used to convert the electrocardiogram data processed by the electrocardiogram signal data sub-module into a display format, and drive the LCD screen to display the electrocardiogram;

[0018] The LCD display control sub-module is responsible for the control and management of the LCD screen, and sends control signals to the LCD display driving sub-module;

[0019] The electrocardiogram signal data sub-module is used to process the electrocardiogram signals from sensors or external inputs, digitize and format them, and provide them to the LCD display driving sub-module for display.

[0020] Further, the feature extraction module includes an R-wave detection algorithm sub-module, a QRS wave detection algorithm sub-module, and a heart rate calculation sub-module;

[0021] The R-wave detection algorithm sub-module is used to combine the improved differential threshold method with zero-crossing detection, adaptive threshold, and R-wave backtracking re-detection to accurately locate the R-wave and calculate the RR interval value;

[0022] The QRS wave detection algorithm sub-module is used to detect the positions of the Q-wave and S-wave based on the differential signal, and calculate the electrocardiogram features through the QRS wave width;

[0023] The heart rate calculation sub-module is used to calculate the heart rate through R-wave positioning and RR interval value.

[0024] Further, the preprocessing module includes a FIR band-pass filter and a median filter;

[0025] The FIR band-pass filter is used to remove the noise in the electrocardiogram signal, which is implemented by FPGA. After generating the filter coefficients in MATLAB, they are loaded into the FIR ip core of the FPGA;

[0026] The median filter is designed based on the bit comparison method to remove the baseline drift in the signal.

[0027] On the other hand, an embodiment of the present invention further provides a method for electrocardiogram monitoring and disease analysis based on FPGA, which is implemented by the system for electrocardiogram monitoring and disease analysis based on FPGA as described above. The method includes the following steps:

[0028] Complete electrocardiogram monitoring and disease analysis through the heart rhythm judgment algorithm module, low-power Bluetooth module, feature extraction module, and preprocessing module.

[0029] Further, the method for electrocardiogram monitoring and disease analysis based on FPGA further includes the following steps:

[0030] Use the low-power Bluetooth module to receive electrocardiogram signal data and store the electrocardiogram signal data in the ROM module;

[0031] Use the FIR band-pass filter to remove the noise of the electrocardiogram signal data to obtain the first data;

[0032] According to the first data, use the median filter to perform smooth signal processing to remove the baseline drift and obtain the second data;

[0033] According to the second data, use the R-wave detection algorithm sub-module of the feature extraction module to accurately locate the R-wave by using the differential threshold method, zero-crossing detection, and adaptive threshold method, and calculate the RR interval value;

[0034] According to the second data, use the QRS wave detection algorithm sub-module of the feature extraction module to locate the Q-wave and S-wave through the differential signal and calculate the width of the QRS wave;

[0035] According to the RR interval value, calculate the heart rate through the heart rate calculation sub-module of the feature extraction module;

[0036] According to the RR interval value and the width of the QRS wave, perform abnormal detection through the heart rhythm judgment algorithm module to obtain abnormal data;

[0037] According to the abnormal data, drive the buzzer to sound an alarm through the flag bit.

[0038] Further, the method for electrocardiogram monitoring and disease analysis based on FPGA further includes the following steps:

[0039] Convert the discrete points into a continuous electrocardiogram signal waveform through the pixel connection algorithm;

[0040] Display the heart rate, disease result, and time information of the electrocardiogram signal waveform through the selected area of the LCD screen.

[0041] On the other hand, an embodiment of the present invention further provides a device for electrocardiogram monitoring and disease analysis based on FPGA, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method for electrocardiogram monitoring and disease analysis based on FPGA as described above is implemented.

[0042] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the method for electrocardiogram monitoring and disease analysis based on FPGA as described above.

[0043] The embodiments of the present application at least include the following beneficial effects: The present application provides a method and system for electrocardiogram monitoring and disease analysis based on FPGA. The present invention includes a heart rhythm judgment algorithm module, a low-power Bluetooth module, a feature extraction module, and a preprocessing module; the heart rhythm judgment algorithm module is used to detect abnormal heart rhythms through a logical branch discrimination method based on electrocardiogram feature parameters such as QRS wave width and RR interval; the low-power Bluetooth module is used to receive data synchronously through the baud rate and restore the original data; the feature extraction module is used to identify and extract electrocardiogram parameters of R waves and QRS complexes from electrocardiogram signals; the preprocessing module is used to remove noise from electrocardiogram signals. The present invention can accurately identify various arrhythmia conditions by combining the condition judgments of RR intervals and QRS widths. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic diagram of a system for electrocardiogram monitoring and disease analysis based on FPGA provided by an embodiment of the present invention;

[0045] Figure 2 is an RTL diagram of a serial port receiving module provided by an embodiment of the present invention;

[0046] Figure 3 is an RTL diagram of a ROM data storage module provided by an embodiment of the present invention;

[0047] Figure 4 is a MATLAB simulation spectrum diagram of a FIR filter provided by an embodiment of the present invention;

[0048] Figure 5 is an RTL diagram of a median filter design module provided by an embodiment of the present invention;

[0049] Figure 6 is an RTL diagram of a heart rate calculation sub-module provided by an embodiment of the present invention;

[0050] Figure 7 is a diagram of the logical branch discrimination method provided by an embodiment of the present invention;

[0051] Figure 8 It is the VIVADO heart rhythm judgment algorithm module diagram provided by the embodiment of the present invention;

[0052] Figure 9 It is the RTL diagram of the LCD selection sub-module provided by the embodiment of the present invention;

[0053] Figure 10 It is the RTL diagram of the clock division sub-module provided by the embodiment of the present invention;

[0054] Figure 11 It is the RTL diagram of the LCD display driver sub-module provided by the embodiment of the present invention;

[0055] Figure 12 It is the LCD screen display design diagram provided by the embodiment of the present invention;

[0056] Figure 13 It is the RTL diagram of the VIVADO LCD screen display module provided by the embodiment of the present invention;

[0057] Figure 14 It is the schematic diagram of the screen display of the electrocardiogram monitoring system provided by the embodiment of the present invention. Detailed implementation manners

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application described in detail in the appended claims.

[0059] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0060] The terms "at least one", "a plurality of", "each", "any one", etc. used in this application, "at least one" includes one, two or more than two, "a plurality of" includes two or more than two, "each" refers to each one of the corresponding plurality, and "any one" refers to any one of the plurality.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0062] Before elaborating on the embodiments of this application in detail, some nouns and terms involved in the embodiments of this application are first explained, and the nouns and terms involved in the embodiments of this application are applicable to the following explanations.

[0063] 1) FPGA (Field-Programmable Gate Array), a field-programmable gate array, is a programmable integrated circuit.

[0064] 2) QRS complex, an important part of an electrocardiogram (ECG), represents a complete ventricular depolarization process of the heart. The QRS complex consists of three main waves: the Q wave (initial negative wave), the R wave (main upward wave), and the S wave (negative wave after the R wave).

[0065] 3) RR interval, refers to the time interval between two consecutive R wave peaks in an electrocardiogram.

[0066] 4) ROM, a type of computer memory.

[0067] 5) LCD, liquid crystal display.

[0068] 6) FIR (Finite Impulse Response), finite impulse response, is a type of digital filter.

[0069] 7) RTL (Register Transfer Level), register transfer level;

[0070] 8) MATLAB (Matrix Laboratory), is a high-performance computing environment and programming language, mainly used for mathematical calculations, data analysis, algorithm development, visualization, and applications in engineering and scientific fields;

[0071] 9) IP core (Intellectual Property Core), is a designed and reusable functional module or hardware unit;

[0072] 10) FIR IP core, a FIR (Finite Impulse Response) filter IP core for FPGA design.

[0073] The following further elaborates on the embodiments of the present invention in conjunction with the accompanying drawings.

[0074] On the one hand, referring to Figure 1 , the embodiments of the present invention provide a system for electrocardiogram monitoring and disease analysis based on FPGA. The system for electrocardiogram monitoring and disease analysis based on FPGA includes a heart rhythm judgment algorithm module, a low-power Bluetooth module, a feature extraction module, and a preprocessing module;

[0075] The heart rhythm judgment algorithm module is used to detect abnormal heart rhythms through logical branch discrimination based on electrocardiogram feature parameters such as QRS wave width and RR interval.

[0076] The low-power Bluetooth module is used to receive data synchronously through the baud rate and restore the original data.

[0077] The feature extraction module is used to identify and extract electrocardiogram parameters of R waves and QRS complexes from electrocardiogram signals.

[0078] The preprocessing module is used to remove noise from electrocardiogram signals.

[0079] The system for electrocardiogram monitoring and disease analysis based on FPGA disclosed in the embodiments of the present invention further includes a data storage module;

[0080] The data storage module is used to select a specific ROM module for data reading according to the system state.

[0081] The system for electrocardiogram monitoring and disease analysis based on FPGA disclosed in the embodiments of the present invention further includes an electrocardiogram display module;

[0082] The electrocardiogram display module includes a top-level sub-module, an LCD selection sub-module, a clock frequency division sub-module, an LCD display driving sub-module, an LCD display control sub-module, and an electrocardiogram signal data sub-module;

[0083] The top-level sub-module is responsible for calling and managing the LCD selection sub-module, the clock frequency division sub-module, the LCD display driving sub-module, the LCD display control sub-module, and the electrocardiogram signal data sub-module;

[0084] The LCD selection sub-module is used to determine the LCD display screen model according to the configuration requirements of the top-level sub-module;

[0085] The clock frequency division sub-module is used to divide the external high-frequency clock signal into low-frequency clock signals for LCD display driving and electrocardiogram data processing, and generate clock signals for other sub-modules to use;

[0086] The LCD display driver sub-module is used to convert the electrocardiogram data processed by the electrocardiogram signal data sub-module into a display format and drive the LCD screen to display the electrocardiogram;

[0087] The LCD display control sub-module is responsible for the control and management of the LCD screen and sends control signals to the LCD display driver sub-module;

[0088] The electrocardiogram signal data sub-module is used to process the electrocardiogram signals from sensors or external inputs, digitize and format them, and provide them to the LCD display driver sub-module for display.

[0089] The feature extraction module disclosed in the embodiment of the present invention includes an R-wave detection algorithm sub-module, a QRS wave detection algorithm sub-module, and a heart rate calculation sub-module;

[0090] The R-wave detection algorithm sub-module is used to combine the improved differential threshold method with zero-crossing detection, adaptive threshold, and R-wave backtracking re-detection to accurately locate the R-wave and calculate the RR interval value;

[0091] The QRS wave detection algorithm sub-module is used to detect the positions of the Q-wave and S-wave based on the differential signal and calculate the electrocardiogram features through the QRS wave width;

[0092] The heart rate calculation sub-module is used to calculate the heart rate through R-wave positioning and RR interval value.

[0093] As an optional implementation manner, the formulas used in the embodiment of the present invention include:

[0094] T adaptive (t) = α·max(|f(t)|) + β

[0095] Wherein, T adaptive (t) is the adaptive threshold, α and β are adjustment coefficients, max(|f(t)|) is the maximum absolute value of the signal within a specific time period, dynamically adjusts the threshold, and t represents the time point corresponding to the signal. Through the adaptive threshold method, the interference noise of the signal will be automatically suppressed.

[0096] As an optional implementation manner, based on the initially detected R-wave position, the backtracking algorithm is used to further correct the mis-detected position. This method usually uses a dynamic time window for adjustment. It can be expressed as:

[0097]

[0098] Wherein, R final represents the R-wave position after backtracking, arg max t represents the determination of the maximum value position, N is the window length, and f(t + i) is the amplitude of the signal.

[0099] The preprocessing module disclosed in the embodiments of the present invention includes a FIR band-pass filter and a median filter;

[0100] The FIR band-pass filter is used to remove the noise in the electrocardiogram signal, which is implemented by FPGA. After generating the filter coefficients in MATLAB, they are loaded into the FIR ip core of the FPGA;

[0101] The median filter is designed based on the bit comparison method to remove the baseline drift in the signal.

[0102] On the other hand, the embodiments of the present invention also provide a method for electrocardiogram monitoring and disease analysis based on FPGA, which is used to be implemented by the electrocardiogram monitoring and disease analysis system based on FPGA as described above. The method includes the following steps:

[0103] Complete electrocardiogram monitoring and disease analysis through the heart rhythm judgment algorithm module, low-power Bluetooth module, feature extraction module, and preprocessing module.

[0104] The method for electrocardiogram monitoring and disease analysis based on FPGA disclosed in the embodiments of the present invention further includes the following steps:

[0105] Use the low-power Bluetooth module to receive the electrocardiogram signal data and store the electrocardiogram signal data in the ROM module;

[0106] Use the FIR band-pass filter to remove the noise in the electrocardiogram signal data to obtain the first data;

[0107] According to the first data, use the median filter to perform smooth signal processing to remove the baseline drift and obtain the second data;

[0108] According to the second data, use the R-wave detection algorithm sub-module of the feature extraction module to accurately locate the R-wave by using the differential threshold method, zero-crossing detection, and adaptive threshold method, and calculate the RR interval value;

[0109] According to the second data, use the QRS wave detection algorithm sub-module of the feature extraction module to locate the Q-wave and S-wave through the differential signal and calculate the width of the QRS wave;

[0110] According to the RR interval value, calculate the heart rate through the heart rate calculation sub-module of the feature extraction module;

[0111] According to the RR interval value and the width of the QRS wave, perform abnormal detection through the heart rhythm judgment algorithm module to obtain abnormal data;

[0112] According to the abnormal data, drive the buzzer to sound an alarm through the flag bit.

[0113] As an alternative embodiment, when analyzing the RR interval, it is possible to determine the presence of arrhythmia by calculating the standard deviation or variability of the RR interval.

[0114] The embodiments of the present invention perform comprehensive analysis by combining the RR interval, QRS wave width, and other electrocardiogram features to improve the judgment ability of electrocardiogram monitoring.

[0115] The method for electrocardiogram monitoring and disease analysis based on FPGA disclosed in the embodiments of the present invention further includes the following steps:

[0116] Convert discrete points into a continuous electrocardiogram signal waveform through a pixel connection algorithm;

[0117] Display the heart rate, disease results, and time information through a selected area of the LCD screen for the electrocardiogram signal waveform.

[0118] As an alternative embodiment, the embodiments of the present invention propose a heart rate detection and disease analysis algorithm. First, the electrocardiogram signal is processed by a filter, and then the R wave is accurately located by using the differential threshold method combined with zero-crossing detection, the detection sensitivity is improved by the adaptive threshold method, and the backtracking recheck algorithm is added to prevent mispositioning of the R wave. After that, an accurate RR interval value can be obtained to calculate the heart rate. Then, the width of the QRS is obtained by the differential method, and the obtained disease is determined according to the obtained RR interval value and QRS width value. To verify the disease detection algorithm, the seven types of data used come from the MIT-BIH database. Then, visualization is achieved through the LCD screen.

[0119] Reference Figure 1 , the embodiments of the present invention include the following modules:

[0120] 1. Low-power Bluetooth module

[0121] The main function of this module is to obtain the collected electrocardiogram signal from the low-power Bluetooth, and send a completion flag through the "uart_done" signal after the reception is completed in one working cycle of the patch system. The received data is stored in the rom core. Refer to Figure 2 the RTL diagram of the serial port receiving module in

[0122] 2. Data storage module

[0123] This module determines the next state ("next_state") through the "beep[3:0]" signal, thereby selecting a specific ROM module (from "rom1" to "rom8") to read data. Refer to Figure 3RTL diagram of the ROM data storage module. The state machine in the code includes three main processes: initialization, state transition, and ROM data read control. When the "sys_rst_n" reset signal is valid, the system will reset all ROM read enable signals and states. Whenever the state changes, the system will activate the corresponding ROM read enable signal ("rom_rd_en_x") according to the current state and output the data in the selected ROM module to "rom_data", which is convenient for subsequent processing of the electrocardiogram signal.

[0124] Among them, the "rom1" module supports bidirectional operation. Therefore, it is necessary to write the electrocardiogram data into this module first. It will not start reading the stored electrocardiogram signal until it receives the flag bit "uart_done" of a work stop sent by the patch system to achieve sequential output. What is stored in "rom1" is the electrocardiogram signal collected in real time through Bluetooth, while "rom2" to "rom8" respectively store seven segments of electrocardiogram data downloaded from the MIT-BIH database. Users can control the switching order of the ROM modules through buttons, which is convenient for selecting and displaying between different data sets.

[0125] 3. Preprocessing module

[0126] The preprocessing module includes the design of the FIR band-pass filter and the design of the median filter. However, since the bit width of the data is 8 bits, but the bit width of the data output after passing through the FIR filter is 24 bits, in order to implement the subsequent algorithm, the present invention truncates the high bits of the output 24-bit FIR data and intercepts 8-bit data. Because the output of the FIR filter is a signed number, it can be found by observing the simulation waveform that the data with bit positions [24:16] are all sign bits, and the data with bit positions [16:9] are the intercepted signals, and finally the bit width reduction is successfully achieved.

[0127] 3.1. Design of the FIR band-pass filter

[0128] In the process of implementing the FIR filter on the FPGA, the design of this module is completed by using the internal FIR core of the FPGA. According to the frequency range of the electrocardiogram noise and the electrocardiogram signal, MATLAB is used to design parameters such as the type, sampling frequency, cut-off frequency, and stopband attenuation of the FIR low-pass filter. Then, the required filter coefficients are generated based on these parameters. Finally, the FIR filter design of the present invention is completed, and its amplitude-frequency characteristic curve is as Figure 4 shown.

[0129] From Figure 4It can be seen that the frequency pass range of this filter is 0.5 - 43 Hz, and the stopband attenuation is above 60. The designed filter is a 100 - order filter. After the characteristic curve meets the requirements, it is then loaded into the ROM of the FPGA in the form of a.coe file, thus completing the design of the filter.

[0130] 3.2. Design of Median Filter

[0131] In the FPGA implementation of median filtering, the present invention designs the median filtering method based on the principle of bit - comparison method. Taking unsigned binary numbers with a window length of n and a bit - width of m as an example, the implementation steps are as follows:

[0132] (1) Obtain the number of 0s and 1s of the highest bit of these n numbers, that is, divide them into group 0 (m - 1_0) and group 1 (m - 1_1) according to the numerical size of the (m - 1) - th bit. Group 0 contains all the numbers with this bit being 0, and group 1 contains all the numbers with this bit being 1.

[0133] (2) Compare the sizes of m - 1_0, m - 1_1 and n / 2. If m - 1_0 > n / 2, it is judged that the median has a value of 0 at the (m - 1) - th bit; if m - 1_1 > n / 2, it is judged that the median has a value of 1 at the (m - 1) - th bit.

[0134] (3) Continue to make size comparisons of the sub - highest bit (m - 2) of the array where the median obtained in step 1 and step 2 is located, and find the group where the median of the (m - 2) - th bit is located. Compare all bits in the array in the above - mentioned operation in sequence until the median of the lowest bit of these n numbers is judged, and this binary number is the final median output.

[0135] In the embodiment of the present invention, the window length is 75 and the bit - width is 8 bits. Based on the above method, the RTL diagram of the median filtering based on the bit - comparison method implemented on the FPGA is as Figure 5 shown

[0136] 4. Feature Extraction Module

[0137] 4.1. R - wave Detection Algorithm Sub - module

[0138] The traditional differential threshold method uses the way of second - order derivative and fixed threshold to determine the position of the R - wave peak point, but there are problems such as poor anti - interference ability and low detection rate. Therefore, in the embodiment of the present invention, on the basis of the traditional differential threshold method, methods such as zero - crossing detection, adaptive threshold, and R - wave backtracking re - detection are combined to improve and innovate the algorithm. The improved algorithm not only improves the detection efficiency of the R - wave but also greatly increases the processing efficiency of the algorithm.

[0139] The peak value is located by detecting the slope at the zero crossing point, and the R wave is located by adding the differential threshold to detect the maximum differential value. There will inevitably be errors in this process. The present invention realizes the accurate positioning of the R wave by adjusting the threshold value threshold = μ + k·σ. Among them, μ is the local mean value, σ is the local standard deviation, and k is an adjustment coefficient to control the sensitivity. Among them, μ is the average value of 8 RR interval values and will change according to the detected data.

[0140] 4.2. QRS wave detection algorithm sub-module

[0141] The Q wave detection principle is similar to the S wave detection principle. Both are located by detecting the first-order differential value of the detection point and adding an adaptive threshold (the same as the above principle, not elaborated) to increase the accuracy, which can well locate the Q wave and the R wave and complete the width calculation. From the waveform characteristics, the Q wave is the first wave in front of the R wave, and the S wave is the first wave behind the R wave. According to the comparison of the waveform characteristics of the differentiated signal and the original signal, when detecting, taking the peak value of the R wave as the base point, the position of the second zero point detected forward is the starting point of the Q wave, and the position of the second zero point detected backward is the end point of the S wave. The time interval between these two points is the width of the QRS wave.

[0142] 4.3. Heart rate calculation sub-module

[0143] The RR interval is calculated using the previously located R wave, and then the heart rate value is obtained through the formula (60 * sampling frequency) / RR interval. Refer to Figure 6 , and the three registers hear_rate_0 to hear_rate_2 store the hundreds, tens, and units digits of the calculated heart rate, providing data for the subsequent heart rate display.

[0144] 5. Heart rhythm judgment algorithm module

[0145] Under normal circumstances, the contraction and relaxation of the heart are regular. However, during the process of heart contraction and relaxation, if the rhythm of atrial and myocardial cells appears abnormal, or the impulse is conducted to a certain part of the myocardium, the phenomenon of abnormal heart rhythm will occur. According to the electrocardiogram characteristic parameters such as the width of the QRS wave and the RR interval extracted by feature extraction, these are used as the judgment basis for heart rhythm judgment.

[0146] Through the research and analysis of the current situation of the heart rhythm judgment algorithm, the advantages and disadvantages of the current main detection algorithms are understood. Since there are many logical discriminations during heart rhythm judgment and there are many errors in actual detection, this paper selects the logical branch discrimination method with relatively simple operation and strong real-time performance as the discrimination method for heart rhythm judgment. Combining medical relevant materials, the types of abnormal heart rhythms and the discrimination criteria are as Figure 7 .

[0147] In Figure 7 the discrimination standard table of, Represents the average value of eight consecutive detected RR intervals, RR i Represents the currently detected RR interval, RR i+1 Represents the next detected RR interval, and W represents the width of the current QRS.

[0148] Reference Figure 8 The VIVADO heart rhythm judgment algorithm module diagram of , where xindian_flag_2 to xindian_flag_8 are the flag bits obtained according to the heart rhythm judgment algorithm, providing signals for the subsequent display module and also being the flag bits for driving the buzzer. Once a pulse is generated, the buzzer will sound for one second, indicating that the disease occurs at this time.

[0149] 6. Electrocardiogram display module

[0150] To better reflect the characteristics of human-computer interaction and portability, the present invention displays the filtered electrocardiogram waveform, heart rate, and the result of heart rhythm judgment on the LCD display screen. This module mainly includes a top-level sub-module (lcd_rgb_char), an LCD selection sub-module (rd_id), a clock frequency division sub-module (clk_div), an LCD display driving sub-module (lcd_drive), an LCD display control sub-module (lcd_display), and an electrocardiogram signal data sub-module (xindian_fir), where the top-level sub-module is responsible for instantiating the remaining sub-modules.

[0151] 6.1. LCD selection sub-module

[0152] Since the AMD ZYNQ 7010 development board is compatible with 5 different types of LCD screens, although the resolution used in the present invention is 800×480, in order to achieve better compatibility, the LCD selection code is written, referring to Figure 9 The RTL diagram of the LCD selection module.

[0153] 6.2. Clock frequency division sub-module

[0154] Due to the different required clocks of each LCD, the present invention writes a clock frequency division sub-module to divide the 50MHz clock into 25MHz and 12.5MHz, performing a two-frequency division and a four-frequency division. The LCD clock used in the present invention is 25MHz, referring to Figure 10 The RTL diagram of the clock frequency division sub-module.

[0155] 6.3. LCD display driving sub-module

[0156] In the LCD display driver sub-module, the data timing of the LCD is controlled by controlling the line synchronization signal and the field synchronization signal. The process of the LCD displaying an image is as follows: The counting scanner starts from the upper left corner pixel of the LCD and scans the pixel points on the screen in sequence from left to right and from top to bottom. When it scans to the last pixel point, it just completes the display of one frame of the image. The timing parameters of the LCD display screen data input include: the number of cycles (1056 clock cycles), the line synchronization pulse (128 clock cycles), the line display area (800 clock cycles), the line back porch (88 clock cycles), the line front porch (40 clock cycles), the column cycle number (525 clock cycles), the column synchronization pulse (2 clock cycles), the column display area (480 clock cycles), the column back porch (33 clock cycles), and the column front porch (10 clock cycles). According to the above timing parameters, the corresponding parameters in the LCD display driver sub-module are configured and the driving function is designed. The LCD display driver sub-module can output a pixel clock, a line synchronization pulse signal, a field synchronization pulse signal, a line scan position, a field scan position, and a data enable signal for other modules to use. At the same time, it obtains the RGB data of the pixel points to be displayed from the LCD display control sub-module and outputs the lcd_rgb[23:0] pixel data to drive the display of the LCD screen. Refer to Figure 11 RTL diagram of the LCD display driver sub-module.

[0157] 6.4. LCD display control sub-module

[0158] The present invention needs to display waveforms, time (dynamic), heart rate, pictures, and fonts. Refer to Figure 12 , among the three data hear_rate_0 - 2 in the picture, they are used to display the heart rate, while the six data year, mon, day, hour, min, sec are used to display the time (dynamic). The six flag bits xindian_flag_2 - 8 are used to display six different diseases. Also, mid_data_out is the waveform data, which is one of the key points in the display. The regional division of the screen display interface is as Figure 12 shown.

[0159] The area in the upper left corner of the screen (10 - 490) * (60 - 316) is the area for displaying waveforms. (The width of the waveform display is 480, and the height is 256)

[0160] On the right side, from column pixel 512 to column pixel 800, the first 365 rows from top to bottom respectively display the picture of the electrocardiogram system, "onset time" (font), the actual corresponding onset time, "disease" (font), and the actual corresponding disease.

[0161] Rows 438 - 470 respectively show the instantaneous heart rate, the status of the heart rate (with two statuses: normal and abnormal), and the time display (in the order of year, month, day, hour, minute, second) from left to right.

[0162] The line is displayed above the instantaneous heart rate, to the left of the heart rate status, and to the left of the onset time.

[0163] When the line scan value is between 10 and 490 and the field scan is between 60 and 316, i.e., (pixel_xpos >= 10 - 1'b1) && (pixel_xpos < 10 + 480 - 1'b1) && (pixel_ypos >= 60) && (pixel_ypos < 60 + 256), the waveform is displayed. Here, pixel_xpos and pixel_ypos are the coordinates of the pixel points, which is more convenient for viewing. Since the incoming data is 8 - bit, the value range of 60 - 316 corresponds to 256 pixel points per column in the screen waveform display area. The waveform register module determines whether to display the pixel at the coordinate by judging whether the value of wave[y_wave_cnt] is equal to x_wave_cnt. Here, x_wave_cnt and y_wave_cnt are the coordinates of the pixel points relative to the starting point of the character area, so that the electrocardiogram signal can be displayed. However, the waveform displayed in this way is discrete points, and the pixels between two adjacent points of the electrocardiogram waveform in two adjacent columns are not displayed. In order to display a continuous electrocardiogram waveform, the present invention uses an algorithm. The black dots in the figure represent the points of the collected electrocardiogram signal in the corresponding area of the screen. But such points are discrete, so the pixel points need to be connected to the pixel points of the previous and next electrocardiogram signals, and the connection length reaches the mid - point between two adjacent black dots. There are a total of four cases for the size of three adjacent points. The if statement is used to judge these four cases. By comparing y_wave_cnt with the average value of the signal points on both sides, continuous pixels can be obtained, thus obtaining a continuous waveform display.

[0164] For a fixed font at a fixed position. Since there are too many fonts, it can be regarded as a picture. The pixel matrix of the picture is output through the PCtoLCD200 software and stored in the self - defined matrix of the present invention for its call. Figure 12Taking the "instantaneous heart rate" in the lower left corner in [Example] as an example, its position is in the 128*32 pixel area where the row and column scans satisfy (pixel_xpos >= 10 - 1'b1) && (pixel_xpos < 10 + 128 - 1'b1 && (pixel_ypos >= 438) && (pixel_ypos < 438 + 32). When in this area, the 128*32 pixel data of this picture is called from the register defined in the present invention, and the matrix is traversed through char3[y3_cnt][CHAR3_WIDTH - 1'b1 - x3_cnt], and it is lit as long as it is judged to be 1 by if, where y3_cnt and x3_cnt are the coordinates of the pixel point relative to the starting point of the character area, CHAR3_WIDTH is the font width, and the display principles of other fonts are the same. Refer to Figure 13 the VIVADO LCD screen display module. Figure 14 It is an example diagram of an electrocardiogram monitoring system.

[0165] 7. Time management module

[0166] In the system for electrocardiogram monitoring and disease analysis based on FPGA in the embodiments of the present invention, the time management module plays a very crucial role, especially when processing and displaying electrocardiogram (ECG) signals in real time. This module is mainly responsible for coordinating various functions such as the acquisition, processing, display, and storage of electrocardiogram signals, ensuring time synchronization and precise signal processing during the electrocardiogram monitoring process. Specifically, the role and operation rules of the time management module in the system are mainly reflected in the following aspects:

[0167] a. Time synchronization and data management

[0168] The time management module ensures the time synchronization of the entire system, including the coordination of the signal acquisition time, processing time, and display time. It is responsible for processing the timestamps of electrocardiogram data and synchronizing the data stream according to the timestamps, avoiding affecting the accuracy of the results due to data inconsistencies at different time points.

[0169] For example, when processing electrocardiogram signals, the system needs to determine the sampling frequency according to the heart rate (i.e., the frequency of the heartbeat), and process the signals based on this. This is crucial for accurately detecting the heart rate and disease analysis. The time management module ensures the real-time performance and consistency of the signals here.

[0170] b. Sampling frequency and signal processing

[0171] To ensure the precise capture of electrocardiogram signals, the time management module adjusts the sampling frequency. For example, the sampling frequency may be dynamically adjusted according to the changes in the signal. When the heart rate is faster, the system may require a higher sampling frequency to capture more electrocardiogram details.

[0172] c. Abnormal Detection and Disease Analysis

[0173] In terms of disease analysis, the time management module performs abnormal detection based on the time information of the electrocardiogram signal in combination with other indicators (such as QRS width, RR interval, etc.), and plays an important role especially in arrhythmia recognition. For example, arrhythmia may be manifested as irregular RR intervals or abnormal QRS waveforms. The time management module helps identify the disease by analyzing these time indicators.

[0174] d. Optimization of Display and Storage

[0175] To improve the user experience and real-time response ability, the time management module also needs to be responsible for controlling the display module. For example, in electrocardiogram display, the system needs to update the displayed content in a timely manner according to the time interval to avoid the lagging display of signals. In addition, it also needs to control the storage period of signals to ensure that the system performance will not decline due to the accumulation of excessive data.

[0176] e. Data Delay and Real-time Performance

[0177] The time management module will also handle the data delay problem during real-time monitoring and analysis. To reduce the time delay due to transmission and processing, the system may perform operations such as data buffering and flow control to ensure the accurate processing and timely display of each frame of data.

[0178] Compared with the prior art, the present invention has significant advantages, especially in terms of the accuracy of heart rate detection and the accuracy of disease analysis. Traditional electrocardiogram signal detection methods are often affected by noise interference, resulting in inaccurate detection of R waves, which affects the accurate calculation of heart rate and the effect of disease analysis. To solve these problems, the present invention has made innovations on the basis of the traditional differential threshold method, combining multiple advanced methods such as zero-crossing detection, adaptive threshold, and R wave backtracking re-detection. Through zero-crossing detection, the positioning accuracy of R waves is effectively improved, avoiding misjudgment caused by noise; the adaptive threshold dynamically adjusts the detection standard according to the characteristics of the real-time electrocardiogram signal, significantly enhancing the adaptability of the algorithm, especially suitable for detection requirements under different individuals and complex environments; and the R wave backtracking re-detection further reduces the occurrence of missed detections and false detections, thereby improving the overall accuracy of heart rate detection. In addition, the innovation of the present invention in disease analysis is particularly prominent. By combining the conditional determination of RR intervals and QRS widths, the present invention can accurately identify various arrhythmia conditions. This disease determination method based on multi-index analysis greatly improves the judgment ability of electrocardiogram monitoring.

[0179] On the other hand, an embodiment of the present invention further provides a device for electrocardiogram monitoring and disease analysis based on FPGA, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the method for electrocardiogram monitoring and disease analysis based on FPGA as described above.

[0180] The device for electrocardiogram monitoring and disease analysis based on FPGA of the present invention can achieve real-time monitoring, data storage, and disease analysis of electrocardiogram signals through the collaborative work of the processor, memory, and computer program. The IP cores in FPGA (such as FFT transform, filter, signal sampling module, etc.) are used as acceleration components, which can improve the processing efficiency of the system at the hardware level. Utilizing the hardware acceleration characteristics of FPGA, the processing efficiency and response speed are improved, and real-time processing and analysis of electrocardiogram are realized.

[0181] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to execute the method for electrocardiogram monitoring and disease analysis based on FPGA as described above.

[0182] The computer-readable storage medium of the present invention stores computer instructions for execution, allowing the system to run the electrocardiogram monitoring and analysis method on a computer. The ROM in the embodiment of the present invention is used to store electrocardiogram data sets, such as the MIT-BIH data set.

[0183] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A system for ECG monitoring and symptom analysis based on FPGA, characterized in that: The FPGA-based ECG monitoring and disease analysis system includes a heart rhythm judgment algorithm module, a low-power Bluetooth module, a feature extraction module, and a preprocessing module; The heart rhythm judgment algorithm module is used to detect abnormal heart rhythm through a logic branch judgment method based on the QRS wave width and RR interval electrocardiographic characteristic parameters; The low-power Bluetooth module is used to synchronously receive data through the baud rate and restore the original data; The feature extraction module is used to identify and extract the ECG parameters of the R wave and the QRS complex wave from the ECG signal; The preprocessing module is used to remove noise from the electrocardiogram signal.

2. The FPGA-based ECG monitoring and disease analysis system according to claim 1, characterized in that: The FPGA-based ECG monitoring and disease analysis system also includes a data storage module; The data storage module is used to select a specific ROM module to read data according to the system state.

3. The FPGA-based ECG monitoring and disease analysis system according to claim 1, characterized in that: The FPGA-based ECG monitoring and symptom analysis system also includes an ECG display module; The ECG display module includes a top-level submodule, an LCD selection submodule, a clock frequency division submodule, an LCD display drive submodule, an LCD display control submodule, and an ECG signal data submodule; The top-level submodule is responsible for calling and managing the LCD selection submodule, the clock frequency division submodule, the LCD display driver submodule, the LCD display control submodule and the ECG signal data submodule; The LCD selection submodule is used to determine the LCD display model according to the configuration requirements of the top-level submodule; The clock frequency division submodule is used to divide the external high-frequency clock signal into a low-frequency clock signal for LCD display driving and ECG data processing, and generate a clock signal for use by other submodules; The LCD display driving submodule is used to convert the ECG data processed by the ECG signal data submodule into a display format, and drive the LCD screen to display the ECG; The LCD display control submodule is responsible for controlling and managing the LCD screen, and sending control signals to the LCD display drive submodule; The ECG signal data submodule is used to process the ECG signal from the sensor or external input, digitize and format it, and provide it to the LCD display driving submodule for display.

4. The FPGA-based ECG monitoring and disease analysis system according to claim 1, characterized in that: The feature extraction module includes an R wave detection algorithm submodule, a QRS wave detection algorithm submodule and a heart rate calculation submodule; The R wave detection algorithm submodule is used to combine the improved differential threshold method with zero-crossing detection, adaptive threshold and R wave back-testing to accurately locate the R wave and calculate the RR interval value; The QRS wave detection algorithm submodule is used to detect the positions of the Q wave and the S wave based on the differential signal, and calculate the electrocardiogram characteristics through the QRS wave width; The heart rate calculation submodule is used to calculate the heart rate through R wave positioning and RR interval value.

5. The FPGA-based ECG monitoring and disease analysis system according to claim 1, characterized in that: The preprocessing module includes a FIR bandpass filter and a median filter; The FIR bandpass filter is used to remove noise from the ECG signal and is implemented using FPGA. The filter coefficients are generated from MATLAB and loaded into the FIRip core of the FPGA. The median filter is designed based on a bit comparison method to remove the baseline drift in the signal.

6. A method for ECG monitoring and symptom analysis based on FPGA, which is implemented by the system for ECG monitoring and symptom analysis based on FPGA as claimed in any one of claims 1 to 5, characterized in that: The method comprises the following steps: ECG monitoring and symptom analysis are completed through the heart rhythm judgment algorithm module, low-power Bluetooth module, feature extraction module and preprocessing module.

7. The method of electrocardiogram monitoring and symptom analysis based on FPGA according to claim 6, characterized in that: The method further comprises the following steps: Using a low-power Bluetooth module to receive ECG signal data, and storing the ECG signal data in a ROM module; Using a FIR bandpass filter to remove noise from the electrocardiogram signal data to obtain first data; According to the first data, a median filter is used to perform smoothing signal processing to remove baseline drift, thereby obtaining second data; According to the second data, the R wave detection algorithm submodule of the feature extraction module uses a differential threshold method, a zero-crossing point detection method and an adaptive threshold method to accurately locate the R wave and calculate the RR interval value; According to the second data, using the QRS wave detection algorithm submodule of the feature extraction module to locate the Q wave and the S wave through the differential signal, and calculate the width of the QRS wave; According to the RR interval value, the heart rate is calculated by the heart rate calculation submodule of the feature extraction module; According to the RR interval value and the width of the QRS wave, abnormality detection is performed by the heart rhythm judgment algorithm module to obtain abnormal data; According to the abnormal data, the buzzer is driven to sound an alarm through the flag bit.

8. The method of electrocardiogram monitoring and symptom analysis based on FPGA according to claim 6, characterized in that: The method further comprises the following steps: The discrete points are converted into continuous ECG signal waveforms through pixel connection algorithm; The electrocardiogram signal waveform is displayed on a selected area of ​​an LCD screen to display heart rate, disease results, and time information.

9. An FPGA-based ECG monitoring and symptom analysis device, characterized in that: It includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method for ECG monitoring and symptom analysis based on FPGA as described in any one of claims 6 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the FPGA-based ECG monitoring and disease analysis method as described in any one of claims 6 to 8.

Images