Integrated circuit reliability test data analysis method

Abstract

The invention discloses an integrated circuit reliability test data analysis method, which adopts a first weight value and a second weight value to process data in a test data analysis process, can characterize risks to a certain extent, and further has certain predictability for loss caused by complete failure of an integrated circuit. On one hand, electric digital data processing can be realized, and particularly, the detailed technology related to the type or purpose of circuit design is used in the field of integrated circuit testing; on the other hand, it can also be explained that technical mining in the field also has a relatively wide extension prospect.

Description

Technical Field

[0001] This application relates to electrical digital data processing, specifically to detailed technical fields related to the type or purpose of circuit design, and particularly to a method for analyzing integrated circuit reliability test data. Background Art

[0002] The quality and reliability testing of integrated circuits (ICs) are important links to ensure their stable and long-term reliable performance. In an increasingly complex electronic world, the quality of chips is directly related to the effectiveness and reputation of the final products. Therefore, their testing is indispensable.

[0003] The failure process of integrated circuits generally can be divided into three stages: early failure, accidental failure, and wear-out failure. They are not completely independent of each other but have certain relationships. Affected by the design and specification parameters of integrated circuits, the relationships among the above three stages of different types of integrated circuits are not exactly the same. If the reliability of integrated circuits is calculated completely relying on existing formulas, it will lead to large errors, making the analysis results of integrated circuit reliability test data inaccurate.

[0004] Therefore, how to provide a unique method for analyzing integrated circuit reliability test data for different types of integrated circuits based on the differences among integrated circuits has become an urgent problem to be solved.

[0005] Exemplarily, a patent application titled "Integrated Circuit and Testing Method Thereof" (Application No.: CN98803503.0, Main Classification No.: G06F11 / 22) designed an integrated circuit and a method for testing it, indicating that in the field of integrated circuit testing, it is feasible to adopt electrical digital data processing, specifically detailed technologies related to the type or purpose of circuit design. Summary of the Invention

[0006] Embodiments of this application provide a method for analyzing integrated circuit reliability test data to at least partially solve the above technical problems.

[0007] Embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a method for analyzing integrated circuit reliability test data, the method including:

[0009] Based on a preset test means, perform a reliability test on a target integrated circuit, and use the collected data as data to be analyzed;

[0010] Based on the data to be analyzed, determine the failure rate of the target integrated circuit at each moment during which the reliability test is performed;

[0011] Determine the first conversion moment; the first conversion moment is used to characterize the time node for converting from early failure to accidental failure;

[0012] Determine the second conversion moment; the second conversion moment is the starting moment of the specified duration when, after the first conversion moment, the slope of the curve of the failure rate is positive within a preset specified duration;

[0013] Take the time period between the starting moment of performing the reliability test and the first conversion moment as early failure; take the time period between the first conversion moment and the second conversion moment as accidental failure; take the time period between the second conversion moment and the ending moment of performing the reliability test as wear-out failure;

[0014] Determine the first weight value; the first weight value is used to characterize the impact of the defects of the target integrated circuit on the accidental failure;

[0015] Determine the second weight value; the second weight value is used to characterize the impact of the defects of the target integrated circuit on the service life of the target integrated circuit; when the duration of the service life is greater than a preset service life threshold, the second weight value is negatively correlated with the failure rate at the first conversion moment;

[0016] When the average failure rate of the accidental failure is less than a preset failure rate threshold, if the duration of the service life is greater than the service life threshold, then use the first weight value and the second weight value to weight the failure rate to obtain the target failure rate;

[0017] Based on the target failure rate, obtain the data analysis result of the target integrated circuit.

[0018] In an optional embodiment of the present specification, using the first weight value and the second weight value to weight the failure rate to obtain the target failure rate includes:

[0019] Use the first weight value to weight the failure rate of the early failure; use the second weight value to weight the failure rates of the accidental failure and the wear-out failure to obtain the target failure rate.

[0020] In an optional embodiment of the present specification, the method further includes:

[0021] When the average failure rate of the accidental failure is not less than the failure rate threshold, if the duration of the usage period is greater than the usage period threshold, it is determined whether the maximum failure rate of the early failure is greater than a preset maximum failure rate threshold; if so, it is determined that the data analysis result of the target integrated circuit is defective; and / or,

[0022] The first conversion moment is the moment between the time node when the slope of the failure rate curve first appears less than a preset first slope threshold and the time node when the slope of the failure rate curve subsequently first appears greater than a preset second slope threshold; both the first slope threshold and the second slope threshold are less than zero, and the first slope threshold is less than the second slope threshold.

[0023] In an optional embodiment of the present specification, the method further includes:

[0024] If the maximum failure rate of the early failure is not greater than the maximum failure rate threshold, it is determined that the data analysis result of the target integrated circuit is poorly designed.

[0025] In an optional embodiment of the present specification, the method further includes:

[0026] When the average failure rate of the accidental failure is not less than the failure rate threshold, if the duration of the usage period is not greater than the usage period threshold, it is determined that the data analysis result of the target integrated circuit is unqualified.

[0027] In an optional embodiment of the present specification, the method further includes:

[0028] When the average failure rate of the accidental failure is less than the failure rate threshold, if the duration of the usage period is not greater than the usage period threshold, it is determined that the data analysis result of the target integrated circuit is poorly designed.

[0029] In an optional embodiment of the present specification, the method further includes:

[0030] The test means is a high-pressure steam aging test.

[0031] In an optional embodiment of the present specification, the method further includes:

[0032] The first weight value is positively correlated with the ratio of the duration of the early failure to the duration of performing the reliability test, and negatively correlated with the ratio of the accidental failure to the duration of performing the reliability test; and, the first weight value in the case where the ratio of the duration of the early failure to the duration of performing the reliability test is greater than a preset ratio threshold is greater than the first weight value in the case where the ratio of the duration of the early failure to the duration of performing the reliability test is not greater than the ratio threshold.

[0033] In an optional embodiment of the present specification, the method further includes:

[0034] The ratio threshold is negatively correlated with the average failure rate of the early failure.

[0035] In a second aspect, an integrated circuit reliability test data analysis device is further provided in an embodiment of the present application, which is used to implement the method steps in the first aspect.

[0036] In a third aspect, an electronic device is further provided in an embodiment of the present application, including:

[0037] a processor; and

[0038] a memory arranged to store computer-executable instructions, and the executable instructions, when executed, cause the processor to execute the method steps described in the first aspect.

[0039] In a fourth aspect, a computer-readable storage medium is further provided in an embodiment of the present application. The computer-readable storage medium stores one or more programs, and when the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to execute the method steps described in the first aspect.

[0040] The above at least one technical solution adopted in the embodiments of the present application can achieve the following beneficial effects:

[0041] The technical solutions in this specification divide several stages of the service life of the target integrated circuit in terms of the failure rate, which can effectively quantify and characterize the possible defects and design problems of the integrated circuit through its performance, and reflect the individual characteristics of the integrated circuit. Further, in the process of test data analysis, the first weight value and the second weight value are used to process the data. The first weight value is used to characterize the impact of the defects of the target integrated circuit on the accidental failure. The defects are mainly caused by material defects and design problems. Such problems not only occur intensively in the early failure stage, but the resulting impact will also affect the subsequent accidental failure. The accidental failure stage is also the stage that best reflects the service value of the integrated circuit. The method in this specification can more specifically characterize the actual risk situation during the online use of the integrated circuit. The second weight value is used to characterize the impact of the defects of the target integrated circuit on its service life. Even in the wear-out failure stage, the integrated circuit should not cause destructive consequences to its performance due to severe sudden failures. The technical means in this specification can to a certain extent characterize such risks, and thus have a certain predictability of the losses caused by the complete failure of the integrated circuit. On the one hand, it can realize digital data processing, specifically the use of detailed technologies related to the type or purpose of circuit design in the field of integrated circuit testing; on the other hand, it can also show that there is a broad expansion prospect for technology exploration in this field. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments and descriptions thereof are used to explain the present application and shall not unduly limit the present application. In the drawings:

[0043] Figure 1 It is a schematic diagram of the process of a method for analyzing the reliability test data of an integrated circuit provided by an embodiment of this specification;

[0044] Figure 2 It is a schematic diagram of the structure of an electronic device in an embodiment of this specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The present invention will be further described in detail below in conjunction with the specific embodiments and the accompanying drawings. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid overwhelming the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and the general technical knowledge in the art.

[0046] In addition, the features, operations, or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be reordered or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for clearly describing a certain embodiment and do not mean that they are the necessary sequences, unless it is stated otherwise that a certain sequence must be followed.

[0047] The serial numbers assigned to the components in this document, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. And the "connection" and "coupling" mentioned in this application, unless otherwise specified, both include direct and indirect connection (coupling).

[0048] The following will describe in detail the technical solutions provided by the embodiments of the present application in conjunction with the accompanying drawings.

[0049] As Figure 1 shown, the method for analyzing the integrated circuit reliability test data in this specification includes the following steps:

[0050] S100: Based on a preset test method, perform a reliability test on the target integrated circuit, and use the collected data as the data to be analyzed.

[0051] The reliability test in this specification is mainly qualitative and quantitative with the failure rate as the index. When the failure rate of the integrated circuit is too high, resulting in an irreversible loss of the usage performance of the integrated circuit, it is determined that the integrated circuit has completely failed, and the test can be ended. The integrated circuit is IC, and in the related art, the integrated circuit can be used as the target integrated circuit in this specification under the condition that it is allowed.

[0052] In an optional embodiment of this specification, the test means may be a Pressure Cooker Test (PCT). The researchers found through experiments that the subsequent weighting means in this specification can achieve better results in the Pressure Cooker Test. Other existing test means are also applicable to this specification when conditions permit.

[0053] S102: Based on the data to be analyzed, determine the failure rate of the target integrated circuit at each moment during the execution of the reliability test.

[0054] The failure rate refers to the probability of failure occurring at a certain moment. In the related art, all technical means that can be used to calculate the failure rate are applicable to this specification when conditions permit.

[0055] S104: Determine the first conversion moment.

[0056] The first conversion moment in this specification refers to the time node when the conversion from early failure to accidental failure occurs. In early failure, the failure rate of the integrated circuit shows a rapid downward trend. In accidental failure, the failure rate of the integrated circuit remains relatively stable. The reasons for failure are on the one hand randomly generated under environmental influence, and on the other hand affected by factors such as integrated circuit defects.

[0057] In an optional embodiment of this specification, the first conversion moment is the moment between the time node when the slope of the failure rate curve first appears less than a preset first slope threshold and the time node when the slope of the failure rate curve subsequently first appears greater than a preset second slope threshold. Both the first slope threshold and the second slope threshold are empirical values, related to the situation of the integrated circuit and also related to the test conditions. Both the first slope threshold and the second slope threshold are less than zero, and the first slope threshold is less than the second slope threshold.

[0058] S106: Determine the second conversion moment.

[0059] The second conversion moment in this specification is the time node when the conversion from accidental failure to wear-out failure occurs. Ideally, the integrated circuit should be in accidental failure for a relatively long time, and the duration of wear-out failure should not be too short. In wear-out failure, the integrated circuit will show a trend of rapid increase in the failure rate, which is mainly caused by aging. However, in fact, the aging of the integrated circuit is not only related to the usage conditions but also related to various defects of the integrated circuit. The failure impact caused by such defects has actually been reflected in early failure.

[0060] The second conversion moment is the starting moment of the specified duration when, after the first conversion moment, the slope of the curve of the failure rate is positive within the preset specified duration. In practical applications, both the first conversion moment and the second conversion moment can be inflection points. The specified duration can be an empirical value.

[0061] S108: Take the time period between the starting moment of performing the reliability test and the first conversion moment as the early failure; take the time period between the first conversion moment and the second conversion moment as the accidental failure; take the time period between the second conversion moment and the ending moment of performing the reliability test as the wear-out failure.

[0062] Normally, the usage cycle (also known as the "life cycle") of an integrated circuit will include the above three stages. However, there are also extreme cases. For example, if the integrated circuit fails completely during the early failure stage, it can be directly determined that the integrated circuit product is unqualified.

[0063] S110: Determine the first weight value.

[0064] The first weight value in this specification is used to characterize the impact of the defects of the target integrated circuit on the accidental failure. Both the first weight value in this specification and the second weight value to be mentioned later are values greater than 1. The larger the value, the more negative the impact caused by the defects of the integrated circuit. That is to say, the data after weighting the first weight value and the second weight value can reflect the degree of risk.

[0065] In an optional embodiment of this specification, the first weight value can be an empirical value that satisfies the following conditions: The first weight value is positively correlated with the ratio of the duration of the early failure to the duration of performing the reliability test (indicating that the unstable phenomenon presented by the early failure integrated circuit is more obvious and has stronger continuity), and is negatively correlated with the ratio of the accidental failure to the duration of performing the reliability test (in the accidental failure, the integrated circuit is in a relatively stable state, and when the duration of the accidental failure is longer, this negative impact can be diluted); and, the first weight value when the ratio of the duration of the early failure to the duration of performing the reliability test is greater than the preset ratio threshold is greater than the first weight value when the ratio of the duration of the early failure to the duration of performing the reliability test is not greater than the preset ratio threshold (if the proportion of early failure is too large, it indicates that the negative impact is more profound. This negative impact is mainly caused by defects, can be overcome, and has improvement value).

[0066] In an optional embodiment of this specification, the ratio threshold is an empirical value.

[0067] In another alternative embodiment of this specification, the ratio threshold is negatively correlated with the average failure rate of early failures to amplify the data effect and highlight the risks expressed in the data.

[0068] S112: Determine the second weight value.

[0069] The second weight value is used to characterize the impact of the defects of the target integrated circuit on the service life cycle of the target integrated circuit (including the aforementioned three stages). When the duration of the service life cycle is greater than a preset service life cycle threshold (used to characterize the designed service life of the target integrated circuit in an ideal state), the second weight value is negatively correlated with the failure rate at the first conversion moment (indicating that although the failure rate is high, it is generally stable and will not cause overly negative impacts on the use of the integrated circuit. That is to say, the integrated circuit has good robustness and is relatively stable. Even when it enters the wear-out failure stage, there will be no sharp failure, thus avoiding sudden failures without warning. This stability may contribute more to actual use than the signal processing performance of the integrated circuit).

[0070] S114: When the average failure rate of the accidental failures is less than a preset failure rate threshold, if the duration of the service life cycle is greater than the service life cycle threshold, then use the first weight value and the second weight value to weight the failure rate to obtain the target failure rate.

[0071] On the one hand, the target failure rate obtained through weighting can reflect the impact of defects on accidental failures. After all, accidental failures are the main stage for the integrated circuit to stably perform its functions. Quantifying and characterizing the possible risks is conducive to a more comprehensive understanding of the online use situation of the target integrated circuit. On the other hand, it can also quantify the impact of defects on the robustness of the entire service life cycle of the target integrated circuit, making the analysis results more comprehensive.

[0072] In an alternative embodiment of this specification, the weighting method can be to use the first weight value to weight the failure rate of the early failures, in order to amplify the impact of the phenomena shown by the defects of the early failures on the accidental failures, and more importantly, to amplify the mismatch effect between material selection and structural design; use the second weight value to weight the failure rates of the accidental failures and the wear-out failures. The second weight value is used to characterize the impact on the entire service life cycle of the integrated circuit. This impact mainly focuses on the impact on the accidental failures where the integrated circuit stably performs its functions on the one hand; on the other hand, it is necessary to examine whether there is a problem that the integrated circuit will suddenly completely fail during the wear-out failure without giving the user time to handle the risk event.

[0073] In another optional embodiment of this specification, the failure rates of the three stages can also be weighted by a second weight value. This embodiment can be adopted when the average failure rate during the entire usage period is too high (for example, greater than a corresponding preset threshold), so as to further amplify the impact caused by defects.

[0074] The second weight value is determined when the duration of the usage period is greater than a preset usage period threshold. When the duration of the usage period is not greater than the usage period threshold, there is no need to determine the second weight value. At this time, the main consideration is the magnitude relationship between the average failure rate of accidental failures and the preset failure rate threshold. In this embodiment, when the average failure rate of the accidental failures is not less than the failure rate threshold (indicating a high failure rate), if the duration of the usage period is not greater than the usage period threshold (indicating that the target integrated circuit cannot reach the expected service life), then it is determined that the data analysis result of the target integrated circuit is unqualified. When the average failure rate of the accidental failures is less than the preset failure rate threshold, if the duration of the usage period is not greater than the usage period threshold, then it is determined that the data analysis result of the target integrated circuit is poorly designed.

[0075] In addition, in a further optional embodiment of this specification, when the average failure rate of the accidental failures is not less than the failure rate threshold (indicating a high failure rate), if the duration of the usage period is greater than the usage period threshold (indicating that the target integrated circuit can still be used for a long time and has a certain robustness), then it is determined whether the maximum failure rate of the early failures is greater than a preset maximum failure rate threshold (which can be an empirical value and is usually used to characterize the maximum failure rate allowed for the target integrated circuit when it reaches a preset performance index (such as the electrical signal processing efficiency)); if so, it is determined that the data analysis result of the target integrated circuit is defectively poor (there is a mismatch between material selection and structural design, and even both may be problematic). If the maximum failure rate of the early failures is not greater than the maximum failure rate threshold, then it is determined that the data analysis result of the target integrated circuit is poorly designed.

[0076] S116: Obtain the data analysis result of the target integrated circuit based on the target failure rate.

[0077] In the related art, technical means capable of analyzing an integrated circuit based on data collected from testing the integrated circuit are applicable to this specification whenever conditions permit.

[0078] The data analysis results obtained through the technical means in this specification can be used to guide the improvement of details related to the type or purpose of circuit design. For example, when the results obtained from data analysis indicate that the target integrated circuit has defects (both in material selection and structural layout design), designers can improve the materials and structure of the target integrated circuit to make it have better performance. When the results obtained from data analysis indicate that the target integrated circuit only has design defects, designers can improve the structural layout of the target integrated circuit. When the results obtained from data analysis indicate that the target integrated circuit has no defects, the target integrated circuit can be put into use. When the results obtained from data analysis indicate that the target integrated circuit product is unqualified, it can be considered that there is not much room for improvement for this integrated circuit, and efforts can be made to start researching and developing new products.

[0079] Of course, the target integrated circuit may also have problems with material selection. However, the defects caused by material selection are often related to the structural design. This kind of problem is more about the mismatch between material selection and structural design, and usually both will be manifested at the same time.

[0080] The technical solution in this specification divides several stages of the target integrated circuit's usage cycle based on the performance of the failure rate, and can effectively quantify and characterize the possible defects and design problems of the integrated circuit through the usage performance of the integrated circuit, and can reflect the individual characteristics of the integrated circuit. Further, in the process of test data analysis, the first weight value and the second weight value are used to process the data. The first weight value is used to characterize the impact of the defects of the target integrated circuit on the accidental failure. The defects are mainly caused by material defects and design problems. Such problems not only occur concentratedly in the early failure stage, but the resulting impact will also affect the subsequent accidental failure. And the accidental failure stage is also the stage that can best reflect the usage value of the integrated circuit. The method in this specification can more specifically characterize the actual risk situation of the integrated circuit in on-line use. The second weight value is used to characterize the impact of the defects of the target integrated circuit on the usage cycle of the target integrated circuit. Even in the wear-out failure stage, the integrated circuit should not cause destructive consequences to the usage performance due to severe sudden failure. The technical means in this specification can characterize this kind of risk to a certain extent, and thus has a certain predictability for the losses caused by the complete failure of the integrated circuit. On the one hand, it can realize digital data processing, specifically the use of detailed technologies related to the type or purpose of circuit design in the field of integrated circuit testing; on the other hand, it can also show that there is a relatively broad expansion prospect for technology exploration in this field.

[0081] Figure 2It is a schematic structural diagram of an electronic device according to an embodiment of the present application. Please refer to Figure 2 , at the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. Among them, the memory may include a memory, such as a high-speed random access memory (Random-Access Memory, RAM), and may also include a non-volatile memory, such as at least one disk memory, etc. Of course, the electronic device may also include other hardware required for other services.

[0082] The processor, network interface, and memory can be interconnected through an internal bus, and the internal bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 2 only a bidirectional arrow is used in

[0083] but it does not mean that there is only one bus or one type of bus.

[0084] The memory is used to store programs. Specifically, the program may include program code, and the program code includes computer operation instructions. The memory can include a memory and a non-volatile memory, and provide instructions and data to the processor.

[0085] The above is as described in the present application Figure 1A method for analyzing integrated circuit reliability test data disclosed in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0086] The electronic device can also execute Figure 1 a method for analyzing integrated circuit reliability test data, and implement Figure 1 the functions of the illustrated embodiment. The embodiments of the present application will not be elaborated herein.

[0087] The embodiments of the present application also propose a computer-readable storage medium that stores one or more programs. The one or more programs include instructions that, when executed by an electronic device including multiple application programs, execute any of the foregoing methods for analyzing integrated circuit reliability test data.

[0088] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0089] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0090] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0091] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0092] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and a memory.

[0093] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0094] A computer-readable medium includes permanent and non-permanent, removable and non-removable media that can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0095] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.

[0096] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0097] The above description is only for the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A method for analyzing integrated circuit reliability test data, characterized in that: The method comprises: Based on the preset test means, reliability test is performed on the target integrated circuit, and the collected data is used as data to be analyzed; Determining, based on the data to be analyzed, the failure rate of the target integrated circuit at each time point during the execution of the reliability test; Determine a first conversion moment; the first conversion moment is used to represent the time node of conversion from early failure to accidental failure; Determine a second conversion time; the second conversion time is the starting time of the specified time period when the failure rate curve has a positive slope after the first conversion time period; The time period between the start time of executing the reliability test and the first switching time is regarded as an early failure; the time period between the first switching time and the second switching time is regarded as an accidental failure; and the time period between the second switching time and the end time of executing the reliability test is regarded as a loss failure; Determining a first weight value; the first weight value is used to characterize the impact of the defect of the target integrated circuit on the accidental failure; Determine a second weight value; the second weight value is used to characterize the impact of the defect of the target integrated circuit on the use cycle of the target integrated circuit; when the duration of the use cycle is greater than a preset use cycle threshold, the second weight value is negatively correlated with the failure rate of the first conversion moment; In the case where the average failure rate of the accidental failure is less than the preset failure rate threshold, if the duration of the use cycle is greater than the use cycle threshold, the failure rate is weighted by using the first weight value and the second weight value to obtain a target failure rate; Based on the target failure rate, a data analysis result of the target integrated circuit is obtained.

2. The method according to claim 1, characterized in that: The failure rate is weighted by using the first weight value and the second weight value to obtain a target failure rate, including: The first weight value is used to weight the failure rate of the early failure; the second weight value is used to weight the failure rates of the accidental failure and the wear failure to obtain the target failure rate.

3. The method according to claim 1, characterized in that: The method further comprises: In the case where the average failure rate of the accidental failure is not less than the failure rate threshold, if the duration of the use cycle is greater than the use cycle threshold, then it is determined whether the maximum failure rate of the early failure is greater than a preset maximum failure rate threshold; if so, it is determined that the data analysis result of the target integrated circuit is defective; and / or, The first conversion moment is a moment between a time node when the slope of the failure rate curve first appears to be less than a preset first slope threshold and a time node when the slope of the failure rate curve first appears to be greater than a preset second slope threshold; the first slope threshold and the second slope threshold are both less than zero, and the first slope threshold is less than the second slope threshold.

4. The method according to claim 3, characterized in that: The method further comprises: If the maximum failure rate of the early failures is not greater than the maximum failure rate threshold, it is determined that the data analysis result of the target integrated circuit is a poor design.

5. The method according to claim 1, characterized in that: The method further comprises: In the case where the average failure rate of the accidental failures is not less than the failure rate threshold, if the duration of the usage cycle is not greater than the usage cycle threshold, it is determined that the data analysis result of the target integrated circuit is a product failure.

6. The method according to claim 1, characterized in that: The method further comprises: In the case where the average failure rate of the accidental failures is less than the failure rate threshold, if the duration of the usage cycle is not greater than the usage cycle threshold, it is determined that the data analysis result of the target integrated circuit is a poor design.

7. The method according to claim 1, characterized in that: The method further comprises: The test method is a high pressure cooking test.

8. The method according to claim 1, characterized in that: The method further comprises: The first weight value is positively correlated with the ratio of the duration of the early failure to the duration of executing the reliability test, and negatively correlated with the ratio of the accidental failure to the duration of executing the reliability test; and the first weight value when the ratio of the duration of the early failure to the duration of executing the reliability test is greater than a preset ratio threshold is greater than the first weight value when the ratio of the duration of the early failure to the duration of executing the reliability test is not greater than the ratio threshold.

9. The method according to claim 8, characterized in that The method further comprises: The ratio threshold is negatively correlated with the average failure rate of the early failures.

10. A computer-readable storage medium storing one or more programs, which, when executed by an electronic device including a plurality of application programs, causes the electronic device to execute any one of the methods of claims 1 to 9.

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