Low dropout regulator, power management module and electronic product
By designing a low dropout linear voltage regulator without feedback resistance, using the pseudo ESR zero point to achieve frequency compensation, the problems of LDO output noise, large power consumption, and deterioration of transient response are solved, and low noise and low power consumption power management is achieved.
Patent Information
- Application Number
- CN202311630255.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-30
- Publication Date
- 2025-05-30
AI Technical Summary
In the prior art, frequency compensation leads to problems such as high noise, high power consumption, and deterioration of transient response.
A low dropout linear voltage regulator is designed, including an error amplifier, a power tube, a sampling tube, a first resistor, a second resistor, a first capacitor and a second capacitor, and a pseudo ESR zero point is generated without introducing a feedback resistor, reducing output noise and power consumption.
It effectively reduces output noise, reduces cost and power consumption, and avoids deterioration in transient response during frequency compensation.
Smart Images
Figure CN120066191A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and particularly to a low dropout linear regulator, a power management module and an electronic product. Background Art
[0002] Currently, the requirements for power management modules in electronic device applications mainly focus on power consumption and noise. As one of the key power management modules, the requirements for power consumption and noise of LDO (Low Dropout Regulator) are constantly increasing. The reduction of power consumption leads to an increase in the output impedance of the internal nodes of the LDO and a decrease in the frequency of parasitic poles, making frequency compensation complex. For LDOs with large load currents, an external capacitor is a commonly used option. The following are two frequency compensation methods for this structure:
[0003] One method is to increase the external resistor R ESR , as Figure 1 shown, an error amplifier 1 and a power transistor M1 are provided inside the chip; the source of the power transistor M1 is connected to the power supply Vin, and the drain is used as the output terminal of the chip; the error amplifier 1 is connected to the drain of the power transistor M1, compares the output voltage Vout with the reference voltage V REF , and adjusts the power transistor M1 based on the comparison result to control the output voltage Vout; a load capacitor C L and a load equivalent resistor R L are provided outside the chip. The external resistor R ESR is the equivalent series resistance (Equivalent Series Resistance, ESR) of the load capacitor C L on the PCB. The zero point formed by it and the load capacitor C L can cancel the secondary poles of the loop to achieve frequency compensation. The position of the zero point is: However, even for load capacitors C L with the same capacitance value, the equivalent series resistance R L of the load capacitors C ESR produced by different manufacturers is different. Some manufacturers will provide the resistance value of this equivalent series resistance, while some manufacturers will not. Moreover, the resistance value of this equivalent series resistance R ESR will change with temperature, making it difficult to compensate for the stability of the loop. In addition, a large equivalent series resistance increases overshoot and undershoot and deteriorates the power supply rejection ratio at high frequencies; while the equivalent series resistance of cheap small ceramic capacitors is very small and cannot achieve a good compensation effect.
[0004] Another method is to use on-chip pseudo-equivalent series resistance. Jianping Guo et al. proposed a low-power frequency compensation scheme [A Sub 1μA Improved Transient CMOS Low Dropout Regulator without Minimal ESR Requirement] based on a phase-lead compensation topology. The off-chip load capacitance only needs an inexpensive small ceramic capacitor to meet the stability requirements. As Figure 2 shown, the chip internally sets an error amplifier 2, a buffer 3, a power transistor M2, a sampling transistor M3, a resistor Rf1, a resistor Rf2, a resistor Rc, and a capacitor C F ; the source of the power transistor M2 is connected to the power supply Vin, and the drain is used as the chip output terminal; the source of the sampling transistor M3 is connected to the power supply voltage Vin, and the drain is connected to the chip output terminal via the resistor Rc; the resistors Rf1 and Rf2 are connected in series between the chip output terminal and the reference ground; one end of the capacitor C F is connected to the connection node of the resistors Rf1 and Rf2, and the other end is connected to the drain of the sampling transistor M3; the error amplifier 2 is connected to the connection node of the resistors Rf1 and Rf2, compares the feedback signal of the output voltage Vout with the reference voltage V REF , and adjusts the power transistor M2 and the sampling transistor M3 through the buffer 3 based on the comparison result to achieve the control of the output voltage Vout; an external load capacitor C L and a load equivalent resistance R L are set outside the chip. The ratio of the power transistor M2 to the sampling transistor M3 is k:1 (k>>1). Under certain constraint conditions, the zero point generated by this circuit is:
[0005]
[0006] It can be seen that the effect of this circuit is very similar to the equivalent series resistance R L of the load capacitor C in the first scheme, and its corresponding pseudo-ESR value is R ESR / k. The constraint conditions for this equation to hold are: C
[0007]
[0008]
[0009] This compensation scheme introduces resistors Rf1 and Rf2 to generate a pseudo-ESR zero. At the same time, it can be seen from the constraint conditions that the resistance value of resistor Rf1 needs to be very large, and the resistance values of resistor Rf1 and resistor Rf2 are in the same order of magnitude. The noise of resistor Rf1 is transferred to the output with a voltage transfer gain equal to 1, the noise of resistor Rf2 is transferred to the output with a voltage transfer gain of Rf1 / Rf2, and the noise of error amplifier 2 is transferred to the output with a voltage transfer gain of (1 + Rf1 / Rf2). Therefore, although this scheme only requires a cheap small ceramic capacitor for the external capacitor, which reduces the cost, it deteriorates the noise; especially when Rf1 / Rf2 is large, the noise of resistor Rf2 and error amplifier 2 will be greatly amplified, and it cannot meet the low-noise application requirements.
[0010] Some other schemes regenerate a zero to replace the zero generated by the equivalent series resistance of the load capacitor, but active circuits need to be added in these schemes, which means an increase in circuit power consumption.
[0011] It can be seen from this that in the prior art, in order to achieve frequency compensation, either external resistors are added, or on-chip pseudo-equivalent series resistors are used, or new zeros are generated. These schemes inevitably deteriorate the LDO transient response, increase the LDO output noise and power consumption. Therefore, how to reduce the LDO output noise and power consumption while not affecting the LDO transient response has become one of the problems that need to be solved urgently by those skilled in the art.
[0012] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention
[0013] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a low dropout linear regulator, a power management module and an electronic product, which are used to solve the problems such as large LDO output noise, large power consumption and deteriorated transient response caused by frequency compensation in the prior art.
[0014] To achieve the above purpose and other related purposes, the present invention provides a low dropout linear regulator, characterized in that the low dropout linear regulator at least includes:
[0015] An error amplifier, a power transistor, a sampling transistor, a first resistor, a second resistor, a first capacitor and a second capacitor;
[0016] The first end of the power transistor is connected to the power supply voltage, and the second end is used as the output end of the low dropout linear regulator;
[0017] The first end of the sampling tube is connected to the power supply voltage, and the second end is connected to the second end of the power tube via the second resistor;
[0018] The first end of the first resistor is connected to the second end of the power tube, and the second end is connected to the second end of the sampling tube via the first capacitor;
[0019] One end of the second capacitor is connected to the second end of the power tube, and the other end is grounded;
[0020] The first input terminal of the error amplifier is connected to the second end of the first resistor, the second input terminal receives a reference voltage, and the output terminal is connected to the control terminals of the power tube and the sampling tube.
[0021] Optionally, the voltage at the second end of the sampling tube satisfies:
[0022]
[0023] where Vc is the voltage at the second end of the sampling tube; Vout is the output voltage of the low-dropout linear regulator, s is the Laplace variable; R2 is the resistance value of the second resistor; k is the ratio of the width-to-length ratio of the power tube to the sampling tube, and k is greater than 10; R L is the equivalent resistance of the load; C2 is the capacitance value of the second capacitor.
[0024] More optionally, the devices in the low-dropout linear regulator satisfy the following relational expression:
[0025]
[0026]
[0027] where R1 is the resistance value of the first resistor, and C1 is the capacitance value of the first capacitor.
[0028] More optionally, the zero position of the low-dropout linear regulator satisfies:
[0029]
[0030] where ω z is the angular frequency corresponding to the zero position.
[0031] Optionally, the output noise of the low-dropout linear regulator satisfies:
[0032] S n,o (f) = S n,ea (f) + S n,ref (f);
[0033] where S n,o(f) is the output noise power of the low dropout linear regulator; S n,ea (f) is the equivalent input noise power of the error amplifier; S n,ref (f) is the noise power of the reference voltage.
[0034] Optionally, the low dropout linear regulator further includes a buffer, and the buffer is connected between the output end of the error amplifier and the control ends of the power tube and the sampling tube.
[0035] Optionally, the power tube and the sampling tube are PMOS tubes or PNP triodes.
[0036] More optionally, the first input end of the error amplifier is the non-inverting input end, and the second input end is the inverting input end.
[0037] To achieve the above and other related purposes, the present invention further provides a power management module, and the power management module at least includes: the above-mentioned low dropout linear regulator.
[0038] To achieve the above and other related purposes, the present invention further provides an electronic product, and the electronic product at least includes: the above-mentioned low dropout linear regulator.
[0039] As described above, the low dropout linear regulator, the power management module and the electronic product of the present invention have the following beneficial effects:
[0040] 1. The low dropout linear regulator, the power management module and the electronic product of the present invention generate a pseudo-ESR zero point without introducing feedback resistors ( Figure 2 Rf1 and Rf2 in it), and the voltage transfer gain from the noise of the error amplifier to the output end is unit gain (the amplification factor is 1). Since there is no feedback resistor, there is also no noise of the feedback resistor, and the output noise can be effectively reduced.
[0041] 2. Since the present invention does not need to introduce a feedback resistor and does not need to add an active circuit to provide a zero point, the cost can be effectively reduced and the power consumption can be reduced. Description of the Drawings
[0042] Figure 1 It shows a schematic structural diagram of an LDO that realizes frequency compensation by using an off-chip resistor.
[0043] Figure 2 It shows a schematic structural diagram of an LDO that realizes frequency compensation by using an on-chip pseudo-equivalent series resistor.
[0044] Figure 3 It shows a schematic structural diagram of a unity gain compensation module.
[0045] Figure 4It shows a schematic diagram of the principle of the low-dropout linear regulator of the present invention.
[0046] Figure 5 It shows a schematic diagram of the structure of the low-dropout linear regulator of the present invention.
[0047] Description of component labels
[0048] 1 Error amplifier
[0049] 2 Error amplifier
[0050] 3 Buffer
[0051] 4 Unity-gain compensation module
[0052] 41 Error amplifier
[0053] 5 Low-dropout linear regulator
[0054] 51 Error amplifier
[0055] 52 Buffer Detailed implementation manners
[0056] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0057] Please refer to Figures 3 to 5 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0058] As Figure 3 shown, the unity-gain compensation module 4 includes an error amplifier 41, a resistor Ra, and capacitors C f and C L ; one end of the resistor Ra is connected to the output end of the error amplifier 41, and the other end outputs a feedback voltage Vfb and is connected to the inverting input end of the error amplifier 41; the non-inverting input end of the error amplifier 41 receives an input signal In; one end of the capacitor C f is connected to the inverting input end of the error amplifier 41, and the other end is grounded; one end of the capacitor C L is connected to the output end of the error amplifier 41, and the other end is grounded. Based on the unity-gain compensation module 4, while maintaining the capacitor Cf One end is connected to the error amplifier 41, and the other end is adjusted from the reference ground to (1 + sRx Cx)Vout, where s is the Laplace variable, Rx is a preset resistor, Cx is a preset capacitor, and Vout is the output voltage. As Figure 4 shown, we can obtain:
[0059]
[0060] If certain constraints are met, a zero point can be introduced into the transfer function, that is:
[0061]
[0062] Based on the above principle, the present invention proposes a low dropout linear regulator 5, as Figure 5 shown. The low dropout linear regulator 5 includes:
[0063] An error amplifier 51, a power transistor MP, a sampling transistor MS, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.
[0064] As Figure 5 shown, the first end of the power transistor MP is connected to the power supply voltage Vin, and the second end serves as the output end of the low dropout linear regulator 5.
[0065] Specifically, the power transistor MP is used to regulate the output current, thereby realizing the adjustment of the output voltage Vout; any device that can perform power adjustment based on the output signal of the error amplifier 51 is applicable to the present invention, including but not limited to PMOS transistors and PNP bipolar transistors, which will not be elaborated here one by one. In this embodiment, the power transistor MP is implemented using a PMOS transistor. Correspondingly, the source of the power transistor MP is connected to the power supply voltage Vin, and the drain serves as the output end of the low dropout linear regulator 5.
[0066] As Figure 5 shown, the first end of the sampling transistor MS is connected to the power supply voltage Vin, and the second end is connected to the second end of the power transistor MP (i.e., the output end of the low dropout linear regulator 5) via the second resistor R2.
[0067] Specifically, the sampling transistor MS is used for sampling. Any device that can implement the sampling function is applicable to the present invention, including but not limited to PMOS transistors and PNP bipolar transistors, which will not be elaborated here one by one. In this embodiment, to simplify the circuit structure, the control logic of the sampling transistor MS is the same as that of the power transistor MP (i.e., both are turned on when receiving a control signal of the first level and turned off when receiving a control signal of the second level); as an example, the sampling transistor MS is implemented using a PMOS transistor. Correspondingly, the source of the sampling transistor MS is connected to the power supply voltage Vin, and the drain is connected to the second resistor R2.
[0068] AsFigure 5 As shown, the first end of the first resistor R1 is connected to the second end of the power transistor MP, and the second end is connected to the second end of the sampling transistor MS via the first capacitor C1.
[0069] Specifically, in this embodiment, one end of the first resistor R1 is connected to the drain of the power transistor MP, and the second end is connected to the drain of the sampling transistor MS via the first capacitor C1.
[0070] As Figure 5 shown, one end of the second capacitor C2 is connected to the second end of the power transistor MP (i.e., the output end of the low dropout linear regulator 5), and the other end is grounded.
[0071] Specifically, the second capacitor C2 acts as a load capacitor, and based on the conduction and cutoff of the power transistor MP, it realizes charging and discharging to stabilize the output voltage Vout, reduce voltage fluctuations and noise. It should be noted that when the low dropout linear regulator 5 of the present invention is packaged in a chip, in order to reduce the chip area, the second capacitor C2 is often arranged outside the chip; for the case where the chip area requirement is not high, the second capacitor C2 can also be arranged inside the chip. In this embodiment, the second capacitor C2 is implemented by using an inexpensive small ceramic capacitor. In actual use, any capacitor type is applicable to the present invention.
[0072] As Figure 5 shown, the first input end of the error amplifier 51 is connected to the second end of the first resistor R1, the second input end receives the reference voltage V REF , and the output end is connected to the control ends of the power transistor MP and the sampling transistor MS.
[0073] Specifically, the error amplifier 51 amplifies the difference between the feedback voltage Vfb and the reference voltage V REF . In this embodiment, the non-inverting input end of the error amplifier 51 receives the feedback voltage Vfb, the inverting input end receives the reference voltage V REF , outputs an amplified signal of Vfb - V REF and acts on the gates of the power transistor MP and the sampling transistor MS; when the feedback voltage Vfb is greater than the reference voltage V REF , a high-level signal is output to turn off the power transistor MP and the sampling transistor MS, so that the output voltage Vout decreases; when the feedback voltage Vfb is less than the reference voltage V REF , a low-level signal is output to turn on the power transistor MP and the sampling transistor MS, so that the output voltage Vout increases. In actual use, the corresponding relationship between the input signal and the input terminal polarity of the error amplifier 51 can be configured according to the device types and control logics of the power transistor MP and the sampling transistor MS, and it is not limited to this embodiment.
[0074] As another implementation of the present invention, the low dropout linear regulator 5 further includes a buffer 52, and the buffer 52 is connected between the output end of the error amplifier 51 and the control ends of the power transistor MP and the sampling transistor MS.
[0075] Specifically, based on the structure of the low dropout linear regulator 5 of the present invention, the voltage Vc at the second end of the sampling transistor MS satisfies the following relational expression:
[0076]
[0077] where z l is an intermediate variable and satisfies i_sen is the sampling current; s is the Laplace variable; R2 is the resistance value of the second resistor; R L is the equivalent resistance of the load; C2 is the capacitance value of the second capacitor; k is the ratio of the width-to-length ratio of the power transistor MP to the sampling transistor MS, and k >> 1. In this embodiment, a difference of one order of magnitude or more is considered to be much greater. As an example, k is set to 10, 30, 50, 70, 90, 100, 150, 200, 500, 1000, and the specific value is configured according to needs and will not be elaborated here one by one. Then,
[0078]
[0079] In this embodiment, in order to make the above formula hold, each device in the low dropout linear regulator 51 satisfies the following relational expressions (constraint conditions):
[0080]
[0081]
[0082] where R1 is the resistance value of the first resistor and C1 is the capacitance value of the first capacitor. It should be noted that the parameters in the above formulas (4) and (5) are configured according to needs as long as the above formula (3) can hold; in this embodiment, a difference of one order of magnitude or more is considered to be much greater, including but not limited to 10, 25, 50, 80, 90, 100, 150, 200, 700, 1000, and will not be elaborated here one by one.
[0083] The zero point position of the low dropout linear regulator 5 of the present invention satisfies:
[0084]
[0085] where ω z is the angular frequency corresponding to the zero point position. Therefore, the zero point (causing phase rise) formed by the second resistor R2 and the second capacitor C2 of the present invention can cancel the original pole (causing phase drop) to achieve frequency compensation.
[0086] Specifically, the output noise of the low dropout linear regulator 5 of the present invention satisfies:
[0087] S n,o (f) = S n,ea (f) + S n,ref (f) (7);
[0088] Wherein, S n,o (f) is the output noise power of the low dropout linear regulator 5; S n,ea (f) is the equivalent input noise power of the error amplifier 51; S n,ref (f) is the noise power of the reference voltage V REF .
[0089] In the background art Figure 2 the output noise of the corresponding solution satisfies:
[0090]
[0091] Wherein, S n,o1 (f) is the Figure 2 output noise power of the LDO; S n,ea1 (f) is the equivalent input noise power of the error amplifier 2; S n,ref1 (f) is the Figure 2 noise power of the reference voltage V REF in; S n,Rf2 (f) is the power noise of the resistor Rf2; S n,Rf1 (f) is the power noise of the resistor Rf1.
[0092] Based on Equation (7) and Equation (8), it can be seen that the noise of the differential amplifier 51 of the present invention with respect to the reference voltage V REF will not be amplified, but is transferred to the output end with unit gain. Figure 2 The noise of the error amplifier 2 in REF and the noise of the reference voltage V are amplified by times, and the larger Figure 2 is, the larger the amplification factor is; the resistors Rf2 and Rf1 also introduce noise. Therefore, the output noise power of the present invention is much smaller than
[0093] The present invention also provides a power management module, which at least includes: the low dropout linear regulator 5 of the present invention. The power management module may also include, but is not limited to, a DC conversion unit and a voltage regulation unit, which will not be elaborated here one by one.
[0094] The present invention further provides an electronic product, which at least includes: the low dropout linear regulator 5 of the present invention; the low dropout linear regulator 5 supplies power to other modules in the electronic product. The electronic product includes but is not limited to mobile phones, computers, watches, measuring instruments, which will not be elaborated here one by one.
[0095] In summary, the present invention provides a low dropout linear regulator, a power management module and an electronic product, including: an error amplifier, a power transistor, a sampling transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; the first end of the power transistor is connected to the power supply voltage, and the second end serves as the output end of the low dropout linear regulator; the first end of the sampling transistor is connected to the power supply voltage, and the second end is connected to the second end of the power transistor via the second resistor; the first end of the first resistor is connected to the second end of the power transistor, and the second end is connected to the second end of the sampling transistor via the first capacitor; one end of the second capacitor is connected to the second end of the power transistor, and the other end is grounded; the first input end of the error amplifier is connected to the second end of the first resistor, the second input end receives a reference voltage, and the output end is connected to the control ends of the power transistor and the sampling transistor. The low dropout linear regulator, the power management module and the electronic product of the present invention can effectively reduce the output noise while generating a pseudo-ESR zero point without introducing a feedback resistor; at the same time, since there is no need to introduce a feedback resistor, there is also no need to add an active circuit to provide a zero point. Therefore, the cost can be effectively reduced and the power consumption can be lowered. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0096] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A low dropout linear regulator, characterized in that, the low dropout linear regulator at least includes: an error amplifier, a power transistor, a sampling transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; a first end of the power transistor is connected to a power supply voltage, and a second end serves as an output end of the low dropout linear regulator; a first end of the sampling transistor is connected to the power supply voltage, and a second end is connected to the second end of the power transistor via the second resistor; a first end of the first resistor is connected to the second end of the power transistor, and a second end is connected to the second end of the sampling transistor via the first capacitor; one end of the second capacitor is connected to the second end of the power transistor, and the other end is grounded; a first input end of the error amplifier is connected to the second end of the first resistor, a second input end receives a reference voltage, and an output end is connected to control ends of the power transistor and the sampling transistor.
2. The low dropout linear regulator according to claim 1, characterized in that: the voltage at the second end of the sampling transistor satisfies: Where, Vc is the voltage at the second end of the sampling tube; Vout is the output voltage of the low dropout linear regulator, s is the Laplace variable; R2 is the resistance value of the second resistor; k is the ratio of the width-to-length ratio of the power tube to the sampling tube, and k is greater than or equal to 10; R L is the equivalent resistance of the load; C2 is the capacitance value of the second capacitor.
3. The low dropout linear regulator according to claim 2, characterized in that: each device in the low dropout linear regulator satisfies the following relational expression: wherein, R1 is the resistance value of the first resistor, and C1 is the capacitance value of the first capacitor.
4. The low dropout linear regulator according to claim 2 or 3, characterized in that: the zero point position of the low dropout linear regulator satisfies: where ω z is the angular frequency corresponding to the zero point position.
5. The low dropout linear regulator according to claim 1, characterized in that: the output noise of the low dropout linear regulator satisfies: S n,o f) = S n,ea f) + S n,ref f); Among them, S n,o (f) is the output noise power of the low dropout linear regulator; S n,ea (f) is the equivalent input noise power of the error amplifier; S n,ref (f) is the noise power of the reference voltage.
6. The low dropout linear regulator according to claim 1, characterized in that: the low dropout linear regulator further includes a buffer, and the buffer is connected between an output end of the error amplifier and control ends of the power transistor and the sampling transistor.
7. The low dropout linear regulator according to claim 1, characterized in that: the power transistor and the sampling transistor are PMOS transistors or PNP triodes.
8. The low dropout linear regulator according to claim 7, characterized in that: the first input end of the error amplifier is a non-inverting input end, and the second input end is an inverting input end.
9. A power management module, characterized in that, the power management module at least includes: the low dropout linear regulator according to any one of claims 1-8.
10. An electronic product, characterized in that, the electronic product at least includes: the low dropout linear regulator according to any one of claims 1-8.