Micro-power fast response low dropout linear regulator with mode control function

Abstract

The application discloses a micro-power-consumption fast-response low-voltage-difference linear voltage stabilizer with mode control function, which comprises a dual-mode controller, a SET end of an external partial voltage resistor is connected to a negative phase input end of the dual-mode controller, a positive phase end of the dual-mode controller is connected to GND, an output end of the dual-mode controller is connected to a positive phase input end of a controller of an error amplifier, and the dual-mode controller is used for adjusting the stabilizer to be in a fixed output voltage mode or an adjustable output voltage mode; a negative phase input end of the error amplifier is connected to a reference voltage V REF , an output end is connected to an input end of a driving circuit with voltage clamping function; an output end of the driving circuit with voltage clamping function is connected to a gate of an M p1 high-voltage PMOS transistor, a substrate and a source are connected to an input voltage V IN , and a drain is connected to an output end OUT of the stabilizer; when the linear voltage stabilizer is applied, the type of capacitor and the equivalent resistance of capacitor series connection do not need to be considered, and the needs of micro-power-consumption electronic system power supply and battery power supply system can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management integrated circuits, and in particular relates to a micro-power consumption fast response low voltage difference linear regulator with a mode control function. Background Art

[0002] With the continuous advancement of semiconductor process technology, the integration level of linear regulators is significantly increasing, their internal functions are becoming increasingly rich, and their power consumption is gradually decreasing. However, in practical applications, traditional linear regulators still face some challenges. In particular, their quiescent current is often in the milliampere range, which means that even when there is no load, the regulator itself consumes a certain amount of power. When such regulators are used in battery-powered electronic systems, the additional power consumption can significantly reduce the system's standby time and the battery life. This not only limits the normal operation of the powered system, but can also lead to a poor user experience and increased system maintenance costs.

[0003] Furthermore, most linear regulators currently on the market utilize fixed or adjustable output voltage models. To meet diverse user needs, the same linear regulator with a fixed nominal output voltage often needs to be designed in multiple versions, including versions with both a fixed nominal output voltage and an adjustable output voltage. This design approach not only increases tapeout times during the production process but also leads to a multitude of circuit versions with the same structure on the market, increasing management costs and making it inconvenient for users to choose and use.

[0004] Another important aspect of conventional regulator loop stability design is its focus. During the design process, the impact of the output capacitor's series equivalent resistance on loop stability must be considered. Some regulator loop stability designs utilize the output capacitor's series equivalent resistance to introduce a zero point to compensate for the loop phase and ensure system stability. However, this requires the output series equivalent resistance to be within a certain range. Other regulator loop stability designs require the output capacitor's series equivalent resistance to be close to zero to prevent the zero point from causing system loop oscillation. Therefore, mainstream linear regulators have certain requirements for the output capacitor's series equivalent resistance, requiring users to carefully consider this factor when implementing their applications, which undoubtedly increases application complexity and inconvenience. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the present invention provides a micro-power, fast-response, low-voltage difference linear regulator with a mode control function. The quiescent current of each analog branch is at the nanoampere level. Without affecting the normal operation of the regulator, two working modes are adopted. The first working mode is a fixed output voltage mode, which can provide a fixed output nominal voltage; the second working mode is an adjustable output voltage mode, and the output voltage range is 1.25V to 16.0V.

[0006] To achieve the above-mentioned object, the present invention provides the following technical solution: a micro-power fast-response low-voltage difference linear regulator with a mode control function, comprising a dual-mode controller, wherein the negative input terminal of the dual-mode controller is connected to the SET terminal of an external voltage divider resistor, the positive terminal of the dual-mode controller is connected to GND, the output terminal of the dual-mode controller is connected to the positive input terminal of the error amplifier controller, and the dual-mode controller is used to adjust the regulator to a fixed output voltage mode or an adjustable output voltage mode; the regulator output terminal OUT is connected to the third input terminal of the error amplifier, and the negative input terminal of the error amplifier is connected to the reference voltage V REF The output of the error amplifier is connected to the input of the drive circuit with a voltage clamping function, and the output of the drive circuit with a voltage clamping function is connected to M p1 Gate connection of high voltage PMOS transistor, M p1 The substrate and source of the high-voltage PMOS transistor are connected to the input voltage V IN , the drain is connected to the output terminal OUT of the regulator.

[0007] Furthermore, when the SET terminal voltage of the external voltage divider resistor is less than 50mV, the dual-mode controller sets the regulator to a fixed output voltage mode; when the SET terminal voltage of the external voltage divider resistor is greater than 200mV, the dual-mode controller sets the regulator to an adjustable output voltage mode.

[0008] Furthermore, the dual-mode controller includes a two-stage operational amplifier, a first inverter, a second inverter, an internal controllable voltage divider resistor, a one-way analog switch and a two-way analog switch. The input nodes of the dual-mode controller are SET, V OUT , the output node is Z;

[0009] Among them: the two-stage operational amplifier consists of M p1 、M p2 、M n1 、M n2 、M p3 and M p4 、M n3 Transistor composition, additional resistor R p1 、R p2 The resistor and the two-stage operational amplifier form the input and amplification part of the dual-mode controller. The specific connection relationship is: R p1 One end of the resistor is connected to SET, and the other end is connected to g7; M p1 The transistor gate is connected to g7, the source is connected to g3, the drain is connected to g1, and the substrate is connected to g3; M n1 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g1, and the substrate is connected to GND; R p2 One end of the resistor is connected to GND, and the other end is connected to g8; M p2The transistor gate is connected to g8, the source is connected to g3, the drain is connected to g2, and the substrate is connected to g3; M n2 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g2, and the substrate is connected to GND; M p3 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g3, substrate connected to V S ;M p4 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g4, substrate connected to V S ;M n3 The transistor gate is connected to g2, the source is connected to GND, the drain is connected to g4, and the substrate is connected to GND;

[0010] The first inverter is composed of M p5 and M n4 Transistor composition, used to generate the sethigh signal required by the subsequent analog switch, the specific connection relationship is: M p5 The transistor gate is connected to g4 and the source is connected to V S , drain connected to sethigh, substrate connected to V S ;M n4 The transistor gate is connected to g4, the source is connected to GND, the drain is connected to sethigh, and the substrate is connected to GND;

[0011] The second inverter is composed of M p6 and M n5 Transistor composition, used to generate the setlow signal required by the subsequent analog switch, the specific connection relationship is: M p6 The transistor gate is connected to sethigh and the source is connected to V S , drain connected to setlow, substrate connected to V S ;M n5 The transistor gate is connected to sethigh, the source is connected to GND, the drain is connected to setlow, and the substrate is connected to GND;

[0012] The internal controllable voltage divider resistor is R p3 、R p4 Resistors and M n6 The transistor is used to divide the voltage at the OUT terminal of the regulator. The specific connection relationship is: R p4 One end of the resistor is connected to OUT, and the other end is connected to g6; R p3 One end of the resistor is connected to g5 and the other end is connected to g6; M n6 The transistor gate is connected to setlow, the source is connected to GND, the drain is connected to g5, and the substrate is connected to GND;

[0013] One analog switch is M p7 and M n7The transistor is used to control the input source of the Z terminal voltage according to the status of the sethigh and setlow signals. The specific connection relationship is: M p7 The transistor gate is connected to sethigh, the source is connected to g6, the drain is connected to Z, and the substrate is connected to V S ;M n7 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to g6, and the substrate is connected to GND;

[0014] Two-way analog switch by M p8 and M n8 The transistor is used to control the connection between the SET terminal voltage and the Z terminal voltage according to the state of the sethigh and setlow signals. The specific connection relationship is: M p8 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to SET, and the substrate is connected to V S ;M n8 The transistor gate is connected to sethigh, the source is connected to SET, the drain is connected to Z, and the substrate is connected to GND.

[0015] Furthermore, when the setlow signal is high, M n6 The transistor is turned on, the voltage at node g5 is 0V, and the voltage at node g6 is [R p3 / (R p3 +R p4 )]V OUT .

[0016] Furthermore, when the voltage at the SET terminal is less than 50mV, sethigh is low and setlow is high, one analog switch is turned on and two analog switches are turned off. At this time, one analog switch connects the voltage at the Z terminal to the voltage at the g6 node, which is the internal voltage divider. At this time, the regulator is in fixed output voltage mode, and the output voltage is [1+R p4 / R p3 ]V REF .

[0017] Furthermore, when the setlow signal is low, M n6 The transistor is turned off, and the voltages of nodes g6 and g5 are both the OUT terminal voltage V OUT .

[0018] Furthermore, when the SET terminal voltage is greater than 200mV, sethigh is high and setlow is low, one analog switch is closed and the other two analog switches are opened. At this time, the two analog switches connect the Z terminal voltage to the SET node voltage, which is the voltage divider value of the external voltage divider resistors R1 and R2 on the OUT terminal voltage of the regulator. At this time, the regulator is in adjustable output voltage mode, and the output voltage is [1+R1 / R2]V REF .

[0019] Furthermore, the error amplifier is a linear differential amplifier; the external voltage divider resistors include voltage divider resistors R1 and R2; the voltage regulator is in an adjustable output mode, one end of the voltage divider resistor R2 is connected to SET and the other end is connected to GND, and one end of R1 is connected to OUT and the other end is connected to SET; the voltage regulator is in a fixed output mode, the SET end is grounded, and the voltage divider resistors R1 and R2 are not connected to the voltage regulator circuit;

[0020] Furthermore, the driving circuit with voltage clamping function includes a limiter circuit, a voltage follower circuit, a voltage buffer structure and a control circuit. The input node of the driving circuit is ampout and the output node is L9. drver ,in:

[0021] The limiter circuit is composed of M p1 、M p2 、M p3 、M p4 and M n1 Transistor composition, the specific connection method is as follows: M p1 The transistor gate is connected to f1 and the source is connected to V S , the drain is connected to f1, and the substrate is connected to V S ;M p2 The transistor gate is connected to f2, the source is connected to f1, the drain is connected to f2, and the substrate is connected to f1; M p3 The transistor gate is connected to f3, the source is connected to f2, the drain is connected to f3, and the substrate is connected to f2; M p4 The transistor gate is connected to f4, the source is connected to f3, the drain is connected to f4, and the substrate is connected to f3; M n1 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f4, and the substrate is connected to GND;

[0022] The voltage follower circuit consists of Q vp1 Transistor, M p5 Transistor, Q n1 Transistor composition, the specific connection method is as follows: M p5 The transistor gate is connected to L2 highbias , source connected to V S , the drain is connected to f5, and the substrate is connected to V S ; Vertical PNP transistor Q vp1 The collector of the NPN transistor is connected to GND, the base is connected to f4, and the emitter is connected to f5; n1 Collector connected to V S ;The base is connected to f5, and the emitter is connected to ampout;

[0023] When Q n1 When the transistor is turned on, the voltage at the ampout node is not less than V S -4VSG , V SG M p1 The gate-source voltage of the high-voltage PMOS transistor;

[0024] The voltage buffer structure consists of M p6 , Q vp2 , Q n2 、M n2 , Q n3 , Q vp3 The transistor and C1 capacitor are connected as follows: p6 The transistor gate is connected to L2 highbias , source connected to V S , the drain is connected to f6, and the substrate is connected to V S ; Vertical PNP transistor Q vp2 The collector of the NPN transistor is connected to GND, the base is connected to ampout, and the emitter is connected to f6; n2 Collector connected to V S , base connected to ampout, emitter connected to f8; M n2 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f8, and the substrate is connected to GND; one end of the C1 capacitor is connected to f6 and the other end is connected to f8; the NPN transistor Q n3 Collector connected to V S , base connected to f6, emitter connected to L9 driver ; Vertical PNP transistor Q vp3 The collector is connected to GND, the base is connected to f8, and the emitter is connected to L9 driver ;

[0025] The control circuit is composed of M p7 、M p8 , Q n4 , Q n5 Transistor structure, when L control When it is low, M p7 、M p8 , Q n4 , Q n5 The transistor is turned on and M is turned off. p1 High-voltage PMOS transistor.

[0026] Furthermore, the input voltage of the voltage regulator is 3.0V~16.5V, the output current range is 1µA~300mA, the quiescent current is ≤20µA, and when the voltage regulator is in a fixed output voltage mode, the fixed voltage nominal value is set in the range of 1.25V~16.0V through the internal voltage divider resistor; when the voltage regulator is in an adjustable output voltage mode, the adjustable output nominal voltage value range is 1.25V~16.0V according to the external voltage divider resistor setting.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] The present invention discloses a low-power, fast-response, low-dropout linear voltage regulator with mode control. Using a dual-mode controller, the regulator implements two operating modes: fixed output voltage mode and adjustable output voltage mode. This design allows users to select the appropriate mode based on their specific needs, thereby improving the flexibility and efficiency of power management. The regulator's extremely low quiescent current, less than 20µA, offers significant advantages in low-power electronic systems and battery-powered systems. This low power consumption helps extend battery life and improve overall system energy efficiency. The regulator exhibits fast response and is insensitive to the series equivalent resistance of the output capacitor. This eliminates the need to consider capacitor type and series equivalent resistance during operation, simplifying system design and improving system stability and reliability. Whether operating in fixed or adjustable output voltage mode, the regulator offers a wide output voltage range (1.25V to 16.0V). This provides users with more options to meet the output voltage requirements of diverse application scenarios. Users can easily switch between fixed and adjustable output voltage modes by simply configuring external voltage divider resistors. This design simplifies the use and maintenance of the voltage regulator and reduces the complexity of system design. The voltage regulator of the present invention boasts a compact structure and excellent performance, providing users with an efficient, stable, and flexible power management solution. This helps improve overall system performance and meet the stringent power management requirements of modern electronic systems.

[0029] The input voltage of the voltage stabilizer of the present invention is 3.0V to 16.5V, the output current range is 1µA to 300mA, and the quiescent current is ≤20µA. When the SET terminal voltage is less than 50mV, the dual-mode controller sets the operating mode of the voltage stabilizer of the present invention to the fixed output voltage mode; when the SET terminal voltage is greater than 200mV, the dual-mode controller sets the operating mode of the voltage stabilizer of the present invention to the adjustable output voltage mode. In the fixed output voltage mode, the fixed voltage nominal value is set in the range of 1.25V to 16.0V through the internal voltage divider resistor. In the adjustable output voltage mode, the adjustable output voltage range is 1.25V to 16.0V. The user can set the required nominal voltage value based on the external voltage divider resistor.

[0030] The low-power, fast-response voltage regulator of this invention achieves fast response and stable output without adding external capacitors, meeting the needs of diverse application scenarios and overcoming the shortcomings of existing technologies. Users can easily configure the regulator to operate in either fixed or adjustable output voltage modes, depending on the application, thus providing an efficient, stable, and flexible power management solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a micro-system structure diagram of a low-power, fast-response, low-dropout linear regulator with mode control function;

[0032] Figure 2 This is the error amplifier circuit diagram of the present invention;

[0033] Figure 3 is a circuit diagram of a driving circuit with a voltage clamping function according to the present invention;

[0034] Figure 4 This is a circuit diagram of the dual-mode controller of the present invention.

[0035] In the accompanying drawings: 100, error amplifier; 200, drive circuit with voltage clamping function; 300, M p 1 high-voltage PMOS transistor; 400, external voltage divider resistor; 500, dual-mode controller. DETAILED DESCRIPTION

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1 As shown, the present invention provides a micro-power fast response low voltage difference linear regulator with mode control function, specifically including an error amplifier 100, a driving circuit 200 with a voltage clamping function, p1 High-voltage PMOS transistor 300, external voltage divider resistor 400, dual-mode controller 500. Error amplifier 100 negative input terminal is connected to reference voltage V REF , the positive input terminal is connected to a1, the output terminal OUT of the voltage regulator is connected to the third input terminal of the error amplifier 100 to improve the transient response of the voltage regulation loop, and the output terminal is connected to a2; the input terminal of the driving circuit 200 with voltage clamping function is a2, and the output terminal is connected to a3; M p1 The gate of the high-voltage PMOS transistor 300 is connected to a3, and the substrate and source are connected to the input voltage V IN The drain is connected to the regulator output terminal OUT. The negative input terminal of the dual-mode controller 500 is connected to SET, the positive input terminal is connected to GND, and the output terminal is connected to a1. The external voltage divider resistor 400 includes voltage divider resistors R1 and R2. If the voltage regulator is in adjustable output mode, one end of voltage divider resistor R2 is connected to SET and the other end is connected to GND. One end of R1 is connected to OUT and the other end is connected to SET. If the voltage regulator is in fixed output mode, the SET terminal is grounded, and the voltage divider resistors R1 and R2 are not connected to the voltage regulator circuit.

[0038] The SET node voltage is sampled by the dual-mode controller 500 to control the output voltage mode of the voltage regulator. When the SET terminal voltage is less than 50mV, the micro-power voltage regulation loop enters the fixed output voltage mode, the output voltage of the voltage regulator is a fixed nominal value, and the fixed output voltage of the voltage regulator is determined by the voltage divider inside the voltage regulator chip. When the SET terminal voltage is greater than 200mV, the micro-power voltage regulation loop enters the adjustable output voltage mode, the output voltage of the voltage regulator is in an adjustable mode, and the nominal value of the output voltage of the voltage regulator is adjusted by the voltage divider resistor outside the voltage regulator chip.

[0039] The present invention comprises an error amplifier 100, a driving circuit 200, and an M p1 The high-voltage PMOS transistor 300 and the dual-mode controller 500 form a micro-power consumption fast response voltage regulation loop. The voltage regulation loop phase is about 60 degrees and the loop gain is about 60dB, thereby achieving a regulated voltage output.

[0040] like Figure 2 As shown, the error amplifier 100 has its input ports as the Z node and V REF Node and OUT node, the output node is ampout, including the amplifier main part, input protection part, frequency compensation part, linearization part, voltage stabilization part and transient enhancement circuit, among which:

[0041] The main part of the amplifier: including transistor M p1 、M p2 、M n3 、M n4 、M n5 、M n6 , where M n3 and M n5 A differential input transistor pair is formed to compare and amplify the output signal of the dual-mode controller 500. The output signal of the dual-mode controller 500 is input through the Z node. n3 and M n5 The gate input, source grounded, drain output differential current; M n4 and M n6 Acts as a current mirror to provide a tail current source for the amplifier;

[0042] The specific connection relationship of the linear differential amplifier is:

[0043] M n3 The transistor gate is connected to a6, the source is connected to a3, the drain is connected to a2, the substrate is connected to GND, and a6 is connected to R p1 One end of the resistor, R p1 The other end of the resistor is connected to the output terminal Z of the dual-mode controller 500;

[0044] M n4 The transistor gate is connected to L5 lowbiasBias voltage, source connected to GND, drain connected to a3, substrate connected to GND;

[0045] M p1 Transistor gate connected to a2, source connected to V S , drain connected to a2, substrate connected to V S ;

[0046] M n5 Transistor gate connected to a8, source connected to a4, drain connected to ampout, substrate connected to GND, a8 connected to V REF (reference voltage);

[0047] M n6 Transistor gate connected to L5 lowbias , source connected to GND, drain connected to a4, substrate connected to GND;

[0048] M p2 Transistor gate connected to a2, source connected to V S , drain connected to ampout, substrate connected to V S .

[0049] Input protection part: R p1 and R p2 resistors are designed at the gates of the amplifier input transistors M n3 , M n5 , for preventing abnormal electrical stress damage. The connection relationship of the input protection part is as follows:

[0050] R p1 resistor one end connected to Z (one port of the dual-mode controller 500), the other end connected to a6;

[0051] R p2 resistor one end connected to a8, the other end connected to V REF (reference voltage).

[0052] Frequency compensation part: C5 capacitor and R p3 resistor form an RC network, introduce main pole and zero, provide voltage loop frequency compensation; the connection relationship of the frequency compensation part is as follows:

[0053] C5 capacitor one end connected to a2, the other end connected to a7;

[0054] R p3 resistor one end connected to ampout, the other end connected to a7.

[0055] Linearization part: R p4 resistor cooperates with the internal circuit of the linear differential amplifier to realize linearization, provide AC ground, reduce low-frequency gain, and compensate phase margin; the connection relationship of the linearization part is as follows:

[0056] R p4 Connect one end of the resistor to a3 and the other end to a4, connecting the differential input transistor pair to the current mirror;

[0057] Voltage stabilization part: Capacitors C2, C3, and C4 stabilize the voltages at the a6, cfeedback, and OUT terminals, respectively, to prevent voltage mutations and improve circuit stability. The connection relationship of the voltage stabilization part is as follows:

[0058] One end of capacitor C2 is connected to OUT (output of the regulator), and the other end is connected to a6;

[0059] One end of capacitor C4 is connected to OUT, and the other end is connected to a4;

[0060] One end of capacitor C3 is connected to cfeedback, and the other end is connected to a3;

[0061] Transient enhancement circuit: including transistor M n1 、M n2 、M n7 、M n8 And capacitor C1, according to the change of OUT terminal voltage, quickly adjust the output voltage of ampout terminal, and improve the transient response speed of micro-power voltage regulation loop; the connection relationship of transient enhancement circuit is as follows:

[0062] M n1 The transistor gate is connected to L5 lowbias (bias voltage), source and substrate connected to GND, drain connected to a1;

[0063] M n2 The transistor gate is connected to OUT, the source is connected to a1, the drain is connected to a2, and the substrate is connected to GND;

[0064] One end of capacitor C1 is connected to a1, and the other end is connected to GND;

[0065] M n7 The transistor gate is connected to OUT, the source is connected to a5, the drain is connected to ampout, and the substrate is connected to GND;

[0066] M n8 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to a5, and the substrate is connected to GND.

[0067] The linear differential amplifier outputs the final p2 and M n5 、M n6 The current mirror structure, and M n7 and M n8 The transient enhancement circuit obtains a stable output voltage ampout.

[0068] The error amplifier 100 of the present invention achieves precise amplification of the input signal and regulated output through mechanisms such as differential input, current mirror, input protection, frequency compensation, linearization and low-frequency gain reduction, voltage stabilization, and transient enhancement.

[0069] like Figure 3 As shown, the driving circuit 200 with voltage clamping function has an input node of ampout and an output node of L9. drver , including a limiter circuit, a voltage follower circuit, a voltage buffer structure and a control circuit, wherein:

[0070] Limiting circuit: by M p1 、M p2 、M p3 、M p4 and M n1 These transistors are connected in a specific way. When the input signal changes, M p1 、M p2 、M p3 、M p4 The transistors are turned on or off in sequence, thus limiting the voltage of the f4 node to a certain range. n1 The transistor acts as part of the clipping circuit and receives the L5 signal through its gate. lowbias The source is grounded and the drain is connected to the f4 node, which further limits the voltage of the f4 node. vp1 , Q n1 The transistors form a follower structure, ensuring that the voltage at the ampout node is approximately equal to the voltage at the f4 node, thereby achieving voltage protection for subsequent circuits. The specific connection method is as follows:

[0071] M p1 The transistor gate is connected to f1 and the source is connected to V S , the drain is connected to f1, and the substrate is connected to V S ;

[0072] M p2 The transistor gate is connected to f2, the source is connected to f1, the drain is connected to f2, and the substrate is connected to f1;

[0073] M p3 The transistor gate is connected to f3, the source is connected to f2, the drain is connected to f3, and the substrate is connected to f2;

[0074] M p4 The transistor gate is connected to f4, the source is connected to f3, the drain is connected to f4, and the substrate is connected to f3;

[0075] M n1 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f4, and the substrate is connected to GND.

[0076] Voltage follower circuit: composed of Q vp1 Transistor, M p5 Transistor, Q n1 The main function of this circuit is to follow the voltage change of f4 node and output to ampout node, while ensuring that the voltage of ampout node will not be less than V S -4V SG The specific connection is as follows:

[0077] M p5 Transistor gate connected to L2 highbias , source connected to V S , drain connected to f5, substrate connected to V S ;

[0078] Longitudinal PNP transistor Q vp1 collector connected to GND, base connected to f4, emitter connected to f5;

[0079] NPN transistor Q n1 collector connected to V S ; base connected to f5, emitter connected to ampout.

[0080] Q vp1 Transistor as a longitudinal PNP transistor, its base is connected to f4 node, collector is grounded, and emitter is connected to the drain of M p5 Transistor; when the voltage of f4 node changes, the emitter current of Q vp1 Transistor also changes, which in turn affects the base current of Q p5 Transistor through M n1 Transistor. Q n1 Transistor as an NPN transistor, its collector is connected to V S , emitter is connected to ampout node. When Q n1 Transistor is turned on, it limits the decrease of ampout node voltage, thus ensuring that the voltage of ampout node will not be less than V S -4V SG . (V SG is the gate-source voltage of PMOS transistor)

[0081] Voltage buffer structure: composed of M p6 , Q vp2 , Q n2 , M n2 , Q n3 , Q vp3 Transistors and C1 capacitor. This structure has the characteristics of high input equivalent impedance and low output equivalent impedance, which can effectively isolate the high impedance output node of the error amplifier and the large parasitic capacitance input node of the power transistor M p1 , thus optimizing the performance of the circuit.

[0082] The specific connection method is as follows:

[0083] M p6 The transistor gate is connected to L2 highbias , source connected to V S , the drain is connected to f6, and the substrate is connected to V S ;

[0084] Vertical PNP transistor Q vp2 The collector is connected to GND, the base is connected to ampout, and the emitter is connected to f6.

[0085] NPN transistor Q n2 Collector connected to V S , base connected to ampout, emitter connected to f8;

[0086] M n2 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f8, and the substrate is connected to GND.

[0087] One end of capacitor C1 is connected to f6 and the other end is connected to f8;

[0088] NPN transistor Q n3 Collector connected to V S , base connected to f6, emitter connected to L9 driver ;

[0089] Vertical PNP transistor Q vp3 The collector is connected to GND, the base is connected to f8, and the emitter is connected to L9 driver .

[0090] M p6 The transistor is part of the driver circuit, and its gate receives L2 highbias Signal, source connected to V S , the drain is connected to the f6 node. vp2 Transistor, Q n2 Transistor, M n2 Transistor, Q n3 Transistor, Q vp3 The transistor and capacitor C1 together form a voltage buffer structure. This structure can effectively isolate the high-impedance output node of the error amplifier 100 and the power transistor M through the characteristics of high input equivalent impedance and low output equivalent impedance. p1 The large parasitic capacitance of the input node. C1 acts as a buffer capacitor to ensure that the voltage difference between the f6 and f8 nodes does not change suddenly, thereby accelerating the transient response of the loop.

[0091] Control circuit: by M p7 、M p8 , Qn4 , Q n5 When L control When it is low, M p7 、M p8 , Q n4 , Q n5 The transistor is turned on so that the input and output voltages of the driving circuit are close to the power supply voltage, thereby turning off the power transistor M. p1 At this time, the output of the micro-power regulator is 0V, realizing the control function of the circuit.

[0092] The driving circuit 200 with voltage clamping function realizes effective control and protection of the circuit voltage through the coordinated work of the amplitude limiting circuit, the voltage following circuit, the voltage buffer structure and the control circuit.

[0093] like Figure 4 As shown, the input nodes of the dual-mode controller 500 are SET, V OUT , the output node is Z, including two-stage operational amplifier, a first inverter, a second inverter, an internal controllable voltage divider resistor, one analog switch and two analog switches, where:

[0094] Two-stage operational amplifier: p1 、M p2 、M n1 、M n2 、M p3 and M p4 、M n3 Transistor composition. Through design differentiation M p1 、M p2 Transistor and M n1 、M n2 The aspect ratio of the transistor, M n4 and M p5 The buffer stage is formed to separate the differential amplifier and the selector. The amplifier has a certain hysteresis voltage to prevent malfunction caused by noise or interference. The additional resistor R p1 、R p2 The resistors work together with the two-stage operational amplifier to form the input and amplification portion of the dual-mode controller 500. The specific connection relationship of the two-stage operational amplifier is:

[0095] R p1 One end of the resistor is connected to SET and the other end is connected to g7;

[0096] M p1 The transistor gate is connected to g7, the source is connected to g3, the drain is connected to g1, and the substrate is connected to g3;

[0097] M n1 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g1, and the substrate is connected to GND;

[0098] R p2 One end of the resistor is connected to GND and the other end is connected to g8;

[0099] M p2 The transistor gate is connected to g8, the source is connected to g3, the drain is connected to g2, and the substrate is connected to g3;

[0100] M n2 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g2, and the substrate is connected to GND;

[0101] M p3 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g3, substrate connected to V S ;

[0102] M p4 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g4, substrate connected to V S ;

[0103] M p3 The transistor gate is connected to g2, the source is connected to GND, the drain is connected to g4, and the substrate is connected to GND.

[0104] The first inverter: M p5 and M n4 The transistors are used to generate the sethigh signal required by the subsequent analog switch; the specific connection relationship is:

[0105] M p5 The transistor gate is connected to g4 and the source is connected to V S , drain connected to sethigh, substrate connected to V S ;

[0106] M n4 The transistor gate is connected to g4, the source is connected to GND, the drain is connected to sethigh, and the substrate is connected to GND.

[0107] The second inverter: p6 and M n5 The transistors are used to generate the setlow signal required by the subsequent analog switch; the specific connection relationship is:

[0108] M p6 The transistor gate is connected to sethigh and the source is connected to V S , drain connected to setlow, substrate connected to V S ;

[0109] M n5The transistor gate is connected to sethigh, the source is connected to GND, the drain is connected to setlow, and the substrate is connected to GND.

[0110] Internal controllable voltage divider resistor: R p3 、R p4 Resistors and M n6 The transistors are used to divide the voltage at the OUT terminal of the regulator under certain conditions. The specific connection relationship is:

[0111] R p4 Connect one end of the resistor to OUT and the other end to g6;

[0112] R p3 One end of the resistor is connected to g5 and the other end is connected to g6;

[0113] M n6 The transistor gate is connected to setlow, the source is connected to GND, the drain is connected to g5, and the substrate is connected to GND.

[0114] One-way analog switch: M p7 and M n7 The transistors control the input source of the Z terminal voltage according to the states of the sethigh and setlow signals. The specific connection relationship is:

[0115] M p7 The transistor gate is connected to sethigh, the source is connected to g6, the drain is connected to Z, and the substrate is connected to V S ;

[0116] M n7 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to g6, and the substrate is connected to GND.

[0117] Two-way analog switch: M p8 and M n8 The transistor composition also controls the connection between the SET terminal voltage and the Z terminal voltage according to the state of the sethigh and setlow signals; the specific connection relationship is:

[0118] M p8 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to SET, and the substrate is connected to V S ;

[0119] M n8 The transistor gate is connected to sethigh, the source is connected to SET, the drain is connected to Z, and the substrate is connected to GND.

[0120] The working principle is:

[0121] Input voltage comparison: through R p1 The resistor introduces the SET terminal voltage into the M pThe gate of transistor 1, along with the other parts of the two-stage operational amplifier, compares the input voltage. p2 The resistor brings the GND voltage to the M p2 The gate of the transistor serves as the other input.

[0122] Operational amplifier and hysteresis: The two-stage operational amplifier amplifies the input voltage and generates hysteresis voltage through the differentiated transistor width-to-length ratio. This helps prevent malfunctions caused by noise or interference.

[0123] The inverter generates a switching signal: the first inverter and the second inverter generate sethigh and setlow signals respectively according to the outputs of the two-stage operational amplifier.

[0124] Internal controllable voltage divider resistor:

[0125] When the setlow signal is high, M n6 The transistor is turned on and the voltage at node g5 is approximately 0V. At this time, R p3 and R p4 The resistor divides the voltage at the OUT terminal of the regulator, and the voltage at the g6 node is [RV / (R p3 +R p4 )]V OUT .

[0126] When the setlow signal is low, M n6 The transistor is turned off, and the voltages of nodes g6 and g5 are both the OUT terminal voltage V OUT .

[0127] Analog switch selects input source:

[0128] When the voltage at the SET terminal is less than 50mV, sethigh is low level and setlow is high level. n7 and M p7 Transistor is turned on, M n8 and M p8 The transistor is turned off. At this time, an analog switch connects the voltage at the Z terminal to the voltage at the G6 node, which is the internal voltage divider. At this time, the regulator is in fixed output voltage mode, and the output voltage is [1+R p4 / R p3 ]V REF .

[0129] When the voltage at the SET terminal is greater than 200mV, sethigh is high and setlow is low. n7 and M p7 Transistor off, M n8 and M p8The transistor is turned on. At this time, the two analog switches connect the voltage at the Z terminal to the voltage at the SET node, which is the voltage divided by the external voltage divider resistors R1 and R2 on the voltage at the OUT terminal of the regulator. At this time, the regulator is in adjustable output voltage mode, and the output voltage is [1+R1 / R2]V REF .

[0130] Through the above structure and working principle, the dual-mode controller 500 can switch between the fixed output voltage mode and the adjustable output voltage mode according to different input voltages, and has a certain anti-interference ability.

[0131] The driving circuit 200 with voltage clamping function works as follows: Figure 3 As shown, M p1 、M p2 、M p3 、M p4 、M n1 The transistor forms a limiting circuit, and the voltage at node f4 is V S -4V SG , Q vp1 Transistor, M p5 Transistor, Q n1 The transistors form a voltage follower circuit. If the voltage at the ampout node is less than V S -4V SG , Q n1 The transistor is turned on, limiting the decrease of the ampout node, so the minimum voltage of the ampout node is V S -4V SG , limiting the power transistor M p1 (like Figure 1 As shown) the gate-source voltage is less than or equal to V S -4V SG . M p6 , Q vp1 , Q n2 、M n2 , Q n3 , Q vp3 The transistor and C1 capacitor form a voltage buffer structure with high input equivalent impedance and low output equivalent impedance, effectively connecting the error amplifier high impedance output node and the power transistor M p1 The large parasitic capacitance input node isolation pushes the pole generated by the power transistor gate to the high frequency. This pole will not affect the phase margin of the micro-power voltage regulation loop; the C1 capacitor ensures that the voltage difference between the f6 and f8 nodes will not suddenly change, thus accelerating the loop transient response. p7 、M p8 , Q n4 , Q n5 The control circuit is formed. When L control When it is low, M p7 、Mp8 , Q n4 , Q n5 The input and output voltages of the driver circuit with voltage clamping function are close to the power supply voltage, and the power transistor M p1 Off, the micropower regulator output is 0V.

[0132] The present invention discloses a micro-power fast-response low-voltage dropout linear regulator with a mode control function. The input voltage is 3.0V to 16.5V, the output current range is 1µA to 300mA, the quiescent current is ≤20µA, the fixed voltage nominal value is set in the range of 1.25V to 16.0V through the internal voltage divider resistor, and the adjustable output voltage range is 1.25V to 16.0V. The user can set the required nominal voltage value according to the external voltage divider resistor. The voltage regulator of the present invention has two working modes: fixed output voltage mode and adjustable output voltage mode; it consists of an error amplifier 100, a drive circuit 200, and an M p1 The high-voltage PMOS transistor 300 forms a micro-power fast-response voltage-stabilizing loop to achieve a regulated output. A transient enhancement circuit is proposed to effectively improve the transient response of the voltage-stabilizing loop without affecting the phase margin and low-frequency gain of the micro-power regulated loop. A power transistor gate-source limiting circuit is proposed (in the driving circuit 200, M p1 、M p2 、M p3 、M p4 、M n1 The transistor forms a limiting circuit. Figure 1 Medium M p1 Power transistors are thin-gate oxide, high-voltage transistors. If the gate-source voltage is not limited, the transistor's gate-source will breakdown under high voltage. Limiting the gate-source voltage to a certain range effectively prevents gate-source damage. This linear regulator is insensitive to the series equivalent resistance of the output capacitor, eliminating the need to consider capacitor type and series equivalent resistance. It can meet the power supply needs of micro-power electronic systems and battery-powered systems. This regulator is flexible and convenient to use. Users can configure it appropriately to meet the output voltage requirements of different application scenarios.

[0133] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A micro-power fast response low voltage dropout linear regulator with mode control function, characterized in that: The invention comprises a dual-mode controller (500), wherein the negative phase input terminal of the dual-mode controller (500) is connected to the SET terminal of the external voltage divider resistor (400), the positive phase terminal of the dual-mode controller (500) is connected to GND, the output terminal of the dual-mode controller (500) is connected to the positive phase input terminal of the controller of the error amplifier (100), and the dual-mode controller (500) is used to adjust the voltage regulator to a fixed output voltage mode or an adjustable output voltage mode; the output terminal OUT of the voltage regulator is connected to the third input terminal of the error amplifier (100), and the negative phase input terminal of the error amplifier (100) is connected to the reference voltage V REF The output end of the error amplifier (100) is connected to the input end of the drive circuit (200) with a voltage clamping function, and the output end of the drive circuit (200) with a voltage clamping function is connected to the M p1 The gate connection of the high voltage PMOS transistor (300), M p1 The substrate and source of the high-voltage PMOS transistor (300) are connected to the input voltage V IN , the drain is connected to the output terminal OUT of the regulator; The dual-mode controller (500) includes a two-stage operational amplifier, a first inverter, a second inverter, an internal controllable voltage divider resistor, a one-way analog switch and a two-way analog switch. The input nodes of the dual-mode controller (500) are SET, V OUT , the output node is Z; The first inverter is used to generate a sethigh signal required by the subsequent analog switch, and the second inverter is used to generate a setlow signal required by the subsequent analog switch; One analog switch is M p7 and M n7 The transistor is used to control the input source of the Z terminal voltage according to the status of the sethigh and setlow signals. The specific connection relationship is: M p7 The transistor gate is connected to sethigh, the source is connected to g6, the drain is connected to Z, and the substrate is connected to V S ;M n7 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to g6, and the substrate is connected to GND; Two-way analog switch by M p8 and M n8 The transistor is used to control the connection between the SET terminal voltage and the Z terminal voltage according to the status of the sethigh and setlow signals. The specific connection relationship is: M p8 The transistor gate is connected to setlow, the source is connected to Z, the drain is connected to SET, and the substrate is connected to V S ;M n8 The transistor gate is connected to sethigh, the source is connected to SET, the drain is connected to Z, and the substrate is connected to GND.

2. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 1, characterized in that: When the SET terminal voltage of the external voltage divider resistor (400) is less than 50mV, the dual-mode controller (500) sets the voltage regulator to a fixed output voltage mode; when the SET terminal voltage of the external voltage divider resistor (400) is greater than 200mV, the dual-mode controller (500) sets the voltage regulator to an adjustable output voltage mode.

3. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 1, characterized in that: The two-stage operational amplifier consists of M p1 、M p2 、M n1 、M n2 、M p3 and M p4 、M n3 Transistor composition, additional resistor R p1 、R p2 The resistor and the two-stage operational amplifier form the input and amplification part of the dual-mode controller (500), and the specific connection relationship is: R p1 One end of the resistor is connected to SET, and the other end is connected to g7; M p1 The transistor gate is connected to g7, the source is connected to g3, the drain is connected to g1, and the substrate is connected to g3; M n1 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g1, and the substrate is connected to GND; R p2 One end of the resistor is connected to GND, and the other end is connected to g8; M p2 The transistor gate is connected to g8, the source is connected to g3, the drain is connected to g2, and the substrate is connected to g3; M n2 The transistor gate is connected to g1, the source is connected to GND, the drain is connected to g2, and the substrate is connected to GND; M p3 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g3, substrate connected to V S ;M p4 The transistor gate is connected to L2 highbias , source connected to V S , drain connected to g4, substrate connected to V S ;M n3 The transistor gate is connected to g2, the source is connected to GND, the drain is connected to g4, and the substrate is connected to GND; The first inverter is composed of M p5 and M n4 Transistor composition, the specific connection relationship is: M p5 The transistor gate is connected to g4 and the source is connected to V S , drain connected to sethigh, substrate connected to V S ;M n4 The transistor gate is connected to g4, the source is connected to GND, the drain is connected to sethigh, and the substrate is connected to GND; The second inverter is composed of M p6 and M n5 Transistor composition, the specific connection relationship is: M p6 The transistor gate is connected to sethigh and the source is connected to V S , drain connected to setlow, substrate connected to V S ;M n5 The transistor gate is connected to sethigh, the source is connected to GND, the drain is connected to setlow, and the substrate is connected to GND; The internal controllable voltage divider resistor is R p3 、R p4 Resistors and M n6 The transistor is used to divide the voltage at the OUT terminal of the regulator. The specific connection relationship is: R p4 One end of the resistor is connected to OUT, and the other end is connected to g6; R p3 One end of the resistor is connected to g5 and the other end is connected to g6; M n6 The transistor gate is connected to setlow, the source is connected to GND, the drain is connected to g5, and the substrate is connected to GND.

4. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 3, characterized in that: When the setlow signal is high, M n6 The transistor is turned on, the voltage at node g5 is 0V, and the voltage at node g6 is [R p3 / (R p3 +R p4 )]V OUT .

5. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 4, characterized in that: When the SET terminal voltage is less than 50mV, sethigh is low and setlow is high, one analog switch is turned on and two analog switches are turned off. At this time, one analog switch connects the Z terminal voltage to the g6 node voltage, which is the internal voltage divider. At this time, the regulator is in fixed output voltage mode, and the output voltage is [1+R p4 / R p3 ]V REF .

6. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 3, characterized in that: When the setlow signal is low, M n6 The transistor is turned off, and the voltages of nodes g6 and g5 are both the OUT terminal voltage V OUT .

7. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 6, characterized in that: When the SET terminal voltage is greater than 200mV, sethigh is high and setlow is low, one analog switch is closed and the other two analog switches are opened. At this time, the two analog switches connect the Z terminal voltage to the SET node voltage, which is the voltage divider value of the resistors R1 and R2 of the external voltage divider resistor (400) on the OUT terminal voltage of the regulator. At this time, the regulator is in adjustable output voltage mode, and the output voltage is [1+R1 / R2]V REF .

8. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 1, characterized in that: The error amplifier (100) is a linear differential amplifier; the external voltage divider resistor (400) includes voltage divider resistors R1 and R2; the voltage regulator is in an adjustable output mode, one end of the voltage divider resistor R2 is connected to SET and the other end is connected to GND; one end of R1 is connected to OUT and the other end is connected to SET; the voltage regulator is in a fixed output mode, the SET end is grounded, and the voltage divider resistors R1 and R2 are not connected to the voltage regulator circuit.

9. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 1, characterized in that: A driving circuit (200) with a voltage clamping function comprises a limiter circuit, a voltage follower circuit, a voltage buffer structure and a control circuit. The input node of the driving circuit is ampout, and the output node is L9. drver ,in: The limiting circuit is composed of M p1 、M p2 、M p3 、M p4 and M n1 Transistor composition, the specific connection method is as follows: M p1 The transistor gate is connected to f1 and the source is connected to V S , the drain is connected to f1, and the substrate is connected to V S ;M p2 The transistor gate is connected to f2, the source is connected to f1, the drain is connected to f2, and the substrate is connected to f1; M p3 The transistor gate is connected to f3, the source is connected to f2, the drain is connected to f3, and the substrate is connected to f2; M p4 The transistor gate is connected to f4, the source is connected to f3, the drain is connected to f4, and the substrate is connected to f3; M n1 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f4, and the substrate is connected to GND; The voltage follower circuit consists of Q vp1 Transistor, M p5 Transistor, Q n1 Transistor composition, the specific connection method is as follows: M p5 The transistor gate is connected to L2 highbias , source connected to V S , the drain is connected to f5, and the substrate is connected to V S ; Vertical PNP transistor Q vp1 The collector of the NPN transistor is connected to GND, the base is connected to f4, and the emitter is connected to f5; n1 Collector connected to V S ;The base is connected to f5, and the emitter is connected to ampout; When Q n1 When the transistor is turned on, the voltage at the ampout node is not less than V S -4V SG , V SG M p1 、M p2 、M p3 、M p4 The gate-source voltage of the high-voltage PMOS transistor; The voltage buffer structure consists of M P6 , Q vp2 , Q n2 、M n2 , Q n3 , Q vp3 The transistor and C1 capacitor are connected as follows: p6 The transistor gate is connected to L2 highbias , source connected to V S , the drain is connected to f6, and the substrate is connected to V S ; Vertical PNP transistor Q vp2 The collector of the NPN transistor is connected to GND, the base is connected to ampout, and the emitter is connected to f6; n2 Collector connected to V S , base connected to ampout, emitter connected to f8; M n2 The transistor gate is connected to L5 lowbias , the source is connected to GND, the drain is connected to f8, and the substrate is connected to GND; one end of the C1 capacitor is connected to f6 and the other end is connected to f8; the NPN transistor Q n3 Collector connected to V S , base connected to f6, emitter connected to L9 driver ; Vertical PNP transistor Q vp3 The collector is connected to GND, the base is connected to f8, and the emitter is connected to L9 driver ; The control circuit is composed of M p7 、M p8 , Q n4 , Q n5 Transistor configuration, when L control When it is low, M p7 、M p8 , Q n4 , Q n5 Transistor is on, M p1 The high voltage PMOS transistor (300) is turned off.

10. The micro-power fast-response low-dropout linear regulator with mode control function according to claim 1, characterized in that: The input voltage of the voltage regulator is 3.0V~16.5V, the output current range is 1µA~300mA, and the quiescent current is ≤20µA. When the voltage regulator is in fixed output voltage mode, the fixed voltage nominal value is set in the range of 1.25V~16.0V through the internal voltage divider resistor; when the voltage regulator is in adjustable output voltage mode, the adjustable output nominal voltage value range is 1.25V~16.0V according to the external voltage divider resistor setting.

Images