Wideband linear regulator circuit with high power supply noise suppression

Abstract

This invention provides a wideband linear regulator circuit with high power supply noise suppression, comprising: a bandgap reference voltage source, a charge pump, an error amplifier, a summing module, a segmented FFRC compensation module, a buffer, an N-type power transistor MN, and a resistor feedback network; the bandgap reference voltage source generates a reference voltage; the charge pump performs voltage conversion and supplies power to the corresponding modules; the error amplifier compares the reference voltage with the sampled voltage output from the resistor feedback network, amplifies the comparison result, and outputs it to the summing module; the segmented FFRC compensation module generates a compensation voltage based on changes in load current and outputs the compensation voltage to the summing module; the summing module combines the compensation voltage with the amplified comparison result; and the buffer drives the N-type power transistor MN to suppress power supply noise entering the linear regulator circuit based on the compensation voltage, thereby achieving adaptive power supply noise suppression according to changes in load current.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a wideband linear voltage regulator circuit with high power supply noise suppression. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), smart wearable devices, and various sensors, these smart devices have been widely applied in people's daily lives. To ensure the normal and stable operation of these devices, the requirements for power management units (PMUs) are becoming increasingly stringent. A crucial component of power management chips is the low dropout regulator (LDO) circuit. LDOs are typically connected after DC-DC switching regulators to reduce power supply ripple and provide a clean voltage source for noise-sensitive modules. The advantages of LDOs include low circuit complexity, low power consumption, low output noise and power supply ripple, fast transient response, stability, and low cost. In recent years, the demand for integrating the entire power management system into a single system-on-a-chip (SoC) solution has been increasing, leading to higher operating frequencies of switching regulators to allow for greater integration. This trend increases the frequency of output ripple, and some modules sensitive to power supply ripple, such as high-speed, high-precision digital-to-analog converters, RF circuits, and phase-locked loops (PLLs), require a low-noise, low-ripple power supply voltage. Traditional DC-DC switching regulators operate at relatively low frequencies, and conventional LDOs can handle ripple in the lower frequency range, minimizing interference from power supply ripple in the power supply circuit. However, as the operating frequencies of DC-DC switching regulators increase, conventional LDOs connected to them cannot guarantee that noise-sensitive modules will not be affected by the noise of the DC-DC switching regulator. Therefore, designing a linear regulator with high power supply noise suppression is of great significance.

[0003] Currently, feed-forward ripple cancellation (FFRC) is commonly used to eliminate power supply noise. FFRC adds an extra feedforward path between the power supply and the power transistor control terminal, in addition to the original feedback path, so that the power supply ripple appears at the power transistor control terminal with an appropriate gain. The feedback path must first detect the change in output voltage and then adjust accordingly; while the feedforward path does not need to detect the output but directly detects the input change. Therefore, compared to the feedback path, the feedforward path adjusts the power transistor faster, thus improving the power supply noise suppression capability of the LDO.

[0004] However, the effectiveness of FFRC technology largely depends on the gain of the feedforward path. Generally, the feedforward gain of FFRC technology is a fixed value and will not dynamically adjust the compensation value according to the operating state of the circuit. It can only improve the power supply rejection ratio (PSRR) within a very limited range of variation, such as the limited load current range of 1-25mA. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention employs an NMOS transistor as the power transistor and an FFEC compensation structure, providing a wideband linear voltage regulator circuit with high power supply noise suppression, specifically comprising:

[0006] This invention provides a wideband linear voltage regulator circuit with high power supply noise suppression, comprising:

[0007] Bandgap reference voltage source, charge pump, error amplifier, summation module, segmented FFRC compensation module, buffer, N-type power transistor MN, resistor feedback network;

[0008] The first terminal of the bandgap reference voltage source is used to receive an external voltage V. in The second terminal of the bandgap reference voltage source is connected to the non-inverting input terminal of the error amplifier and the third terminal of the segmented FFRC compensation module, respectively.

[0009] The first terminal of the segmented FFRC compensation module is used to receive external voltage V. in The second terminal is used to receive voltage V. cp The fourth end connects to the first end of the summation module;

[0010] The second terminal of the summation module is connected to the output terminal of the error amplifier, the third terminal is connected to the second terminal of the buffer, and the fourth terminal is used to receive the voltage V. cp ;

[0011] The first terminal of the buffer is used to receive an external voltage V through a charge pump. in The third terminal is connected to the fifth terminal of the segmented FFRC compensation module and the gate of the N-type power transistor MN. The charge pump is used to convert the external voltage V in Converted to voltage V cp ;

[0012] The drain of the N-type power transistor MN is used to connect to the external voltage V. in ;

[0013] The source of the N-type power transistor MN is the output terminal of a wide-bandwidth linear regulator circuit with high power supply noise suppression, and is connected to the first terminal of the resistor feedback network and the sixth terminal of the segmented FFRC compensation module, respectively.

[0014] The second terminal of the resistor feedback network is connected to the inverting input of the error amplifier, and the third terminal is grounded.

[0015] The first terminal of the segmented FFRC compensation module is used to receive external voltage V. in The second terminal is used to receive voltage V. cp ;

[0016] The power supply terminal of the error amplifier is used to receive voltage V. cp ;

[0017] A bandgap reference voltage source is used to generate a reference voltage V. REF ;

[0018] Error amplifier, used to compare reference voltage V REF The sampled voltage output from the resistor feedback network is compared and then amplified before being output to the summing module;

[0019] The segmented FFRC compensation module is used to generate a compensation voltage based on the load current variation of the broadband high power supply noise suppression linear voltage regulator circuit, and output the compensation voltage to the summing module.

[0020] The summation module is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and AC voltage, and output the integrated result to the buffer.

[0021] A buffer is used to drive the N-type power transistor MN and stabilize the output voltage of a high power supply noise suppression linear regulator circuit.

[0022] The N-type power transistor MN is used to convert the gate voltage into a large current and output a stable voltage value. Based on the compensation voltage, it suppresses the power supply noise of the linear regulator circuit.

[0023] The beneficial effects of this invention are:

[0024] The wideband linear voltage regulator circuit with high power supply noise suppression provided by this invention includes: a bandgap reference voltage source, a charge pump, an error amplifier, a summing module, a segmented FFRC compensation module, a buffer, an N-type power transistor MN, and a resistor feedback network; the bandgap reference voltage source is used to generate a reference voltage V. REF A charge pump is used to transfer an external voltage V. in The value is converted to voltage V cp Error amplifier, used to compare reference voltage V REFThe sampling voltage output from the resistor feedback network is amplified and output to the summing module; the segmented FFRC compensation module generates a compensation voltage based on the load current variation of the broadband high power supply noise suppression linear regulator circuit and outputs the compensation voltage to the summing module; the summing module combines the compensation voltage and the amplified comparison result, integrates the DC voltage and AC voltage, and outputs the integrated result to the buffer; the buffer drives the N-type power transistor MN to stabilize the output voltage of the high power supply noise suppression linear regulator circuit; the N-type power transistor MN converts the gate voltage into a large current and outputs a stable voltage value. Based on the compensation voltage, it suppresses the power supply noise entering the high power supply noise suppression linear regulator circuit, thereby generating a compensation voltage based on the load current variation and adaptively suppressing power supply noise based on this compensation voltage.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0026] Figure 1 A schematic diagram of a wideband linear voltage regulator circuit with high power supply noise suppression provided by the present invention;

[0027] Figure 2 A schematic diagram of the compensation principle provided by the present invention;

[0028] Figure 3 This invention provides a method for achieving g under different process angles and different loads. ds / g m A curve graph;

[0029] Figure 4 A g provided by the present invention ds / g m A schematic diagram of quantization values ​​in different load ranges;

[0030] Figure 5 A schematic diagram of a current comparator provided by the present invention;

[0031] Figure 6 A schematic diagram of experimental results provided by the present invention;

[0032] Figure 7 This is a schematic diagram of another experimental result provided by the present invention;

[0033] Figure 8 This is another schematic diagram of experimental results provided by the present invention;

[0034] Figure 9 This is a schematic diagram illustrating another experimental result provided by the present invention. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0036] To address the problems existing in the prior art, this invention provides a wideband linear regulator circuit with high power supply noise suppression. The compensation ripple size is controlled according to the load current. That is, as the load current range varies, the compensation ripple size injected into the gate of the power transistor adaptively changes, so that the compensation current generated cancels the noise current transmitted to the LDO output terminal, thereby giving the LDO a relatively high power supply noise suppression capability throughout the entire load range.

[0037] Figure 1 A schematic diagram of a wideband linear voltage regulator circuit with high power supply noise suppression provided by the present invention is shown below. Figure 1 As shown, the wideband high power supply noise suppression linear regulator circuit 100 includes:

[0038] Bandgap reference voltage source 10, charge pump 20, error amplifier 30, summation module 40, segmented FFRC compensation module 50, buffer 60, N-type power transistor MN and resistor feedback network 70.

[0039] The first terminal of the bandgap reference voltage source 10 is used to receive an external voltage V. in The second terminal of the bandgap reference voltage source 10 is connected to the non-inverting input terminal of the error amplifier 30 and the third terminal of the segmented FFRC compensation module 50, respectively.

[0040] The first terminal of the segmented FFRC compensation module 50 is used to receive external voltage V. in The second terminal is used to receive voltage V. cp The fourth end connects to the first end of the summation module.

[0041] The second terminal of the summation module 40 is connected to the output terminal of the error amplifier 30, the third terminal is connected to the second terminal of the buffer 60, and the fourth terminal is used to receive the voltage V. cp .

[0042] The first terminal of the buffer 60 is used to receive an external voltage V via a charge pump. in The third terminal is connected to the fifth terminal of the segmented FFRC compensation module 50 and the gate of the N-type power transistor MN.

[0043] Charge pump 20 is used to transfer external voltage V in Converted to voltage V cp Provides a voltage ratio (V) for the N-type power transistor MN. in It has a high gate voltage and supplies power to modules such as error amplifiers and summing amplifiers.

[0044] The drain of the N-type power transistor MN is used to connect to the external voltage V.in .

[0045] The source of the N-type power transistor MN is the output terminal of the linear regulator circuit 100 with wideband high power supply noise suppression, and is connected to the first terminal of the resistor feedback network 70 and the sixth terminal of the segmented FFRC compensation module 50, respectively.

[0046] The second terminal of the resistor feedback network 70 is connected to the inverting input terminal of the error amplifier 30, and the third terminal is grounded.

[0047] The first terminal of the segmented FFRC compensation module 50 is used to receive external voltage V. in The second terminal is used to receive voltage V. cp .

[0048] The power supply terminal of error amplifier 30 is used to receive voltage V. cp .

[0049] Bandgap reference voltage source 10 is used to generate reference voltage V. REF .

[0050] Error amplifier 30 is used to compare the reference voltage V. REF The sampled voltage output by the resistor feedback network 70 is amplified and then output to the summing module 40.

[0051] The segmented FFRC compensation module 50 is used to generate a compensation voltage based on the load current variation of the broadband high power supply noise suppression linear regulator circuit 100, and output the compensation voltage to the summing module 40.

[0052] The summation module 40 is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and AC voltage, and output the integrated result to the buffer 60.

[0053] Buffer 60 is used to drive the N-type power transistor MN and stabilize the output voltage of the high power supply noise suppression linear regulator circuit.

[0054] The N-type power transistor MN is used to convert the gate voltage into a large current and output a stable voltage value. Based on the compensation voltage, it suppresses the power supply noise of the linear regulator circuit.

[0055] In the circuit provided by this invention, an NMOS transistor is used as the power transistor, and an FFEC compensation structure is employed. The segmented FFRC compensation module 50 generates a compensation voltage based on the load current variation of the wideband high power supply noise suppression linear regulator circuit 100, and outputs the compensation voltage to the summing module 40. This compensation voltage is integrated with the output of the error amplifier 30 through the summing amplifier SUM, and after passing through the buffer 60, it is injected into the gate terminal of the N-type power transistor MN. The transconductance g of the power transistor is then used to determine the voltage.m This is converted into the compensation current at the output of a broadband linear regulator circuit with high power supply noise suppression, and the power supply noise is reduced through the internal resistance 1g of the power transistor. ds The noise current coupled to the output of the wideband high power supply noise suppression linear regulator circuit is canceled, thereby avoiding the interference of power supply noise on the output voltage of the power transistor, and giving the wideband high power supply noise suppression linear regulator circuit a high power supply noise suppression capability.

[0056] In one possible implementation, such as Figure 1 As shown, the segmented FFRC compensation module 50 includes:

[0057] Amplifier FA, PMOS transistors P1, PMOS transistors P2, PMOS transistors P3, NMOS transistors N1 and NMOS transistors N2, resistor R B And resistance adaptive adjustment unit 501.

[0058] resistor R B The first terminal, the source of PMOS transistor P2, and the source of PMOS transistor P3 are all used to receive external voltage V. in .

[0059] The power supply terminal of amplifier FA is used to receive voltage V. cp The inverting input terminal is connected to the resistor R. B The second terminal is connected to the non-inverting input terminal, which is used to receive the reference voltage V output by the bandgap reference voltage source 10. REF Specifically, voltage V cp The voltage supplied to the charge pump. Specifically, the clamping effect of amplifier FA causes resistor R to... B The second terminal is grounded, and the power supply noise is v. in Through resistor R B Converted to noise compensation current v in R B , where R B For resistor R B The resistance value.

[0060] The drain of NMOS transistor N1 is connected to the drain of PMOS transistor P1, the gate of NMOS transistor N1, and the gate of NMOS transistor N2, respectively.

[0061] The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P2 and the gate of PMOS transistor P3, respectively.

[0062] The drain of NMOS transistor N2 is connected to the drain of PMOS transistor P2.

[0063] The source of NMOS transistor N2, the source of NMOS transistor N1, and the fifth and sixth terminals of the resistance adaptive adjustment unit 501 are all grounded.

[0064] The first terminal of the resistance adaptive adjustment unit 501 is connected to the drain of the PMOS transistor P3, and the second terminal is used to receive the external voltage V. in The third terminal is connected to the gate of the N-type power transistor MN, and the fourth terminal is connected to the source of the N-type power transistor MN.

[0065] The resistance adaptive adjustment unit 501 is used to adjust its own resistance value according to the change of load current of the wideband high power supply noise suppression linear voltage regulator circuit 100, so that the segmented FFRC compensation module adaptively adjusts the magnitude of the output compensation voltage.

[0066] The principle of FFRC compensation is explained below. For the compensation voltage generation model, please refer to [link / reference needed]. Figure 2 . Figure 2 Only modules closely related to the FFRC compensation principle are shown, including the bandgap reference (BGR), charge pump, error amplifier (EA), an auxiliary module (AUX) composed of a segmented FFRC compensation module and a summation module, and an N-type power transistor MN. The compensation voltage v generated by the auxiliary module... AUX Injected into the gate terminal of the N-type power transistor MN, by the transconductance g m It is converted into the compensation current at the output of a broadband linear voltage regulator circuit with high power supply noise suppression, and is related to the power supply noise v. in The internal resistance of the N-type power transistor MN is 1g. ds The noise current coupled to the output of the broadband, high-power-noise-suppression linear regulator circuit is canceled. This can be expressed by the formula:

[0067] Δi=g m ·v AUX +g ds ·v in ≈0.

[0068] Therefore, the compensation voltage v AUX The value of should be:

[0069]

[0070] Under different processes and different loads, The values ​​vary; see [reference]. Figure 3 Embodiments of the present invention control v by varying the connected resistor value. AUX The value changes. See also the section on distinguishing different load intervals. Figure 4 In each interval, it is specified The quantization value can further improve the feasibility of the circuit.

[0071] like Figure 1 As shown, the power transistor used is an N-type power transistor MN. The N-type power transistor MN uses a common-drain connection, resulting in a high impedance when viewed from the power supply through the drain terminal of the N-type transistor. Therefore, it has better power supply noise suppression capabilities compared to a P-type transistor. For ease of understanding, Figure 1 The load capacitance C is also shown. L and load R L .

[0072] Furthermore, optional, such as Figure 1 As shown, the resistance adaptive adjustment unit 501 includes:

[0073] NMOS transistors N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and resistor R T1 Resistance R T2 Resistance R T3 and resistance R T4 , and a first current comparator 5011, a second current comparator 5012, a third current comparator 5013 and a fourth current comparator 5014.

[0074] The drain connection resistor R of NMOS transistor N3 T1 The first terminal has its gate connected to the output terminal of the first current comparator 5011, and its source connected to resistor R. T1 The second terminal, resistor R T2 The first terminal and the drain of NMOS transistor N4.

[0075] The gate of NMOS transistor N4 is connected to the output of the second current comparator 5012, and its source is connected to resistor R. T2 The second terminal, resistor R T3 The first terminal and the drain of NMOS transistor N5.

[0076] The gate of NMOS transistor N5 is connected to the output of the third current comparator 5013, and its source is connected to resistor R. T3 The second terminal, resistor R T4 The first terminal and the drain of NMOS transistor N6.

[0077] The gate of NMOS transistor N6 is connected to the output of the fourth current comparator 5014, and the source is connected to resistor R. T4 The second end and ground signal.

[0078] The first input terminals of the first current comparator 5011, the second current comparator 5012, the third current comparator 5013, and the fourth current comparator 5014 are all used to receive external voltage V. in .

[0079] The second input terminals of the first current comparator 5011, the second current comparator 5012, the third current comparator 5013, and the fourth current comparator 5014 are all connected to the gate of the N-type power transistor MN.

[0080] The third input terminals of the first current comparator 5011, the second current comparator 5012, the third current comparator 5013, and the fourth current comparator 5014 are all connected to the source of the N-type power transistor MN.

[0081] Each current comparator is used to control the switching state of the corresponding NMOS transistor according to the load current of the wideband high power supply noise suppression linear voltage regulator circuit 100, so as to adjust the resistance value of the resistance adaptive adjustment unit 501.

[0082] Furthermore, while the circuit structures of the current comparators are identical, the component parameters differ, and options include, for example... Figure 5 As shown, each current comparator includes:

[0083] The current comparators consist of NMOS transistors N1-1, NMOS transistors N2-1, NMOS transistors N3-1, NMOS transistors N4-1, PMOS transistors P1-1, amplifier SA1, Schmitt trigger U1, and inverter U2, with different parameters for the PMOS transistors in each current comparator.

[0084] The drain of NMOS transistor N1-1 and the source of PMOS transistor P1-1 are both used to receive external voltage V. in NMOS transistor N1-1 is a replica of N-type power transistor MN. For example, the replication ratio is 1 / 1000.

[0085] The gate of NMOS transistor N1-1 is connected to the gate of N-type power transistor MN, and the source is connected to the non-inverting input of amplifier SA1 and the drain of NMOS transistor N2-1, respectively.

[0086] The inverting input of amplifier SA1 is connected to the source of N-type power transistor MN, and the output is connected to the gate of NMOS transistor N2-1.

[0087] The source of NMOS transistor N2-1 is connected to the drain and gate of NMOS transistor N3-1, and the gate of NMOS transistor N4-1, respectively.

[0088] The source of NMOS transistor N3-1 and the source of NMOS transistor N4-1 are both grounded to the signal.

[0089] The gate of PMOS transistor P1-1 is used to receive the first bias signal, and its drain is connected to the drain of NMOS transistor N4-1 and the input of Schmitt trigger U1, respectively.

[0090] The output of Schmitt trigger U1 is connected to the input of inverter U2, and the output of inverter U2 is the output of current comparator.

[0091] Optionally, when the load current is less than 45mA, NMOS transistors N3, N4, N5, and N6 are all turned on; when the load current is greater than or equal to 45mA and less than 66mA, NMOS transistor N3 is turned off, and NMOS transistors N4, N5, and N6 are all turned on; when the load current is greater than or equal to 66mA and less than 88mA, NMOS transistors N3 and N4 are turned off, and NMOS transistors N5 and N6 are turned on; when the load current is greater than or equal to 88mA and less than 100mA, NMOS transistors N3, N4, and N5 are turned off, and N6 is turned on; when the load current is greater than or equal to 100mA, NMOS transistors N3, N4, N5, and N6 are all turned off.

[0092] Specifically, the compensation voltage at the drain (point S) of PMOS transistor P3 is expressed as:

[0093] v s =ΣR Ti / R B ·v in ,

[0094] To make ΣR Ti / R B equal The quantized value. Each current comparator uses a different size PMOS transistor, resulting in a different fixed current generated by the PMOS transistor. When the load current is greater than the fixed current value, the current comparator outputs a signal T. i If it is low potential, then it is high potential.

[0095] For example, the current generated by the corresponding replica transistor is compared with four fixed currents of 45μA, 66μA, 88μA, and 100μA, which is equivalent to comparing the load current with 45mA, 66mA, 88mA, and 100mA. When the load current I... load When the current is <45mA, the output signals T1, T2, T3, and T4 of the four current comparators are all at high potentials. Current flows through the switching transistor at point S, and the four resistors are short-circuited; therefore, there is no compensation voltage. When 45mA ≤ I... load When the current is less than 66mA, T1 is at a low potential, and T2, T3, and T4 are at a high potential. The current flows through resistor R. T1 Compensation voltage v s =R T1 / R B ·v in When 66mA≤I loadWhen the current is less than 88mA, T1 and T2 are at low potentials, and T3 and T4 are at high potentials. Current flows through resistor R. T1 Resistance R T2 Compensation voltage v s =(R T1 +R T2 ) / R B ·v in When 88mA≤I load When the current is less than 100mA, T1, T2, and T3 are at low potentials, and T4 is at a high potential. Current flows through resistor R. T1 Resistance R T2 Resistance R T3 Compensation voltage v s =(R T1 +R T2 +R T3 ) / R B ·v in . When I load When the current is ≥100mA, T1, T2, T3, and T4 are all at low potentials, and the current flows through resistor R. T1 Resistance R T2 Resistance R T3 Resistance R T4 Compensation voltage v s =(R T1 +R T2 +R T3 +R T4 ) / R B ·v in R Ti This represents the resistance value of resistor RTi (i = 1, 2, 3, 4).

[0096] This circuit uses four current comparators and a switching transistor to control the magnitude of the compensated ripple, performing compensation in segments according to changes in the load current. That is, as the load current range varies, the magnitude of the compensated ripple injected into the gate of the power transistor adaptively changes. The resulting compensated current cancels out the noise current transmitted to the output of the wideband high power noise suppression linear regulator circuit, thus enabling the wideband high power noise suppression linear regulator circuit to have relatively high power noise suppression capability across the entire load range of 0-100mA.

[0097] Furthermore, optional, such as Figure 1 As shown, the summation module 40 includes:

[0098] resistor R BKB Capacitor C S1 Capacitor C S2 SUM is a summing amplifier.

[0099] resistor R BKB and capacitor CS2 After being connected in parallel, it is connected between the inverting input and output of amplifier SUM.

[0100] The inverting input of amplifier SUM is also connected to capacitor C. S1 Connect the segmented FFRC compensation module.

[0101] The non-inverting input of amplifier SUM is connected to the output of error amplifier.

[0102] Wherein, capacitor C S1 and capacitor C S2 Used to replicate the AC signal proportionally to the inverting input of amplifier SUM.

[0103] Furthermore, optional, such as Figure 1 As shown, buffer 60 includes:

[0104] NMOS transistor N7, NMOS transistor N8, PMOS transistor P4, and PMOS transistor P5.

[0105] The source of PMOS transistor P4 is used to receive voltage V. cp The gate is used to receive the second bias voltage, and the drain is connected to the source of PMOS transistor P5, the drain of NMOS transistor N8, the gate of N-type power transistor MN, and the fifth terminal of segmented FFRC compensation module 50, respectively.

[0106] The gate of PMOS transistor P5 is connected to the third terminal of the summing module, and its drain is connected to the gate of NMOS transistor N8 and the drain of NMOS transistor N7, respectively.

[0107] The gate of NMOS transistor N7 is used to receive the third bias voltage.

[0108] The source of NMOS transistor N7 and the source of NMOS transistor N8 are both grounded to the signal.

[0109] Furthermore, optional, such as Figure 1 As shown, the resistive feedback network 70 includes:

[0110] Resistors R1 and R2.

[0111] The first end of resistor R1 is connected to the source of N-type power transistor MN, and the second end is connected to the inverting input of error amplifier 30 and the first end of resistor R2, respectively.

[0112] The second terminal of resistor R2 is grounded.

[0113] To further demonstrate the beneficial effects of the present invention, a set of experimental data is also provided. Figure 6 The figure shows the PSRR curves before and after applying the FFRC compensation technology provided in this embodiment of the invention when the load current is 45mA. Figure 7 The figure shows the PSRR curves before and after applying the FFRC compensation technology provided in this embodiment of the invention when the load current is 66mA. Figure 8 The figure shows the PSRR curves before and after applying the FFRC compensation technology provided in this embodiment of the invention when the load current is 88mA. Figure 9 The figure shows the PSRR curves before and after applying the FFRC compensation technology provided in this embodiment of the invention when the load current is 100mA. The yellow line in the figure represents the PSRR curve without the FFRC compensation technology of this invention, and the red line represents the PSRR curve with the FFRC compensation technology of this invention. It can be seen that the present invention has a significant compensation effect in the frequency range of 0-500kHz.

[0114] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0115] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A wideband linear voltage regulator circuit with high power supply noise suppression, characterized in that, include: Bandgap reference voltage source, charge pump, error amplifier, summation module, segmented FFRC compensation module, buffer, N-type power transistor MN, resistor feedback network; The first terminal of the bandgap reference voltage source is used to receive an external voltage V. in The second terminal of the bandgap reference voltage source is connected to the non-inverting input terminal of the error amplifier and the third terminal of the segmented FFRC compensation module, respectively. The first terminal of the segmented FFRC compensation module is used to receive the external voltage V. in The second terminal is used to receive voltage V. cp The fourth end is connected to the first end of the summing module; The second terminal of the summing module is connected to the output terminal of the error amplifier, the third terminal is connected to the second terminal of the buffer, and the fourth terminal is used to receive the voltage V. cp ; The first end of the buffer is used to receive the external voltage V through the charge pump. in The third terminal is connected to the fifth terminal of the segmented FFRC compensation module and the gate of the N-type power transistor MN, respectively. The charge pump is used to convert the external voltage V in Converted to the voltage V cp ; The drain of the N-type power transistor MN is used to connect to the external voltage V. in ; The source of the N-type power transistor MN is the output terminal of the wideband high power supply noise suppression linear regulator circuit, and is connected to the first terminal of the resistor feedback network and the sixth terminal of the segmented FFRC compensation module, respectively. The second end of the resistor feedback network is connected to the inverting input of the error amplifier, and the third end is grounded. The power supply terminal of the error amplifier is used to receive the voltage V. cp ; The bandgap reference voltage source is used to generate the reference voltage V. REF ; The error amplifier is used to compare the reference voltage V. REF The sampled voltage output by the resistor feedback network is compared with the summation module, and the amplified comparison result is output to the summation module. The segmented FFRC compensation module is used to generate a compensation voltage based on the load current variation of the wideband high power supply noise suppression linear voltage regulator circuit, and output the compensation voltage to the summing module. The summation module is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and the AC voltage, and output the integrated result to the buffer. The buffer is used to drive the N-type power transistor MN and stabilize the output voltage of the high power supply noise suppression linear regulator circuit. The N-type power transistor MN is used to convert the gate voltage into a large current and output a stable voltage value. According to the compensation voltage, it suppresses the power supply noise entering the high power supply noise suppression linear regulator circuit. The segmented FFRC compensation module includes: amplifier FA, PMOS transistors P1, PMOS transistors P2, PMOS transistors P3, NMOS transistors N1 and NMOS transistors N2, and resistor R. B and resistance adaptive adjustment unit; The resistor R B The first terminal, the source of PMOS transistor P2, and the source of PMOS transistor P3 are all used to receive the external voltage V. in ; The power supply terminal of the amplifier FA is used to receive the voltage V. cp The inverting input terminal is connected to the resistor R. B The second terminal is connected, and the non-inverting input terminal is used to receive the reference voltage V output by the bandgap reference voltage source. REF ; The drain of the NMOS transistor N1 is connected to the drain of the PMOS transistor P1, the gate of the NMOS transistor N1, and the gate of the NMOS transistor N2, respectively. The gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P2 and the gate of the PMOS transistor P3, respectively. The drain of the NMOS transistor N2 is connected to the drain of the PMOS transistor P2; The source of NMOS transistor N2, the source of NMOS transistor N1, and the fifth and sixth terminals of the resistance adaptive adjustment unit are all connected to the ground signal. The first terminal of the resistance adaptive adjustment unit is connected to the drain of the PMOS transistor P3, and the second terminal is used to receive the external voltage V. in The third terminal is connected to the gate of the N-type power transistor MN, and the fourth terminal is connected to the source of the N-type power transistor MN. The resistance adaptive adjustment unit is used to adjust its own resistance value according to the change of load current of the wideband high power supply noise suppression linear voltage regulator circuit, so that the segmented FFRC compensation module adaptively adjusts the magnitude of the output compensation voltage.

2. The circuit according to claim 1, characterized in that, The resistance adaptive adjustment unit includes: NMOS transistors N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and resistor R T1 Resistance R T2 Resistance R T3 and resistance R T4 , and a first current comparator, a second current comparator, a third current comparator and a fourth current comparator; The drain of the NMOS transistor N3 is connected to the resistor R. T1 The first terminal has its gate connected to the output terminal of the first current comparator, and its source connected to the resistor R. T1 The second terminal, the resistor R T2 The first terminal and the drain of the NMOS transistor N4; The gate of the NMOS transistor N4 is connected to the output terminal of the second current comparator, and its source is connected to the resistor R. T2 The second terminal, the resistor R T3 The first terminal and the drain of the NMOS transistor N5; The gate of the NMOS transistor N5 is connected to the output terminal of the third current comparator, and its source is connected to the resistor R. T3 The second terminal, the resistor R T4 The first terminal and the drain of the NMOS transistor N6; The gate of the NMOS transistor N6 is connected to the output terminal of the fourth current comparator, and the source is connected to the resistor R. T4 The second end and the ground signal; The first input terminals of the first current comparator, the second current comparator, the third current comparator, and the fourth current comparator are all used to receive the external voltage V. in ; The second input terminals of the first current comparator, the second current comparator, the third current comparator, and the fourth current comparator are all connected to the gate of the N-type power transistor MN. The third input terminal of the first current comparator, the third input terminal of the second current comparator, the third input terminal of the third current comparator, and the third input terminal of the fourth current comparator are all connected to the source of the N-type power transistor MN; Each of the current comparators is used to control the switching state of the corresponding NMOS transistor according to the load current of the wideband high power supply noise suppression linear voltage regulator circuit, so as to adjust the resistance value of the resistance adaptive adjustment unit.

3. The circuit according to claim 2, characterized in that, include: When the load current is less than 45mA, NMOS transistors N3, N4, N5, and N6 are all turned on. When the load current is greater than or equal to 45mA and less than 66mA, NMOS transistor N3 is turned off, and NMOS transistors N4, NMOS transistor N5 and NMOS transistor N6 are all turned on. When the load current is greater than or equal to 66mA and less than 88mA, NMOS transistors N3 and N4 are turned off, and NMOS transistors N5 and N6 are turned on. When the load current is greater than or equal to 88mA and less than 100mA, NMOS transistors N3, N4, and N5 are turned off, and NMOS transistor N6 is turned on. When the load current is greater than or equal to 100mA, NMOS transistors N3, N4, N5, and N6 are all turned off.

4. The circuit according to claim 2, characterized in that, Each of the aforementioned current comparators includes: NMOS transistor N1-1, NMOS transistor N2-1, NMOS transistor N3-1, NMOS transistor N4-1, PMOS transistor P1-1, amplifier SA1, Schmitt trigger U1, and inverter U2, wherein the parameters of the PMOS transistors in each current comparator are different; The drain of the NMOS transistor N1-1 and the source of the PMOS transistor P1-1 are both used to receive the external voltage V. in The NMOS transistor N1-1 is a replica of the N-type power transistor MN; The gate of the NMOS transistor N1-1 is connected to the gate of the N-type power transistor MN, and the source is connected to the non-inverting input terminal of the amplifier SA1 and the drain of the NMOS transistor N2-1, respectively. The inverting input terminal of the amplifier SA1 is connected to the source of the N-type power transistor MN, and the output terminal is connected to the gate of the NMOS transistor N2-1. The source of NMOS transistor N2-1 is connected to the drain and gate of NMOS transistor N3-1, and the gate of NMOS transistor N4-1, respectively. The source of NMOS transistor N3-1 and the source of NMOS transistor N4-1 are both connected to the ground signal; The gate of the PMOS transistor P1-1 is used to receive the first bias signal, and the drain is connected to the drain of the NMOS transistor N4-1 and the input terminal of the Schmitt trigger U1, respectively. The output terminal of the Schmitt trigger U1 is connected to the input terminal of the inverter U2, and the output terminal of the inverter U2 is the output terminal of the current comparator.

5. The circuit according to any one of claims 1-4, characterized in that, The summation module includes: resistor R BKB Capacitor C S1 Capacitor C S2 SUM amplifier; The resistor R BKB and the capacitor C S2 After being connected in parallel, it is connected across the inverting input and output terminals of the amplifier SUM; The inverting input terminal of the amplifier SUM is also connected to the capacitor C. S1 Connect the segmented FFRC compensation module; The non-inverting input terminal of the amplifier SUM is connected to the output terminal of the error amplifier.

6. The circuit according to claim 5, characterized in that, The buffer includes: NMOS transistor N7, NMOS transistor N8, PMOS transistor P4 and PMOS transistor P5; The source of the PMOS transistor P4 is used to receive the voltage V. cp The gate is used to receive the second bias voltage, and the drain is connected to the source of the PMOS transistor P5, the drain of the NMOS transistor N8, the gate of the N-type power transistor MN, and the fifth terminal of the segmented FFRC compensation module, respectively. The gate of the PMOS transistor P5 is connected to the third terminal of the summing module, and the drain is connected to the gate of the NMOS transistor N8 and the drain of the NMOS transistor N7, respectively. The gate of the NMOS transistor N7 is used to receive the third bias voltage; The source of both NMOS transistor N7 and NMOS transistor N8 is connected to the ground signal.

7. The circuit according to claim 6, characterized in that, The resistance feedback network includes: Resistors R1 and R2; The first end of the resistor R1 is connected to the source of the N-type power transistor MN, and the second end is connected to the inverting input of the error amplifier and the first end of the resistor R2, respectively. The second end of the resistor R2 is connected to the ground signal.

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