Linear voltage regulator with isolated supply current

Abstract

A linear voltage regulator with isolated supply current is disclosed. The voltage regulator is configured and controlled such that its output current closely matches its input current (any quiescent current consumed by the regulator is negligible relative to the amount of current passed by the regulator). In some embodiments, the voltage regulator is implemented as an analog component. In other embodiments, the voltage regulator includes or cooperates with digital elements such as an analog-to-digital converter, a digital processing core, or a digital-to-analog converter.

Description

[0001] This application claims the benefit of U.S. Patent Application No. 16 / 940,669, filed July 28, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of the subject matter described herein generally relate to a test system for measuring the current consumed by a device under test, and to a current-isolated voltage regulator suitable for said test system. Background Technology

[0003] Electronic devices, systems, and components undergo continuous electrical testing after deployment and / or periodically during manufacturing. For example, electronic devices may be tested to measure the amount of current they consume during different operating modes. Abnormally low or high current readings may be an indication of a malfunction, error, or manufacturing defect.

[0004] Low-power electronic devices, such as battery-powered medical devices, can utilize switch-mode power supplies (SMPS), which provide on-demand switching during the low load currents that occur during the device's standby mode. In such devices, switching during standby mode occurs on demand. Therefore, the switching cycle typically extends until the input filter capacitors fail while smoothing the current. This results in discontinuous input currents, which often resemble pulse trains with a high dynamic range. In this respect, the non-switching current between "wake-up" current pulses can be four to five orders of magnitude lower than that between switching pulses. For a given pulse width, as the switching cycle increases (i.e., the duty cycle decreases), the overall current measurement accuracy is increasingly affected by the non-switching current. This combination of factors adversely affects the effectiveness and accuracy of most readily available current measurement systems, which are primarily designed to measure continuous currents and / or currents with low dynamic ranges. Therefore, when such devices are tested with conventional (and economically feasible) current measurement equipment, the measurement accuracy of discontinuous currents with high dynamic ranges deteriorates.

[0005] Test systems for measuring current may include voltage regulators that supply operating power to the device under test. Conventional low-dropout or linear voltage regulators utilize the regulator's input voltage to power certain components, such as internal reference voltages and error amplifiers. Therefore, the input current of this type of voltage regulator will always be higher than the output current. While this type of voltage regulator is suitable for some applications, it may not be appropriate for applications where a match between the output current and input current is desired. Summary of the Invention

[0006] This document discloses a test system and related current measurement techniques for accurately and efficiently measuring the current consumed by a device under test (DUT), wherein the current exhibits discontinuous and high dynamic range characteristics. This document also discloses linear voltage regulators that operate in a current-isolated manner, such that the regulator output current is closely matched to the regulator input current. Other desirable features and characteristics will become apparent from the following detailed description and the appended claims, taking into account the accompanying drawings and the foregoing technical and background information.

[0007] This document discloses a test system for measuring the current consumption of a device under test (DUT). The test system includes: a power capacitor having a power supply terminal and a ground terminal, configured to provide a capacitor voltage at the power supply terminal; a voltage regulator having a regulator input terminal and a regulator output terminal, configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a switching circuit for regulating the electrical connection between a direct current (DC) voltage source, the power capacitor, and the voltage regulator; and a controller coupled to the power capacitor, the voltage regulator, and the switching circuit. The controller can be configured to: control the switching circuit to place the test system in a charging state to charge the power capacitor with the DC voltage source; after the power capacitor has reached its charging voltage, control the switching circuit to place the test system in a measurement state, such that the power capacitor provides the capacitor voltage to the voltage regulator; and after the power capacitor has responded to a load reaching its discharge voltage, calculate the current provided by the power capacitor during a recorded time period during operation of the test system in the measurement state. The current is calculated based on the sampled values ​​of the charging voltage, the sampled values ​​of the discharging voltage, and the discharge characteristics of the power capacitor.

[0008] According to some embodiments, a test system for measuring the current consumption of a DUT includes: a power capacitor having a power supply terminal and a ground terminal, and configured to provide a capacitor voltage at the power supply terminal; a voltage regulator having a regulator input terminal and a regulator output terminal, and configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a first switching element located between a DC voltage source and the regulator input terminal; a second switching element located between the DC voltage source and the power supply terminal of the power capacitor; and a controller coupled to the power capacitor, the voltage regulator, the first switching element, and the second switching element. The controller can be configured to: close the first and second switching elements to charge the power capacitor using the DC voltage source; after the power capacitor has reached its charging voltage, open the first and second switching elements so that the power capacitor supplies the capacitor voltage to the voltage regulator; record the measurement start time associated with opening the first switching element when the second switching element is opened; close the first switching element after the power capacitor has reached its discharge voltage in response to the load; record the measurement end time associated with closing the first switching element when the second switching element is opened; and calculate the current supplied by the power capacitor between the measurement start time and the measurement end time based on the sampled value of the charging voltage of the power capacitor, the sampled value of the discharge voltage of the power capacitor, and the discharge characteristics of the power capacitor.

[0009] This paper also discloses an automated method for measuring the current of a DUT using a test system having a power capacitor, a voltage regulator for generating the DUT's operating voltage, a DC voltage source for regulating the DC voltage, a switching circuit for the electrical connection between the power capacitor and the voltage regulator, and a processor-based controller. The method involves: automatically controlling the switching circuit with the controller to place the test system in a charging state, such that the DC voltage source charges the power capacitor; after the power capacitor has reached the charging voltage, automatically controlling the switching circuit with the controller to switch the test system to a measurement state, such that the power capacitor provides a capacitor voltage to the voltage regulator when the test system is in the measurement state, wherein the DUT is coupled to the regulator output terminal of the voltage regulator when the test system is in the measurement state; recording the measurement start time with the controller; automatically controlling the switching circuit with the controller to switch the test system to a post-measurement state after the power capacitor has reached the discharge voltage in response to the operation of the DUT; recording the measurement end time with the controller; calculating the current consumed by the DUT between the measurement start time and the measurement end time based on the sampled value of the charging voltage, the sampled value of the discharge voltage, and the discharge characteristics of the power capacitor; and generating the calculated current as the output of the test system.

[0010] This article also discloses a linear voltage regulator. The linear voltage regulator includes: an input voltage terminal for regulating an input voltage; an output voltage terminal for regulating an output voltage; a series-path field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a reference voltage source for providing a reference voltage to the linear voltage regulator, the reference voltage source being powered by an independent voltage supply isolated from the input voltage terminal; a buffer amplifier having a buffered output, a positive buffered input coupled to the output voltage terminal, and a negative buffered input coupled to the buffered output, the buffer amplifier being powered by the independent voltage supply; a feedback voltage divider network coupled between the buffered output and a ground terminal, the feedback voltage divider network providing a scaled output voltage at the voltage divider output; and an error amplifier having an error output coupled to the transistor, a positive error input coupled to the voltage divider output to receive the scaled output voltage, and a negative error input coupled to the reference voltage source to receive the reference voltage, the error amplifier being powered by the independent voltage supply. The output of the error amplifier is based on the difference between the reference voltage and the scaled output voltage. The output of the error amplifier controls the impedance of the transistor to adjust the regulator output voltage at the output voltage terminal.

[0011] Another embodiment of a linear voltage regulator is also disclosed. This linear voltage regulator includes: an input voltage terminal for regulating an input voltage; an output voltage terminal for regulating an output voltage; a series-path field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a buffer amplifier having a buffered output, a positive buffered input coupled to the output voltage terminal, and a negative buffered input coupled to the buffered output, the buffer amplifier being powered by an independent voltage supply isolated from the input voltage terminal; a feedback voltage divider network coupled between the buffered output and a ground terminal, the feedback voltage divider network providing a scaled output voltage at the voltage divider output; and an analog-to-digital converter (ADC) having... An analog voltage input coupled to the voltage divider output to receive the scaled output voltage, and having a first digital output interface to provide a digital representation of the scaled output voltage, the ADC is powered by the independent voltage supply; a digital processing core having a first digital input interface coupled to the first digital output interface and a second digital output interface, the digital processing core being configured to generate a digital control output at the second digital output interface based on the difference between the digital representation of the scaled output voltage and a digital representation of a reference voltage, the digital processing core being powered by the independent voltage supply; and a digital-to-analog converter (DAC) having a second digital input interface coupled to the second digital output interface and an analog output coupled to the transistor. The DAC is configured to convert the digital control output into an analog control voltage and provide the analog control voltage at the analog output. The analog control voltage controls the impedance of the transistor to adjust the regulator output voltage at the output voltage terminal. The DAC is powered by the independent voltage supply.

[0012] This document also discloses a linear voltage regulator system. The system includes: an input voltage terminal for regulating an input voltage; an output voltage terminal for regulating an output voltage; a reference voltage terminal for a reference voltage; a series-path field-effect transistor coupled between the input voltage terminal and the output voltage terminal; and an error amplifier having an error output coupled to the transistor, a positive error input directly connected to the output voltage terminal to receive the regulator output voltage, and a negative error input coupled to the reference voltage terminal to receive the reference voltage. The error amplifier is powered by an independent voltage supply isolated from the input voltage terminal. The output of the error amplifier is based on the difference between the reference voltage and the regulator output voltage. The output of the error amplifier controls the impedance of the transistor to adjust the regulator output voltage at the output voltage terminal.

[0013] This summary is provided to introduce, in a simplified form, a series of concepts further described below in the detailed embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. Attached Figure Description

[0014] A more complete understanding of the subject matter can be derived by referring to the following detailed description and claims in conjunction with the accompanying drawings, in which the same reference numerals refer to similar elements throughout the drawings.

[0015] Figure 1 It is a block diagram depicting an embodiment of a test system in a typical test environment;

[0016] Figure 2 This is a schematic diagram of an embodiment of a test system connected to the device under test;

[0017] Figure 3 This is a flowchart illustrating an embodiment of an automated method for measuring the current of a device under test;

[0018] Figure 4 This includes, for example, in the case of Figure 2 The graph shows the voltage level sampled during a typical current measurement test performed by the test system as a function of time; and

[0019] Figures 5 to 7 This is a schematic diagram of an embodiment of a linear voltage regulator with isolated power supply current. Detailed Implementation

[0020] The following detailed descriptions are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as being more preferred or advantageous than other implementations. Furthermore, one is not to be bound by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed descriptions.

[0021] The techniques and processes described herein may refer to functional block components and / or logic block components, and to symbolic representations of operations, processing tasks, and functions that can be performed by various computing components or devices. Such operations, tasks, and functions are sometimes referred to as computer-executed, processor-based, software-implemented, computer-implemented, etc. It should be understood that the various block components shown in the figures can be implemented by any number of hardware, software, and / or firmware components configured to perform specified functions. For example, embodiments of the system or components may employ various integrated circuit components, such as memory elements, digital signal processing elements, logic elements, lookup tables, etc., which can perform various functions under the control of one or more microprocessors or other control devices.

[0022] When implemented in software or firmware, the various elements of the system described herein are essentially segments of code or instructions that perform various tasks. In some embodiments, the program or code segment is stored in a tangible processor-readable medium, which can include any medium capable of storing or transmitting information. Examples of non-transitory and processor-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, etc.

[0023] "Node" – as used herein, "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented with a single physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished, even if the signals are received or output at a common node).

[0024] "Coupled"—The following description may refer to elements, nodes, or features that are "coupled" together. As used herein, unless otherwise expressly stated, "coupled" means that one element / node / feature is directly or indirectly, and not necessarily mechanically, engaged with another element / node / feature (or directly or indirectly connected to another element / node / feature). Therefore, although Figure 2 The schematic diagrams shown depict an exemplary arrangement of elements, but additional intervening elements, devices, features, or components may be present in embodiments of the depicted test system. Furthermore, the connecting lines shown in the various figures included herein are intended to indicate exemplary functional relationships and / or physical connections between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter.

[0025] Figure 1This is a block diagram depicting an embodiment of a test system 100 in a typical test environment, including a device under test (DUT) 102 coupled to the test system 100 in a manner that allows the test system 100 to perform one or more electrical tests on it. The test system 100 may be implemented as a "bench test" component having a rack or housing containing various devices, components, and electronic parts. In some embodiments, the test system 100 includes a power cord 104 having a standard AC power outlet 106 for connection to a mains power supply. Alternatively or additionally, the test system 100 may receive a DC operating voltage from an external power supply 108, which obtains AC voltage from the mains power supply via a power cord 110 and an AC power outlet 112. In this arrangement, the test system 100 may include at least one input interface 114 to obtain DC voltage from the external power supply 108 (e.g., cable receptacle, wire clamp terminal, connector, etc.).

[0026] Test system 100 includes at least one DUT power interface 118 that establishes an electrical connection 120 between the voltage regulator of test system 100 and DUT 102. The DUT power interface 118 can be implemented with various form factors, depending on the configuration of DUT 102, the local power supply of DUT 102, the testing method of DUT 102, etc. For example, the DUT power interface 118 may, without limitation, include or cooperate with any of the following: electrical connectors; cable receptacles, wire clamp terminals, adapters, etc. In some embodiments, the DUT power interface 118 includes or cooperates with a DC voltage line or cable that is terminated with a structure simulating the shape and size of a battery (such as a 1.5-volt AA battery) typically used as a power source for DUT 102. The termination structure includes electrical contacts simulating the positive and negative terminals of the DUT's battery, allowing the voltage regulator of test system 100 to supply operating voltage to DUT 102 during testing.

[0027] The DUT 102 can be any electronic device with the operating voltage and current specifications supported by the test system 100. In this respect, the test system 100 must be able to generate sufficient DC operating voltage and current to power the DUT 102 during testing. In some applications, the DUT 102 is a portable battery-powered medical device, such as a personal insulin infusion device. In some embodiments, the DUT 102 operates in a low-power standby mode characterized by a discontinuous and high dynamic range standby current waveform. According to a non-limiting example, the standby current waveform comprises discontinuous pulses with a peak value of approximately 100 mA and a duration of only tens of microseconds, with an intermediate current of approximately 1.00 μA between pulses, possibly occurring every 10-100 milliseconds. As previously mentioned, conventional galvanometers struggle to accurately measure currents with such a high dynamic range.

[0028] The test system 100 disclosed herein represents an effective, low-cost, and ingenious solution to the aforementioned problems. Test system 100 employs a current measurement method based on the charging and discharging characteristics of a power capacitor with a known calibration capacitance. The power capacitor serves as the power source for DUT 102, and the charge on the capacitor is directly related to the current supplied or absorbed, as defined by physics and the electrical characteristics of the capacitor. Test system 100 uses the power capacitor to measure the total current consumed by DUT 102 during the measurement period, regardless of the current waveform type, dynamic range, etc., of the DUT. As explained in more detail below, test system 100 employs an automated circuit configuration to isolate the current path from the power capacitor to DUT 102. Any leakage current or quiescent current consumed by components of test system 100 is negligible relative to the amount of current to be measured, or is isolated such that it has no effect on the current measurement.

[0029] Figure 2 This is a schematic diagram depicting an embodiment of a test system 100 coupled to a DUT 102. For Figure 2 In this embodiment, all items shown (except DUT 102) are part of test system 100. For clarity and simplicity, power cord 104, AC power socket 106, input interface 114, and DUT power interface 118 (see [link]). Figure 1 None of them were in Figure 2 The following is shown. Embodiments of the test system 100 shown include, but are not limited to: a power capacitor 202; a voltage regulator 204; a switching circuit having a first switching element 206 and a second switching element 208; a controller 210; a controller clock 212; a display device 214; a DC voltage source 216; one or more isolated power supplies 217; a first current isolation buffer 218; a second current isolation buffer 220; a third current isolation buffer 222; a diode 223; a capacitance calibration circuit 224; and various conductive paths, traces, interconnections, or elements for coupling the components of the test system 100 together as needed.

[0030] The first switching element 206 is coupled between the DC voltage source 216 of the voltage regulator 204 and the regulator input terminal 230. The second switching element 208 is coupled between the DC voltage source 216 of the power capacitor 202 and the power supply terminal 232 (the power supply terminal 232 is electrically coupled to the positive conductor or positive plate of the power capacitor 202, such as...). Figure 2(As depicted in the diagram). The power capacitor 202 has a ground terminal 234 electrically coupled to the ground potential of the test system 100. The diode 223 has an anode 236 coupled to the power supply terminal 232 of the power capacitor 202, and a cathode 238 coupled to the regulator input terminal 230 of the voltage regulator 204. The voltage regulator 204 has a regulator output terminal 240 that can be coupled to the DUT 102 for testing purposes. In this respect, the DUT 102 can be detachably connected to the test system 100 to establish electrical coupling between the regulator output terminal 240 and the electronics of the DUT 102.

[0031] The controller 210 is at least coupled to the power capacitor 202, the voltage regulator 204, the first switching element 206, the second switching element 208, the display device 214, and the controller clock 212. According to the described embodiment: controller 210 is coupled to voltage regulator 204 via analog output terminal or terminal 244; third current isolation buffer 222 is coupled between regulator output terminal 240 and controller 210 via analog input terminal or terminal 246; controller 210 is coupled to display device via display output interface 248; controller 210 is coupled to controller clock via clock interface 250; second current isolation buffer 220 is coupled between power supply terminal 232 of power capacitor 202 and second voltage input terminal 252 of controller 210; controller 210 is coupled to first switching element 206 via first switch control terminal or terminal 254; controller 210 is coupled to second switching element 208 via second switch control terminal or terminal 256; and first current isolation buffer 218 is coupled between regulator input terminal 230 and first voltage input terminal 258 of controller 210. Figure 2 In the diagram, SW1 and SW2 represent switch control signals used to control the switching states of the first switch element 206 and the second switch element 208, respectively.

[0032] Multiple isolated power supplies 217 are suitably coupled to certain components, devices, or features of the test system 100 according to a particular embodiment. For clarity and simplicity, the various couplings associated with the multiple isolated power supplies are not detailed in the provided text. Figure 2 The capacitance calibration circuit 224 can be implemented as a separate circuit module (e.g., as depicted in the image). Figure 2 As depicted herein, or may be implemented in conjunction with at least some of other components and features of the test system 100, such as controller 210, voltage regulator 204, diode 223, and corresponding interconnections. For clarity and simplicity, the various couplings associated with the capacitance calibration circuit are not described in the diagram. Figure 2 Described in the text.

[0033] DC voltage source 216 provides multiple operating voltages to test system 100. In some embodiments, test system 100 includes DC voltage source 216, such as... Figure 2 As depicted in [the text]. If inside the test system 100, the DC voltage source 216 can be powered by the mains power supply. However, in some embodiments, the DC voltage source 216 can be external to the test system 100. The DC voltage source 216 charges the power capacitor 202 when the second switching element 208 is closed and provides a DC input voltage to the voltage regulator 204 when the first switching element 206 is closed. The voltage regulator 204 is configured and controlled to generate an appropriate DUT operating voltage at the regulator output terminal 240 based on the DC input voltage present at the regulator input terminal 230. Therefore, the DC voltage source 216 provides a DC voltage that is high enough to charge the power capacitor 202 to its charging voltage level and high enough to allow the voltage regulator 204 to generate the operating voltage required by the DUT 102. In some non-limiting embodiments, the nominal operating voltage of the DUT 102 is 1.5VDC, and the DC voltage source 216 provides 12.0VDC.

[0034] The switching circuit includes at least a first switching element 206 and a second switching element 208. Switching elements 206 and 208 can be implemented as solid-state (transistor-based) switches or as electromechanical relays. Ideally, switching elements 206 and 208 consume almost no current. A transistor-based switch is suitable if the switching leakage current is low enough to be negligible relative to the expected amount of the DUT current to be measured. For example, if the measured DUT current is expected to be in the range of about one nanoamp or greater, a switch with leakage current in the picoamp range may be suitable for the test system (such that the ratio of the measured current to the leakage current is at least 1000:1). Relays typically exhibit almost no leakage current and are therefore suitable for test system 100.

[0035] For this specific application, the capacitance of power capacitor 202 should be stable under varying operating voltages, operating temperatures, and environmental conditions. Therefore, the type (composition) of power capacitor 202 should provide tightly controlled capacitance. For example, power capacitor 202 could be a polypropylene film type high-voltage capacitor (e.g., typically greater than 100 volts). The capacitance can be selected to meet the needs and requirements of the specific application. For the example mentioned here (where DC voltage source 216 provides 12VDC and DUT 102 is powered by a 1.5VDC source), the capacitance of power capacitor 202 could be a value in the range of approximately 1.0mF to approximately 10.0mF (for smaller, low-power devices). These capacitor sizes are readily available in polypropylene film.

[0036] Diode 223 is a passive component and can be a conventional off-the-shelf product. Diode 223 has very low reverse leakage current, which should be approximately 1,000 times smaller than the expected measurement current. Therefore, silicon diodes are best suited for this application (rather than Schottky diodes). Diode 223 does not consume any measurable quiescent current, and therefore it can be present in the current path being measured (e.g., ...). Figure 2 (As depicted in the text).

[0037] Voltage regulator 204 is digitally controlled by controller 210 such that the current consumed by voltage regulator 204 is isolated, isolated, or otherwise disregarded when measuring DUT current. The controller (at analog input terminal 246) samples the regulator output voltage and (at analog output terminal 244) generates appropriate control signals to continuously increase or decrease the regulator output voltage as needed. As explained in more detail below, voltage regulator 204 is powered by isolated power supplies 217 instead of the DC voltage present at regulator input terminal 230. Therefore, the quiescent current consumed by voltage regulator 204 is associated with isolated power supplies 217, and voltage regulator 204 operates in current isolation relative to the current consumed by DUT 102 during testing. See below for further details. Figures 5 to 7 Additional details about the voltage regulator 204 are described below.

[0038] Each of the current isolation buffers 218, 220, and 222 can be implemented as a unity-gain operational amplifier with a conventional layout and configuration. Although not in Figure 2 As shown, however, if current isolation buffers 218, 220, 222 need to be compatible with the analog input of controller 210, these current isolation buffers may include or cooperate with a simple voltage divider circuit. Current isolation buffers 218, 220, 222 allow controller 210 to sample the corresponding voltage without consuming any measurable current. Current isolation buffers 218, 220, 222 are powered by isolated power supply(s) 217, and these current isolation buffers have very low input leakage current. The input leakage current is low enough that it is negligible relative to the current of the DUT to be measured. Therefore, even if current isolation buffers 218, 220, 222 branch off from the measurement current path, the measured DUT current remains accurate and precise. In other words, buffers 218, 220, 222 are appropriately configured and arranged to isolate the controller 210 from the test current path between the power capacitor 202 and the DUT 102.

[0039] Test system 100 calculates the current consumed by DUT 102 during the measurement period and generates the calculated current as an output. Display device 214 represents a type of output device that can be used to display the calculated current as an output. Display device 214 can be integrated with the housing or rack of test system 100, or it can be implemented as a separate peripheral component connected to and / or communicating with test system 100. Any type of display technology and form factor can be used with display device 214, and specific implementation details of display device 214 will not be described herein. In addition to or instead of display device 214, test system 100 may include or cooperate with other output devices or systems (such as printers, audio transducers, mechanical output devices, or interfaces for sending notifications, emails, text messages, electronic reports, etc.).

[0040] Controller 210 can be implemented as one or more physical devices, such as a microcontroller unit, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), etc. In some embodiments, controller 210 may be implemented as a "single-device" microcontroller unit (e.g., CPU) including a processor core, a storage medium for processor-executable program instructions, an input / output interface, at least one digital-to-analog converter (DAC), at least one analog-to-digital converter (ADC), memory (volatile and non-volatile), and other peripheral components or elements. Controller 210 may be based on off-the-shelf components programmed, configured, and / or customized for use in testing system 100. For this purpose, controller 210 may be configured to perform the various processes, methods, operations, and functions described herein.

[0041] As previously mentioned, the test system 100 is designed, configured, and operated such that the current consumed by the DUT 102 can be measured accurately and precisely in an isolated manner. To this end, the leakage current, quiescent current, and / or operating current consumed by certain components, devices, and elements of the test system 100 are minimized to a negligible level, or the sources of such current are isolated from the test current path. In this regard, operating voltages can be provided using isolated power supplies 217 to one or more of the following: a first switching element 206; a second switching element 208; a voltage regulator 204; a controller 210; a display device 214; a controller clock 212; a first current isolation buffer 218; a second current isolation buffer 220; a third current isolation buffer 222; and a capacitance calibration circuit 224.

[0042] As explained in more detail below, the known capacitance of power capacitor 202 is used to calculate the current consumed by DUT 102 during the measurement period. Although power capacitor 202 is chosen to make its capacitance relatively stable and constant, it may still be prone to slight changes over time. Therefore, having an accurate calibration capacitance value is important. Capacitance calibration circuit 224 can be coupled to power capacitor 202 to calibrate the capacitance of power capacitor 202. Calibration can be performed at any time, such as when test system 100 is powered on, before each current measurement, daily, weekly, etc. Capacitance calibration circuit 224 can be implemented to enable test system 100 to self-calibrate using, for example, a constant and known current source, which can cooperate with other components of test system 100 to perform calibration routines. When calibration is performed, a fixed current source (e.g., a constant 1.0mA current) replaces DUT 102. For calibration, the unknown variable is capacitance, which can be calculated based on the discharge characteristics of power capacitor 202. The calibrated capacitor can be stored as a known value for subsequent current measurements, where the unknown variable is the current consumed by DUT 102. Test system 100 itself can also be calibrated as needed (e.g., annually, monthly). Calibration of test system 100 may require external calibration equipment to calibrate the voltage source, a fixed current source for obtaining the calibration capacitor, the ADC and DAC of controller 210, etc.

[0043] The switching circuit is configured and controlled by controller 210 to regulate the electrical connection between the DC voltage source, power capacitor 202, and voltage regulator 204. In this regard, controller 210 can be configured to control the switching circuit by independently opening and closing switching elements 206, 208 as needed. Controller 210 activates or starts switching elements 206, 208 to place the test system 100 in different states or operating modes, including but not limited to: charging state; measurement state; and post-measurement state.

[0044] In the charging state, controller 210 keeps first switching element 206 and second switching element 208 closed to charge power capacitor 202 with the source voltage provided by DC voltage source 216. When both switching elements 206 and 208 are closed, diode 223 is not forward biased, and therefore, no current flows through diode 223. Therefore, the voltage of power capacitor 202 can be sampled and monitored by controller 210 via second voltage input terminal 252. When operating in the charging state, the source voltage of DC voltage source 216 is present at regulator input terminal 230, which enables voltage regulator 204 to generate a regulated DUT operating voltage for DUT 102. The DUT operating voltage allows DUT 102 to operate while power capacitor 202 is charging. Therefore, DUT 102 can be initialized, prepared for testing, placed in its low-current standby mode, etc., while being powered by DC voltage source 216.

[0045] In measurement mode, controller 210 keeps first switching element 206 and second switching element 208 open to provide capacitor voltage to regulator input terminal 230. Opening switching elements 206, 208 isolates DC voltage source 216 from other components of test system 100. Therefore, in measurement mode, power capacitor 202 acts as a voltage source instead of DC voltage source 216—power capacitor 202 provides its capacitor voltage to voltage regulator 204 via diode 223. When both switching elements 206, 208 are open, diode 223 is forward biased by the capacitor voltage, and thus, the diode allows discharge of power capacitor 202 through test current path 270. The test current path (depicted in dashed lines) starts from power capacitor 202, passes through diode 223, through voltage regulator 204, and reaches DUT 102, which represents the electrical load consuming power supplied by power capacitor 202. When operating in measurement mode, the capacitor voltage is present at regulator input terminal 230, which enables voltage regulator 204 to generate a regulated DUT operating voltage for DUT 102 (assuming the capacitor voltage remains sufficiently high). When operating in measurement mode, the capacitor voltage can be sampled by controller 210 (via second voltage input terminal 252), and the voltage present at regulator input terminal 230 can be sampled by controller 210 (via first voltage input terminal 258).

[0046] In the post-measurement state, controller 210 keeps the first switching element 206 closed and the second switching element 208 open. When test system 100 is in the post-measurement state, DC voltage source 216 provides its voltage to regulator input terminal 230 and cathode 238 of diode 223 via the first switching element 206. In the post-measurement state, diode 223 is reverse biased, and thus suppresses further discharge of power capacitor 202. Therefore, when test system 100 is in the post-measurement state, the source voltage generated by DC voltage source 216 can be sampled by controller 210 (via first voltage input terminal 258), and the discharge voltage of power capacitor 202 can be sampled by controller 210 (via second voltage input terminal 252).

[0047] Now refer to Figure 3 The diagram describes the operation of the test system 100 and is a flowchart illustrating an embodiment of an automated current measurement process 300. Process 300 is executed by the test system 100 to measure the current consumed by the DUT 102. The description of process 300 may involve the above-mentioned combinations. Figure 1 and Figure 2 The mentioned components. It should be understood that process 300 may include any number of additional or alternative tasks. Figure 3 The tasks shown need not be performed in the order presented, and process 300 can be incorporated into a more comprehensive program or process with additional functionality not described in detail herein. Furthermore, as long as the intended overall functionality remains intact, Figure 3 One or more of the tasks shown may be omitted from an embodiment of process 300.

[0048] Process 300 can begin by calibrating the capacitance of power capacitor 202 (task 302). As explained above, calibration does not need to be performed for every measurement, and therefore, task 302 can be performed periodically, according to a specific schedule, etc. However, task 302 is shown for completeness. The following description of process 300 assumes that test system 100 has an accurate capacitance calibration value, which can be used to calculate the amount of current consumed by DUT 102 during the measurement. DUT 102 is connected to test system 100 in a suitable manner (task 304) to establish an electrical coupling between regulator output terminal 240 and the electronics of DUT 102. In this way, voltage regulator 204 can be used as a power supply for DUT 102.

[0049] After the DUT 102 is connected to the test system 100, the current measurement routine begins. The test may begin automatically in response to the connection of the DUT 102, or it may require user instructions or commands. In some embodiments, the test system 100 uses a controller 210 to automatically control the switching circuitry to put the test system into a charging state (task 306). As mentioned above, when the test system 100 is in the charging state, the controller 210 keeps the first switching element 206 and the second switching element 208 closed, causing the DC voltage source 216 to charge the power capacitor 202. Furthermore, the DC voltage source 216 provides an input voltage to the voltage regulator 204, which in turn provides the appropriate operating voltage to the DUT 102. Therefore, the DUT 102 can be initialized and otherwise prepared for the current measurement routine.

[0050] The charging state is maintained until the power capacitor 202 is charged (e.g., the capacitor voltage has reached the charging voltage level). If the power capacitor 202 has not yet reached the charging voltage (the "No" branch of query task 308), the test system remains in the charging state. If the power capacitor 202 has reached the charging voltage (the "Yes" branch of query task 308), process 300 continues by automatically controlling the switching circuit with controller 210 to transition the test system 100 from the charging state to the measurement state (task 310). In some embodiments, query task 308 involves comparing the capacitor voltage with a charging voltage threshold such that when the capacitor voltage reaches the charging voltage threshold, the switching circuit is automatically controlled to place the test system 100 in the measurement state. Controller 210 may sample the capacitor voltage at the second voltage input terminal 252 for this comparison purpose. In some embodiments, query task 308 involves monitoring the elapsed time after entering the charging state such that when the elapsed time exceeds a charging time threshold, the switching circuit is automatically controlled to place the test system in the measurement state. Controller 210 may maintain a counter or timer (based on the operation of controller clock 212) to monitor the elapsed time.

[0051] This example assumes that the power capacitor 202 has reached its charging voltage and the test system 100 has transitioned to the measurement state. As mentioned above, the controller 210 disconnects the first switching element 206 and the second switching element 208 to place the test system 100 into the measurement state, and keeps these switches open while the test system operates in the measurement state. In the measurement state, the DC voltage source 216 is disconnected from the remaining components, and the power capacitor 202 supplies its capacitor voltage to the voltage regulator 204. In response to the transition to the measurement state, the controller 210 begins (or resumes) sampling the voltage at the first voltage input terminal 258 and the second voltage input terminal 252 (task 312) and records the measurement start time (task 314). In some embodiments, tasks 310, 312, and 314 are performed simultaneously, such that the measurement start time is recorded, the voltage is sampled, and the switching elements 206 and 208 are simultaneously disconnected. Therefore, the measurement start time is associated with the disconnection of the switching elements 206 and 208.

[0052] The measurement state is maintained until the power capacitor 202 reaches its discharge voltage in response to the load (i.e., the operation of DUT 102). At this point, the capacitor voltage decreases over time due to the current consumed by DUT 102. If the power capacitor 202 has not yet reached its discharge voltage (the "No" branch of task 316), the test system 100 remains in the measurement state. If the power capacitor 202 has reached its discharge voltage (the "Yes" branch of task 316), process 300 continues by automatically controlling the switching circuit with controller 210 to transition the test system 100 from the measurement state to the post-measurement state (task 318). The test system 100 is designed and operated such that the power capacitor 202 does not discharge excessively during the measurement state to ensure that the voltage characteristics of the power capacitor remain linear.

[0053] In some embodiments, the interrogation task 316 involves comparing the capacitor voltage with a minimum capacitor voltage threshold such that when the capacitor voltage is below or equal to the minimum capacitor voltage threshold, the switching circuit is automatically controlled to place the test system 100 into a post-measurement state. The controller 210 may sample the capacitor voltage at the second voltage input terminal 252 for this comparison purpose. For the example presented herein, the minimum capacitor voltage threshold may be approximately 8VDC when the DC voltage source 216 provides 12VDC. In some embodiments, the interrogation task 316 involves monitoring elapsed time after entering the measurement state (i.e., after disconnecting the switching elements 206, 208), such that when the elapsed time is greater than or equal to a maximum time threshold, the switching circuit is automatically controlled to place the test system 100 into a post-measurement state. The controller 210 may maintain a counter or timer (based on the operation of the controller clock 212) to monitor this elapsed time. For the example presented herein, the maximum time threshold may be approximately one to two seconds.

[0054] This example assumes that the power capacitor 202 has reached its discharge voltage and the test system 100 has transitioned to the post-measurement state. As mentioned above, the controller 210 closes the first switching element 206 and keeps the second switching element 208 open to place the test system 100 in the post-measurement state, and maintains these switching conditions while the test system 100 operates in the post-measurement state. In the post-measurement state, the DC voltage source 216 is coupled to: the cathode 238 of the diode 223; the input of the first current isolation buffer 218; and the regulator input terminal 230. However, the open state of the second switching element 208 keeps the DC voltage source 216 disconnected from: the power capacitor 202; the anode 236 of the diode 223; and the input of the second current isolation buffer 220. Therefore, the diode 223 is reverse biased, the power capacitor 202 no longer discharges, and the capacitor voltage (which is sampled at the second voltage input terminal 252) remains stable in the post-measurement state. Furthermore, in the post-measurement state, the voltage provided by the DC voltage source 216 corresponding to the charging voltage of the power capacitor 202 can be sampled at the first voltage input terminal 258.

[0055] In response to transitioning to the post-measurement state, controller 210 records the measurement end time (task 320). In some embodiments, tasks 318 and 320 are performed simultaneously, such that the first switching element 206 is closed and the measurement end time is recorded simultaneously. Therefore, the measurement end time is associated with the closing of the first switching element 206. Controller 210 may stop sampling the voltage at the first voltage input terminal 258 and the second voltage input terminal 252 at any appropriate time after transitioning to the post-measurement state (task 322). Controller 210 continues to sample these voltages for a period of time in the post-measurement state for reasons explained below to ensure voltage stability.

[0056] Process 300 continues by calculating the current supplied (and consumed by DUT 102) during a recorded time period while the test system 100 is in measurement mode (task 324). In this example, the time period is defined by the recorded measurement start time and the recorded measurement end time, and calculations are made based on sampled values ​​of the charging voltage of the power capacitor 202, sampled values ​​of the discharging voltage of the power capacitor 202, and the discharge characteristics of the power capacitor 202—that is, the relationship between capacitance and capacitor voltage over time relative to current. More specifically, controller 210 calculates based on the expressed... Calculate the current consumed by DUT 102 between the recorded measurement start time and the recorded measurement end time, where: C is the known (calibrated) capacitance of the power capacitor; V c It is a sampled value of the charging voltage; V d It is the sampled value of the discharge voltage; t i It is the recorded start time of the measurement; and t f The recorded measurement end time is the time recorded. Controller 210 records the measurement start time and measurement end time, samples the capacitor voltage at the second voltage input terminal 252, and samples the input voltage of voltage regulator 204 at the first voltage input terminal 258. Therefore, the current consumed by DUT 102 can be easily determined at task 324.

[0057] Process 300 continues by generating the calculated current as the output of test system 100 (task 326). For example, display device 214 can be controlled and driven in an appropriate manner to display the calculated current in any desired format (e.g., digital readout). For this particular example, test system 100 displays the standby current consumed by DUT 102 during a measurement period (typically a few seconds). Standby current represents the average value of the instantaneous current measured over the recorded time period.

[0058] Figure 4 This includes, for example, in the case of Figure 2The graph shown is a plot of the voltage level sampled during a typical current measurement test performed by the test system 100, representing the change over time. The horizontal time axis indicates the measurement start time (t). i ) and measurement end time (t) f The vertical voltage axis represents the charging voltage (V) of the power capacitor 202. c ) and discharge voltage (V d ).exist Figure 4 In the diagram, dashed curve 402 corresponds to the voltage present at regulator input terminal 230, the cathode 238 of diode 223, and the input of the first current isolation buffer 218. In other words, curve 402 represents the voltage sampled at the first voltage input terminal 258 of controller 210. Dashed curve 404 corresponds to the voltage present at power supply terminal 232 of power capacitor 202, the anode 236 of diode 223, and the input of the second current isolation buffer 220. In other words, curve 404 represents the voltage sampled at the second voltage input terminal 252 of controller 210. Due to the states of switching elements 206 and 208 during the charging state and the measurement state, the two curves 402 and 404 track each other during the charging state (before the measurement start time) and the measurement state (between the measurement start time and the measurement end time). Due to the closing of the first switching element 206 (while the second switching element 208 remains open), the two curves 402 and 404 diverge at the measurement end time. As explained above, the transition from the measurement state to the post-measurement state reconnects the DC voltage source 216 to the voltage regulator 204, making the source voltage (i.e., the charging voltage) immediately available for sampling at the first voltage input terminal 258. However, the capacitor voltage remains stable in the post-measurement state. Therefore, the discharge voltage of the power capacitor 202 can be used for sampling at the second voltage input terminal 252.

[0059] for Figure 2 In the illustrated embodiment, it is assumed that the charging voltage of the power capacitor 202 is equal to the voltage generated by the DC voltage source 216. Therefore, the charging voltage value can be sampled at the first voltage input terminal 258 at a sampling time that occurs before the measurement start time and / or after the measurement end time (i.e., when the test system 100 is in the post-measurement state). Alternatively or additionally, the charging voltage value can be sampled at the second voltage input terminal 252 at a sampling time that occurs before the measurement start time.

[0060] Figure 2The embodiment of the test system 100 shown samples the discharge voltage at the second voltage input terminal 252 during a sampling time that occurs after the measurement end time, while the capacitor voltage remains constant. For example, the test system 100 may wait for multiple sampling periods or a specified amount of time before sampling the discharge voltage, or it may continue sampling the discharge voltage level but only consider the sampled values ​​obtained after a specified amount of time (e.g., 100 ms, one second, etc.). This sampling scheme takes into account the equivalent series resistance (ESR) of the power capacitor 202. The effect of ESR on the sampled voltage is... Figure 4 The diagram is schematically depicted. At the start of the measurement, curves 402 and 404 both exhibit a sudden voltage drop. This drop occurs when switching elements 206 and 208 are disconnected to insert power capacitor 202 into current path 270; the voltage drop is caused by the ESR of power capacitor 202. However, at the end of the measurement, power capacitor 202 is removed from current path 270. Therefore, the ESR of power capacitor 202 causes a rapid voltage recovery before the capacitor voltage stabilizes to its discharge voltage level. Controller 210 uses the sampled value of the stabilized capacitor voltage to calculate the current consumed by DUT 102.

[0061] Referring again to Task 324 and the expression used to calculate the measured current, the charging voltage (V) can be expressed as follows: c Sampling is performed as follows: sampling times occurring before the measurement start time are recorded at the first voltage input terminal 258 of the controller 210; sampling times occurring after the measurement end time are recorded at the first voltage input terminal 258 of the controller 210; and / or sampling times occurring before the measurement start time are recorded at the second voltage input terminal 252 of the controller 210. Discharge voltage (V) d The sampling time occurring after the measurement end time is sampled at the second voltage input terminal 252. Although not required, the charging voltage and discharging voltage can be sampled at the same sampling time (when the test system 100 is in the post-measurement state).

[0062] The current measurement procedure described herein can reliably and accurately measure the average current consumed by the DUT, even when the current exhibits a very high dynamic range and relatively low peak current values. The test system 100 described herein can be manufactured from inexpensive and readily available parts and components, and can be modified as needed to effectively support different types of DUTs with varying functional specifications, voltage requirements, and current consumption characteristics.

[0063] As mentioned above, voltage regulator 204 is suitably configured and controlled such that its output current is very closely matched to its input current (i.e., any quiescent current consumed by voltage regulator 204 is negligible relative to the measured DUT current). A linear voltage regulator is used to produce a constant output voltage from a variable input voltage of a higher order of magnitude. A linear voltage regulator typically includes a series-path transistor (which may be a MOSFET or BJT), an error amplifier, a reference voltage, and a feedback divider network. The reference voltage establishes a fixed voltage value for comparison purposes. The feedback divider network produces a scaled version of the output voltage, with a reduction rate equal to the desired output voltage divided by the reference voltage. The error amplifier compares the scaled output voltage with the reference voltage and drives the series-path transistor to change its resistance. Ideally, the transistor is driven to minimize the difference between the output voltage and the reference voltage.

[0064] A typical linear voltage regulator following conventional design methods includes three terminals: an input voltage terminal (VIN); an output voltage terminal (VOUT); and a ground terminal (GND). An input voltage is applied between the VIN and GND terminals, and a regulated output voltage is supplied between the VOUT and GND terminals. A series-path transistor places the VIN and VOUT terminals in a series circuit. Theoretically, the current flowing into the VIN terminal (I0)... IN It should be equal to the current flowing out of the VOUT terminal (I). OUT However, I IN Always higher than I OUT (For this type of conventional voltage regulator), because the regulator inherently consumes the amount of current associated with the operation of the reference voltage, error amplifier, and feedback divider network. Depending on the topology and implementation of the voltage regulator, I IN with I OUT The magnitude of the difference is highly variable and may also vary depending on the applied load.

[0065] In some applications (e.g., the test system 100 described above), it may be expected that I IN with I OUT Matching. This occurs, for example, when it is necessary to accurately measure the applied load current without affecting the voltage at the VOUT terminal. If I IN with I OUT If the voltage drop across the shunt resistor is the same as that across the VIN terminal, then the shunt resistor can be connected in series with the VIN terminal, and the voltage drop across the shunt resistor will be the same as that across the I terminal. OUT The magnitude of the current is proportional. In this case, the voltage drop in the shunt resistor will not affect the regulated output voltage of the voltage regulator, because the regulator will naturally take into account the drop at the VIN terminal.

[0066] According to some embodiments described herein, the current consumed by the voltage regulator itself is isolated from the current supplied to the load. The current isolation design and configuration of the voltage regulator results in I... IN with I OUT The value matches, where any difference is relative to I. IN and I OUT The magnitude is negligible or insignificant. In this respect, Figure 2 An embodiment is depicted in which the controller 210 controls the voltage regulator 204 without consuming current from the power capacitor 202. Furthermore, the voltage regulator 204, the controller 210, and the third current isolation buffer 222 obtain their operating voltage from the isolated power supply(s) 217 ​​instead of from the power capacitor 202. Figures 5 to 7 An embodiment of a linear voltage regulator with isolated supply current is depicted. The test system 100 can be modified (if necessary) to use... Figures 5 to 7 The voltage regulator shown. Figure 5 A linear voltage regulator 500 based on analog design is described. Figure 6 The text describes a linear voltage regulator 600 that includes an ADC, a DAC, and a processing core or a cooperating linear voltage regulator. Figure 7 A linear voltage regulator 700, including a DAC or working in conjunction with it, is described.

[0067] refer to Figure 5 The linear voltage regulator 500 typically includes, but is not limited to: a series-path transistor 502; an error amplifier 504; a reference voltage source 506 for providing a reference voltage for the voltage regulator 500; a buffer amplifier 508; a feedback voltage divider network including a first resistor 510 and a second resistor 512; an input voltage terminal 514 (labeled VIN) for the regulator input voltage; an output voltage terminal 516 (labeled VOUT) for the regulator output voltage; a power supply voltage terminal 518 (labeled VSPLY); and a ground terminal 520 (labeled GND).

[0068] To achieve proper current isolation, the series-path transistor 502 is a metal-oxide-semiconductor field-effect transistor (MOSFET). In the depicted embodiment, transistor 502 is a p-channel enhancement-mode MOSFET. Transistor 502 is coupled between input voltage terminal 514 and output voltage terminal 516. More specifically, the source of transistor 502 is coupled to input voltage terminal 514, the drain of transistor 502 is coupled to output voltage terminal 516, and the gate of transistor 502 is coupled to the error output 530 of error amplifier 504. A feedback voltage divider network is coupled between buffer output 548 and ground terminal 520. The negative error input 532 of error amplifier 504 is coupled to the positive terminal 534 of reference voltage source 506, while the positive error input 536 of error amplifier 504 is coupled to the feedback voltage divider network. More specifically, the positive error input 536 is coupled between a first resistor 510 and a second resistor 512 connected in series. It is worth noting that the error amplifier 504 is powered by an independent voltage supply, which can be coupled between the power supply voltage terminal 518 and the ground terminal 520 (the line from the error amplifier 504 to the power supply voltage terminal 518 and the ground terminal 520 indicates the power supply voltage connection). The negative terminal 540 of the reference voltage source 506 is coupled to the ground terminal 520, and the reference voltage source 506 is powered by an independent voltage supply (the reference voltage source 506 is coupled to the power supply voltage terminal 518 to obtain the power supply voltage).

[0069] The buffer amplifier 508 is configured as a unity-gain follower with high input impedance. The positive buffer input 544 of the buffer amplifier 508 is coupled to the drain of the transistor 502 and to the output voltage terminal 516. The negative buffer input 546 of the buffer amplifier 508 is coupled to the buffer output 548 of the buffer amplifier 508 and to the first terminal 550 of the first resistor 510. Notably, the buffer amplifier 508 is powered by an independent voltage supply (the lines leading from the buffer amplifier 508 to the power supply voltage terminal 518 and the ground terminal 520 indicate the power supply voltage connection). As mentioned above, the second terminal 552 of the first resistor 510 is coupled to the first terminal 554 of the second resistor 512 and to the positive error input 536 of the error amplifier 504. The second terminal 556 of the second resistor 512 is coupled to the ground terminal 520, thereby establishing a feedback voltage divider network. The resistor values ​​are selected such that the feedback voltage divider network provides a scaled output voltage (ideally matched to a reference voltage) at the voltage divider output, which corresponds to a node defined by the second terminal 552 of the first resistor 510, the first terminal 554 of the second resistor 512, and the positive error input 536 of the error amplifier 504.

[0070] The basic operating principle of the linear voltage regulator 500 is similar to that described above for a conventional three-terminal voltage regulator. In this respect, the output of the error amplifier 504 controls the impedance of the transistor 502 to adjust the regulator output voltage appearing at the output voltage terminal 516. The output of the error amplifier 504 is based on the difference between the reference voltage appearing at the negative error input 532 and the scaled output voltage appearing at the positive error input 536. For example, if the scaled output voltage is higher than the reference voltage, the output voltage of the error amplifier 504 can be adjusted to gradually increase the series path resistance of the transistor 502 to decrease the regulator output voltage. Conversely, if the scaled output voltage is lower than the reference voltage, the output voltage of the error amplifier 504 can be adjusted to gradually decrease the series path resistance of the transistor 502 to increase the regulator output voltage.

[0071] Voltage regulator 500 achieves power supply current isolation via buffer amplifier 508. Buffer amplifier 508 is configured and arranged to operate as a unity-gain (1:1) follower, such that the voltage at buffer output 548 matches the voltage at positive buffer input 544 (it is the output of buffer amplifier 508, not transistor 502, that drives the feedback voltage divider network). Current isolation is further achieved using power supply voltage terminal 518 and ground terminal 520, coupled to provide source voltage and operating current to error amplifier 504, reference voltage source 506, and buffer amplifier 508—components powered by a separate voltage supply coupled to power supply voltage terminal 518, which is isolated from input voltage terminal 514. Therefore, input voltage terminal 514 supplies current only to output voltage terminal 516 via transistor 502. The inherently high input impedance of buffer amplifier 508 results in a negligible current draw from output voltage terminal 516.

[0072] Transistor 502 is implemented as a MOSFET (NMOS or PMOS, although) Figure 2A PMOS implementation is described to utilize extremely low gate-source and gate-drain currents. A MOSFET operating near steady-state conditions has gate-source and gate-drain currents that are negligible relative to the series path current. Furthermore, the high input impedance of the positive buffer input 544 of the buffer amplifier 508 ensures that the current flowing into the positive buffer input 544 is negligible compared to the desired current measurement resolution (e.g., less than 1:1000). In this respect, the buffer amplifier 508 isolates the current path from the input voltage terminal 514 to the output voltage terminal 516, such that the ratio of the current flowing into the positive buffer input 544 to the current flowing in the current path is less than 1:1000. As an example, if the desired current measurement resolution is 1.0 μA, the input impedance of the buffer amplifier 508 should be around 1.0 GΩ or higher, resulting in an input current of 1.0 nA or lower.

[0073] An independent voltage supply (which supplies power to terminal 518) supplies the quiescent current required by the operating error amplifier 504, the reference voltage source 506, and the buffer amplifier 508. This arrangement provides additional current isolation because the quiescent current is separate from and different from the current flowing through transistor 502.

[0074] refer to Figure 6 Voltage regulator 600 typically includes, but is not limited to: a series-path transistor 602; a buffer amplifier 608; a feedback voltage divider network including a first resistor 610 and a second resistor 612; an input voltage terminal 614 (labeled VIN); an output voltage terminal 616 (labeled VOUT); a power supply voltage terminal 618 (labeled VSPLY); a ground terminal 620 (labeled GND); an ADC 670; a digital processing core 672; and a DAC 674. The arrangement and configuration of voltage regulator 600 are similar to those described above for voltage regulator 500. However, the embodiment of voltage regulator 600 shown replaces error amplifier 504 with a combination of ADC 670, processing core 672, and DAC 674. Therefore, for simplicity and convenience, common or equivalent aspects of voltage regulators 500 and 600 will not be referenced. Figure 6 Provide a redundant and detailed description.

[0075] The series-path transistor 602 is implemented as a MOSFET, with its source coupled to the input voltage terminal 614, its drain coupled to the output voltage terminal 616, and its gate coupled to the analog output 630 of the DAC 674. The analog voltage input 636 of the ADC 670 is coupled to the divider output of the feedback divider network to receive the scaled output voltage generated by the feedback divider network. More specifically, the analog voltage input 636 is coupled between a first resistor 610 and a second resistor 612 connected in series. The positive buffer input 644 of the buffer amplifier 608 is coupled to the drain of the transistor 602 and to the output voltage terminal 616. The negative buffer input 646 of the buffer amplifier 608 is coupled to the buffer output 648 of the buffer amplifier 608 and to the first end 650 of the first resistor 610. As mentioned above, the second end 652 of the first resistor 610 is coupled to the first end 654 of the second resistor 612, and is also coupled to the analog voltage input 636 of the ADC 670. The second end 656 of the second resistor 612 is coupled to the ground terminal 620, thereby establishing a feedback voltage divider network.

[0076] Despite Figure 6 While depicted as separate blocks, the ADC 670, processing core 672, and DAC 674 can be combined into a single device or component according to desired implementations. For example, the ADC 670, processing core 672, and DAC 674 can be implemented as features or elements of a microcontroller device. In the illustrated embodiment, the ADC 670 is appropriately coupled to the processing core 672 to transmit digital information. Similarly, the processing core 672 is appropriately coupled to the DAC 674 to transmit digital information. In this regard, the ADC 670 has a digital output interface 680 coupled to the digital input interface 682 of the processing core 672. Furthermore, the processing core 672 has a digital output interface 684 coupled to the digital input interface 686 of the DAC 674.

[0077] DAC 674 cooperates with reference voltage source 688, which provides a reference voltage for digital-to-analog conversion. Similarly, ADC 670 cooperates with reference voltage source 690, which provides a reference voltage for analog-to-digital conversion. The reference voltage used by DAC 674 is typically higher than that used by ADC 670. Therefore, reference voltage source 688 can be different from and separate from reference voltage source 690 (as shown). ADC 670, processing core 672, DAC 674, buffer amplifier 608, reference voltage source 688, and reference voltage source 690 are powered by independent voltage supplies (as described above). Therefore, these components are coupled to power supply voltage terminal 618 and ground terminal 620. For simplicity, Figure 6 The separate connection between the power supply voltage terminal 618 and the reference voltage sources 688 and 690 is not shown.

[0078] The basic operating principle of the linear voltage regulator 600 is similar to that described above for the voltage regulator 500. A feedback voltage divider network provides a scaled output voltage to the ADC 670. The digital output interface 680 of the ADC 670 provides a digital representation of the scaled output voltage appearing at the analog voltage input 636. The processing core 672 receives the digital representation of the scaled output voltage through its digital input interface 682. The processing core 672 implements an algorithm that attempts to minimize the difference between the sampled voltage and a specified reference voltage. In this respect, the processing core 672 calculates the difference between the digital representation of the scaled output voltage and a digital representation of a programmed, stored, or otherwise specified reference voltage. The processing core 672 generates a digital control output at its digital output interface 684, which is based on the calculated difference. The digital control output is provided to the DAC 674 through the digital input interface 686.

[0079] The DAC 674 is configured and operated to convert a digital control output into a corresponding analog control voltage that appears at the analog output 630 of the DAC 674. The analog control voltage controls the impedance of the transistor 602 to adjust the regulator output voltage that appears at the output voltage terminal 616.

[0080] As described above with reference to voltage regulator 500, transistor 602, buffer amplifier 608, and independent voltage power supply (which supplies power voltage terminal 618) cooperate to provide current isolation for voltage regulator 600. Therefore, input voltage terminal 614 supplies current to output voltage terminal 616 only via transistor 602.

[0081] refer to Figure 7 Voltage regulator 700 typically includes, but is not limited to: a series-path transistor 702; an error amplifier 704; an input voltage terminal 714 (labeled VIN) for regulating the input voltage; an output voltage terminal 716 (labeled VOUT) for regulating the output voltage; a power supply voltage terminal 718 (labeled VSPLY) for an independent voltage supply; a ground terminal 720 (labeled GND); and a reference voltage terminal 721 (labeled VREF) for a reference voltage. Certain aspects of voltage regulator 700 are similar to those described above with respect to voltage regulators 500 and 600. Therefore, for the sake of brevity and convenience, common or equivalent aspects of voltage regulators 500, 600, and 700 will not be referred to. Figure 7 Provide a redundant and detailed description.

[0082] The series-path transistor 702 is implemented as a MOSFET, with its source coupled to the input voltage terminal 714, its drain coupled to the output voltage terminal 716, and its gate coupled to the error output 730 of the error amplifier 704. The negative error input 732 of the error amplifier 704 is coupled to the reference voltage terminal 721 to receive the reference voltage. In some embodiments, the positive error input 736 of the error amplifier 704 is directly connected to the drain of the transistor 702 and directly connected to the output voltage terminal 716 (in other words, no intermediate parts, devices, or elements are arranged between the output voltage terminal 716 and the positive error input 736). Therefore, the error amplifier 704 receives the regulator output voltage directly in the feedback path. The error amplifier 704 is powered by an independent voltage supply, which may be coupled between the power supply voltage terminal 718 and the ground terminal 720. As previously mentioned, this independent voltage supply is isolated from the input voltage terminal 714.

[0083] The illustrated embodiment of voltage regulator 700 employs an external DAC 750 and an associated reference voltage source 752. The DAC 750 and reference voltage source 752 replace the internal reference voltage of the error amplifier 704, feedback voltage divider network, and 1:1 buffer amplifier (these components are described in the context of the voltage regulators 500 and 600 above). The DAC 750 and reference voltage source 752 obtain their operating power from a source other than the voltage used as the input to the voltage regulator 700. For example, the DAC 750 and reference voltage source 752 may be powered by a separate voltage supply and / or by another auxiliary voltage supply. Figure 7 (Not shown in the image).

[0084] DAC 750 generates a fixed analog voltage equal to the desired regulator output voltage. Error amplifier 704 compares the voltage at output voltage terminal 716 with the voltage applied to reference voltage terminal 721 and drives series-path transistor 702 to maintain a minimum possible difference. The positive error input 736 of error amplifier 704 has a very high impedance (as mentioned above with reference buffer amplifier 508) to limit the amount of current drawn by error amplifier 704 from output voltage terminal 716.

[0085] DAC 750 serves as a fixed reference voltage source, and its analog output is coupled to reference voltage terminal 721. DAC 750 represents a digitally programmable component that can be configured to provide a desired reference voltage up to a maximum voltage based on the voltage generated by reference voltage source 752. Therefore, the reference voltage provided by DAC 750 can be digitally programmed and adjusted to match the expected regulator output voltage present at output voltage terminal 716. In alternative embodiments, a suitably configured analog voltage source or fixed voltage supply can be used instead of DAC 750. For example, if the regulator output voltage is expected to be 1.5VDC, an external 1.5VDC voltage source can be coupled to reference voltage terminal 721.

[0086] The basic operating principle of the linear voltage regulator 700 is similar to that described above for the voltage regulator 500. The regulator output voltage (not a scaled version thereof) is directly supplied to the positive error input 736 of the error amplifier 704 via the reference voltage terminal 721, and an external DAC 750 provides the desired reference voltage to the negative error input 732 of the error amplifier 704. The error amplifier 704 generates its output based on the difference between the reference voltage and the regulator output voltage, and this output controls the impedance of the transistor to adjust the regulator output voltage as needed.

[0087] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including equivalents known and foreseeable at the time of filing this patent application.

Claims

1. A linear voltage regulator, comprising: An input voltage terminal, which is used to regulate the input voltage of the regulator; An output voltage terminal, which is used to regulate the output voltage of the regulator; A series-path field-effect transistor, wherein the series-path field-effect transistor is coupled between the input voltage terminal and the output voltage terminal; A reference voltage source, wherein the reference voltage source is used to provide a reference voltage to the linear voltage regulator; A buffer amplifier, the buffer amplifier including a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output; A feedback voltage divider network coupled between the buffer output and the ground terminal provides a scaled output voltage at the voltage divider output; as well as An error amplifier includes an error output coupled to the series-path field-effect transistor, a positive error input coupled to the voltage divider output to receive the scaled output voltage, and a negative error input coupled to the reference voltage source to receive the reference voltage, wherein the error output of the error amplifier is based on the difference between the reference voltage and the scaled output voltage, and wherein the error output of the error amplifier controls the impedance of the series-path field-effect transistor to adjust the regulator output voltage at the output voltage terminal. The reference voltage source, the buffer amplifier, and the error amplifier are all located inside the linear voltage regulator and are all powered by an independent voltage power supply isolated from the input voltage terminal. The independent voltage power supply is an isolated power supply outside the linear voltage regulator that powers the linear voltage regulator.

2. The linear voltage regulator of claim 1, further comprising a power supply voltage terminal for the independent voltage power supply, wherein: The buffer amplifier is coupled to the power supply voltage terminal and also coupled to the ground terminal; The error amplifier is coupled to the power supply voltage terminal and also coupled to the ground terminal; and The reference voltage source is coupled to the power supply voltage terminal and also coupled to the ground terminal.

3. The linear voltage regulator as described in any one of claims 1 and 2, wherein, The series-path field-effect transistor is a metal-oxide-semiconductor field-effect transistor, i.e., a MOSFET.

4. The linear voltage regulator as described in claim 3, wherein: The MOSFET has a source, a drain, and a gate; The source of the MOSFET is coupled to the input voltage terminal; The drain of the MOSFET is coupled to the output voltage terminal; and The gate of the MOSFET is coupled to the error output of the error amplifier.

5. The linear voltage regulator as claimed in any one of claims 1 to 2, wherein, The feedback voltage divider network includes: A first resistor is coupled between the buffer output of the buffer amplifier and the output of the voltage divider; and A second resistor is coupled between the voltage divider output and the ground terminal.

6. The linear voltage regulator as claimed in any one of claims 1 to 2, wherein, The buffer amplifier is configured as a unity-gain follower.

7. The linear voltage regulator as claimed in any one of claims 1 to 2, wherein, The high input impedance of the positive buffer input isolates the current path from the input voltage terminal to the output voltage terminal, such that the ratio of the current flowing into the positive buffer input to the current flowing in the current path is less than 1:1000.

8. A linear voltage regulator, comprising: An input voltage terminal, which is used to regulate the input voltage of the regulator; An output voltage terminal, which is used to regulate the output voltage of the regulator; A series-path field-effect transistor, wherein the series-path field-effect transistor is coupled between the input voltage terminal and the output voltage terminal; A buffer amplifier, the buffer amplifier including a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output; A feedback voltage divider network coupled between the buffer output and the ground terminal provides a scaled output voltage at the voltage divider output; An analog-to-digital converter, or ADC, includes an analog voltage input coupled to the voltage divider output to receive the scaled output voltage, and the ADC includes a first digital output interface to provide a digital representation of the scaled output voltage; A digital processing core, the digital processing core including a first digital input interface coupled to the first digital output interface, and including a second digital output interface, the digital processing core being configured to generate a digital control output at the second digital output interface based on the difference between a digital representation of the scaled output voltage and a digital representation of a reference voltage; as well as A digital-to-analog converter (DAC) includes a second digital input interface coupled to the second digital output interface and an analog output coupled to the series-path field-effect transistor (SFET). The DAC is configured to convert the digital control output into an analog control voltage and provide the analog control voltage at the analog output, wherein the analog control voltage controls the impedance of the SFET to adjust the regulator output voltage at the output voltage terminal. The buffer amplifier, the ADC, the digital processing core, and the DAC are all powered by an independent voltage power supply isolated from the input voltage terminal, wherein the independent voltage power supply is an isolated power supply for the linear voltage regulator located outside the linear voltage regulator.

9. The linear voltage regulator of claim 8, further comprising a power supply voltage terminal for the independent voltage power supply, wherein: The buffer amplifier is coupled to the power supply voltage terminal and also coupled to the ground terminal; The ADC is coupled to the power supply voltage terminal and also coupled to the ground terminal; The processing core is coupled to the power supply voltage terminal and also coupled to the ground terminal; and The DAC is coupled to the power supply voltage terminal and also to the ground terminal.

10. The linear voltage regulator as claimed in any one of claims 8 and 9, wherein, The series-path field-effect transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET).

11. The linear voltage regulator of claim 10, wherein: The MOSFET has a source, a drain, and a gate; The source of the MOSFET is coupled to the input voltage terminal; The drain of the MOSFET is coupled to the output voltage terminal; and The gate of the MOSFET is coupled to the analog control voltage output of the DAC.

12. The linear voltage regulator as claimed in any one of claims 8 to 9, wherein, The feedback voltage divider network includes: A first resistor is coupled between the buffer output of the buffer amplifier and the output of the voltage divider; and A second resistor is coupled between the voltage divider output and the ground terminal.

13. The linear voltage regulator as claimed in any one of claims 8 to 9, wherein, The buffer amplifier is configured as a unity-gain follower.

14. The linear voltage regulator as claimed in any one of claims 8 to 9, wherein, The high input impedance of the positive buffer input isolates the current path from the input voltage terminal to the output voltage terminal, such that the ratio of the current flowing into the positive buffer input to the current flowing in the current path is less than 1:1000.

15. A linear voltage regulator system, comprising: An input voltage terminal, which is used to regulate the input voltage of the regulator; An output voltage terminal, which is used to regulate the output voltage of the regulator; A reference voltage terminal, wherein the reference voltage terminal is used to reference a voltage; A series-path field-effect transistor, wherein the series-path field-effect transistor is coupled between the input voltage terminal and the output voltage terminal; as well as An error amplifier includes an error output coupled to the series-path field-effect transistor, a positive error input directly connected to the output voltage terminal to receive the regulator output voltage, and a negative error input coupled to the reference voltage terminal to receive the reference voltage. The error amplifier is powered by an independent voltage supply isolated from the input voltage terminal. The error output of the error amplifier is based on the difference between the reference voltage and the regulator output voltage. The error output of the error amplifier controls the impedance of the series-path field-effect transistor to adjust the regulator output voltage at the output voltage terminal. The linear voltage regulator system further includes an external digitally programmable digital-to-analog converter (DAC) and an associated reference voltage source, the external DAC being coupled to the reference voltage terminal to provide the reference voltage to the error amplifier.

16. The linear voltage regulator system of claim 15, further comprising a power supply voltage terminal for the independent voltage power supply, wherein, The error amplifier is coupled to the power supply voltage terminal and also coupled to the ground terminal.

17. The linear voltage regulator system as claimed in any one of claims 15 and 16, wherein, The series-path field-effect transistor is a metal-oxide-semiconductor field-effect transistor, i.e., a MOSFET.

18. The linear voltage regulator system of claim 17, wherein: The MOSFET has a source, a drain, and a gate; The source of the MOSFET is coupled to the input voltage terminal; The drain of the MOSFET is coupled to the output voltage terminal; and The gate of the MOSFET is coupled to the error output of the error amplifier.

19. The linear voltage regulator system of any one of claims 15 to 16, further comprising a fixed voltage supply coupled to the reference voltage terminal to provide the reference voltage to the error amplifier.

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