Low-dropout linear regulator circuit and memory

Abstract

The disclosure provides a low dropout linear regulator circuit and a memory, the circuit comprising: a first transistor, a second transistor and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; the first end of the first transistor and the second end of the second transistor are connected to receive a power supply voltage; the second end of the first transistor and the first end of the second transistor are connected to output a target voltage; the control end of the second transistor receives a power-on control signal, and the second transistor is used to output the target voltage during the power-on process; the feedback control circuit is connected with the control end of the first transistor, the feedback control circuit is used to receive the power-on control signal, control the first transistor to be disconnected during the power-on process, and control the first transistor to output the target voltage after the power-on is completed; wherein the power-on control signal is in an enabled state during the power-on process, and is in a disabled state during the remaining period. The disclosure can reduce the circuit area, avoid overvoltage and simplify the timing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a low-dropout linear regulator circuit and a memory. Background Technology

[0002] A low-dropout linear regulator (LDO) is a power management device widely used in electronic devices. When the input voltage fluctuates within a normal range, it can stabilize the output voltage around a fixed value. Compared to traditional linear regulators, LDOs have a lower voltage drop between the input and output voltages and typically have extremely low intrinsic noise and a high power supply rejection ratio.

[0003] The working principle of an LDO is to convert the input voltage into a stable output voltage through a control loop, utilizing the regulation effect of an internal transistor or field-effect transistor within the linear region. When the output voltage changes, the LDO samples the output voltage through a feedback loop and compares it with a reference voltage. The amplifier circuit amplifies the difference and adjusts the circuit's operating state based on the difference, thereby stabilizing the output voltage.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides an LDO circuit and a memory.

[0006] In a first aspect, embodiments of this disclosure provide an LDO circuit, including: a first transistor, a second transistor, and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold.

[0007] The first terminal of the first transistor and the second terminal of the second transistor are connected to receive the power supply voltage; the second terminal of the first transistor and the first terminal of the second transistor are connected to output the target voltage.

[0008] The control terminal of the second transistor receives a power-on control signal. Based on the control of the power-on control signal, the second transistor is used to output a target voltage during the power-on process.

[0009] The feedback control circuit is connected to the control terminal of the first transistor. The feedback control circuit is used to receive the power-on control signal, and based on the power-on control signal, control the first transistor to disconnect during the power-on process, and control the first transistor to output the target voltage after the power-on is completed.

[0010] The power-on control signal is enabled during the power-on process and disabled at other times.

[0011] In some embodiments, the second transistor is a PMOS transistor, used to clamp the target voltage to the power supply voltage during power-on.

[0012] In some embodiments, the LDO circuit further includes a power-on protection circuit; the control terminal of the first transistor is connected to the power-on protection circuit;

[0013] The power-on protection circuit is used to receive the power-on control signal and, based on the power-on control signal, control the first transistor to disconnect during the power-on process.

[0014] In some embodiments, the power-on protection circuit includes a third transistor;

[0015] The first terminal of the third transistor is connected to the control terminal of the first transistor, the second terminal of the third transistor is connected to a preset power supply, and the control terminal of the third transistor receives the power-on control signal.

[0016] In some embodiments, the power-on protection circuit further includes at least one fourth transistor; when there are multiple fourth transistors, the multiple fourth transistors are connected in series;

[0017] The second terminal of the third transistor is connected to the first terminal of the first fourth transistor, and the second terminal of the last fourth transistor is connected to the preset power supply.

[0018] The control terminal of each of the fourth transistors receives the power-on control signal.

[0019] In some embodiments, the first transistor, the third transistor, and the fourth transistor are all NMOS transistors, and the second transistor is a PMOS transistor; the power-on control signal includes a first power-on control signal and a second power-on control signal, and the first power-on control signal and the second power-on control signal are a pair of inverted signals;

[0020] The control terminal of the second transistor receives the first power-on control signal, and the control terminals of the third transistor and each of the fourth transistors receive the second power-on control signal.

[0021] In some embodiments, the gate dielectric layer thickness of the third transistor is greater than the preset threshold, while the gate dielectric layer thicknesses of the second transistor MP and the fourth transistor are less than the preset threshold.

[0022] In some embodiments, the feedback control circuit includes:

[0023] A first feedback circuit is used to receive the target voltage, perform voltage division on the target voltage, and generate a first voltage.

[0024] A first comparison circuit is connected to the first feedback circuit. The first input terminal of the first comparison circuit is used to receive a first reference voltage, and the second input terminal of the first comparison circuit is used to receive the first voltage. The output terminal of the first comparison circuit is used to output a first comparison signal.

[0025] A level converter, connected to the first comparator circuit, is used to receive the first comparison signal and the power-on control signal. When the power-on control signal is in an enabled state, it performs voltage conversion on the first comparison signal and outputs a feedback control signal to control the on / off state of the first transistor. When the power-on control signal is in an enabled state, it outputs the default state feedback control signal to control the first transistor to turn off.

[0026] In some embodiments, the level converter includes: a cross-coupled circuit, a first ground circuit, a second ground circuit, and a third ground circuit; the cross-coupled circuit is connected to the first ground circuit at a first node, and to the second ground circuit and the third ground circuit at an output node, wherein the signal at the output node is the feedback control signal;

[0027] The first grounding circuit is used to receive the power-on control signal and the first comparison signal, and when the power-on control signal is in an enabled state and the first comparison signal is a first value, it connects the first node to the grounding terminal.

[0028] The second grounding circuit is used to receive the power-on control signal and the inverted signal of the first comparison signal. When the power-on control signal is in an enabled state and the inverted signal of the first comparison signal is a first value, the output node is connected to the grounding terminal.

[0029] The third grounding circuit is connected between the output node and the grounding terminal to receive the power-on control signal and to connect the output node to the grounding terminal when the power-on control signal is enabled.

[0030] The cross-coupling circuit is used to receive the first comparison signal, the inverted signal of the first comparison signal, and the first power supply voltage; to perform cross-coupling processing on the comparison signal and the inverted signal of the comparison signal, and to output the first power supply voltage to the first node or the output node.

[0031] In a second aspect, embodiments of this disclosure provide a memory including the LDO circuit described in the first aspect.

[0032] This disclosure provides an LDO circuit and a memory. The LDO circuit includes: a first transistor, a second transistor, and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; a first terminal of the first transistor and a second terminal of the second transistor are connected to receive a power supply voltage; the second terminal of the first transistor and the first terminal of the second transistor are connected to output a target voltage; the control terminal of the second transistor receives a power-on control signal, and based on the control of the power-on control signal, the second transistor outputs the target voltage during power-on; the feedback control circuit is connected to the control terminal of the first transistor, and the feedback control circuit receives the power-on control signal, and based on the power-on control signal, controls the first transistor to disconnect during power-on and controls the first transistor to output the target voltage after power-on; wherein the power-on control signal is in an enabled state during power-on and in an disabled state during other periods.

[0033] In this circuit, the first transistor is the output transistor of the LDO circuit. Its gate dielectric layer thickness is less than a preset threshold, meaning the first transistor is a thin-oxide MOSFET, which effectively reduces the circuit area. During power-up, the first transistor is off, and the second transistor clamps the target voltage output by the LDO to the power supply voltage. After power-up, the second transistor is turned off, and the first transistor outputs the target voltage. Thus, during power-up, the second transistor protects the first transistor from overvoltage. Simultaneously, since the first transistor does not overvoltage, complex timing control of its gate voltage slope is unnecessary; only a single power-up control signal is needed for rapid power-up, resulting in a fast-responding and high-current-capacity LDO circuit. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the LDO provided in the embodiments of this disclosure. Figure 1 ;

[0035] Figure 2 This is a schematic diagram of the structure of the LDO provided in the embodiments of this disclosure. Figure 2 ;

[0036] Figure 3 This is a schematic diagram of the structure of an LDO circuit provided in an embodiment of this disclosure. Figure 1 ;

[0037] Figure 4 This is a schematic diagram of the structure of an LDO circuit provided in an embodiment of this disclosure. Figure 2 ;

[0038] Figure 5 This is a schematic diagram of the structure of an LDO circuit provided in an embodiment of this disclosure. Figure 3 ;

[0039] Figure 6This is a schematic diagram of a power-on protection circuit provided in an embodiment of this disclosure;

[0040] Figure 7 This is a power-on timing diagram provided in an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of the structure of a level converter provided in an embodiment of this disclosure;

[0042] Figure 9 This is a schematic diagram of the structure of an LDO circuit provided in an embodiment of this disclosure. Figure 4 ;

[0043] Figure 10 This is a schematic diagram of the structure of an LDO circuit provided in an embodiment of this disclosure. Figure 5 . Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0046] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0047] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0048] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0049] Low dropout linear regulator (LDO);

[0050] Dynamic Random Access Memory (DRAM);

[0051] Double Data Rate (DDR);

[0052] Low-power DDR (LPDDR);

[0053] Digital LDO (Digital LDO, DLDO);

[0054] Analog LDO (ALDO);

[0055] Standard (SPEC);

[0056] The number of chips that can be cut from a wafer (DPW).

[0057] Metal-oxide-semiconductor field-effect transistor (MOS transistor);

[0058] P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor);

[0059] N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor);

[0060] Level shifter (LS);

[0061] Safety Operation Area (SOA);

[0062] Power on;

[0063] Second-stage Switching Core Voltage (Vdd2sc);

[0064] Second-stage core voltage (Vdd2c).

[0065] LPDDR and other memory contains many internal power supplies, most of which use LDOs (including DLDOs and ALDOs). LDOs use a negative feedback control system to dynamically adjust the conduction level of the internal output transistors, so as to maintain a stable output voltage when the input voltage fluctuates or the load changes.

[0066] See Figure 1 In this diagram, (a) is a schematic diagram of a DLDO, and (b) is a schematic diagram of an ALDO. Figure 1 As shown, the DLDO consists of a first feedback circuit Feedback1, a first amplifier Amp1, a level shifter LS, and a first output transistor MOUT1. The first output transistor MOUT1 is an NMOS transistor, with its gate connected to the output of the level shifter LS and its drain receiving an external power supply voltage Vdd2c. When the first output transistor MOUT1 is turned on, its source outputs the internal power supply voltage Vdd2sc. The first feedback circuit Feedback1 receives the internal power supply voltage Vdd2sc and outputs a first feedback signal (not shown in the figure) to the inverting input of the first amplifier Amp1. The non-inverting input of the first amplifier Amp1 receives a reference voltage Vref (or reference voltage), and the output of the first amplifier Amp1 is connected to the input of the level shifter LS. The first amplifier Amp1 is essentially a comparator.

[0067] The ALDO consists of a second feedback circuit (Feedback2), a second amplifier (Amp2), and a second output transistor (MOUT2). The second output transistor (MOUT2) is an NMOS transistor, with its gate connected to the output of the second amplifier (Amp2). Its drain receives an external power supply voltage (Vdd2c). When the second output transistor (MOUT2) is turned on, its source outputs an internal power supply voltage (Vdd2sc). The second feedback circuit (Feedback2) receives the internal power supply voltage (Vdd2sc) and outputs a second feedback signal (not shown in the diagram) to the non-inverting input of the second amplifier (Amp2). The inverting input of the second amplifier (Amp2) receives a reference voltage (Vref). The second amplifier (Amp2) is essentially an error amplifier.

[0068] Previous LDOs used thick oxide MOSFETs (thick oxide transistors) as output transistors, such as... Figure 1As shown, both the first output transistor MOUT1 and the second output transistor MOUT2 are thick-oxide MOSFETs. It should be noted that the difference between thick-oxide NMOS transistors and thin-oxide MOSFETs (Thin MOS, or simply thin-oxide transistors) lies in the thickness of the gate oxide layer (or gate dielectric layer). Thick-oxide MOSFETs have a thicker gate oxide layer and higher breakdown voltage, while thin-oxide MOSFETs have a thinner oxide layer and lower breakdown voltage. For example, a MOSFET with a breakdown voltage less than 1.2V can be called a thin-oxide MOSFET, and a MOSFET with a breakdown voltage greater than or equal to 1.2V but less than 3.4V can be called a thick-oxide MOSFET. Furthermore, based on different process nodes, a preset threshold can be set, classifying MOSFETs with a gate oxide layer thickness greater than or equal to the preset threshold as thick-oxide MOSFETs, and MOSFETs with a gate oxide layer thickness less than the preset threshold as thin-oxide MOSFETs.

[0069] Under the specified drive capability required by the SPEC, thick-oxide MOSFETs have a larger threshold voltage (Vth). For the same gate-source voltage minus threshold voltage (Vgs-Vth), thick-oxide MOSFETs require a larger area. This not only increases chip size and reduces DPW, but also results in larger parasitic capacitance due to the larger output transistor size, severely impacting response speed.

[0070] Therefore, to reduce the size of the output transistor, this solution uses a thin-film MOSFET as the output transistor, achieving a large current capability with a smaller area, while simultaneously reducing parasitic capacitance and accelerating response speed. See also Figure 2 , where (a) is in Figure 1 Based on (a), a schematic diagram of a DLDO using a thin-film MOS transistor as the first output transistor MOUT1 is shown; (b) is a diagram of a DLDO using a thin-film MOS transistor as the first output transistor. Figure 1 Based on (b), here is a schematic diagram of ALDO with a thin oxide MOS transistor as the second output transistor MOUT2; (c) is also a schematic diagram of ALDO, but the difference from (b) is that the output transistor is a PMOS transistor, denoted as the third output transistor MOUT3.

[0071] for Figure 2In schemes using thin-film MOSFETs as output transistors, to address the power-on SOA (System-on-Action) problem, it's necessary to limit the gate voltage of the output transistor or implement slope control at the gate during power-on. Slope control refers to controlling the rise rate of the gate voltage during power-on, making it rise slowly. This process requires multiple different control signals to control the power-on process. However, limiting the gate voltage of the output transistor limits the current output capability. If slope control is used for the gate voltage during power-on, because the internal power supply voltage Vdd2sc needs to power multiple internal devices, its power supply network is large with large parasitic capacitance. If the internal power supply voltage Vdd2sc rises slowly, nodes A / B / C also need slow slope control, leading to complex control and limiting the power-on time. In memories such as LPDDR, the execution time of operations such as activation is typically tens of nanoseconds, requiring LDOs to respond quickly within a few nanoseconds.

[0072] Based on this, in order to solve the problems of large output transistor size or slow response speed of LDO, this disclosure proposes a new LDO circuit structure that can achieve small area, fast response, and strong current capability. The LDO circuit includes: a first transistor, a second transistor, and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; a first terminal of the first transistor and a second terminal of the second transistor are connected to receive a power supply voltage; the second terminal of the first transistor and the first terminal of the second transistor are connected to output a target voltage; the control terminal of the second transistor receives a power-on control signal, and based on the control of the power-on control signal, the second transistor outputs the target voltage during power-on; the feedback control circuit is connected to the control terminal of the first transistor, and the feedback control circuit receives the power-on control signal, and based on the power-on control signal, controls the first transistor to disconnect during power-on and controls the first transistor to output the target voltage after power-on; wherein, the power-on control signal is in an enabled state during power-on and in an disabled state at other times.

[0073] In this circuit, the first transistor is the output transistor of the LDO circuit. Its gate dielectric layer thickness is less than a preset threshold, meaning the first transistor is a thin-oxide MOSFET, which effectively reduces the circuit area. During power-up, the first transistor is off, and the second transistor clamps the target voltage output by the LDO to the power supply voltage. After power-up, the second transistor is turned off, and the first transistor outputs the target voltage. Thus, during power-up, the second transistor protects the first transistor from overvoltage. Simultaneously, since the first transistor does not overvoltage, complex timing control of its gate voltage slope is unnecessary; a single power-up control signal is sufficient for rapid power-up, resulting in a fast-responding and high-current-capacity LDO circuit.

[0074] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0075] In one embodiment of this disclosure, see [link to embodiment]. Figure 3 It shows a schematic diagram of the composition structure of an LDO circuit provided in an embodiment of this disclosure, such as... Figure 3 As shown, the LDO circuit 10 includes: a first transistor M1, a second transistor M2, and a feedback control circuit 101; the gate dielectric layer thickness of the first transistor M1 is less than a preset threshold.

[0076] The first terminal of the first transistor M1 is connected to the second terminal of the second transistor M2 to receive the power supply voltage Vdd2c; the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 to output the target voltage Vdd2sc.

[0077] The control terminal of the second transistor M2 receives the power-on control signal. Based on the control of the power-on control signal, the second transistor M2 is used to output the target voltage Vdd2sc during the power-on process.

[0078] The feedback control circuit 101 is connected to the control terminal of the first transistor M1. The feedback control circuit 101 is used to receive the power-on control signal, and based on the power-on control signal, control the first transistor M1 to disconnect during the power-on process, and control the first transistor M1 to output the target voltage Vdd2sc after the power-on is completed.

[0079] The power-on control signal is enabled during the power-on process and disabled at other times.

[0080] It should be noted that, in this embodiment, the input voltage (i.e., power supply voltage) of the LDO circuit 10 is taken as Vdd2c, and the output voltage (i.e., target voltage) of the LDO circuit 10 is taken as Vdd2sc. In other scenarios, the corresponding types of input and output voltages can be set as needed.

[0081] exist Figure 3 In the example, the first transistor M1 is an NMOS transistor, the second transistor M2 is a PMOS transistor, the control terminal is the gate, the first terminal can be the drain, and the second terminal can be the source. In other examples, the transistor type can also be the same as... Figure 3 The results are different.

[0082] It should also be noted that, based on the thickness of the gate dielectric layer, MOSFETs can be classified into thick-gate MOSFETs and thin-gate MOSFETs. Thick-oxide MOSFETs and thin-oxide MOSFETs are traditional terms used when the gate dielectric layer is an oxide layer. In this application, the gate dielectric layer is not limited to an oxide layer; the following description will only use an oxide layer as an example. Furthermore, in the embodiments of this disclosure, a preset threshold is the critical value for determining whether a MOSFET is a thin-oxide MOSFET or a thick-oxide MOSFET. If the thickness of the gate dielectric layer of the MOSFET is less than the preset threshold, the MOSFET is considered a thin-oxide MOSFET; otherwise, it is considered a thick-oxide MOSFET. The value of the preset threshold is related to factors such as process conditions, process node, product type, and gate dielectric layer material. The withstand voltage value is also related to factors such as product type and process node.

[0083] For example, MOSFETs with a breakdown voltage less than 1.2V can be considered thin-oxide MOSFETs, and MOSFETs with a breakdown voltage greater than or equal to 1.2V can be considered thick-oxide MOSFETs. The gate dielectric layer thickness of a MOSFET with a breakdown voltage of 1.2V (which can be denoted as a preset transistor) is a preset threshold. The above numerical examples (such as the breakdown voltage threshold of 1.2V) are merely illustrative. However, when influencing factors such as product type, process node, and process conditions are fixed, the preset threshold for the gate oxide layer of thick-oxide and thin-oxide transistors is fixed.

[0084] In other classification methods, based on the thickness of the gate dielectric layer, MOSFETs can be further divided into thick-gate MOSFETs, medium-gate MOSFETs (i.e., MOSFETs with medium-thickness gate dielectric layers), and thin-gate MOSFETs. That is, compared to the classification method of thick-gate and thin-gate MOSFETs, an additional type of MOSFET with medium voltage withstand capability is added. For example, MOSFETs with a voltage withstand capability less than 1.2V can be considered thin-gate MOSFETs, MOSFETs with a voltage withstand capability greater than or equal to 1.2V and less than 2.4V can be considered medium-thickness MOSFETs, and MOSFETs with a voltage withstand capability greater than 2.4V can be considered thick-thickness MOSFETs. The above values ​​are merely examples. Thus, in this embodiment, a preset threshold is the critical value for defining a MOSFET as a thin-gate or medium-gate MOSFET. If the thickness of the gate dielectric layer of the MOSFET is less than the preset threshold, the MOSFET is considered a thin-gate MOSFET; otherwise, it is considered a medium-thickness or thick-gate MOSFET.

[0085] Thus, the first transistor M1 serves as the output transistor in the LDO circuit 10. By using a thin-oxide MOS transistor, the circuit area can be effectively reduced, parasitic capacitance can be decreased, and circuit performance can be improved.

[0086] It should also be noted that the second transistor M2 is connected in parallel with the first transistor M1. During power-up, the power-up control signal is in an enabled state. The enabled power-up control signal is used to turn on the second transistor M2, thereby using the second transistor M2 to transmit the external power supply voltage Vdd2c of the LDO circuit 10 to the internal circuit, to obtain the target voltage Vdd2sc required by the internal circuit, which is the output voltage of the LDO circuit 10. It should also be noted that the power-up mentioned here refers to the power-up of the target voltage Vdd2sc.

[0087] In other words, the second transistor M2 is used to clamp the target voltage Vdd2sc output by the LDO circuit 10 to the power supply voltage Vdd2c during the power-on process, while the first transistor M1 is in the off state, thereby protecting the first transistor M1 and preventing it from overvoltage during the voltage build-up period of the power-on process, effectively solving the SOA problem.

[0088] It should also be noted that the feedback control circuit 101 is the circuit in the LDO circuit 10 that implements feedback, comparison, and other related functions. In this embodiment, the feedback control circuit 101 is also controlled by a power-on control signal. The power-on control signal in the enabled state is used to control the feedback control circuit 101 to be in a preset working state. Here, the preset working state means that the control of the first transistor M1 by the feedback control circuit 101 is independent of the target voltage Vdd2sc, but the first transistor M1 is fixedly turned off. The power-on control signal in the disabled state controls the feedback control circuit 101 to be in a normal working state. Here, the normal working state means that the feedback control circuit 101 outputs a corresponding signal to the control terminal of the first transistor M1 based on the target voltage Vdd2sc, so as to control the on / off state and the degree of conduction of the first transistor M1, and ensure that the first transistor M1 outputs a stable target voltage Vdd2sc.

[0089] like Figure 3 As shown, the output signal of the feedback control circuit 101 is denoted as the feedback control signal. The control terminal of the first transistor M1 receives the feedback control signal. Based on the feedback control signal, the first transistor M1 is used to output the target voltage Vdd2sc after power-on.

[0090] Thus, when the power-on control signal is enabled, i.e. during power-on, the feedback control circuit 101 is in a preset working state, outputting a default state feedback control signal to control the first transistor M1 to turn off, thus preventing overvoltage in the first transistor M1; when the power-on control signal is disabled, i.e. after power-on, the feedback control circuit 101 is in a normal working state, outputting a feedback control signal to the control terminal of the first transistor M1 based on the feedback and comparison results, to control the conduction state of the first transistor M1, so as to output a stable target voltage Vdd2sc.

[0091] It should also be noted that the LDO circuit 10 in this embodiment can be either ALDO or DLDO. The composition of the feedback control circuit 101 will differ for different LDO circuits 10, which will be described in detail later.

[0092] In some embodiments, such as Figure 4 As shown, the LDO circuit 10 also includes a power-on protection circuit 102; the control terminal of the first transistor M1 is connected to the power-on protection circuit 102.

[0093] The power-on protection circuit 102 is used to receive the power-on control signal and, based on the power-on control signal, control the first transistor M1 to disconnect during the power-on process.

[0094] It should be noted that the power-on protection circuit 102 is used to further protect the first transistor M1 to prevent overvoltage during power-on. During power-on, the enabled power-on control signal is used to control the power-on protection circuit 102 to be in the working state. At this time, the signal output by the power-on protection circuit 102 acts on the control terminal of the first transistor M1, controlling the first transistor M1 to turn off. After power-on is completed, the disabled power-on control signal is used to control the power-on protection circuit 102 to be in the non-working state, and does not affect the state of the first transistor M1.

[0095] Thus, during power-up, the second transistor M2 is turned on, clamping the target voltage Vdd2sc of the LDO circuit 10 output to the power supply voltage Vdd2c, while the power-up protection circuit 102 disconnects the first transistor M1. On one hand, the first transistor M1 uses a thin-oxide MOSFET, saving area and reducing parasitic capacitance. On the other hand, only one power-up control signal is needed during power-up, eliminating the need for multiple control signals to control the slope of the output transistor's gate and avoiding complex power-up control timing. Furthermore, during power-up, the second transistor M2 clamps the output voltage of the LDO circuit 10, while the first transistor M1 is in the off state, thus protecting the first transistor M1 and preventing overvoltage during the voltage build-up period of power-up.

[0096] It should also be noted that after power-on, the power-on control signal switches to the disabled state, disconnecting the second transistor M2 and controlling the power-on protection circuit 102 to be in a non-operating state. At this time, the control terminal signal of the first transistor M1 is a feedback control signal, which is used to control the on / off state of the first transistor M1 so that the first transistor M1 can output the target voltage Vdd2sc after power-on. Since the voltage at the second terminal of the first transistor M1 has been clamped by the second transistor M2 during the power-on process, the first transistor M1 will not overvoltage after power-on.

[0097] Furthermore, since the second transistor M2 only needs to quickly clamp the output voltage of the LDO circuit 10 to the power supply voltage Vdd2c during power-on and then disconnect it after power-on, the second transistor M2 will not be over-voltaged during this process. Therefore, in this embodiment of the present disclosure, the second transistor M2 can also be a thin-oxide MOS transistor, that is, the gate dielectric layer thickness of the second transistor M2 is less than a preset threshold.

[0098] It should also be noted that the first transistor M1, as the output transistor of the LDO circuit 10, needs to provide the target voltage Vdd2sc to multiple power-consuming circuits in the memory. Therefore, compared to the second transistor M2, the first transistor M1 is usually larger in size. So, although the second transistor M2 and the power-on protection circuit 102 are added to the circuit, the overall circuit area can still be effectively reduced.

[0099] In this way, by using thin-film MOSFETs and a single power-on control signal, not only can the area of ​​the output transistor be reduced, ultimately reducing the area of ​​the LDO circuit, but also rapid power-on can be achieved, meeting the requirements of small area and high speed.

[0100] In some embodiments, such as Figure 4 As shown, the power-on protection circuit 102 is connected to the preset power supply 103. When the power-on control signal is in the enabled state, the preset power supply 103 is connected to the control terminal of the first transistor M1 to disconnect the first transistor M1.

[0101] It should be noted that the preset power supply 103 provides a fixed logic state (denoted as the preset level) for turning off the first transistor M1. For example, in Figure 4 In this example, the first transistor M1 is an NMOS transistor. Therefore, the preset power supply 103 is grounded to provide logic 0 and turn off the NMOS transistor. In other examples, if the first transistor M1 is a PMOS transistor, the preset power supply 103 can be a power supply circuit to provide logic 1 and turn off the PMOS transistor.

[0102] Based on this, such as Figure 5 As shown, in some embodiments, the power-on protection circuit 102 includes a third transistor M3;

[0103] The first terminal of the third transistor M3 is connected to the control terminal of the first transistor M1, the second terminal of the third transistor M3 is connected to a preset power supply, and the control terminal of the third transistor M3 receives a power-on control signal.

[0104] It should be noted that, in Figure 5Taking the second transistor M2 as a PMOS transistor and the third transistor M3 as an NMOS transistor as an example, the power-on control signal can be divided into a first power-on control signal PwrOn and a second power-on control signal PwrOnB. The first power-on control signal PwrOn and the second power-on control signal PwrOnB are a pair of inverted signals with the same timing but opposite phases. Only one of them needs to be inverted using a NOT gate to obtain the other. Therefore, the LDO circuit 10 may also include a NOT gate (not shown in the figure) to receive the first power-on control signal PwrOn, invert the first power-on control signal PwrOn to obtain the second power-on control signal PwrOnB, and provide it to the power-on protection circuit 102.

[0105] like Figure 5 As shown, the control terminal of the second transistor M2 receives the first power-on control signal PwrOn, and the control terminal of the third transistor M3 receives the second power-on control signal PwrOnB; in this example, the second terminal of the third transistor M3 is specifically grounded, that is, the preset power supply is the ground terminal. Figure 5 (Not shown as reference numeral 103). In this case, for the first power-on control signal PwrOn, its enabled state is logic 0 and its disabled state is logic 1; for the second power-on control signal PwrOnB, its enabled state is logic 1 and its disabled state is logic 0.

[0106] In this way, when the first power-on control signal PwrOn and the second power-on control signal PwrOnB are enabled, the second transistor M2 and the third transistor M3 are both turned on, respectively clamping the output voltage of the LDO circuit 10 and pulling down the control terminal of the first transistor M1 to ground, avoiding SOA problems, speeding up the power-on speed, and simplifying the control timing.

[0107] It should be noted that the second terminal of the third transistor M3 can be directly grounded, or it can be grounded through another circuit. For example... Figure 5 As shown, the power-on protection circuit 102 may further include a fourth transistor M4, the first terminal of which is connected to the second terminal of the third transistor M3, and the second terminal of the fourth transistor M4 is grounded. Thus, when the fourth transistor M4 is turned on, the second terminal of the third transistor M3 can be grounded.

[0108] It should also be noted that the number of the fourth transistor M4 can be as follows: Figure 5 The circuit shown can be one, but it can also have multiple transistors. That is, the power-on protection circuit 102 also includes at least one fourth transistor M4; at least one fourth transistor M4 is connected in series;

[0109] The second terminal of the third transistor M3 is connected to the first terminal of the first fourth transistor M4, and the second terminal of the last fourth transistor M4 is connected to the preset power supply.

[0110] Each fourth transistor M4 receives a power-on control signal at its control terminal.

[0111] It should be noted that the fourth transistor M4 is also controlled by the power-on control signal. When the power-on control signal is enabled, the fourth transistor M4 is turned on to connect the third transistor M3 and the preset power supply; when the power-on control signal is disabled, the fourth transistor M4 is turned off to disconnect the third transistor M3 and the preset power supply.

[0112] Taking two fourth transistors M4 as an example, such as Figure 6 As shown, the first fourth transistor is denoted as fourth transistor M4-1, and the second fourth transistor (which is also the last fourth transistor) is denoted as fourth transistor M4-2. The first terminal of fourth transistor M4-1 is connected to the second terminal of third transistor M3, and the second terminal of fourth transistor M4-1 is connected to the first terminal of fourth transistor M4-2, realizing the series connection of fourth transistors M4-1 and M4-2. The second terminal of fourth transistor M4-2 is grounded.

[0113] Still with Figure 5 For example, in this embodiment of the disclosure, each fourth transistor M4 can also be an NMOS transistor. Then, similar to the third transistor M3, the control terminal of each fourth transistor M4 also receives the second power-on control signal PwrOnB.

[0114] It should be noted that, as Figure 5 As shown, the first transistor M1, the second transistor M2, and the fourth transistor M4 are all thin-oxide MOSFETs, meaning the thickness of their gate dielectric layer is less than a preset threshold. This results in a small size, preventing a large circuit area and minimizing the parasitic capacitance of the connection node (denoted as node X) between the first transistor M1, the feedback control circuit 101, and the power-on protection circuit 102. Meanwhile, the third transistor M3 can be a thick-oxide MOSFET, meaning the thickness of its gate dielectric layer is greater than a preset threshold. Since the third transistor M3 is only used for pull-down during power-on and does not require a large size, using a thick-oxide MOSFET will not significantly impact the circuit area.

[0115] It should also be noted that, Figure 5 The diagram shown is a schematic of a DLDO circuit. Figure 5 As shown, in a DLDO, the feedback control circuit 101 may include:

[0116] The first feedback circuit 1011 is used to receive the target voltage Vdd2sc, perform voltage division on the target voltage Vdd2sc, and generate the first voltage V1.

[0117] The first comparison circuit 1012 is connected to the first feedback circuit 1011. The first input terminal of the first comparison circuit 1012 is used to receive the first reference voltage Vref1, and the second input terminal of the first comparison circuit 1012 is used to receive the first voltage V1. The output terminal of the first comparison circuit 1012 is used to output the first comparison signal C1.

[0118] The level converter 1013 is connected to the first comparator circuit 1012 and is used to receive the first comparison signal C1 and the power-on control signal. When the power-on control signal is in the disabled state, it performs voltage conversion on the first comparison signal C1 and outputs a feedback control signal to control the on / off state of the first transistor M1. When the power-on control signal is in the enabled state, it outputs a default state feedback control signal to control the first transistor M1 to turn off.

[0119] It should be noted that, in Figure 5 In this example, the level converter 1013 receives the first power-on control signal PwrOn. In other examples, it can also be the second power-on control signal PwrOnB, which is not specifically limited.

[0120] It should also be noted that the first feedback circuit 1011 can be a resistor string, composed of multiple resistors connected in series. One end of the resistor string receives the target voltage Vdd2sc, and the other end is grounded. Depending on the actual requirements of the circuit, a specific connection node in the resistor string is selected as the output terminal of the first feedback circuit 1011 to output the first voltage V1. For example... Figure 5 As shown, the resistor string consists of three resistors connected in series, and the connection node between the first and second resistors serves as the output terminal of the first feedback circuit 1011.

[0121] In other words, the first feedback circuit 1011 is actually a resistor voltage divider network that can divide or sample the target voltage Vdd2sc to obtain a first voltage V1 that is proportional to the target voltage Vdd2sc.

[0122] It should also be noted that, such as Figure 5 As shown, the first input terminal of the first comparator circuit 1012 can be its non-inverting input terminal "+", and the second input terminal of the first comparator circuit 1012 can be its inverting input terminal "-". The first reference voltage Vref1 is a high-precision, high-stability reference voltage. The first comparator circuit 1012 compares the first reference voltage Vref1 with the first voltage V1, and based on the relationship between the two, outputs a corresponding comparison signal to control the conduction level of the first transistor M1, so as to ensure that the voltage drops when the target voltage Vdd2sc is too high, and rises when the target voltage Vdd2sc is too low, thus ensuring that the target voltage Vdd2sc remains stable overall.

[0123] The first comparison circuit 1012 is essentially a comparator used to determine and compare the relative magnitudes of two input signals and output a defined logic level.

[0124] like Figure 5 As shown, a level converter 1013 is also connected between the control terminal of the first comparator circuit 1012 and the first transistor M1. The level converter 1013 is a device used to realize the conversion between different voltage domains. The level converter 1013 can convert the voltage of the first comparison signal C1, converting the voltage domain of the signal from the voltage domain of the first comparator circuit 1012 to the voltage domain of the first transistor M1, so as to avoid the first comparison signal C1 being unable to effectively control the first transistor M1 or the first comparison signal C1 causing damage to the first transistor M1; at the same time, the level converter 1013 can also act as a buffer device to protect the device by isolating the first comparator circuit 1012 and the first transistor M1.

[0125] It should also be noted that, such as Figure 5 As shown, the first power-on control signal PwrOn is used to control whether the level converter 1013 performs voltage conversion, that is, to control whether the feedback control circuit 101 is in a preset working state (corresponding to the level converter 1013 not performing voltage conversion) or a normal working state (corresponding to the level converter 1013 performing voltage conversion).

[0126] As mentioned earlier, during power-up, the power-up protection circuit 102 pulls down node X to ensure that the first transistor M1 is off. Simultaneously, the level converter 1013 does not perform level conversion to avoid outputting a feedback control signal that would turn on the first transistor M1. Therefore, during power-up, the first power-up control signal PwrOn is enabled, used to control the level converter 1013 not to perform level conversion. At this time, the level converter 1013 outputs a default state feedback control signal. Figure 5 In the default state, logic 0 is used to ensure that the first transistor M1 is not turned on. After power-on, the first power-on control signal PwrOn is in the disabled state, which is used to control the level converter 1013 to perform level conversion. At this time, the level converter 1013 performs level conversion based on the first comparison signal C1 to obtain a feedback control signal to control the conduction degree of the first transistor M1.

[0127] exist Figure 5 Based on this, see Figure 7 It shows the corresponding power-on timing diagram. Combined with... Figure 5 and Figure 7 As shown:

[0128] After the power supply voltage Vdd2c is powered on, firstly, PwrOn=0 and PwrOnB=1, and the target voltage Vdd2sc starts to be powered on. After the target voltage Vdd2sc is powered on, PwrOn=1 and PwrOnB=0.

[0129] like Figure 5 As shown, when PwrOn=0, the second transistor M2 is turned on, and the target voltage Vdd2sc is clamped to the power supply voltage Vdd2c through the second transistor M2. Simultaneously, when PwrOnB=1, both the third transistor M3 and the fourth transistor M4 are turned on, and the gate of the first transistor M1 is pulled down to 0, preventing the first transistor M1 from turning on. Also, when PwrOn=0, the output of the level shifter 1013 is pulled down to 0, and there is no fighting at node X. During this process, neither the NMOS nor the PMOS transistors experience overvoltage.

[0130] After power-on, PwrOn=1, PwrOnB=0, the power supply voltage of level converter 1013 is established, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all turned off, level converter 1013 works normally, and the voltage at node X can be Vdd2sc+Vgs, where Vgs is the gate-source voltage of the first transistor M1, and neither the NKOS transistor nor the PMOS transistor has overvoltage.

[0131] It can be seen that, based on Figure 5 The circuit structure shown not only saves circuit area and reduces parasitic capacitance, but also enables rapid power-on and improves response speed.

[0132] Furthermore, for the level converter 1013, such as Figure 8 As shown, the level converter 1013 may include: a cross-coupled circuit 204, a first grounding circuit 201, a second grounding circuit 202, and a third grounding circuit 203; the cross-coupled circuit 204 is connected to the first grounding circuit 201 at a first node X1, and connected to the second grounding circuit 202 and the third grounding circuit 203 at an output node X2, and the signal at the output node X2 is a feedback control signal;

[0133] The first grounding circuit 201 is used to receive the power-on control signal and the first comparison signal (in... Figure 8 (referred to as In), when the power-on control signal is in the disabled state and the first comparison signal In is the first value, the first node X1 is connected to the ground terminal;

[0134] The second grounding circuit 202 is used to receive the inverted signal of the power-on control signal and the first comparison signal (denoted as the inverted comparison signal InF). When the power-on control signal is in the disabled state and the inverted signal InF of the first comparison signal is the first value, the output node X2 is connected to the ground terminal.

[0135] The third grounding circuit 203 is connected between the output node X2 and the grounding terminal. It is used to receive the power-on control signal and connect the output node X2 to the grounding terminal when the power-on control signal is enabled.

[0136] The cross-coupling circuit 204 is used to receive the first comparison signal In, the inverted signal InF of the first comparison signal, and the first power supply voltage Vpgsc; to perform cross-coupling processing on the comparison signal In and the inverted signal InF of the comparison signal, and to output the first power supply voltage Vpgsc to the first node X1 or the output node X2.

[0137] It should be noted that, as Figure 8 As shown, the power-on control signal received by the first grounding circuit 201 and the second grounding circuit 202 is specifically the first power-on control signal PwrOn, and the power-on control signal received by the third grounding circuit 203 is specifically the second power-on control signal PwrOnB.

[0138] It should also be noted that the first power-on control signal PwrOn and the second power-on control signal PwrOnB are an inverted pair of signals, and the first comparison signal In and the inverted comparison signal InF are also an inverted pair of signals. Therefore, as Figure 8 As shown, the level converter 1013 may further include a first NOT gate 205 and a second NOT gate 206; wherein:

[0139] The first NOT gate 205 is used to receive the first comparison signal In, perform inversion processing, and output the inverted comparison signal InF, which in turn provides the inverted comparison signal InF to the second grounding circuit 202 and the cross-coupling circuit 204.

[0140] The second NOT gate 206 is used to receive the first power-on control signal PwrOn, invert it, and output the second power-on control signal PwrOnB, which is then provided to the third grounding circuit 203.

[0141] As mentioned earlier, during power-up, the power-up control signal is enabled, and the level converter 1013 does not perform level conversion; its output is a fixed voltage, for example, a fixed logic 0. At this time, the second power-up control signal PwrOnB, which is enabled, controls the third grounding circuit 203 to perform a pull-down operation, pulling down the feedback control signal of the level converter 1013 output to 0. Simultaneously, the first power-up control signal PwrOn, which is enabled, prevents both the first grounding circuit 201 and the second grounding circuit 202 from performing pull-down operations. Regardless of the states of the first comparison signal In and the inverting comparison signal InF, the first grounding circuit 201 and the second grounding circuit 202 will not affect the state of the output node X2.

[0142] After power-on, the power-on control signal is in an enabled state. At this time, the second power-on control signal PwrOnB, also in an enabled state, shuts down the third grounding circuit 203, preventing it from pulling down the output of the level converter 1013. Simultaneously, the first power-on control signal PwrOn, also in an enabled state, turns on the first grounding circuit 201 and the second grounding circuit 202. For the first grounding circuit 201, if the first comparison signal is the first value, the first node X1 is pulled down to ground; if the first comparison signal is the second value, the first node X1 is not pulled down. For the second grounding circuit 202, if the inverting comparison signal is the first value, the output node X2 is pulled down to ground; if the inverting comparison signal is the second value, the output node X2 is not pulled down. Simultaneously, the cross-coupling circuit 204 performs cross-coupling amplification to ensure that the first node X1 and the output node X2 maintain a stable logic state.

[0143] Specifically, such as Figure 8 As shown, the first grounding circuit 201 includes the fifth transistor M5 and the sixth transistor M6, the second grounding circuit 202 includes the seventh transistor M7 and the eighth transistor M8, the third grounding circuit 203 includes the ninth transistor M9, and the cross-coupling circuit 204 includes the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13.

[0144] The first terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 receives the first comparison signal In, and the second terminal of the fifth transistor M5 is grounded. The control terminal of the sixth transistor M6 receives the first power-on control signal PwrOn. The first terminal of the seventh transistor M7 is connected to the second terminal of the eighth transistor M8. The control terminal of the seventh transistor M7 receives the inverted comparison signal InF, and the second terminal of the seventh transistor M7 is grounded. The control terminal of the eighth transistor M8 receives the first power-on control signal PwrOn.

[0145] The second terminal of the ninth transistor M9 is grounded, and the control terminal of the ninth transistor M9 receives the second power-on control signal PwrOnB;

[0146] The second terminal of the tenth transistor M10 and the second terminal of the eleventh transistor M11 both receive the first power supply voltage Vpgsc.

[0147] The first terminal of the tenth transistor M10 is connected to the second terminal of the twelfth transistor M12; the first terminal of the eleventh transistor M11 is connected to the second terminal of the thirteenth transistor M13.

[0148] The control terminal of the twelfth transistor M12 receives the first comparison signal; the control terminal of the thirteenth transistor M13 receives the inverted comparison signal.

[0149] The first terminal of the twelfth transistor M12, the first terminal of the sixth transistor M6, and the control terminal of the eleventh transistor M11 are connected, and the connection node is the first node X1.

[0150] The first terminal of the thirteenth transistor M13, the first terminal of the eighth transistor M8, the control terminal of the tenth transistor M10, and the first terminal of the ninth transistor M9 are connected, and the connection node is the output node X2.

[0151] It should be noted that for transistors M5 through M13, the control terminal can be the gate, the first terminal can be the drain, and the second terminal can be the source. Among them, transistors M5, M6, M7, M8, and M9 can be NMOS transistors, while transistors M10, M11, M12, and M13 can be PMOS transistors.

[0152] based on Figure 8 The circuit structure shown has a first value of 1 and a second value of 0. In other possible circuit structures, the first value could also be 0 and the second value could be 1.

[0153] During power-on, the first power-on control signal PwrOn is 0 and the second power-on control signal PwrOnB is 1, which controls the sixth transistor M6 and the eighth transistor M8 to disconnect and controls the ninth transistor M9 to turn on. As a result, the first grounding circuit 201 and the second grounding circuit 202 are not grounded, and the ninth transistor M9 pulls the output node X2 down to ground.

[0154] After power-on, the first power-on control signal PwrOn is 1, and the second power-on control signal PwrOnB is 0, controlling the sixth transistor M6 and the eighth transistor M8 to conduct, and controlling the ninth transistor M9 to turn off. At this time, the ninth transistor M9 no longer pulls down the output node X2. Instead, the first grounding circuit 201, the second grounding circuit 202, and the cross-coupling circuit 204 pull up one of the first node X1 and the output node X2 and pull down the other based on the first comparison signal In and the inverting comparison signal InF. The logic state of the feedback control signal output by the output node X2 is the same as that of the first comparison signal In, but the specific voltage values ​​of the two are different.

[0155] The high-level voltage of the first comparison signal In is the high-level voltage of the power supply of the first comparison circuit 1012, and the high-level voltage of the feedback control signal is the voltage of the first power supply voltage Vpgsc. This achieves level conversion, ensuring that the voltage domain of the feedback control signal matches that of the first transistor M1, thus preventing the first transistor M1 from being unable to be driven or from being damaged.

[0156] It should also be noted that the aforementioned Figure 5 A circuit diagram corresponding to a DLDO. In some other embodiments, the LDO can also be an ALDO. For example... Figure 9 or Figure 10 As shown, in the ALDO circuit, the feedback control circuit 101 includes:

[0157] The second feedback circuit 1014 is used to receive the target voltage Vdd2sc, perform voltage division on the target voltage Vdd2sc, and generate the second voltage V2.

[0158] The second comparator circuit 1015 is connected to the second feedback circuit 1014. The first input terminal of the second comparator circuit 1015 is used to receive the second voltage V2, the second output terminal of the second comparator circuit 1015 is used to receive the second reference voltage Vref2, the output terminal of the second comparator circuit 1015 is used to output a feedback control signal, and the output terminal of the second comparator circuit 1015 is connected to the control terminal of the first transistor M1. The power-on control signal is used to control whether the second comparator circuit 1015 outputs a feedback control signal based on the comparison result.

[0159] It should be noted that the second feedback circuit 1014 can be a resistor string, composed of multiple resistors connected in series. One end of the resistor string receives the target voltage Vdd2sc, and the other end is grounded. Depending on the actual requirements of the circuit, a specific connection node in the resistor string is selected as the output terminal of the second feedback circuit 1014 to output the second voltage V2. For example... Figure 9 or Figure 10As shown, the resistor string consists of two resistors connected in series, with the connection point between the first and second resistors serving as the output terminal. The second reference voltage Vref2 is a high-precision, high-stability reference voltage.

[0160] The second comparator circuit 1015 is essentially a comparator, typically operating in the protected zone. It compares the voltages at the non-inverting and inverting inputs to determine the voltage magnitude and outputs a logic level. For example, when the voltage at the non-inverting input is greater than that at the inverting output, it outputs logic 1; when the voltage at the inverting input is greater than that at the non-inverting input, it outputs logic 0.

[0161] It should also be noted that, such as Figure 9 or Figure 10 As shown, in ALDO, no level shifter is required; the output of the second comparator circuit 1015 is directly connected to the control terminal of the first transistor M1. The first input terminal of the second comparator circuit 1015 can be its positive input (+), and the second input terminal can be its inverting input (-). The second comparator circuit 1015 may also include a control terminal for receiving a power-on control signal, such as a first power-on control signal PwrOn or a second power-on control signal PwrOnB. During power-on, the power-on control signal is enabled, controlling the second comparator circuit 1015 to output a feedback control signal of the default state. After power-on, it outputs a feedback control signal of the corresponding state based on the comparison result of the second voltage V2 and the second reference voltage Vref2.

[0162] like Figure 9 As shown, the first transistor is an NMOS transistor, so the default state of the feedback control signal is logic 0. During power-on, the power-on protection circuit 102 pulls down the control terminal of the first transistor M1 to ground.

[0163] like Figure 10 As shown, the first transistor is a PMOS transistor, so the default state of the feedback control signal is logic 1. During power-on, the power-on protection circuit 102 pulls up the control terminal of the first transistor M1 to logic 1.

[0164] It should also be noted that the difference between DLDO and ALDO lies not only in the presence or absence of a level converter LS and a comparator circuit, but also in their specific operating modes, other circuit components, and control methods. The accompanying drawings and related descriptions of the embodiments disclosed herein are only simplified representations of their basic operating modes. The drawings do not show the complete circuit structure of the LDO circuit, nor do they show the specific components of each circuit structure in detail. For details not shown, reference can be made to the general implementation methods in the art for understanding and execution.

[0165] In summary, this disclosure provides an LDO circuit, involving the circuit design and power-on timing control when using thin-oxide transistors as the output transistor of the LDO circuit. It is applicable not only to ALDOs but also to DLDOs. By using thin-oxide transistors as the output transistors, the problem of insufficient driving capability and large area associated with thick-oxide transistors in traditional LDO output stages is solved, effectively reducing the size of the output transistor and decreasing parasitic capacitance. Simultaneously, the feedback control circuit is controlled, and the second transistor M2 and power-on protection circuit 102 address the SOA problem during power-on. Upon power-on, the second transistor M2 clamps the LDO circuit's output voltage to the power supply voltage Vdd2c. The gate of the output transistor is pulled down to 0 by the power-on protection circuit 102 until the gate control voltage (dominate voltage) is established. This eliminates the need for complex power-on control timing, meeting the requirements of small area and high speed, and effectively avoiding the SOA problem caused by a large gate-source voltage Vgs during output transistor power-on.

[0166] In another embodiment of this disclosure, a memory is also provided, including the LDO circuit 10 of the foregoing embodiments.

[0167] It should be noted that the memory can be DRAM. For DRAM, it can not only conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6. No restrictions are imposed here.

[0168] It should also be noted that there are a large number of internal power supplies in LPDDR5 and LPDDR6. Based on the solution of the present disclosure embodiment, the area of ​​the memory can be significantly saved because the area of ​​the LDO circuit 10 can be reduced.

[0169] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0170] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0171] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0172] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0173] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0174] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0175] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0176] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A low-dropout linear regulator (LDO) circuit, characterized in that, include: A first transistor, a second transistor, and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold. The first terminal of the first transistor and the second terminal of the second transistor are connected to receive the power supply voltage; the second terminal of the first transistor and the first terminal of the second transistor are connected to output the target voltage. The control terminal of the second transistor receives a power-on control signal. Based on the control of the power-on control signal, the second transistor is used to output a target voltage during the power-on process. The feedback control circuit is connected to the control terminal of the first transistor. The feedback control circuit is used to receive the power-on control signal, and based on the power-on control signal, control the first transistor to disconnect during the power-on process, and control the first transistor to output the target voltage after the power-on is completed. The power-on control signal is enabled during the power-on process and disabled during other periods. The feedback control circuit includes: A first feedback circuit is used to receive the target voltage, perform voltage division on the target voltage, and generate a first voltage. A first comparison circuit is connected to the first feedback circuit. The first input terminal of the first comparison circuit is used to receive a first reference voltage, and the second input terminal of the first comparison circuit is used to receive the first voltage. The output terminal of the first comparison circuit is used to output a first comparison signal. A level converter, connected to the first comparator circuit, is used to receive the first comparison signal and the power-on control signal. When the power-on control signal is in an enabled state, it performs voltage conversion on the first comparison signal and outputs a feedback control signal to control the on / off state of the first transistor. When the power-on control signal is in an enabled state, it outputs the default state feedback control signal to control the first transistor to turn off.

2. The LDO circuit according to claim 1, characterized in that, The second transistor is a PMOS transistor, used to clamp the target voltage to the power supply voltage during power-on.

3. The LDO circuit according to claim 1, characterized in that, The LDO circuit also includes a power-on protection circuit; the control terminal of the first transistor is connected to the power-on protection circuit. The power-on protection circuit is used to receive the power-on control signal and, based on the power-on control signal, control the first transistor to disconnect during the power-on process.

4. The LDO circuit according to claim 3, characterized in that, The power-on protection circuit includes a third transistor; The first terminal of the third transistor is connected to the control terminal of the first transistor, the second terminal of the third transistor is connected to a preset power supply, and the control terminal of the third transistor receives the power-on control signal.

5. The LDO circuit according to claim 4, characterized in that, The power-on protection circuit further includes at least one fourth transistor; when there are multiple fourth transistors, the multiple fourth transistors are connected in series. The second terminal of the third transistor is connected to the first terminal of the first fourth transistor, and the second terminal of the last fourth transistor is connected to the preset power supply. The control terminal of each of the fourth transistors receives the power-on control signal.

6. The LDO circuit according to claim 5, characterized in that, The first transistor, the third transistor, and the fourth transistor are all NMOS transistors, and the second transistor is a PMOS transistor; the power-on control signal includes a first power-on control signal and a second power-on control signal, and the first power-on control signal and the second power-on control signal are a pair of inverted signals; The control terminal of the second transistor receives the first power-on control signal, and the control terminals of the third transistor and each of the fourth transistors receive the second power-on control signal.

7. The LDO circuit according to claim 5, characterized in that, The gate dielectric layer thickness of the third transistor is greater than the preset threshold, and the gate dielectric layer thickness of the fourth transistor is less than the preset threshold.

8. The LDO circuit according to any one of claims 1-7, characterized in that, The level converter includes: a cross-coupled circuit, a first grounding circuit, a second grounding circuit, and a third grounding circuit; the cross-coupled circuit is connected to the first grounding circuit at a first node, and to the second grounding circuit and the third grounding circuit at an output node, wherein the signal at the output node is the feedback control signal; The first grounding circuit is used to receive the power-on control signal and the first comparison signal, and when the power-on control signal is in an enabled state and the first comparison signal is a first value, it connects the first node to the grounding terminal. The second grounding circuit is used to receive the power-on control signal and the inverted signal of the first comparison signal. When the power-on control signal is in an enabled state and the inverted signal of the first comparison signal is a first value, the output node is connected to the grounding terminal. The third grounding circuit is connected between the output node and the grounding terminal to receive the power-on control signal and to connect the output node to the grounding terminal when the power-on control signal is enabled. The cross-coupling circuit is used to receive the first comparison signal, the inverted signal of the first comparison signal, and the first power supply voltage; to perform cross-coupling processing on the comparison signal and the inverted signal of the comparison signal, and to output the first power supply voltage to the first node or the output node.

9. A memory, characterized in that, It includes at least one LDO circuit as described in any one of claims 1-8.

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