A data synchronization circuit and apparatus

Abstract

The application provides a data synchronization circuit and device, which comprises a signal input module, a signal modulation module, a demodulation module and a fast push-pull logic module; the signal input module is used for acquiring input data and a clock signal; the signal modulation module is used for modulating the input data based on the clock signal to generate a modulation signal; the fast push-pull logic module is used for fast push-pull based on the input data and the clock signal to acquire a fast push-pull signal; the demodulation module comprises a Schmitt trigger; the demodulation module is used for preliminarily demodulating the modulation signal to acquire a preliminary demodulation signal, and then push-pulling the preliminary demodulation signal based on the fast push-pull signal to acquire a push-pull modulation signal; and the Schmitt trigger is used for filtering the push-pull modulation signal and outputting a terminal demodulation signal. The application provides a data synchronization circuit and device, which can reduce signal delay and pulse width distortion phenomenon, guarantee the stability and reliability of a timing logic circuit, and reduce data errors and circuit malfunction problems.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital information transmission, in particular to a data synchronization circuit and device. BACKGROUND

[0002] In the field of electronic circuit technology, especially in the timing logic circuit, data generally only changes when the clock edge comes. For synchronous logic circuit, all the clock signals of the internal control circuit are from the same reference clock source, and the data will change only when the unified clock edge triggers. In asynchronous logic circuit, the dynamic change of data may be driven by different clock sources, so the phase relationship between input data and clock is completely irrelevant. Thus when the clock edge comes, the input data may be in the process of changing, which makes the output of asynchronous logic circuit produce indefinite state, affecting the stability and reliability of the circuit.

[0003] In addition to the correctness of the output logic level, two indicators are also valued. One is the delay of the output signal compared with the input signal. For example, the time difference between the rising edge of the output signal and the rising edge of the input signal. The other is the pulse width distortion, which is the difference between the pulse width of the output signal and the pulse width of the input signal, which can also be defined as the difference between the rising edge delay time and the falling edge delay time. In the prior art, when data is transmitted in different clock domains, in order to avoid indefinite state, the conventional asynchronous data synchronization method is often used, that is, the double synchronization-two sampling method is used to reduce the probability of indefinite state. In the process of two sampling method, the worst case has a delay of nearly 2 clock cycles. The maximum pulse width distortion is close to 1 clock cycle. For some fields such as high-speed signal processing, real-time communication and precision measurement, which have very high requirements on time sensitivity, this processing method will cause delay and pulse width distortion, affect the stability and reliability of the timing logic circuit, and cause data errors, circuit malfunctions and other problems. SUMMARY

[0004] The present application aims to provide a data synchronization circuit and device to solve the above technical problems, reduce signal delay and pulse width distortion, ensure the stability and reliability of the timing logic circuit, and reduce data errors, circuit malfunctions and other problems.

[0005] In order to solve the above technical problems, the present application provides a data synchronization circuit, which comprises a signal input module, a signal modulation module, a demodulation module and a fast push-pull logic module; wherein:

[0006] The signal input module is used to obtain input data and clock signals;

[0007] The signal modulation module is used to modulate the input data based on the clock signal to generate a modulated signal;

[0008] The fast push-pull logic module is configured to perform fast push-pull based on the input data and the clock signal, and obtain a fast push-pull signal;

[0009] The demodulation module comprises a Schmitt trigger;

[0010] The demodulation module is configured to perform preliminary demodulation on the modulated signal, obtain a preliminary demodulation signal, and then push-pull the preliminary demodulation signal based on the fast push-pull signal, to obtain a push-pull modulated signal; and the Schmitt trigger is configured to filter the push-pull modulated signal and output a terminal demodulation signal.

[0011] In the above scheme, the input data and the clock signal are input into the fast push-pull logic module to generate a fast push-pull signal, so that the modulated signal can be fast pushed and pulled; the fast push-pull logic module can avoid the situation that the preliminary demodulation signal presents a first falling edge that is fast and a last rising edge that is slow, thereby preventing the terminal demodulation signal processed by the Schmitt trigger from presenting a problem of a small rising edge delay and a large falling edge delay, effectively reducing the delay of the terminal demodulation signal, and suppressing the pulse width distortion phenomenon, so as to realize accurate synchronization of data, guarantee the stability and reliability of the timing logic circuit, and reduce the occurrence of data errors and circuit misoperation problems.

[0012] Further, the signal modulation module comprises a first inverter and a first NOR gate;

[0013] The first inverter is configured to convert the input data into logic state inversion data, and transmit the logic state inversion data to the first NOR gate;

[0014] The first NOR gate is configured to perform NOR operation on the logic state inversion data based on the clock signal, and generate a modulated signal.

[0015] In the above scheme, the first NOR gate performs NOR operation: when the input data is at a low level, the modulated signal after being modulated by the first NOR gate is at a low level state; and when the input data is at a high level, the modulated signal after being modulated by the first NOR gate is an inverse of the clock signal.

[0016] Further, the demodulation module comprises a narrow pulse module and a filter module;

[0017] The narrow pulse module is configured to perform preliminary demodulation and narrow pulse on the modulated signal, to obtain a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filter module;

[0018] The Schmitt trigger is arranged in the filter module;

[0019] The filter module is configured to push-pull the preliminary demodulation signal based on the fast push-pull signal, and output a terminal demodulation signal through the Schmitt trigger.

[0020] In the scheme, the pulse narrowing module can perform pulse width compression processing on the modulation signal to obtain a preliminary demodulation signal with a clock frequency of 2 times; and the filter module can make the waveform of the signal smoother. Irregular signal waveform can be made more regular, signal jitter can be reduced, and signal stability can be improved.

[0021] Further, the pulse narrowing module includes a delay device and a second NOR gate.

[0022] The delay device is configured to delay the modulation signal to obtain a delayed modulation signal, and transmit the delayed modulation signal to the second NOR gate.

[0023] The second NOR gate is configured to perform NOR operation on the modulation signal and the delayed modulation signal to generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filter module.

[0024] In the scheme, the delay device cooperates with the modulation signal, the second NOR gate performs NOR operation on the modulation signal and the delayed modulation signal to realize pulse width compression processing, and a preliminary demodulation signal with a clock frequency of 2 times is obtained; the delay device has a signal timing adjustment function, and by delaying the modulation signal, the time correlation of the signal is changed, and the timing of each signal in the circuit is accurately controlled.

[0025] Further, the filter module includes a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor, and a second inverter.

[0026] The gate of the second PMOS tube is connected to the output end of the second NOR gate, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the source of the second PMOS tube is connected to a power supply; the gate of the first NMOS tube is connected to the output end of the second NOR gate, and the source of the first NMOS tube is connected to ground; the first NMOS tube and the second PMOS tube are configured to perform asymmetric charging and discharging on the preliminary demodulation signal to obtain a push-pull front signal, and transmit the push-pull front signal to the fast push-pull logic module, so that the fast push-pull logic module pushes and pulls the push-pull front signal to obtain a push-pull modulation signal, and transmits the push-pull modulation signal to the Schmitt trigger.

[0027] The first access end of the current limiting resistor is connected to the source of the second PMOS tube, the second access end of the current limiting resistor is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is configured to limit the charging current of the voltage stabilizing capacitor.

[0028] The first access end of the voltage stabilizing capacitor is connected with the second access end of the current limiting resistor and the input end of the Schmitt trigger, the second access end of the voltage stabilizing capacitor is connected with the ground, and the voltage stabilizing capacitor is used for stabilizing the push-pull front signal.

[0029] The second inverter is used for reversing the logic state of the push-pull modulation signal filtered by the Schmitt trigger, so as to output a terminal demodulation signal.

[0030] In the above scheme, the asymmetric charging and discharging changes the characteristics of the push-pull front signal by controlling the charging and discharging speed and path of the voltage stabilizing capacitor, so as to adjust the signal waveform, reduce the pulse width distortion, and realize accurate data synchronization.

[0031] Further, the asymmetric charging and discharging mode has two modes of slow charging and fast discharging and fast charging and slow discharging.

[0032] The slow charging and fast discharging mode is specifically: in the charging stage, the gate-source voltage of the first PMOS transistor is greater than the opening voltage of the first PMOS transistor, the first PMOS transistor is in a relatively cut-off state, and the power supply current slowly charges the voltage stabilizing capacitor through the current limiting resistor, so that the voltage of the voltage stabilizing capacitor slowly rises; in the discharging stage, the gate-source voltage of the first NMOS transistor is greater than the opening voltage of the first NMOS transistor, the first NMOS transistor is rapidly turned on, so that the charge stored on the voltage stabilizing capacitor can be quickly released through the first NMOS transistor, the voltage of the voltage stabilizing capacitor rapidly drops, and the slow charging and fast discharging push-pull front signal is obtained.

[0033] The fast charging and slow discharging mode is specifically: in the charging stage, the gate-source voltage of the first PMOS transistor is less than the opening voltage of the first PMOS transistor, the first PMOS transistor is rapidly turned on, the power supply current quickly flows to the voltage stabilizing capacitor, and the voltage of the voltage stabilizing capacitor rapidly rises; in the discharging stage, the gate-source voltage of the first NMOS transistor is less than the opening voltage of the first NMOS transistor, the first NMOS transistor is in a relatively cut-off state, the voltage stabilizing capacitor is discharged through the current limiting resistor, the discharging current is small, and the voltage of the voltage stabilizing capacitor slowly drops, and the fast charging and slow discharging push-pull front signal is obtained.

[0034] In the above scheme, the slow charging and fast discharging makes the push-pull front signal present the characteristics of slow rising edge and fast falling edge. If no such processing is added, the push-pull front signal after the Schmitt trigger may present small rising edge delay and large falling edge delay, resulting in the pulse width of the terminal demodulation signal being larger than that of the input data; and the slow charging and fast discharging can improve this condition, reduce the pulse width distortion, and ensure the accuracy of data transmission; the fast charging and slow discharging makes the push-pull front signal present the characteristics of fast rising edge and slow falling edge. If no such processing is added, the push-pull front signal after the Schmitt trigger may present large rising edge delay and small falling edge delay, resulting in the pulse width of the terminal demodulation signal being larger than that of the input data; and the fast charging and slow discharging can improve this condition, reduce the pulse width distortion, and ensure the accuracy of data transmission.

[0035] Further, the fast push-pull logic module comprises an AND gate and a first PMOS tube.

[0036] The AND gate is used for AND operation of the clock signal and the input data, obtaining a preliminary push-pull signal, and transmitting the preliminary push-pull signal to the first PMOS tube.

[0037] The drain of the first PMOS tube is connected to the input end of the Schmitt trigger, the gate of the first PMOS tube is connected to the output end of the AND gate, and the source of the first PMOS tube is connected to the power supply; the first PMOS tube is used for fast push-pull of the potential of the push-pull front signal, obtaining a push-pull modulation signal, and transmitting the push-pull modulation signal to the Schmitt trigger.

[0038] In the above scheme, after the fast push-pull module is introduced to fast push-pull the push-pull front signal, the pulse width distortion problem caused by asymmetric charging and discharging can be improved, and excessive pulse width distortion can be avoided.

[0039] Further, the fast push-pull has two modes of fast pull-up and fast pull-down.

[0040] The fast pull-up mode is specifically that the first PMOS tube is used for pulling up the potential of the push-pull front signal to the power supply voltage, obtaining a pull-up push-pull modulation signal, and transmitting the push-pull modulation signal to the Schmitt trigger.

[0041] The fast pull-down mode is specifically that the first PMOS tube is used for pulling down the potential of the push-pull front signal to the ground potential, obtaining a pull-down push-pull modulation signal, and transmitting the push-pull modulation signal to the Schmitt trigger.

[0042] In the above scheme, in the process of slow charging and fast discharging, if only the second PMOS tube and the current limiting resistor are used to charge the voltage stabilizing capacitor, the rising edge of the push-pull modulation signal will be very slow. In the fast pull-up mode, the first PMOS tube is used to pull up the push-pull modulation signal, and when the gate-source voltage of the first PMOS tube is less than the opening voltage, the first PMOS tube is turned on. At this time, the first PMOS tube can quickly pull up the potential of the pre-push-pull signal to the power supply voltage, and the pull-up push-pull modulation signal is obtained, which avoids the problem of pulse width distortion caused by the slow rising edge of the push-pull modulation signal. In the process of fast charging and slow discharging, there is a problem that the falling edge of the pre-push-pull signal is not fast enough. The fast pull-down can ensure that the signal quickly falls to the low level, avoid the adverse effects of the slow falling edge of the pre-push-pull signal on the pulse width distortion, and ensure the accuracy of data transmission and the stability of signal processing.

[0043] The application provides a data synchronization device, which comprises a shell, a data synchronization circuit provided in the shell, a data input interface, a data output interface and a power supply interface provided on the shell, a signal input module electrically connected to the data input interface, a demodulation module electrically connected to the data output interface, and a fast push-pull logic module electrically connected to the power supply interface.

[0044] The data synchronization device provided by the above scheme has a simple structure, and in actual application, only the signal input module needs to be connected to the data input interface, the demodulation module needs to be connected to the data output interface, and the fast push-pull logic module needs to be powered on through the power supply interface, so that the data synchronization can be stably and reliably completed, the delay of the terminal demodulation signal is effectively reduced, the pulse width distortion phenomenon is inhibited, the precise synchronization of data is realized, the stability and reliability of the time sequence logic circuit are ensured, and the occurrence of data errors and circuit misoperation problems is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A data synchronization circuit structure diagram is provided for an embodiment of the application.

[0046] Figure 2 A circuit structure diagram of a data synchronization circuit is provided for an embodiment of the application.

[0047] Figure 3 A signal waveform diagram of a data synchronization circuit is provided for an embodiment of the application.

[0048] Figure 4 A signal waveform diagram of a data synchronization circuit without a fast push-pull module is provided for an embodiment of the application. DETAILED DESCRIPTION

[0049] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0050] Please refer to Figure 1 The embodiment provides a data synchronization circuit, and a specific architecture thereof can be referred to Figure 1 , comprising:

[0051] The signal input module is configured to obtain input data and a clock signal.

[0052] The signal modulation module is configured to modulate the input data based on the clock signal to generate a modulation signal.

[0053] The fast push-pull logic module is configured to perform fast push-pull based on the input data and the clock signal to obtain a fast push-pull signal.

[0054] The demodulation module comprises a Schmitt trigger. The demodulation module is configured to preliminarily demodulate the modulation signal to obtain a preliminary demodulation signal, and then push-pull the preliminary demodulation signal based on the fast push-pull signal to obtain a push-pull modulation signal. The Schmitt trigger is configured to filter the push-pull modulation signal and output a terminal demodulation signal.

[0055] The embodiment provides a data synchronization circuit, and proposes a new data synchronization method to provide smaller delay and data pulse width distortion. The input data and the clock signal are input into the fast push-pull logic module together to generate a fast push-pull signal, so that the modulation signal can be fast pushed and pulled. The fast push-pull logic module can avoid the situation that the preliminary demodulation signal presents a first falling edge fast and a last rising edge slow, thereby preventing the terminal demodulation signal after being processed by the Schmitt trigger from having a smaller rising edge delay and a larger falling edge delay, effectively reducing the delay of the terminal demodulation signal, and suppressing the pulse width distortion phenomenon, so as to realize accurate synchronization of data, guarantee the stability and reliability of the timing logic circuit, and reduce the occurrence of data errors and circuit misoperation problems.

[0056] Please refer to Figure 2 , which is a circuit structure diagram of the data synchronization circuit provided by the embodiment. The signal modulation module comprises a first inverter and a first NAND gate.

[0057] The first inverter is configured to convert the input data into logic state inversion data and transmit the logic state inversion data to the first NAND gate.

[0058] The first NOR gate is used for performing NOR operation on the logic state inversion data based on the clock signal and generating a modulation signal.

[0059] In the embodiment, the input data is first modulated by the clock in OOK mode, and the OOK modulation can be implemented by a NOR gate or an AND gate. In the embodiment, the NOR gate is used, and the first NOR gate performs NOR operation. When the input data is at a low level, the modulation signal after the modulation of the first NOR gate is at a low level. When the input data is at a high level, the modulation signal after the modulation of the first NOR gate is the inverse of the clock signal, thereby solving the problem of data synchronization. The use of the NOR gate can effectively reduce the delay, so that the circuit can detect the level of the input data once every half clock signal period.

[0060] Further, the demodulation module comprises a narrow pulse module and a filter module.

[0061] The narrow pulse module is configured to preliminarily demodulate and narrow the pulse of the modulation signal to obtain a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filter module.

[0062] The Schmitt trigger is arranged in the filter module.

[0063] The filter module is configured to push-pull the preliminary demodulation signal based on the fast push-pull signal and output a terminal demodulation signal through the Schmitt trigger.

[0064] In the embodiment, the narrow pulse module can perform pulse width compression processing on the modulation signal to obtain a preliminary demodulation signal with a clock frequency of 2 times. The filter module can make the waveform of the signal more smooth. Irregular signal waveforms can be made more regular, lower charging waveforms are filtered out, signal jitter is reduced, a square wave signal output is obtained, and signal stability is improved. The terminal demodulation signal is only changed when the clock signal is at a low level, so that when the terminal demodulation signal is collected at the rising edge of the clock signal, indefinite state errors do not occur.

[0065] Further, the narrow pulse module comprises a delay device and a second NOR gate.

[0066] The delay device is configured to delay the modulation signal to obtain a delayed modulation signal, and transmit the delayed modulation signal to the second NOR gate.

[0067] The second NOR gate is configured to perform NOR operation on the modulation signal and the delayed modulation signal to generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filter module.

[0068] In the embodiment, the delay device cooperates with the modulation signal, the second NOR gate performs NOR operation on the modulation signal and the delayed modulation signal, realizes pulse width compression processing, and obtains a preliminary demodulation signal of a narrow pulse with a clock frequency of 2 times; the delay device has a signal timing adjustment function, and realizes accurate regulation of the timing of each signal in the circuit by delaying the modulation signal and changing the time correlation of the signal.

[0069] Further, the filter module comprises a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor and a second inverter.

[0070] The gate of the second PMOS tube is connected to the output end of the second NOR gate, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the source of the second PMOS tube is connected to a power supply; the gate of the first NMOS tube is connected to the output end of the second NOR gate, and the source of the first NMOS tube is connected to the ground; the first NMOS tube and the second PMOS tube are used for asymmetrically charging and discharging the preliminary demodulation signal, obtaining a push-pull front signal, and transmitting the push-pull front signal to the fast push-pull logic module, so that the fast push-pull logic module pushes and pulls the push-pull front signal to obtain a push-pull modulation signal, and transmits the push-pull modulation signal to the Schmitt trigger;

[0071] The first access end of the current limiting resistor is connected to the source of the second PMOS tube, the second access end of the current limiting resistor is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is used for limiting the charging current of the voltage stabilizing capacitor;

[0072] The first access end of the voltage stabilizing capacitor is connected to the second access end of the current limiting resistor and the input end of the Schmitt trigger, and the second access end of the voltage stabilizing capacitor is connected to the ground; the voltage stabilizing capacitor is used for stabilizing the push-pull front signal;

[0073] The second inverter is used for inverting the logic state of the push-pull modulation signal filtered by the Schmitt trigger to output a terminal demodulation signal.

[0074] In the embodiment, the first NMOS tube and the second PMOS tube constitute an inverter, perform asymmetric charging and discharging, change the characteristics of the push-pull front signal by controlling the charging and discharging speed and path of the voltage stabilizing capacitor, and play a role of adjusting the signal waveform, reducing the pulse width distortion, and realizing accurate synchronization of data.

[0075] Further, the asymmetric charging and discharging mode has two modes of slow charging and fast discharging and fast charging and slow discharging.

[0076] The slow charging and fast discharging mode specifically includes: in the charging phase, the gate-source voltage of the first PMOS is greater than the opening voltage of the first PMOS, the first PMOS is in a relatively cut-off state, the power current slowly charges the voltage stabilizing capacitor through the current limiting resistor, and the voltage of the voltage stabilizing capacitor slowly rises; in the discharging phase, the gate-source voltage of the first NMOS is greater than the opening voltage of the first NMOS, the first NMOS is rapidly turned on, so that the charge stored on the voltage stabilizing capacitor can be quickly released through the first NMOS, the voltage of the voltage stabilizing capacitor rapidly decreases, and the slow charging and fast discharging push-pull front signal is obtained.

[0077] The fast charging and slow discharging mode specifically includes: in the charging phase, the gate-source voltage of the first PMOS is less than the opening voltage of the first PMOS, the first PMOS is rapidly turned on, the power current quickly flows to the voltage stabilizing capacitor, and the voltage of the voltage stabilizing capacitor rapidly rises; in the discharging phase, the gate-source voltage of the first NMOS is less than the opening voltage of the first NMOS, the first NMOS is in a relatively cut-off state, the voltage stabilizing capacitor is discharged through the current limiting resistor, the discharging current is small, and the voltage of the voltage stabilizing capacitor slowly decreases, and the fast charging and slow discharging push-pull front signal is obtained.

[0078] In the embodiment, the slow charging and fast discharging makes the push-pull front signal have the characteristics of slow rising edge and fast falling edge. If this processing is not added, the rising edge of the push-pull front signal may be delayed small and the falling edge may be delayed large after the Schmitt trigger, so that the pulse width of the terminal demodulation signal is greater than that of the input data; and the slow charging and fast discharging can improve this condition, reduce the pulse width distortion, and ensure the accuracy of data transmission; the fast charging and slow discharging makes the push-pull front signal have the characteristics of fast rising edge and slow falling edge. If this processing is not added, the rising edge of the push-pull front signal may be delayed large and the falling edge may be delayed small after the Schmitt trigger, so that the pulse width of the terminal demodulation signal is greater than that of the input data; and the fast charging and slow discharging can improve this condition, reduce the pulse width distortion, and ensure the accuracy of data transmission.

[0079] Further, the fast push-pull logic module includes an AND gate and a first PMOS.

[0080] The AND gate is used for performing AND operation on the clock signal and the input data, obtaining a preliminary push-pull signal, and transmitting the preliminary push-pull signal to the first PMOS.

[0081] The drain of the first PMOS is connected to the input end of the Schmitt trigger, the gate of the first PMOS is connected to the output end of the AND gate, and the source of the first PMOS is connected to the power supply; the first PMOS is used for quickly pushing and pulling the potential of the push-pull front signal, obtaining a push-pull modulation signal, and transmitting the push-pull modulation signal to the Schmitt trigger.

[0082] In the embodiment, since the AND gate is used to perform AND operation on the clock signal and the input data, if the input data has become low level at this time, the preliminary push-pull signal will become low level following the falling edge of the clock signal when the clock signal changes from high level to low level; after the preliminary push-pull signal becomes low level, the first PMOS transistor will become conductive, at this time, the push-pull modulation signal is pulled high to high level; if the fast push-pull logic module is not added, the push-pull modulation signal without the fast push-pull logic module rises slowly and falls quickly, and the terminal demodulation signal after the Schmitt trigger will have the phenomenon that the rising edge delay is small and the falling edge delay is large, the pulse width of the terminal demodulation signal will be greater than the pulse width of the input data, resulting in the increase of the pulse width distortion; and after the fast push-pull module is introduced to quickly push and pull the pre-push-pull signal, the pulse width distortion problem caused by the asymmetric charging and discharging can be improved, and the excessive pulse width distortion can be avoided.

[0083] Further, the fast push-pull has two modes of fast pull-up and fast pull-down;

[0084] The fast pull-up mode specifically is that the first PMOS transistor is used to pull the potential of the pre-push-pull signal to the power supply voltage to obtain the pull-up push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

[0085] The fast pull-down mode specifically is that the first PMOS transistor is used to pull the potential of the pre-push-pull signal to the ground potential to obtain the pull-down push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

[0086] In the embodiment, in the process of slow charging and fast discharging, if only the second PMOS transistor and the current limiting resistor are used to charge the voltage stabilizing capacitor, the rising edge of the push-pull modulation signal will be very slow. When the fast pull-up mode is used, the first PMOS transistor pulls up the push-pull modulation signal, when the gate-source voltage of the first PMOS transistor is less than the opening voltage thereof, the first PMOS transistor is conductive, at this time, the first PMOS transistor can quickly pull the potential of the pre-push-pull signal to the power supply voltage to obtain the pull-up push-pull modulation signal, and the pulse width distortion problem caused by the slow rising edge of the pre-push-pull signal is avoided; in the process of fast charging and slow discharging, there is a problem that the falling edge of the pre-push-pull signal is not fast enough, the fast pull-down can quickly pull down the pre-push-pull signal to low level, the adverse effects caused by the slow falling edge of the pre-push-pull signal are avoided, and the accuracy of data transmission and the stability of signal processing are ensured; after the fast push-pull, the terminal demodulation signal is reduced from 2 period delay to 0.5 period delay.

[0087] Please refer to Figure 3It is a signal waveform diagram of a data synchronization circuit provided by the embodiment, and the embodiment generates the signal waveform diagram in the fast pull-up mode in the fast push-pull; in the diagram, data_in is input data, clk is a clock signal, a is a modulation signal, b is a preliminary demodulation signal, c is a preliminary push-pull signal, d is a push-pull modulation signal, and data_out is a terminal demodulation signal; Figure 4 It is a signal waveform diagram without the fast push-pull logic module, in which data_in is input data, clk is a clock signal, a is a modulation signal, b is a preliminary demodulation signal, c is a preliminary push-pull signal, d is a push-pull modulation signal, and data_out is a terminal demodulation signal; by comparing Figure 4 and Figure 3 It is found that only the last edge signals of the push-pull modulation signal and the terminal demodulation signal are different; Figure 3 After the fast pull-up mode in the fast push-pull is adopted, the maximum delay and the pulse width distortion of the terminal demodulation signal data_out are both 1 / 2 clock period, which achieves the purpose of effectively reducing the delay of the terminal demodulation signal and suppressing the pulse width distortion phenomenon.

[0088] Further, the embodiment provides a data synchronization device, and the data synchronization circuit device includes a shell, the shell is provided with the above-mentioned data synchronization circuit; the shell is provided with a data input interface, a data output interface and a power supply interface; the data input interface is electrically connected with the signal input module, the data output interface is electrically connected with the demodulation module, and the power supply interface is electrically connected with the fast push-pull logic module.

[0089] The data synchronization device provided in the embodiment has a simple structure, and in actual application, only the signal input module needs to be connected through the data input interface, the demodulation module needs to be connected through the data output interface, and the fast push-pull logic module needs to be powered through the power supply interface, so that the data synchronization can be stably and reliably completed, the delay of the terminal demodulation signal is effectively reduced, the pulse width distortion phenomenon is suppressed, the precise synchronization of data is realized, the stability and reliability of the time sequence logic circuit are ensured, and the occurrence of data errors and circuit misoperation problems is reduced.

[0090] The embodiment can be applied to the transmission scene of motor PWM driving signals in an isolation chip. Since the PWM signals are closely related to the dead time, and the dead time directly affects the energy loss and efficiency in the motor driving process. At the same time, the pulse width distortion plays a key role in the accuracy of motor control. Therefore, reducing the delay of the PWM signal in the transmission process and reducing the pulse width distortion phenomenon is crucial for optimizing the motor driving performance, improving the overall energy efficiency of the motor system, and achieving accurate motor control. The embodiment provides a data synchronization circuit, effectively solves the problems of signal delay and pulse width distortion, improves the accuracy of motor control, reduces energy loss, provides reliable protection for efficient and stable operation of the motor, and has wide application prospect and obvious practical value.

[0091] The above is the preferred embodiment of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, several improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A data synchronization circuit, characterized by, The signal input module, the signal modulation module, the demodulation module and the fast push-pull logic module are included. The signal input module is used for acquiring input data and a clock signal. The signal modulation module includes a first inverter and a first NOR gate. The first inverter is used for converting the input data into logic state inversion data and transmitting the logic state inversion data to the first NOR gate. The first NOR gate is used for performing NOR operation on the logic state inversion data based on the clock signal and generating a modulation signal. The fast push-pull logic module is used for performing fast push-pull based on the input data and the clock signal and acquiring a fast push-pull signal. The demodulation module includes a narrowing pulse module and a filtering module. The narrowing pulse module includes a delay device and a second NOR gate. The delay device is used for delaying the modulation signal and acquiring a delayed modulation signal, and transmitting the delayed modulation signal to the second NOR gate. The second NOR gate is used for performing NOR operation on the modulation signal and the delayed modulation signal, generating a preliminary demodulation signal, and transmitting the preliminary demodulation signal to the filtering module. A Schmitt trigger is arranged in the filtering module. The filtering module is used for pushing and pulling the preliminary demodulation signal based on the fast push-pull signal and outputting a terminal demodulation signal through the Schmitt trigger.

2. A data synchronization circuit according to claim 1, characterized in that The filtering module includes a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor and a second inverter. The gate of the second PMOS tube is connected to the output end of the second NOR gate, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the source of the second PMOS tube is connected to a power supply. The gate of the first NMOS tube is connected to the output end of the second NOR gate, and the source of the first NMOS tube is connected to the ground. The first NMOS tube and the second PMOS tube are used for performing asymmetric charging and discharging on the preliminary demodulation signal, acquiring a pre-push-pull signal, and transmitting the pre-push-pull signal to the fast push-pull logic module, so that the fast push-pull logic module pushes and pulls the pre-push-pull signal, acquires a push-pull modulation signal, and transmits the push-pull modulation signal to the Schmitt trigger. The first access end of the current limiting resistor is connected to the drain of the second PMOS tube, the second access end of the current limiting resistor is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is used for limiting the charging current of the voltage stabilizing capacitor.

3. A data synchronization circuit according to claim 2, wherein, The first access end of the voltage stabilizing capacitor is connected to the second access end of the current limiting resistor and the input end of the Schmitt trigger, and the second access end of the voltage stabilizing capacitor is connected to the ground. The second inverter is used for inverting the logic state of the push-pull modulation signal filtered by the Schmitt trigger to output a terminal demodulation signal. The asymmetric charging and discharging mode has two modes of slow charging and fast discharging and fast charging and slow discharging. The slow charging and fast discharging mode is specifically: in the charging phase, the gate-source voltage of the first PMOS tube is greater than the opening voltage of the first PMOS tube, the first PMOS tube is in a relatively cut-off state, the power supply current slowly charges the voltage stabilizing capacitor through the current limiting resistor, and the voltage of the voltage stabilizing capacitor slowly rises; in the discharging phase, the gate-source voltage of the first NMOS tube is greater than the opening voltage of the first NMOS tube, the first NMOS tube is quickly turned on, the charge stored on the voltage stabilizing capacitor can be quickly released through the first NMOS tube, the voltage of the voltage stabilizing capacitor quickly drops, and a slow charging and fast discharging push-pull front signal is obtained. The fast charging and slow discharging mode is specifically: in the charging phase, the gate-source voltage of the first PMOS tube is less than the opening voltage of the first PMOS tube, the first PMOS tube is quickly turned on, the power supply current quickly flows to the voltage stabilizing capacitor, and the voltage of the voltage stabilizing capacitor quickly rises; in the discharging phase, the gate-source voltage of the first NMOS tube is less than the opening voltage of the first NMOS tube, the first NMOS tube is in a relatively cut-off state, the voltage stabilizing capacitor is discharged through the current limiting resistor, the discharging current is small, the voltage of the voltage stabilizing capacitor slowly drops, and a fast charging and slow discharging push-pull front signal is obtained.

4. A data synchronization circuit according to claim 3, characterized in that The fast push-pull logic module comprises an AND gate and a first PMOS tube; wherein: The AND gate is used for performing AND operation on the clock signal and the input data to obtain a preliminary push-pull signal, and transmitting the preliminary push-pull signal to the first PMOS tube; The drain of the first PMOS tube is connected to the input end of the Schmitt trigger, the gate of the first PMOS tube is connected to the output end of the AND gate, and the source of the first PMOS tube is connected to the power supply; the first PMOS tube is used for quickly pushing and pulling the potential of the push-pull front signal to obtain a push-pull modulation signal, and transmitting the push-pull modulation signal to the Schmitt trigger.

5. A data synchronization circuit according to claim 4, characterized in that The fast push-pull has two modes of fast pull-up and fast pull-down; wherein: The fast pull-up mode is specifically: the first PMOS tube is used for pulling up the potential of the push-pull front signal to the power supply voltage to obtain a pull-up push-pull modulation signal, and transmitting the pull-up push-pull modulation signal to the Schmitt trigger; The fast pull-down mode is specifically: the first PMOS tube is used for pulling down the potential of the push-pull front signal to the ground potential to obtain a pull-down push-pull modulation signal, and transmitting the pull-down push-pull modulation signal to the Schmitt trigger.

6. A data synchronization apparatus, characterized by comprising: The shell is provided with a data input interface, a data output interface and a power supply interface; the data input interface is electrically connected with the signal input module, the data output interface is electrically connected with the demodulation module, and the power supply interface is electrically connected with the fast push-pull logic module.

Images