Data processing method, device and system and storage medium
By calling a simple instruction set in a microprocessor to process peripheral bus and sensor data, the high power consumption problem caused by the complex instruction set in the prior art is solved, and low power data processing is achieved.
Patent Information
- Application Number
- CN202311624711.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-29
- Publication Date
- 2025-05-30
AI Technical Summary
In the prior art, when processing peripheral bus and sensor data, the instruction set used by microprocessors is too complex, resulting in high power consumption and difficult to meet low power consumption business scenarios.
Data from peripheral bus and sensors are processed by calling a stored simple set of instructions in the microprocessor, including read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions and jump instructions.
This reduces the power consumption of data processing, avoids the need for data processing by the central processor using complex instruction sets, and expands the scope of application of instruction sets.
Smart Images
Figure CN120066238A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computers, and particularly to a data processing method, apparatus, system, and storage medium. Background Art
[0002] With the development of computer technology, many sensors are installed on wearable electronic watches, bracelets and other devices to obtain data on human health, behavior, etc. Among them, devices such as watches and bracelets are mostly in the screen-off standby scenario, and at this time, the processor in the device needs to continuously receive and process data from sensors and external buses. Summary of the Invention
[0003] The present disclosure provides a data processing method, apparatus, system, and storage medium to solve the problems in the related art, simplify the instructions in the instruction set, and reduce the power consumption of the microprocessor.
[0004] In a first aspect embodiment of the present disclosure, a data processing method is proposed, which is applied to an embedded system. The embedded system includes a microprocessor and a peripheral bus. The method includes: the microprocessor calls an instruction in the instruction set to process first data, where the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions, and the first data includes data of the peripheral bus and / or data of the sensor.
[0005] In some embodiments, the parameters of the instruction include at least one of an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter, where the instruction code is used to indicate the corresponding instruction operation, the first parameter and / or the second parameter is used to indicate a general register or an immediate number, the third parameter is used to indicate a constant or an immediate number, and the fourth parameter is used to indicate a general register.
[0006] In some embodiments, the data of the peripheral bus includes at least one of the address space data of the peripheral bus, the address space data of the general register, and the data of the general register; the data of the sensor includes the address space data of the general register and / or the data of the general register.
[0007] In some embodiments, the bit width of the instruction is 64 bits; the bit width of the instruction code is 3 bits; the bit width of the first parameter is 8 bits; the bit width of the second parameter is 32 bits; the bit width of the third parameter is 5 bits; the bit width of the fourth parameter is 16 bits.
[0008] In some embodiments, a read access instruction consists of an instruction code, a first parameter, a second parameter, and a third parameter. The read access instruction is used to read data from the address space of a peripheral bus. The first parameter and the second parameter are used to indicate general registers, and the third parameter is used to indicate a constant, where the constant is used to indicate a first operation.
[0009] In some embodiments, the first operation includes at least one of the following: reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter and reading the data of the general register indicated by the first parameter into the memory space; reading the data of the general register indicated by the first parameter into the memory space; reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter; reading the data of the general register indicated by the first parameter into the memory space, where the data of the general register includes first data, and the first data is used to indicate the valid length of the data of the general register.
[0010] In some embodiments, a write access instruction consists of an instruction code, a first parameter, and a second parameter. The write access instruction is used to write first data to the address space of a peripheral bus, and the first parameter and the second parameter are used to indicate general registers.
[0011] In some embodiments, a judgment instruction consists of an instruction code, a first parameter, a second parameter, and a third parameter. The judgment instruction is used to implement a logical judgment. The first parameter is used to indicate a general register, and the second parameter and the third parameter are used to indicate immediate numbers. The immediate number indicated by the second parameter is used as the comparison target number for the logical judgment, and the immediate number indicated by the third parameter is used to indicate the logical judgment condition.
[0012] In some embodiments, the method further includes: determining the result of the logical judgment; and updating the address of the next instruction based on the result.
[0013] In some embodiments, a wait instruction consists of an instruction code, a first parameter, and a second parameter. The wait instruction is used to wait for a first signal. The first parameter and the second parameter are used to indicate immediate numbers. The immediate number indicated by the first parameter is used to indicate the type of the first signal, and the immediate number indicated by the second parameter is used to indicate the identifier of the peripheral bus. The first signal is related to the first data.
[0014] In some embodiments, when the immediate number indicated by the first parameter is used to indicate an interrupt signal of the peripheral bus, the second parameter is valid.
[0015] In some embodiments, an interrupt instruction consists of an instruction code, a first parameter, and a second parameter. The interrupt instruction is used to send an interrupt signal to the main control chip. The first parameter and the second parameter are used to indicate immediate values. The immediate value indicated by the first parameter is used to indicate the type of the interrupt, and the immediate value indicated by the second parameter is used to indicate the identifier of the sensor corresponding to the interrupt. The interrupt signal is used to interrupt the processing of the first data.
[0016] In some embodiments, the method further includes: updating a register in an interrupt state based on the interrupt instruction.
[0017] In some embodiments, a logical operation instruction includes an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter. The logical operation instruction is used to implement a logical operation. The first parameter and the fourth parameter are used to indicate general-purpose registers, and the second parameter and the third parameter are used to indicate immediate values. The immediate value indicated by the second parameter is used to indicate the right operand of the logical operation, and the immediate value indicated by the third parameter is used to indicate the operation symbol of the logical operation. The right operand belongs to the first data.
[0018] In some embodiments, a jump instruction includes an instruction code and a first parameter. The jump instruction is used to indicate the jump of a program related to the first data, and the first parameter is used to indicate a general-purpose register.
[0019] In some embodiments, the method further includes: updating the address of the next instruction based on the first parameter.
[0020] An embodiment of the second aspect of the present disclosure provides a data processing device, which includes: a processing module, configured to call an instruction in an instruction set through a microprocessor to process first data, where the instruction set is stored in the microprocessor, and the instructions include a read access instruction, a write access instruction, a judgment instruction, a wait instruction, an interrupt instruction, a logical operation instruction, and a jump instruction, and the first data includes data of a peripheral bus and / or data of a sensor.
[0021] An embodiment of the third aspect of the present disclosure provides an embedded system, which includes: a microprocessor, configured to call an instruction in an instruction set to process first data, where the instruction set is stored in the microprocessor, and the instructions include a read access instruction, a write access instruction, a judgment instruction, a wait instruction, an interrupt instruction, a logical operation instruction, and a jump instruction, and the first data includes data of a peripheral bus and / or data of a sensor.
[0022] In some embodiments, the embedded system further includes a peripheral bus, a memory, and a main control chip.
[0023] An embodiment of the fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in the embodiment of the first aspect of the present disclosure.
[0024] In summary, according to the data processing method proposed by the present disclosure, which is applied to an embedded system, the embedded system includes a microprocessor and a peripheral bus. The method includes: the microprocessor calls instructions in the instruction set to process the first data, where the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions. The first data includes data of the peripheral bus and / or data of sensors. The method of the present disclosure realizes the processing of the first data by the microprocessor calling the stored simple instruction set, thereby avoiding the processing of the first data by the central processor using a complex instruction set and reducing the power consumption of data processing.
[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings
[0026] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.
[0027] Figure 1 It is a schematic diagram of an application scenario of a data processing method provided by an embodiment of the present disclosure;
[0028] Figure 2 It is a flowchart of a data processing method provided by an embodiment of the present disclosure;
[0029] Figure 3 It is a schematic diagram of an instruction structure provided by an embodiment of the present disclosure;
[0030] Figure 4 It is a flowchart of a data processing method provided by an embodiment of the present disclosure;
[0031] Figure 5 It is a flowchart of another data processing method provided by an embodiment of the present disclosure;
[0032] Figure 6 It is a flowchart of another data processing method provided by an embodiment of the present disclosure;
[0033] Figure 7 It is a flowchart of yet another data processing method provided by an embodiment of the present disclosure;
[0034] Figure 8 It is a flowchart of another data processing method provided by an embodiment of the present disclosure;
[0035] Figure 9 It is a flowchart of another data processing method provided by an embodiment of the present disclosure;
[0036] Figure 10 Flow chart of yet another data processing method provided by an embodiment of the present disclosure;
[0037] Figure 11 Structural schematic diagram of a data processing device provided by an embodiment of the present disclosure;
[0038] Figure 12 Structural schematic diagram of an embedded system provided by an embodiment of the present disclosure. Detailed implementation manners
[0039] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure as detailed in the appended claims.
[0040] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present disclosure. The singular forms "a" and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0041] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "when" as used herein may be interpreted as "when" or "while" or "in response to determining".
[0042] For ease of understanding, the background technology related to this application is introduced first.
[0043] With the development of computer technology, many sensors are installed on wearable electronic watches, bracelets and other devices to obtain data on human health, behavior, etc. Among them, devices such as watches and bracelets are mostly in the screen-off standby scenario, and at this time, the processor in the device needs to continuously receive data from the sensors and / or the external bus for processing.
[0044] Before introducing the detailed solution of the present disclosure, the scenario to which the solution of the present disclosure is applied is described first.Figure 1 This is an application scenario diagram of the data processing method in an embodiment. As Figure 1 shown, this application scenario includes: microprocessor 101, Random Access Memory (RAM) 102, Central Processing Unit (CPU) 103, peripheral bus 104, and Sensors 105.
[0045] In the related art, when the CPU collects peripheral bus data and / or sensor data, the instruction set used contains too many instructions and is not suitable for low-power service scenarios.
[0046] Therefore, to solve the problems existing in the related art, the present disclosure proposes a data processing method. Taking the scenario as shown in Figure 1 as an example, the microprocessor 101 calls the instructions in the instruction set of the present disclosure to process the data of the peripheral bus 104 and / or the data of the sensor 105. Among them, the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions. Thus, by the microprocessor calling the stored simple instruction set, the processing of the data of the peripheral bus and / or the data of the sensor is realized, avoiding the use of a complex instruction set by the central processor to process the above data, and reducing the power consumption of data processing.
[0047] It can be understood that the description of the embodiments of the present disclosure is to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and does not constitute a limitation on the data processing method, device, and storage medium proposed in the embodiments of the present disclosure. Those of ordinary skill in the art know that with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions proposed in the embodiments of the present disclosure are equally applicable to similar technical problems.
[0048] Figure 2 This is a flowchart of a data processing method provided by an embodiment of the present disclosure. As Figure 2 shown, this data processing method is applied to an embedded system, and the embedded system includes a microprocessor and a peripheral bus. The method includes step 201.
[0049] Step 201, the microprocessor calls the instructions in the instruction set to process the first data.
[0050] In some embodiments, the microprocessor calls the instructions in the instruction set to process the first data, thus avoiding the use of a complex instruction set by the central processor to process the first data, and reducing the power consumption of data processing.
[0051] Optionally, in some embodiments, the microprocessor may include 8 general-purpose registers.
[0052] In some embodiments, the instruction set is stored in a microprocessor. Optionally, the microprocessor may include eight general-purpose registers.
[0053] In some embodiments, the instructions in the instruction set include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions.
[0054] The parameters of the above instructions include at least one of an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter. Among them, the instruction code is used to indicate the corresponding instruction operation, the first parameter and / or the second parameter are used to indicate a general-purpose register or an immediate value, the third parameter is used to indicate a constant or an immediate value, and the fourth parameter is used to indicate a general-purpose register.
[0055] In some embodiments, the general-purpose register can be used to store first data.
[0056] In some embodiments, the first data includes data of a peripheral bus and / or data of a sensor.
[0057] In some embodiments, the data of the peripheral bus includes at least one of the address space data of the peripheral bus, the address space data of the general-purpose register, and the data of the general-purpose register; the data of the sensor includes the address space data of the general-purpose register and / or the data of the general-purpose register.
[0058] In other words, the data of the general-purpose register and / or the address space data of the general-purpose register can be the data of the peripheral bus or the data of the sensor, and the present disclosure does not limit this.
[0059] It should be understood that in the same general-purpose register, the data of the general-purpose register includes the address space data of the general-purpose register.
[0060] Optionally, in some embodiments, the peripheral bus is, for example, an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, etc., and the present disclosure does not limit this.
[0061] In some embodiments, the bit width of the instruction is 64 bits, the bit width of the instruction code is 3 bits, the bit width of the first parameter is 8 bits, the bit width of the second parameter is 32 bits, the bit width of the third parameter is 5 bits, and the bit width of the fourth parameter is 16 bits. Optionally, the structure of the instruction can be as Figure 3 shown.
[0062] In summary, according to the data processing method proposed in the present disclosure, which is applied to an embedded system including a microprocessor, the data processing method includes: the microprocessor calls instructions in the instruction set to process first data, where the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions, and the first data includes data of a peripheral bus and / or data of a sensor. The method of the present disclosure realizes the processing of the first data by the microprocessor calling the stored simple instruction set, thereby avoiding the use of a complex instruction set by the central processor to process the first data and reducing the power consumption of data processing.
[0063] Figure 4 FIG. is a schematic flowchart of a data processing method proposed in an embodiment of the present disclosure. As Figure 4 shown, based on the embodiment shown in Figure 2 the above, step 201 is further explained, and the data processing method includes step 401.
[0064] Step 401, the microprocessor calls a read access instruction to process the first data.
[0065] In some embodiments, the microprocessor calls a read access instruction to read the address space data of the peripheral bus or perform a first operation.
[0066] In some embodiments, the read access instruction is composed of an instruction code, a first parameter, a second parameter, and a third parameter. Among them, the read access instruction is used to read the address space data of the peripheral bus, the first parameter and the second parameter are used to indicate general-purpose registers, and the third parameter is used to indicate a constant, and the constant is used to indicate the first operation.
[0067] Specifically, the general-purpose register indicated by the first parameter is used to store the read address space data of the peripheral bus, and the address of the peripheral bus is stored in the general-purpose register indicated by the second parameter.
[0068] Specifically, different constants indicated by the third parameter can indicate different first operations, that is, the first operation corresponding to the first constant can be to read the address space data of the general-purpose register indicated by the second parameter into the general-purpose register indicated by the first parameter and read the data of the general-purpose register indicated by the first parameter into the memory space; the first operation corresponding to the second constant can be to read the data of the general-purpose register indicated by the first parameter into the memory space; the first operation corresponding to the third constant can be to read the address space data of the general-purpose register indicated by the second parameter into the general-purpose register indicated by the first parameter; the first operation corresponding to the fourth constant can be to read the data of the general-purpose register indicated by the first parameter into the memory space, where the data of the general-purpose register includes the first data, and the first data is used to indicate the effective length of the data of the general-purpose register.
[0069] Exemplarily, the pseudo-code of the read access instruction is, for example: LD R1,(R2),#flag; where LD is the instruction code, R1 is the general register indicated by the first parameter, R2 is the general register indicated by the second parameter, and #flag is the constant indicated by the third parameter.
[0070] In summary, according to the data processing method proposed by the present disclosure, the method includes: the microprocessor calls a read access instruction to process the first data. By setting different execution modes indicated by different parameters, the method of the present disclosure realizes the read access of the microprocessor to the first data through simple instructions, thereby expanding the applicable range of the instruction set, realizing different read processing of the first data in different situations, and reducing the power consumption of data processing.
[0071] Figure 5 It is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure. As Figure 5 shown, on the basis of the embodiment shown in Figure 2 the step 201 is further explained, and the data processing method includes step 501.
[0072] Step 501, the microprocessor calls a write access instruction to process the first data.
[0073] In some embodiments, the microprocessor calls a write access instruction to write the first data into the address space of the peripheral bus.
[0074] In some embodiments, the write access instruction is composed of an instruction code, a first parameter, and a second parameter. Wherein, the write access instruction is used to write the first data into the address space of the peripheral bus, and the first parameter and the second parameter are used to indicate general registers.
[0075] In some embodiments, the general register indicated by the first parameter is used to store the first data to be written, and the general register indicated by the second parameter is used to store the address of the peripheral bus to be written.
[0076] Exemplarily, the pseudo-code of the write access instruction is, for example: ST R1,(R2); where ST is the instruction code, R1 is the general register indicated by the first parameter, and R2 is the general register indicated by the second parameter.
[0077] In summary, according to the data processing method proposed by the present disclosure, the method includes: the microprocessor calls a write access instruction to process the first data. By setting the parameter indicating the write address and the parameter indicating the write data, the method realizes writing the first data into the address space of the peripheral bus through simple instructions, and reduces the power consumption of data processing.
[0078] Figure 6 It is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure. AsFigure 6 As shown in Figure 2 Based on the embodiment shown in, step 201 is further explained. The data processing method includes steps 601-603.
[0079] Step 601, the microprocessor calls a judgment instruction to process the first data.
[0080] In some embodiments, the microprocessor calls a judgment instruction to implement a logical judgment on the first data.
[0081] In some embodiments, the judgment instruction consists of an instruction code, a first parameter, a second parameter, and a third parameter. Among them, the judgment instruction is used to implement a logical judgment. The first parameter is used to indicate a general register, and the second parameter and the third parameter are used to indicate immediate numbers. The immediate number indicated by the second parameter is the comparison target number for the logical judgment, and the immediate number indicated by the third parameter is used to indicate the logical judgment condition.
[0082] In some embodiments, the general register indicated by the first parameter is used to store the first data that needs to be judged and compared.
[0083] In some embodiments, different immediate numbers indicated by the third parameter correspond to different judgment conditions. For example, the logical judgment condition indicated by the first immediate number can be that the first data is greater than the above comparison target number, the logical judgment condition indicated by the second immediate number can be that the first data is equal to the above comparison target number, and the logical judgment condition indicated by the third immediate number can be that the first data is less than the above comparison target number.
[0084] Exemplarily, the pseudocode of the judgment instruction is, for example: IF R1,#val,#flag; where, IF is the instruction code, R1 is the general register indicated by the first parameter, #val is the immediate number indicated by the second parameter, and #flag is the immediate number indicated by the third parameter.
[0085] Step 602, determine the logical judgment result.
[0086] In some embodiments, the microprocessor can determine whether the logical judgment is successful through the first data, the comparison target number, and the logical judgment condition, that is, whether the first data and the comparison target number match the logical judgment condition.
[0087] For example, when the first data is 5, the comparison target number is 7, and the logical judgment condition is that the first data is greater than the comparison target number, it can be determined that this logical judgment does not hold.
[0088] Step 603, based on the result, update the address of the next instruction.
[0089] In some embodiments, if the microprocessor determines that the logical judgment of the judgment instruction holds, the value of the program counter (PC) can be incremented by 1, i.e., PC + 1, to update the address of the next instruction.
[0090] In some embodiments, if the microprocessor determines that the logical judgment of the judgment instruction does not hold, the value of the program counter can be incremented by 1, i.e., PC + 2, to update the address of the next instruction.
[0091] It should be understood that the above method of updating the instruction address is only an example, and based on the judgment result, the value of the program counter can also be changed to other values, which is not limited in this disclosure.
[0092] In summary, according to the data processing method proposed in this disclosure, the method includes: the microprocessor calls a judgment instruction to process the first data; determines the logical judgment result; and based on the result, updates the address of the next instruction. The method of this disclosure realizes logical judgment on the first data through simple instructions by setting parameters indicating the first data, parameters for comparing with the target number, and parameters indicating the logical judgment conditions, and according to different judgment results, updates different instruction addresses, avoiding instruction conflicts, expanding the applicable range of the instruction set, and reducing the power consumption of data processing.
[0093] Figure 7 FIG. is a schematic flowchart of a data processing method proposed in an embodiment of this disclosure. As Figure 7 shown, based on the embodiment shown in Figure 2 the step 201 is further explained, and the data processing method includes step 701.
[0094] Step 701, the microprocessor calls a wait instruction to process the first data.
[0095] In some embodiments, the microprocessor calls a wait instruction to wait for the first signal, and the first signal is related to the first data.
[0096] In some embodiments, an instruction consists of an instruction code, a first parameter, and a second parameter. Among them, the wait instruction is used to wait for the first signal, and the first parameter and the second parameter are used to indicate immediate numbers. The immediate number indicated by the first parameter is used to indicate the type of the first signal, and the immediate number indicated by the second parameter is used to indicate the identifier of the peripheral bus.
[0097] In some embodiments, the first signal can be an interrupt signal of the peripheral bus or a debug signal for single-step debugging, which is not limited in this disclosure.
[0098] In some embodiments, different immediate values indicated by the first parameter correspond to different first signals. For example, the first signal indicated by the first immediate value may be an interrupt signal of a peripheral bus, and the first signal indicated by the second immediate value may be a debugging signal for single-step debugging.
[0099] In some embodiments, when the immediate value indicated by the first parameter is used to indicate an interrupt signal of a peripheral bus, the second parameter is valid.
[0100] Exemplarily, the pseudo-code of the wait instruction is, for example: WAIT#flag,#master_id; where WAIT is the instruction code, #flag is the immediate value indicated by the first parameter, and #master_id is the immediate value indicated by the second parameter, that is, the identifier of the peripheral bus.
[0101] In summary, according to the data processing method proposed by the present disclosure, the method includes: a microprocessor invoking a wait instruction to process first data. By setting different immediate values corresponding to different first signals, the method of the present disclosure realizes the wait processing of different first signals through simple instructions, avoids instruction conflicts, expands the applicable range of the instruction set, and reduces the power consumption of data processing.
[0102] Figure 8 FIG. is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure. As Figure 8 shown, based on the embodiment shown in Figure 2 FIG., step 201 is further explained. The data processing method may further include steps 801 and 802.
[0103] Step 801, the microprocessor invokes an interrupt instruction to process first data.
[0104] In some embodiments, the microprocessor invokes an interrupt instruction to send an interrupt signal to a central control chip, where the interrupt signal is used to interrupt the processing of first data.
[0105] In some embodiments, the above interruption of the processing of first data may refer to the microprocessor stopping acquiring data from a sensor, that is, the microprocessor disconnecting from the sensor.
[0106] In some embodiments, the interrupt instruction is composed of an instruction code, a first parameter, and a second parameter. The interrupt instruction is used to send an interrupt signal to a main control chip. The first parameter and the second parameter are used to indicate immediate values. The immediate value indicated by the first parameter is used to indicate the type of interrupt, and the immediate value indicated by the second parameter is used to indicate the identifier of the sensor corresponding to the interrupt.
[0107] In some embodiments, the types of the above interrupts include: not performing any operation when the sensor is in the interrupt state, still reading data when the sensor is in the interrupt state, etc. The present disclosure does not limit the types of interrupts.
[0108] Exemplarily, the pseudo code of the interrupt instruction is, for example: INT#flag,#sensors_id; where INT is the instruction code, #flag is the immediate number indicated by the first parameter, #sensors_id is the immediate number indicated by the second parameter, that is, the identifier of the sensor.
[0109] Step 802, update the register in the interrupt state based on the interrupt instruction.
[0110] In some embodiments, the microprocessor can determine the interrupted sensor through the second parameter in the interrupt instruction, so as to determine the register corresponding to the sensor as the interrupt state.
[0111] In summary, according to the data processing method proposed by the present disclosure, the method includes: the microprocessor calls an interrupt instruction to process the first data. The method of the present disclosure realizes the interrupt processing of different sensors through simple instructions by setting different immediate numbers corresponding to different interrupt types, avoiding instruction conflicts and resource waste, expanding the applicable range of the instruction set, and reducing the power consumption of data processing.
[0112] Figure 9 It is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure. As Figure 9 shown, on the basis of the embodiment shown in Figure 2 the further explanation of step 201 is as follows. The data processing method may further include step 901.
[0113] Step 901, the microprocessor calls a logical operation instruction to process the first data.
[0114] In some embodiments, the microprocessor calls a logical operation instruction to implement the logical operation on the first data.
[0115] In some embodiments, the logical operation instruction includes an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter. Among them, the logical operation instruction is used to implement a logical operation. The first parameter and the fourth parameter are used to indicate general registers, the second parameter and the third parameter are used to indicate immediate numbers. The immediate number indicated by the second parameter is used to indicate the right operand of the logical operation, and the immediate number indicated by the third parameter is used to indicate the operation symbol of the logical operation. The right operand belongs to the first data.
[0116] In some embodiments, the logical operation symbols include at least one of addition, subtraction, and OR.
[0117] In some embodiments, the general register indicated by the first parameter is used to store the logical operation result of the first data, and the general register indicated by the fourth parameter is used to store the left operand for the logical operation, where the left operand is the first data.
[0118] Exemplarily, the pseudocode of the logical operation instruction is, for example: ALU R1,#val,#flag,#R2; where ALU is the instruction code, R1 is the general register indicated by the first parameter, #val is the immediate value indicated by the second parameter, that is, the right operand of the logical operation, #flag is the logical operation symbol indicated by the third parameter, and #R2 is the general register indicated by the fourth parameter.
[0119] In summary, according to the data processing method proposed by the present disclosure, the method includes: the microprocessor calls a logical operation instruction to process the first data. By setting different immediate values corresponding to different logical operations, the method of the present disclosure can perform various logical operations on the first data through simple instructions, avoiding instruction conflicts, expanding the applicable range of the instruction set, and reducing the power consumption of data processing.
[0120] Figure 10 It is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure. As Figure 10 shown, on the basis of the embodiment shown in Figure 2 the data processing method may further include step 1001 to further explain step 201.
[0121] Step 1001, the microprocessor calls a jump instruction to process the first data.
[0122] In some embodiments, the microprocessor calls a jump instruction to implement the jump of a program related to the first data. For example, to implement the jump from the logical operation program of the first data to the write access program.
[0123] In some embodiments, the jump instruction includes an instruction code and a first parameter, where the jump instruction is used to indicate the jump of a program related to the first data, and the first parameter is used to indicate a general register.
[0124] In some embodiments, the general register indicated by the first parameter is used to store the jump address.
[0125] Exemplarily, the pseudocode of the jump instruction is, for example: JMP R1; where JMP is the instruction code and R1 is the general register indicated by the first parameter.
[0126] Step 1102, update the address of the next instruction based on the first parameter.
[0127] In some embodiments, the microprocessor updates the address of the next instruction based on a first parameter. In other words, the microprocessor can assign the value of the program counter to the PC value in the general-purpose processor indicated by the first parameter to update the address of the next instruction.
[0128] In summary, according to the data processing method proposed in the present disclosure, the method includes: the microprocessor calls a jump instruction to process first data; and updates the address of the next instruction based on a first parameter. By setting the first parameter to indicate the address after the jump, the method of the present disclosure realizes program jumps through simple instructions, expands the applicable range of the instruction set, and reduces the power consumption of data processing.
[0129] Therefore, the present solution has the following beneficial effects:
[0130] 1. In this solution, the microprocessor calls the stored instruction set to process the first data, thus avoiding the use of complex instruction sets by the central processing unit to process the first data and reducing the power consumption of data processing.
[0131] 2. By setting an instruction set containing multiple instructions, this solution enables the microprocessor to perform various processes on the first data through simple instructions, improves the applicable range of the instruction set and the processor applying this instruction set, and reduces the power consumption of data processing.
[0132] Figure 11 FIG. 16 is a schematic structural diagram of a data processing apparatus 1100 provided for an embodiment of the present disclosure. The data processing apparatus includes:
[0133] A processing module 1110, configured to call an instruction in an instruction set to process first data, where the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions, and the first data includes data on a peripheral bus and / or data from a sensor.
[0134] In some embodiments, the parameters of the instruction include at least one of an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter, where the instruction code is used to indicate the corresponding instruction operation, the first parameter and / or the second parameter are used to indicate a general register or an immediate number, the third parameter is used to indicate a constant or an immediate number, and the fourth parameter is used to indicate a general register.
[0135] In some embodiments, the data on the peripheral bus includes at least one of the address space data of the peripheral bus, the address space data of the general register, and the data of the general register; the data from the sensor includes the address space data and / or the data of the general register.
[0136] In some embodiments, the bit width of the instruction is 64 bits; the bit width of the instruction code is 3 bits; the bit width of the first parameter is 8 bits; the bit width of the second parameter is 32 bits; the bit width of the third parameter is 5 bits; the bit width of the fourth parameter is 16 bits.
[0137] In some embodiments, the read access instruction is composed of an instruction code, a first parameter, a second parameter, and a third parameter. The read access instruction is used to read data from the address space of the peripheral bus. The first parameter and the second parameter are used to indicate general registers, and the third parameter is used to indicate a constant, where the constant is used to indicate a first operation.
[0138] In some embodiments, the first operation includes at least one of the following: reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter, and reading the data of the general register indicated by the first parameter into the memory space; reading the data of the general register indicated by the first parameter into the memory space; reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter; reading the data of the general register indicated by the first parameter into the memory space, where the data of the general register includes first data, and the first data is used to indicate the effective length of the data of the general register.
[0139] In some embodiments, the write access instruction is composed of an instruction code, a first parameter, and a second parameter. The write access instruction is used to write first data to the address space of the peripheral bus, and the first parameter and the second parameter are used to indicate general registers.
[0140] In some embodiments, the judgment instruction is composed of an instruction code, a first parameter, a second parameter, and a third parameter. The judgment instruction is used to implement a logical judgment. The first parameter is used to indicate a general register, and the second parameter and the third parameter are used to indicate immediate values. The immediate value indicated by the second parameter is used as the comparison target number for the logical judgment, and the immediate value indicated by the third parameter is used to indicate the judgment condition.
[0141] In some embodiments, the processing module 1110 is further configured to determine the result of the logical judgment; and update the address of the next instruction based on the result.
[0142] In some embodiments, the wait instruction is composed of an instruction code, a first parameter, and a second parameter. The wait instruction is used to wait for a first signal. The first parameter and the second parameter are used to indicate immediate values. The immediate value indicated by the first parameter is used to indicate the type of the first signal, and the immediate value indicated by the second parameter is used to indicate the identifier of the peripheral bus. The first signal is related to the first data.
[0143] In some embodiments, when the immediate value indicated by the first parameter is used to indicate the interrupt signal of the peripheral bus, the second parameter is valid.
[0144] In some embodiments, an interrupt instruction consists of an instruction code, a first parameter, and a second parameter. The interrupt instruction is used to send an interrupt signal to the main control chip. The first parameter and the second parameter are used to indicate immediate numbers. The immediate number indicated by the first parameter is used to indicate the type of the interrupt, and the immediate number indicated by the second parameter is used to indicate the identifier of the sensor corresponding to the interrupt. The interrupt signal is used to interrupt the processing of the first data.
[0145] In some embodiments, the processing module 1110 is further configured to update the register in the interrupt state based on the interrupt instruction.
[0146] In some embodiments, a logical operation instruction includes an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter. The logical operation instruction is used to implement a logical operation. The first parameter and the fourth parameter are used to indicate general-purpose registers. The second parameter and the third parameter are used to indicate immediate numbers. The immediate number indicated by the second parameter is used to indicate the right operand of the logical operation, and the immediate number indicated by the third parameter is used to indicate the operation symbol of the logical operation. The right operand belongs to the first data.
[0147] In some embodiments, a jump instruction includes an instruction code and a first parameter. The jump instruction is used to indicate the jump of a program related to the first data, and the first parameter is used to indicate a general-purpose register.
[0148] In some embodiments, the processing module 1110 is further configured to update the address of the next instruction based on the first parameter.
[0149] In summary, according to the data processing device provided by the present disclosure, the processing of the first data is realized by the microprocessor calling the stored instruction set, thereby avoiding the processing of the first data by the central processing unit using a complex instruction set and reducing the power consumption of data processing.
[0150] Since the device provided by the embodiments of the present disclosure corresponds to the methods provided by the above several embodiments, the implementation manners of the methods are also applicable to the device provided by this embodiment and will not be described in detail in this embodiment.
[0151] Figure 12 The structure diagram of an embedded system provided by an embodiment of the present disclosure is as Figure 12 shown. The embedded system includes: The microprocessor 1210 is configured to execute the above Figures 2 - 10 shown method.
[0152] In some embodiments, the embedded system further includes a peripheral bus, a memory, and a main control chip.
[0153] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.
[0154] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0155] Any process or method description represented in a flowchart or described in other ways herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations, where the functions may be executed in a manner that is not shown or discussed, including in a substantially simultaneous manner according to the involved functions or in a reverse order, which should be understood by those skilled in the technical field to which the embodiments of the present invention belong.
[0156] The logic and / or steps represented in a flowchart or described in other ways herein, for example, may be considered as a sequenced list of executable instructions for implementing a logical function, and may be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in connection with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (control method), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or, if necessary, other suitable processing, and then stored in a computer memory.
[0157] It should be understood that each part of the embodiments of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
[0158] Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.
[0159] In addition, each functional unit in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.
[0160] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A data processing method, characterized in that, applied to an embedded system, the embedded system includes a microprocessor and a peripheral bus, and the method includes: The microprocessor calls an instruction in the instruction set to process the first data, wherein the instruction set is stored in the microprocessor, and the instructions include read access instructions, write access instructions, judgment instructions, wait instructions, interrupt instructions, logical operation instructions, and jump instructions, and the first data includes data of the peripheral bus and / or data of the sensor.
2. The method according to claim 1, characterized in that, The parameters of the instruction include at least one of: an instruction code, a first parameter, a second parameter, a third parameter, and a fourth parameter, wherein the instruction code is used to indicate the corresponding instruction operation, and the first parameter and / or the second parameter are used to indicate a general register or an immediate number, the third parameter is used to indicate a constant or an immediate number, and the fourth parameter is used to indicate a general register.
3. The method according to claim 1, characterized in that, The data of the peripheral bus includes at least one of: address space data of the peripheral bus, address space data of the general register, and data of the general register; The data of the sensor includes: address space data of the general register and / or data of the general register.
4. The method according to claim 2, characterized in that, The bit width of the instruction is 64bit; the bit width of the instruction code is 3bit; the bit width of the first parameter is 8bit; the bit width of the second parameter is 32bit; the bit width of the third parameter is 5bit; the bit width of the fourth parameter is 16bit.
5. The method according to any one of claims 1-4, characterized in that, The read access instruction is composed of the instruction code, the first parameter, the second parameter, and the third parameter, wherein, the read access instruction is used to read the address space data of the peripheral bus, the first parameter and the second parameter are used to indicate general registers, and the third parameter is used to indicate a constant, and the constant is used to indicate the first operation.
6. The method according to claim 5, characterized in that, The first operation includes at least one of the following: Reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter, and reading the data of the general register indicated by the first parameter into the memory space; Reading the data of the general register indicated by the first parameter into the memory space; Reading the address space data of the general register indicated by the second parameter into the general register indicated by the first parameter; Reading the data of the general register indicated by the first parameter into the memory space, wherein the data of the general register includes the first data, and the first data is used to indicate the valid length of the data of the general register.
7. The method according to any one of claims 1-4, characterized in that, The write access instruction is composed of the instruction code, the first parameter, and the second parameter, Among them, the write access instruction is used to write first data to the address space of the peripheral bus, and the first parameter and the second parameter are used to indicate the general register.
8. The method according to any one of claims 1-4, wherein, the judgment instruction is composed of the instruction code, the first parameter, the second parameter, and the third parameter, wherein, the judgment instruction is used to implement logical judgment, the first parameter is used to indicate the general register, the second parameter and the third parameter are used to indicate immediate numbers, the immediate number indicated by the second parameter is used as the comparison target number for the logical judgment, and the immediate number indicated by the third parameter is used to indicate the logical judgment condition.
9. The method according to claim 8, wherein, the method further includes: determining the result of the logical judgment; updating the address of the next instruction based on the result.
10. The method according to any one of claims 1-4, wherein, the wait instruction is composed of the instruction code, the first parameter, and the second parameter, wherein, the wait instruction is used to wait for a first signal, the first parameter and the second parameter are used to indicate immediate numbers, the immediate number indicated by the first parameter is used to indicate the type of the first signal, the immediate number indicated by the second parameter is used to indicate the identifier of the peripheral bus, and the first signal is related to the first data.
11. The method according to claim 10, wherein, when the immediate number indicated by the first parameter is used to indicate the interrupt signal of the peripheral bus, the second parameter is valid.
12. The method according to any one of claims 1-4, wherein, the interrupt instruction is composed of the instruction code, the first parameter, and the second parameter, wherein, the interrupt instruction is used to send an interrupt signal to the main control chip, the first parameter and the second parameter are used to indicate immediate numbers, the immediate number indicated by the first parameter is used to indicate the type of the interrupt, the immediate number indicated by the second parameter is used to indicate the identifier of the sensor corresponding to the interrupt, and the interrupt signal is used to interrupt the processing of the first data.
13. The method according to claim 12, wherein, the method further includes: updating the register in the interrupt state based on the interrupt instruction.
14. The method according to any one of claims 1-4, wherein, the logical operation instruction includes the instruction code, the first parameter, the second parameter, the third parameter, and the fourth parameter, wherein, the logical operation instruction is used to implement a logical operation, the first parameter and the fourth parameter are used to indicate the general register, the second parameter and the third parameter are used to indicate immediate numbers, the immediate number indicated by the second parameter is used to indicate the right operand of the logical operation, the immediate number indicated by the third parameter is used to indicate the operation symbol of the logical operation, and the right operand belongs to the first data.
15. The method according to any one of claims 1-4, wherein, the jump instruction includes the instruction code and the first parameter, Among them, the jump instruction is used to indicate the jump of the program related to the first data, and the first parameter is used to indicate a general-purpose register.
16. The method according to claim 15, wherein, the method further includes: updating the address of the next instruction based on the first parameter.
17. A data processing device, wherein, the data processing device includes: a processing module, configured to call an instruction in an instruction set through a microprocessor to process first data, wherein the instruction set is stored in the microprocessor, and the instructions include a read access instruction, a write access instruction, a judgment instruction, a wait instruction, an interrupt instruction, a logical operation instruction, and a jump instruction, and the first data includes data of a peripheral bus and / or data of a sensor.
18. An embedded system, wherein, the embedded system includes: a microprocessor, configured to call an instruction in an instruction set to process first data, wherein the instruction set is stored in the microprocessor, and the instructions include a read access instruction, a write access instruction, a judgment instruction, a wait instruction, an interrupt instruction, a logical operation instruction, and a jump instruction, and the first data includes data of a peripheral bus and / or data of a sensor.
19. The embedded system according to claim 18, wherein, the embedded system further includes a peripheral bus, a memory, and a main control chip.
20. A non-transitory computer-readable storage medium storing computer instructions, wherein, the computer instructions are used to cause the computer to execute the method according to any one of claims 1-16.