Memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a storage medium. A memory system includes: a memory device including a plurality of memory blocks; a memory controller coupled to the memory device and configured to: in response to a write command, determine a second memory block from a plurality of first memory blocks at least partially in an erased state among the plurality of memory blocks based on a data retention parameter of each of the memory blocks; the second storage block is the first storage block with the maximum data retention parameter in the plurality of first storage blocks; and writing the data to be written on the second storage block.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to a memory system, an operation method thereof, and a storage medium. Background Art

[0002] A memory device is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, a NAND (Not-And) type memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics. Summary of the Invention

[0003] Based on this, embodiments of the present application propose a memory system, an operation method thereof, and a storage medium.

[0004] Embodiments of the present application provide a memory system, which includes: a memory device including a plurality of storage blocks; and a memory controller coupled to the memory device and configured to: in response to a write command, based on the data retention parameters of each storage block, determine a second storage block from among a plurality of first storage blocks that are at least partially in an erased state among the plurality of storage blocks; the second storage block being the first storage block with the largest data retention parameter among the plurality of first storage blocks; and write the data to be written on the second storage block.

[0005] In some embodiments, the first storage block includes at least one of the following: a storage block that has not been written with data; a storage block that has been written with dummy data and the dummy data has been erased; a storage block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

[0006] In some embodiments, the memory controller is configured to: when it is determined that there is at least part of invalid data in the storage block written with user data among the plurality of storage blocks, perform an erase operation on the storage block written with user data.

[0007] In some embodiments, the memory controller is configured to: if all storage blocks are written with dummy data when the memory system leaves the factory, perform an erase operation on all storage blocks when the memory system is powered on for the first time after leaving the factory.

[0008] In some embodiments, the memory controller is configured to: upon the first power-on of a storage block with no written data or upon completion of an erase operation of a storage block that has undergone an erase operation, obtain the characteristic operating temperature of the memory system; obtain the holding duration during which at least a portion of the first storage block is in an erased state; and determine the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the holding duration during which at least a portion of the first storage block is in an erased state.

[0009] In some embodiments, during the period when at least a portion of the first storage block is in an erased state, the characteristic operating temperature of the memory system undergoes multiple temperature ranges; the memory controller is configured to: obtain the characteristic operating temperature of the memory system in each temperature range; obtain the holding duration corresponding to each temperature range among the multiple temperature ranges; sequentially determine the sub-data retention parameters corresponding to each temperature section among the multiple temperature ranges; wherein, for each temperature section, determine the sub-data retention parameter corresponding to the corresponding temperature section based on the characteristic operating temperature of the memory system in the corresponding temperature range and the holding duration corresponding to the corresponding temperature range; sum up the sub-data retention parameters corresponding to each temperature section to obtain the data retention parameter of the first storage block.

[0010] In some embodiments, the memory controller is configured to: the relationship between the data retention parameter and the characteristic operating temperature and holding duration of the memory system is as follows:

[0011]

[0012] where t T1 is the data retention parameter, t T2 is the holding duration, T1 is the reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is the lifetime coefficient, and k is the Boltzmann constant.

[0013] In some embodiments, the memory system further includes: a temperature sensor configured to collect the operating temperature of the memory system; the memory controller is configured to: based on the operating temperature of the memory system collected by the temperature sensor, determine the multiple operating temperatures of the memory system from the moment of the first power-on of a storage block with no written data or the completion of the erase operation of a storage block that has undergone an erase operation until the moment when the write command is received; and use the average value of the operating temperature of the memory system at the time of erase completion or during the holding duration as the characteristic operating temperature of the memory system.

[0014] In some embodiments, the memory system further includes: a timer configured to record a time difference; and a memory controller configured to determine, based on the time difference recorded by the timer, a time difference from the moment of first power-on of a storage block that has never been written with data or the moment of completion of an erase operation of a storage block that has performed an erase operation to the moment of receiving the write command, and use the determined time difference as the retention duration.

[0015] In some embodiments, the invalid data includes data indicated by the host system to be erased, updated, or rewritten.

[0016] In some embodiments, the amount of data to be written corresponding to the write command is greater than a preset threshold.

[0017] An embodiment of the present application also provides an operation method for a memory system, the operation method including: in response to a write command, determining a second storage block from a plurality of first storage blocks that are at least partially in an erased state among a plurality of storage blocks of the memory system based on the data retention parameter of each storage block, where the second storage block is a first storage block with the largest data retention parameter among the plurality of first storage blocks; and writing the data to be written on the second storage block.

[0018] In some embodiments, the first storage block includes at least one of the following: a storage block that has not been written with data; a storage block that has been written with dummy data and the dummy data has been erased; and a storage block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

[0019] In some embodiments, the method further includes: when it is determined that there is at least part of invalid data in the storage blocks of the memory system that have been written with user data, performing an erase operation on the storage blocks that have been written with user data.

[0020] In some embodiments, the method further includes: if all storage blocks are written with dummy data when the memory system leaves the factory, performing an erase operation on all the storage blocks at the first power-on after the memory system leaves the factory.

[0021] In some embodiments, the method further includes: in response to the first power-on of a storage block that has not been written with data or the completion of the erase operation of a storage block that has performed an erase operation, obtaining the characteristic operating temperature of the memory system; obtaining the retention duration of at least part of the first storage block in an erased state; and determining the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration of at least part of the first storage block in an erased state.

[0022] In some embodiments, during a period when at least a part of the first storage block is in an erased state, the characteristic operating temperature of the memory system experiences multiple temperature ranges; obtaining the characteristic operating temperature of the memory system includes: obtaining the characteristic operating temperature of the memory system in each temperature range; obtaining the holding duration during which at least a part of the first storage block is in an erased state includes: obtaining the holding duration corresponding to each temperature range among the multiple temperature ranges; determining the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the holding duration during which at least a part of the first storage block is in an erased state includes: sequentially determining the sub-data retention parameters corresponding to each temperature section among the multiple temperature ranges; wherein, for each temperature section, based on the characteristic operating temperature of the memory system in the corresponding temperature range and the holding duration corresponding to the corresponding temperature range, determining the sub-data retention parameter corresponding to the corresponding temperature section; and summing the sub-data retention parameters corresponding to each temperature section to obtain the data retention parameter of the first storage block.

[0023] In some embodiments, determining the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the holding duration during which at least a part of the first storage block is in an erased state includes: calculating the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the holding duration according to the following relational expression;

[0024]

[0025] wherein, t T1 is the data retention parameter, t T2 is the holding duration, T1 is the reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is the lifetime coefficient, and k is the Boltzmann constant.

[0026] In some embodiments, obtaining the characteristic operating temperature of the memory system includes: determining, based on the operating temperature of the memory system collected by the temperature sensor of the memory system, multiple operating temperatures of the memory system from the moment of the first power-on of a storage block that has never been written with data or the moment when the erase operation of a storage block that has executed an erase operation is completed to the moment when the write command is received; and taking the average value of the operating temperature of the memory system at the end of the erase operation or the operating temperature during the holding duration as the characteristic operating temperature of the memory system.

[0027] In some embodiments, obtaining the holding duration of at least a part of the first memory block being in the erased state includes: determining, based on the time difference recorded by a timer of the memory system, the time difference from the moment when the first memory block is powered on for the first time among the memory blocks without written data or the moment when the erase operation of the memory block that has executed the erase operation ends to the moment when the write command is received; and using the determined time difference as the holding duration.

[0028] In some embodiments, the invalid data includes data indicated by the host system to be erased, updated, or rewritten.

[0029] In some embodiments, the data volume of the data to be written corresponding to the write command is greater than a preset threshold.

[0030] An embodiment of the present application further provides a storage medium, on which executable instructions are stored. When the executable instructions are executed, the steps of the method described in the embodiments of the present application can be implemented.

[0031] In an embodiment of the present application, in response to a write command, the memory controller in the memory system determines, based on the data holding parameters of each memory block, a second memory block from among a plurality of first memory blocks that are at least partially in the erased state in the memory devices of the memory system, where the second memory block has the largest data holding parameter, and writes the data to be written on the second memory block. In the embodiments of the present application, by selecting, from among at least partially erased first memory blocks, a first memory block with the largest data holding parameter, that is, a first memory block with the best data holding ability, as the write memory block for the data, the holding ability of the written data can be at a relatively good level. In this way, the reliability of the data stored in the memory system can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of an exemplary system with a memory system according to an embodiment of the present application;

[0033] Figure 2a Schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present application;

[0034] Figure 2b Schematic diagram of an exemplary solid state drive with a memory system according to an embodiment of the present application;

[0035] Figure 3a Schematic diagram of the distribution of memory cells of a three-dimensional NAND memory according to an embodiment of the present application;

[0036] Figure 3b Schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0037] Figure 4 FIG. 1 is a cross-sectional schematic view of a memory cell array including NAND-type memory strings according to an embodiment of the present application;

[0038] Figure 5 FIG. 2 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0039] Figure 6 FIG. 3 is a schematic flow chart of an operation method of a memory system provided by an embodiment of the present application; Figure 1 ;

[0040] Figure 7 FIG. 4 is a schematic diagram of the changes of holes and electrons in a storage layer after an erase state retention process according to an embodiment of the present application;

[0041] Figure 8 FIG. 5 is a schematic diagram of the original threshold voltage shift of a memory cell, the data retention threshold voltage shift without an erase state retention process, and the data retention threshold voltage shift without an erase state retention process according to an embodiment of the present application;

[0042] Figure 9 FIG. 6 is a schematic diagram of an exemplary composition structure of a memory system provided by an embodiment of the present application;

[0043] Figure 10 FIG. 7 is a schematic diagram of the process of a storage block entering a storage block pool according to an embodiment of the present application;

[0044] Figure 11 FIG. 8 is a second schematic flow chart of an operation method of a memory system provided by an embodiment of the present application;

[0045] Figure 12 FIG. 9 is a schematic block diagram of a readable storage medium provided by an embodiment of the present application.

[0046] In the above figures (which are not necessarily drawn to scale), like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. DETAILED DESCRIPTION

[0047] Hereinafter, exemplary embodiments of the present application will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0049] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals denote like elements.

[0050] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present application. And when discussing a second element, component, region, layer, or portion, it does not necessarily imply that a first element, component, region, layer, or portion exists in the present application.

[0051] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0053] In order to be able to more comprehensively understand the features and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The attached drawings are for reference and illustration only and are not used to limit the embodiments of the present application.

[0054] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND-type memory. For the sake of convenience of understanding, the three-dimensional NAND-type memory is taken as an example for description.

[0055] Figure 1 A block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present application is shown. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As Figure 1 shown, system 100 can include a host system 108 and a memory system 102. The memory system 102 has one or more memory devices 104 and a memory controller 106. The host system 108 can be a processor (e.g., a central processing unit (CPU)) of an electronic device or a system-on-chip (SoC) (e.g., an application processor (AP)). The host system 108 can be configured to send data to or receive data from the memory device 104.

[0056] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host system 108, and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host system 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment such as a Solid State Disk (SSD) or an embedded multimedia card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0057] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process the error correction code (ECC) regarding the data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host system 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0058] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end-user electronic products. In Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 1 the host system 108 in Figure 2b ). In another example shown in Figure 1 , the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., Figure 1 the host system 108 in

[0059] Figure 3a An exemplary structural schematic diagram of a memory cell array of a 3D NAND-type memory is given. As shown in Figure 3a , the memory cell array of the 3D NAND-type memory is composed of several rows of memory cell rows parallel and staggered with a gate isolation structure. Every several rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks (Blocks). Multiple second gate isolation structures may divide the memory block into multiple finger storage areas (Fingers). The upper select gate isolation structure provided in each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a As shown in

[0060] In some embodiments, each memory block may be coupled to multiple word lines.

[0061] It should be noted that Figure 3a the number of rows of memory cell rows between the gate isolation structure and the upper select gate isolation structure given in is only an exemplary demonstration and is not used to limit the number of memory cell rows included in a finger storage area of the 3D NAND-type memory in this application. In actual applications, the number of memory cell rows included in a finger storage area may be adjusted according to actual situations, such as 2, 4, 8, 16, etc.

[0062] Figure 3b A schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present application is shown. The memory device 300 may be an example of the memory device 104 in Figure 1 . The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. Taking the memory cell array 301 as a three-dimensional NAND-type memory cell array as an example, wherein the memory cells 306 are NAND-type memory cells, and the memory cells 306 are provided in the form of an array of memory strings 308, and each memory string 308 extends vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0063] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC may be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value may be used for the erased state.

[0064] As Figure 3bAs shown, each memory string 308 may include a lower select transistor 310 (also referred to as a source side select transistor, which includes a source select gate BSG) at its source extreme and an upper select transistor 312 (also referred to as a drain side select transistor, which includes a drain select gate TSG) at its drain extreme. The source select transistor BSG 310 and the drain select transistor TSG 312 may be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all the memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0065] As Figure 3b shown, the memory strings 308 may be organized into a plurality of memory blocks 304, and each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 may be coupled through word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations. In some embodiments, in combination with the foregoing Figure 3a, multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. Multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged in multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper select gate isolation structure. Among them, the memory cells in a memory slice sharing the same word line form a physical page.

[0066] Reference Figure 3a 、 Figure 3b , each memory cell 306 in the multiple memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding select transistor (such as the upper select transistor (TSG) 312).

[0067] Figure 4 FIG. shows a cross-sectional schematic view of an exemplary memory cell array 301 including a memory string 308 exemplified by NAND according to some aspects of the present application. As Figure 4 shown, the NAND memory cell array 301 may include a stacked structure 410, and the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412. Among them, the channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layer 411 and the insulating layer 412 may be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412.

[0068] The constituent material of the gate layer 411 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0069] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0070] In some embodiments, the memory string 308 includes a channel structure that extends vertically through the stack structure 410. In some implementations, the channel structure includes channel holes filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0071] Return reference Figure 3b , the peripheral circuit 302 can be coupled to the memory cell array 301 through the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown Figure 5 may also be included.

[0072] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the data to be programmed (write data) to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying the bit line voltage generated from the voltage generator 510.

[0073] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 with the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate the word line voltage (e.g., read voltage, program voltage, pass voltage, channel boost voltage, verify voltage, etc.), bit line voltage, and source line voltage to be supplied to the memory cell array 301.

[0074] The control logic 512 may be coupled to each other part of the peripheral circuits described above, and is configured to control the operations of each other part of the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and acts as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and buffer status information received from the control logic 512 and relay it to the host system. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 301.

[0075] In some embodiments, the steps for the memory system to perform a read operation are as Figure 6 shown, the memory controller is configured as follows: Step 601: Receive a write command; Step 602: Select a storage block for the data to be written; Step 603: Perform an erase operation on the selected memory block; Step 604: Write the data to be written corresponding to the write command into the selected memory block. In this embodiment, the connection between the erase operation and the programming operation (i.e., writing data) is relatively close. Immediately after the erase operation, the programming operation starts, that is, the erase-program interval (EPI, Erase Program Interval) between the erase operation and before the programming operation is very short, and the time for the memory cells in the memory device to be in the erased state is very short. Here, the process between the erase operation and before the programming operation is called the erased state holding process.

[0076] Research has found that as Figure 7 shown, during the process of the memory device being in the erased state during the erase-program interval, due to the loss / recombination of the erase operation, there are fewer electrons and fewer holes in the storage layer. During the subsequent data retention process, only fewer holes can be lost. Therefore, the threshold voltage drift of the memory cells will also be relatively small. Further, Figure 8 in which the solid line represents the original threshold voltage distribution Vt, the thin dashed line represents the threshold voltage distribution Vt of data retention without the erased state holding process, and the thick dashed line represents the threshold voltage distribution Vt of data retention with the erased state holding process. From Figure 8It can be seen that the thin dashed lines of P0, P1, and P2 drift further relative to the thick dashed line, while the thin dashed lines of P3 to P7 drift closer to the thick dashed line. Overall, the drift of the threshold voltage distribution for data retention without an erase state retention process is greater than that of the threshold voltage distribution for data retention with an erase state retention process. In other words, before a programming operation, the storage block retaining the erase state for a period of time is beneficial to the data retention ability of subsequent programming operations (write operations).

[0077] The study also found that the longer the duration of the erase state retention and the higher the temperature during the retention process, the better the data retention ability of subsequent programming operations. The data retention parameter used to characterize the data retention ability is related to the duration of the erase state retention and the temperature change during the retention process. Based on this, in the embodiments of the present application, by selecting a first storage block with the largest data retention parameter, that is, the first storage block with the best data retention ability, from at least some of the first storage blocks in the erase state as the write storage block for data, the data retention ability of the written data can be at a relatively optimal level. In this way, the reliability of the data stored in the memory system can be improved.

[0078] The embodiments of the present application provide a memory system. The memory system 102 includes: a memory device 104 including a plurality of storage blocks; and a memory controller 106 coupled to the memory device 104 and configured to: in response to a write command, determine a second storage block from the plurality of first storage blocks that are at least partially in the erase state among the plurality of storage blocks based on the data retention parameter of each storage block; the second storage block is the first storage block with the largest data retention parameter among the plurality of first storage blocks; and write the data to be written on the second storage block.

[0079] In some specific embodiments, as Figure 9 shown, the memory system 102 is coupled to the host system and executes various feedbacks in response to the instructions of the host system. The memory system 102 may include: a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform read, write, erase, and other operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0080] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a processor 1063, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. Among them, the host interface 1061 is a connection interface between the host system 108 and the memory controller 106. The host interface 1061 allows the host system and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The processor 1063 is used to overall control the memory system 106. In some specific embodiments, the processor 1063 is, for example, a central processing unit (CPU), a microcontroller unit (MCU), etc. The error correction module 1064 may further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible error data during data transmission.

[0081] The garbage collection module 1065 is used to read out the valid data on some storage blocks, rewrite them, and then mark these storage blocks after the storage space of the memory device reaches a certain threshold, so as to obtain new spare storage blocks. The general implementation of garbage collection can be divided into three steps: selecting source storage blocks with less valid data; finding valid data from the source storage blocks; writing the valid data into the target storage blocks. At this time, all the data in the source storage blocks becomes invalid data, and the source storage blocks are marked and can be used as new spare storage blocks. The wear leveling module 1066 is used to make the wear (erase count) of each storage block in the memory system balanced through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting the source storage block where the cold data is located; reading the valid data on the source storage block and writing it to the storage block with a relatively large erase count. At this time, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0082] The memory device 104 and the storage blocks can be understood with reference to the specific structure and specific working mode of the memory device 104 described above, and will not be elaborated here.

[0083] In this embodiment, the memory controller 106 is configured to: receive a write command from the host system; in response to the write command, select a second storage block from at least some of the multiple first storage blocks in the erased state as the storage block for the data to be written; write the data to be written corresponding to the write command into the selected storage block.

[0084] Here, when the memory controller 106 selects a storage block for the data to be written, it selects from the first storage blocks that are at least partially in the erased state. That is to say, in this embodiment, when selecting a storage block, part or all of the storage blocks are in the erased state.

[0085] It should be noted that in the foregoing Figure 6 in the embodiment shown, after responding to the write command, the storage block to be written is selected first, and then the selected storage block is erased, and finally the data is written. This embodiment is different from the foregoing Figure 6 in the embodiment shown, the storage block selected is the first storage block that is at least partially in the erased state. That is to say, in this embodiment, the first storage block may already be in the erased state before receiving the write command.

[0086] Here, the multiple first storage blocks are part of the multiple storage blocks of the memory device 104. There are various situations for the first storage blocks that are at least partially in the erased state.

[0087] In some embodiments, the first storage block includes at least one of the following: a storage block that has not written data; a storage block that has written dummy data and the dummy data has been erased; a storage block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

[0088] Here, the first storage block may be a storage block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased. For the storage block written with user data, the data stored in the written storage block includes valid data and invalid data. In some specific embodiments, the valid data includes data that has not been erased by the host system, has not been indicated by the host system to be erased, has not been updated by the host system, or has not been rewritten by the host system, etc. The invalid data is opposite to the valid data. In some embodiments, the invalid data includes data that has been erased by the host system, has been indicated by the host system to be erased, has been updated by the host system, or has been rewritten by the host system.

[0089] Exemplarily, the first storage block may be a storage block in which all the written user data is invalid data and the storage block has been erased. At this time, the entire storage block is in the erased state.

[0090] Exemplarily, the first storage block may be a storage block in which the written user data part is invalid data and this part of the invalid data has been erased. It should be noted that when performing an erase operation on the storage, the basic unit to be erased can be the entire storage block or a part of the storage block. Here, when the written user data part is invalid data, the physical space within the storage block occupied by the invalid data to be erased needs to be greater than or equal to the physical space within the storage block occupied by the basic unit of erasure (here, the basic unit of erasure is a part of the storage block).

[0091] Considering that the longer the duration of maintaining the erased state, the higher the temperature during the maintaining process, and the better the data retention force for subsequent programming operations. Once it is determined that the amount of invalid data in a certain storage block is greater than or equal to the physical space within the storage block occupied by the basic unit of erasure, the erase operation can be performed on this storage block.

[0092] Based on this, in some embodiments, the memory controller 106 is configured to: when it is determined that there is at least a part of invalid data in the storage block in which user data is written among the multiple storage blocks, perform an erase operation on the storage block in which user data is written.

[0093] It can be understood that since the erase operation is performed in advance in this embodiment, subsequent to receiving a write command from the host system, the erase operation on the selected storage block is saved, improving the write operation efficiency of the memory system, that is, enhancing the write performance.

[0094] It should be noted that the erase scheme for invalid data in the embodiments of the present application is different from the working modes of the foregoing garbage collection module and wear leveling module. In the foregoing garbage collection and wear leveling, after the valid data in the source storage block is moved away, the valid data on the source storage block becomes invalid data, and this source storage block will be marked, and then the erase operation is performed when it is determined to be the selected storage block before the write operation. In the scheme of the embodiments of the present application, when the invalid data in the storage block reaches the minimum erasure unit, the erase is directly performed, not just marking, and the erase operation is not performed before the write operation. The first storage block may also be a storage block in which dummy data is written and this dummy data has been erased. Here, the dummy data is not user data, but meaningless data written into the storage block before leaving the factory to meet some special requirements of the memory. These storage blocks in which the data is written also belong to the first storage block after the erase operation.

[0095] Considering that the longer the duration of maintaining the erased state, the higher the temperature during the maintaining process, and the better the data retention force for subsequent programming operations. If each storage block of the memory system is not in the erased state when leaving the factory, then when the memory system is powered on for the first time after leaving the factory, an erase operation is performed on all storage blocks, and the temperature change situation experienced by each storage block in the erased state is recorded to provide a basis for subsequent calculation of data retention parameters.

[0096] Based on this, in some embodiments, the memory controller 106 is configured to: if all storage blocks are written with dummy data when the memory system leaves the factory, perform an erase operation on all the storage blocks when the memory system is powered on for the first time after leaving the factory.

[0097] The first storage block may also be a storage block that has not been written with data. A storage block that has not been written with data may also be referred to as a blank storage block or an idle storage block. These storage blocks may be in an erased state when the memory system 102 leaves the factory, and these storage blocks remain in the erased state until they are enabled after leaving the factory. These storage blocks may also be storage blocks detected to be in an erased state when the memory system is powered off after an erase operation and then powered on again currently.

[0098] It should be noted that when writing user data into the memory device, generally a storage block is filled up before a new storage block is opened. When a new storage block needs to be opened, it can be determined by comprehensively considering the data retention parameters of all the blank storage blocks currently in the memory system, the storage blocks that have been written with dummy data and the dummy data of which has been erased, and the storage blocks in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

[0099] In some embodiments, the data volume of the data to be written corresponding to the write command is greater than a preset threshold.

[0100] The write command may include a logical address and the corresponding data to be written. Here, the logical addresses included in the write command are consecutive, and the length of the logical address is long. Exemplarily, the data volume of the data to be written corresponding to the logical address is greater than or equal to the capacity of a storage block, or less than but close to the capacity of a storage block. That is to say, the preset threshold here is the capacity of a storage block or slightly less than the capacity of a storage block.

[0101] It can be understood that when the data volume of the data to be written corresponding to the write command is greater than the preset threshold, it belongs to the writing of more data. In the embodiments of the present application, when it is determined that at least part of the data in the storage block for writing user data among multiple storage blocks is invalid data, an erase operation is performed on the storage block for writing user data and it is prepared for subsequent use, so that after responding to the write command subsequently, the improvement in write performance and reliability generated by the solution of omitting the erase operation is more obvious.

[0102] In some embodiments, the memory controller is configured to: after receiving a write command, determine a data retention parameter for each first memory block to characterize the data retention performance of the corresponding first memory block; the larger the data retention parameter, the better the data retention ability of the corresponding first memory block. Determine a first memory block with the largest data retention parameter from the multiple first memory blocks as the second memory block, and the second memory block is the memory block to which data is to be written.

[0103] The specific determination method of the data retention parameter will be introduced in detail below.

[0104] In some embodiments, the memory controller 106 is configured to: in response to the first power-on of a memory block without written data or the completion of the erase operation of a memory block that has performed an erase operation, obtain the characteristic operating temperature of the memory system; obtain the retention duration of at least a part of the first memory block in the erased state; and determine the data retention parameter of the first memory block based on the characteristic operating temperature of the memory system and the retention duration of at least a part of the first memory block in the erased state.

[0105] Here, the acquisition of the data for calculating the data retention parameter can start from the first power-on of a memory block without written data or the completion of the erase operation of a memory block that has performed an erase operation. The memory block that has performed an erase operation can be the memory block that has written dummy data and the dummy data has been erased, or at least part of the written user data is invalid data and the at least part of the invalid data has been erased. Here, the retention duration of at least a part of the first memory block in the erased state can be understood as the time difference between the moment when the first power-on of a memory block without written data or the completion of the erase operation of a memory block that has performed an erase operation ends and the moment when the write command is received. The characteristic operating temperature of the memory system can be the operating temperature at the end of the erase or the average temperature during the retention duration of at least a part of the first memory block in the erased state.

[0106] In some specific embodiments, during the period when at least a part of the first memory block is in the erased state, the characteristic operating temperature of the memory system goes through multiple temperature intervals; the memory controller 106 is configured to: obtain the characteristic operating temperature of the memory system in each temperature interval; obtain the retention duration corresponding to each temperature interval in the multiple temperature intervals; sequentially determine the sub-data retention parameters corresponding to each temperature section in the multiple temperature intervals; wherein, for each temperature section, determine the sub-data retention parameter corresponding to the corresponding temperature section based on the characteristic operating temperature of the memory system in the corresponding temperature interval and the retention duration corresponding to the corresponding temperature interval; sum up the sub-data retention parameters corresponding to each temperature section to obtain the data retention parameter of the first memory block.

[0107] Here, the characteristic operating temperature of the memory system can be: the operating temperature collected for the first time when entering each temperature range, or the average temperature of each temperature range, or the specified temperature of each temperature range. The retention duration during which at least part of the corresponding first memory block is in the erased state is divided into the retention duration corresponding to each temperature range among multiple temperature ranges according to the multiple temperature ranges it has experienced.

[0108] For the case of experiencing multiple sub-temperature ranges, the sub-data retention parameters corresponding to each sub-temperature range can be calculated in sequence, and then the sum of the multiple sub-data retention parameters is obtained as the final data retention parameter. For the case of not subdividing the temperature range or for one sub-temperature range, the specific calculation method is similar.

[0109] In some embodiments, the memory controller 106 is configured such that the relationship between the data retention parameter, the characteristic operating temperature of the memory system, and the retention duration is as follows:

[0110]

[0111] where, t T1 is the data retention parameter, t T2 is the retention duration, T1 is the reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is the lifetime coefficient, and k is the Boltzmann constant.

[0112] In the embodiments of the present application, the data retention parameter is calculated using the formula to predict the data retention performance of the corresponding memory block. The larger the data retention parameter, the better the corresponding data retention performance. In the above calculation method, all the characteristic operating temperatures of the memory system are normalized to the reference temperature T1 for calculation. Exemplarily, the reference temperature T1 can be 40 °C. Here, Ea is the lifetime coefficient, with the unit of electron volt, which is associated with the data bits stored in the memory cell. Exemplarily, Ea is 1 electron volt.

[0113] In the embodiments of the present application, in response to the first power-on of the memory block without written data or the completion of the erase operation of the memory block that has performed the erase operation, the characteristic operating temperature (T2) of the memory system is obtained; the retention duration (t T2 ) of the characteristic operating temperature of the memory system is obtained; based on the characteristic operating temperature (T2) of the memory system and the retention duration (t T2 ), substituting into the above calculation formula, the data retention parameter t T1 is calculated.

[0114] In some specific embodiments, the operating temperature range of the memory system 102 can be divided into multiple temperature intervals. For example, the rated operating temperature range of the memory system 102 (such as -20°C to 80°C) is divided into temperature intervals of 80°C to 60°C, 60°C to 40°C, 40°C to 20°C, 20°C to 0°C, and 0°C to -20°C. At least a part of the first storage block experiences some or all of the above-mentioned multiple temperature intervals during the retention duration in the erased state. In response to the first power-on of a storage block without written data or the completion of the erase operation of a storage block that has performed an erase operation, record the retention duration of the characteristic operating temperature of the memory system within a certain temperature interval; based on the characteristic operating temperature of the memory system and the retention duration within each temperature interval (t T2 ), substitute into the above calculation formula to calculate the sub-data retention parameter t T1 ′ corresponding to each temperature interval. The sum of the sub-data retention parameters t T1 ′ corresponding to each temperature interval is used as the data retention parameter of the corresponding first storage block.

[0115] It should be noted that for T2 substituted into the formula for each temperature interval, it can be the value at which the temperature of the recorded memory system first enters a certain temperature interval. For example, when collecting temperature regularly, the temperature value of the memory system when it first enters the temperature interval of 60°C to 40°C is 55°C, then 55°C is used as T2 to substitute into the formula for calculation; for T2 substituted into the formula for each temperature interval, a specified value or preset value can also be set for each temperature interval. For example, the preset for 80°C to 60°C is 80°C, the preset for 60°C to 40°C is 60°C, the preset for 40°C to 20°C is 40°C, the preset for 20°C to 0°C is 20°C, and the preset for 0°C to -20°C is 0°C, and this preset value is used as T2 to substitute into the above formula for calculation; for T2 substituted into the formula for each temperature interval, it can also be the average value of each temperature interval. Correspondingly, for t T2 substituted into the formula for each temperature interval, it can be the time difference between the moment when the temperature of the recorded memory system first enters a certain temperature interval and the moment when it first enters the next temperature interval.

[0116] In some embodiments, the memory system 102 further includes: a temperature sensor configured to collect the operating temperature of the memory system; and the memory controller 106 configured to: based on the operating temperature of the temperature sensor, determine multiple operating temperatures of the memory system from the moment when the first power-on of a storage block without written data or the completion of the erase operation of a storage block that has performed an erase operation until the moment when the write command is received; and use the operating temperature of the memory system at the time of erase completion or the average value of the operating temperatures during the retention duration as the characteristic operating temperature of the memory system.

[0117] Here, a temperature sensor can be used to record the operating temperature of the memory system. The number of temperature sensors can be one or more. When multiple first storage blocks that are at least partially in the erased state record or collect the operating temperature of the corresponding memory system, they can share the measured value of one temperature sensor or use the average value of the measured values of multiple temperature sensors. The memory controller can periodically obtain the collected temperature values from the temperature sensor. The specific collection period can be adjusted according to the actual situation. The setting of the collection period should be related to the general temperature change rate of the memory system, and more specifically, it can be related to the setting of the temperature range. For example, within a temperature range, a corresponding number of temperature values generally need to be collected to achieve effective collection, and then the corresponding period setting should satisfy the collection of the temperature values of this data volume.

[0118] In some specific embodiments, the temperature sensor is coupled to the memory controller 106. The temperature sensor can be various types of temperature sensors that are easily integrated into the memory system 102. This type of temperature sensor can collect the temperature and transmit the collected temperature to the memory controller 106.

[0119] In some embodiments, the memory system 102 further includes: a timer configured to record a time difference; and the memory controller configured to: based on the time difference recorded by the timer, determine the time difference from the moment when the first storage block that has never been written with data is powered on for the first time or the moment when the erasure operation of the storage block that has performed the erasure operation is completed to the moment when the write command is received; and use the determined time difference as the retention duration.

[0120] Here, a timer can be used to record the time difference from the moment when the first storage block that has never been written with data is powered on for the first time or the moment when the erasure operation of the storage block that has performed the erasure operation is completed to the moment when the write command is received. The number of timers can be one or more. Each timer among the multiple timers can be respectively used to record the time difference of one first storage block.

[0121] In some specific embodiments, the timer can record specific moments, such as the moment when the first storage block that has never been written with data is powered on for the first time or the moment when the erasure operation of the storage block that has performed the erasure operation is completed (timestamp), and the moment when the first storage block receives the write command (timestamp), and obtain the time difference by taking the difference between these specific moments. The timer can also start timing from a specific moment, such as the moment when the first storage block that has never been written with data is powered on for the first time or the moment when the erasure operation of the storage block that has performed the erasure operation is completed, and then end the timing at the next specific moment, such as the moment when the first storage block receives the write command, so as to directly obtain the time difference between the two.

[0122] In some specific embodiments, the timer can be directly integrated into the firmware of the memory system.

[0123] Exemplarily, as Figure 10 shown, when all the data in a certain storage block (Block n) is invalid data, that is, there is no valid data, an erase operation is performed on Block n, and Block n after the erase operation is placed in the storage block pool (Blocktank). For each storage block in the storage block pool, it is necessary to use a temperature sensor to record the temperature change of each storage block, and use a timer to record the duration of each storage block in the erased state. It should be noted that for the aforementioned storage blocks that have not written data or have written dummy data and the dummy data has been erased, they can be placed in the storage block pool after the first power-on to monitor their temperature changes and the duration in the erased state. Subsequently, after receiving a write command, a corresponding second storage block can be selected from the storage block pool.

[0124] It should be noted that the temperature change situation experienced by the storage block in the erased state starts to be recorded again after each erase operation of the storage block. That is to say, when calculating the data retention parameter of the storage block, it is necessary to clear the relevant temperature data and the retention duration data recorded after the previous erase operation and this erase operation, so as to avoid selection errors caused by data accumulation.

[0125] In some embodiments, the memory system includes a Universal Flash Storage (UFS) device or a Solid State Disk (SSD). The memory device includes a NAND-type memory.

[0126] In the embodiments of the present application, when the memory controller in the memory system finds that the invalid data in the storage block reaches the erase minimum unit, an erase operation is performed on the storage block, and the storage block (the first storage block) is placed in the storage block pool. A temperature sensor is used to record the temperature change, and a timer is used to record the retention duration in the erased state for subsequent use. Subsequently, in response to a write command, the memory controller calculates the data retention parameter of each first storage block in the storage block pool, determines a first storage block with the largest data retention parameter from multiple first storage blocks as the second storage block, and writes the data to be written on the second storage block. In the embodiments of the present application, by selecting a first storage block with the largest data retention parameter, that is, the first storage block with the best data retention ability, from at least some of the first storage blocks in the erased state as the write storage block for data, the retention ability of the written data can be at a better level. In this way, the reliability of the data stored in the memory system can be improved. At the same time, it is also possible to save the operation of erasing and selecting storage blocks during the write operation, thereby improving the write performance of the memory system.

[0127] It should be noted that in the embodiments of the present application, in order to obtain better data retention, an erasure operation will be performed once it is found that the invalid data in the storage block reaches the minimum erasure unit. Subsequently, when performing a write operation, there is no need to perform an erasure operation again. However, for a newly opened storage block without user data written, a shallow erasure operation can be performed before writing data subsequently.

[0128] The embodiments of the present application also propose an operation method for a memory system. The operation method includes: in response to a write command, based on the data retention parameters of each storage block, determining a second storage block from multiple first storage blocks that are at least partially in an erased state among the multiple storage blocks of the memory system; the second storage block is the first storage block with the largest data retention parameter among the multiple first storage blocks; and writing the data to be written on the second storage block.

[0129] In some embodiments, referring to Figure 11 , Figure 11 is a schematic flowchart of the steps of the operation method of the memory system provided by an embodiment of the present disclosure. Among them, the operation method includes the following steps:

[0130] Step 1101: Receive a write command;

[0131] Step 1102: Based on the data retention parameters of each storage block, determine a second storage block from multiple first storage blocks that are at least partially in an erased state; the second storage block is the first storage block with the largest data retention parameter among the multiple first storage blocks;

[0132] Step 1103: Write the data to be written corresponding to the write command into the second storage block.

[0133] In some embodiments, the first storage block includes at least one of the following: a storage block without data written; a storage block with dummy data written and the dummy data has been erased; a storage block with at least part of the user data written being invalid data and the at least part of the invalid data has been erased.

[0134] In some embodiments, the method further includes: when it is determined that there is at least part of invalid data in the storage block with user data written among the multiple storage blocks of the memory system, performing an erasure operation on the storage block with user data written.

[0135] In some embodiments, the method further includes: if all storage blocks are written with dummy data when the memory system leaves the factory, performing an erasure operation on all storage blocks when the memory system is powered on for the first time after leaving the factory.

[0136] In some embodiments, the method further includes: in response to the first power-on of a storage block with no data written or the completion of an erase operation of a storage block that has performed an erase operation, obtaining a characteristic operating temperature of the memory system; obtaining a retention duration during which at least a part of the first storage block is in an erased state; and determining a data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration during which at least a part of the first storage block is in an erased state.

[0137] In some embodiments, during a period when at least a part of the first storage block is in an erased state, the characteristic operating temperature of the memory system experiences multiple temperature ranges; the obtaining of the characteristic operating temperature of the memory system includes: obtaining the characteristic operating temperature of the memory system in each temperature range; the obtaining of the retention duration during which at least a part of the first storage block is in an erased state includes: obtaining the retention duration corresponding to each temperature range among the multiple temperature ranges; the determining of the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration during which at least a part of the first storage block is in an erased state includes: sequentially determining sub-data retention parameters corresponding to each temperature range among the multiple temperature ranges; wherein, for each temperature range, determining the sub-data retention parameter corresponding to the corresponding temperature range based on the characteristic operating temperature of the memory system in the corresponding temperature range and the retention duration corresponding to the corresponding temperature range; and summing the sub-data retention parameters corresponding to each temperature range to obtain the data retention parameter of the first storage block.

[0138] In some embodiments, the determining of the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration during which at least a part of the first storage block is in an erased state includes: calculating the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration according to the following relational expression;

[0139]

[0140] wherein, t T1 is the data retention parameter, t T2 is the retention duration, T1 is a reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is a lifetime coefficient, and k is the Boltzmann constant.

[0141] In some embodiments, obtaining the characteristic operating temperature of the memory system includes: determining, based on the operating temperature of the memory system collected by a temperature sensor of the memory system, a plurality of operating temperatures of the memory system from the moment of first power-on of a storage block that has never had data written thereto or the moment when the erasure operation of a storage block that has executed an erasure operation is completed until the moment when the write command is received; and taking the average value of the operating temperature of the memory system at the end of erasure or the operating temperature during the holding period as the characteristic operating temperature of the memory system.

[0142] In some embodiments, obtaining the holding period during which at least a part of the first storage block is in an erased state includes: determining, based on the time difference recorded by a timer of the memory system, the time difference of the first storage block from the moment of first power-on of a storage block that has never had data written thereto or the moment when the erasure operation of a storage block that has executed an erasure operation is completed until the moment when the write command is received; and taking the determined time difference as the holding period.

[0143] In some embodiments, the invalid data includes data indicated by the host system to be erased, updated, or rewritten.

[0144] In some embodiments, the data volume of the data to be written corresponding to the write command is greater than a preset threshold.

[0145] It should be noted that the specific implementation of the operation method of the memory system in the above embodiments can be understood with reference to the specific implementation scheme for determining the storage mode described in the memory system in the foregoing embodiments.

[0146] An embodiment of the present application further provides a storage medium, on which executable instructions are stored, and when the executable instructions are executed, the steps of the method described in the embodiments of the present application can be implemented.

[0147] In some specific embodiments, the storage medium may be a ferromagnetic random access memory (FRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; it may also be various devices including one or any combination of the above memory devices.

[0148] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0149] As an example, the executable instructions may or may not correspond to a file in the file system, and may be stored as part of a file that holds other programs or data. For example, they may be stored in one or more scripts in a hypertext markup language (HTML) document, stored in a single file dedicated to the program in question, or stored in multiple cooperating files (e.g., files that store one or more modules, subroutines, or portions of code).

[0150] As an example, the executable instructions may be deployed to execute on one electronic device, or on multiple electronic devices located at one location, or, on multiple electronic devices distributed at multiple locations and interconnected by a communication network.

[0151] Figure 12Block diagram schematic of a readable storage medium provided by an embodiment of the present application. An embodiment of the present application provides a readable storage medium. The storage medium 1200 stores executable instructions 1201. When the executable instructions 1201 are executed by a processor, the operation method of the memory system in the above technical solution can be implemented. The operation method includes: determining the storage mode of the storage block based on the total amount of valid data in each storage block of the plurality of storage blocks; wherein, different storage modes perform data reading and writing at different rates by configuring the number of data bits stored in each storage unit in the storage block.

[0152] In the method embodiments provided by the present application, the disclosed methods can be arbitrarily combined without conflict to obtain new method embodiments. It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0153] In the several method embodiments provided by the present application, the disclosed methods can be arbitrarily combined without conflict to obtain new method embodiments.

[0154] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory system, characterized in that, it includes: a memory device including a plurality of memory blocks; a memory controller coupled to the memory device and configured to: in response to a write command, based on the data retention parameter of each memory block, determine a second memory block from a plurality of first memory blocks that are at least partially in an erased state among the plurality of memory blocks; the second memory block is the first memory block with the largest data retention parameter among the plurality of first memory blocks; and write the data to be written on the second memory block.

2. The memory system according to claim 1, characterized in that, the first memory block includes at least one of the following: a memory block that has not been written with data; a memory block that has been written with dummy data and the dummy data has been erased; a memory block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

3. The memory system according to claim 2, characterized in that, the memory controller is configured to: when it is determined that there is at least part of invalid data in the memory block written with user data among the plurality of memory blocks, perform an erase operation on the memory block written with user data.

4. The memory system according to claim 2, characterized in that, the memory controller is configured to: if all memory blocks are written with dummy data when the memory system leaves the factory, perform an erase operation on all memory blocks when the memory system is powered on for the first time after leaving the factory.

5. The memory system according to claim 2, characterized in that, the memory controller is configured to: in response to the first power-on of a memory block that has not been written with data or the completion of the erase operation of a memory block that has performed an erase operation, obtain the characteristic operating temperature of the memory system; obtain the retention duration of at least part of the first memory blocks that are in an erased state; and based on the characteristic operating temperature of the memory system and the retention duration of at least part of the first memory blocks that are in an erased state, determine the data retention parameter of the first memory block.

6. The memory system according to claim 5, characterized in that, during the period when at least part of the first memory blocks are in an erased state, the characteristic operating temperature of the memory system experiences multiple temperature ranges; the memory controller is configured to: obtain the characteristic operating temperature of the memory system in each temperature range; obtain the retention duration corresponding to each temperature range in the multiple temperature ranges; successively determine the sub-data retention parameters corresponding to each temperature section in the multiple temperature ranges; wherein, for each temperature section, based on the characteristic operating temperature of the memory system in the corresponding temperature range and the retention duration corresponding to the corresponding temperature range, determine the sub-data retention parameter corresponding to the corresponding temperature section; sum the sub-data retention parameters corresponding to each temperature section to obtain the data retention parameter of the first memory block.

7. The memory system according to claim 5, characterized in that, the memory controller is configured to: the relationship between the data retention parameter and the characteristic operating temperature and retention duration of the memory system is as follows: where t T1 is the data retention parameter, t T2 is the retention duration, T1 is the reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is the lifetime coefficient, and k is the Boltzmann constant.

8. The memory system according to claim 5, Characterized in that, the memory system further includes: a temperature sensor, the temperature sensor is configured to: collect the operating temperature of the memory system; the memory controller is configured to: based on the operating temperature of the memory system collected by the temperature sensor, determine the multiple operating temperatures of the memory system from the moment of the first power-on of the storage block that has never written data or the moment of completion of the erase operation of the storage block that has performed the erase operation until the moment of receiving the write command; and use the average value of the operating temperature of the memory system at the time of completion of the erase or the operating temperature during the holding period as the characteristic operating temperature of the memory system.

9. The memory system according to claim 5, Characterized in that, the memory system further includes: a timer, the timer is configured to: record the time difference; the memory controller is configured to: based on the time difference recorded by the timer, determine the time difference of the first storage block from the moment of the first power-on of the storage block that has never written data or the moment of completion of the erase operation of the storage block that has performed the erase operation until the moment of receiving the write command; and use the determined time difference as the holding period.

10. The memory system according to claim 2, Characterized in that, the invalid data includes data indicated by the host system to be erased, updated or rewritten.

11. The memory system according to claim 1, Characterized in that, the data volume of the data to be written corresponding to the write command is greater than a preset threshold.

12. An operation method of a memory system, Characterized in that, including: in response to a write command, based on the data retention parameter of each storage block, determine a second storage block from multiple first storage blocks that are at least partially in an erased state among the multiple storage blocks of the memory system; the second storage block is the first storage block with the largest data retention parameter among the multiple first storage blocks; and write the data to be written on the second storage block.

13. The operation method according to claim 12, Characterized in that, the first storage block includes at least one of the following: a storage block that has not written data; a storage block that has written dummy data and the dummy data has been erased; a storage block in which at least part of the written user data is invalid data and the at least part of the invalid data has been erased.

14. The operation method according to claim 13, Characterized in that, the method further includes: when it is determined that there is at least part of invalid data in the storage block that has written user data among the multiple storage blocks of the memory system, perform an erase operation on the storage block that has written user data.

15. The operation method according to claim 13, Characterized in that, the method further includes: if all storage blocks are written with dummy data when the memory system leaves the factory, perform an erase operation on all storage blocks when the memory system is powered on for the first time after leaving the factory.

16. The operation method according to claim 13, Characterized in that, the method further includes: Upon the first power-on of a storage block with no written data or upon completion of an erase operation of a storage block that has undergone an erase operation, obtain the characteristic operating temperature of the memory system; Obtain the retention duration during which at least a portion of the first storage block is in an erased state; and Based on the characteristic operating temperature of the memory system and the retention duration during which at least a portion of the first storage block is in an erased state, determine the data retention parameter of the first storage block.

17. The operation method according to claim 16, wherein, During the period when at least a portion of the first storage block is in an erased state, the characteristic operating temperature of the memory system experiences multiple temperature ranges; The obtaining of the characteristic operating temperature of the memory system includes: obtaining the characteristic operating temperature of the memory system in each temperature range; The obtaining of the retention duration during which at least a portion of the first storage block is in an erased state includes: obtaining the retention duration corresponding to each temperature range among the multiple temperature ranges; The determining of the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration during which at least a portion of the first storage block is in an erased state includes: Sequentially determining the sub-data retention parameters corresponding to each temperature segment among the multiple temperature ranges; wherein, for each temperature segment, based on the characteristic operating temperature of the memory system in the corresponding temperature range and the retention duration corresponding to the corresponding temperature range, determine the sub-data retention parameter corresponding to the corresponding temperature segment; and Sum the sub-data retention parameters corresponding to each temperature segment to obtain the data retention parameter of the first storage block.

18. The operation method according to claim 16, wherein, The determining of the data retention parameter of the first storage block based on the characteristic operating temperature of the memory system and the retention duration during which at least a portion of the first storage block is in an erased state includes: Based on the characteristic operating temperature of the memory system and the retention duration, calculate the data retention parameter of the first storage block according to the following relational expression; where t T1 is the data retention parameter, t T2 is the retention duration, T1 is the reference temperature, T2 is the characteristic operating temperature of the memory system, Ea is the lifetime coefficient, and k is the Boltzmann constant.

19. The operation method according to claim 16, wherein, The obtaining of the characteristic operating temperature of the memory system includes: Based on the operating temperature of the memory system collected by the temperature sensor of the memory system, determine multiple operating temperatures of the memory system from the moment of the first power-on of a storage block with no written data or the completion of the erase operation of a storage block that has undergone an erase operation until the moment of receiving the write command; and Take the average value of the operating temperature of the memory system at the time of erase completion or the operating temperature during the retention duration as the characteristic operating temperature of the memory system.

20. The operation method according to claim 16, wherein, The obtaining of the retention duration during which at least a portion of the first storage block is in an erased state includes: Based on the time difference recorded by the timer of the memory system, determine the time difference of the first storage block from the moment of the first power-on of a storage block with no written data or the completion of the erase operation of a storage block that has undergone an erase operation until the moment of receiving the write command; and Take the determined time difference as the retention duration.

21. The operation method according to claim 13, wherein, the invalid data includes data indicated by the host system to be erased, updated or rewritten.

22. The operation method according to claim 12, wherein, the data volume of the data to be written corresponding to the write command is greater than a preset threshold.

23. A storage medium, wherein, executable instructions are stored on the storage medium, and when the executable instructions are executed, the steps of the method according to any one of claims 12-22 can be implemented.

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