Data storage device ensuring programming sequence and operation method thereof

Abstract

The invention provides a data storage device capable of ensuring a program order and an operation method thereof. The data storage device comprises a storage device; a buffer memory device configured to temporarily store write data and a mapping table; and a memory controller configured to control the storage device to program the write data. The memory controller is configured to store logical addresses by mapping the logical addresses to physical addresses sequentially stored in a mapping table in an order in which write commands are received when write commands including the logical addresses are received from the outside, and to store the logical addresses by mapping the logical addresses to the physical addresses sequentially stored in the mapping table when a program operation corresponding to a first write command fails. First mapping information corresponding to the first write command is invalidated, and the first mapping information is updated by assigning a new physical address to a logical address included in the first write command in response to a reprogram command generated for the first write command.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0169744, filed on November 29, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor integrated device, and more particularly, to a data storage device for correcting a programming order and an operation method thereof. Background Art

[0004] A computer system uses a buffer memory to reduce a bottleneck phenomenon caused by a difference in operation speeds between devices that send and receive data from each other.

[0005] A data storage device that performs data input and output operations in response to a request from an external device uses a volatile or non - volatile memory device as a storage medium. Problems caused by a difference in data transfer speeds of devices included in the data storage device can be solved by adopting a buffer memory.

[0006] The data storage device needs to store data cached in the buffer memory in the storage device according to the write order requested by the external device. Summary of the Invention

[0007] Embodiments of the present technology may provide a data storage device and an operation method thereof that guarantee a programming order by managing mapping data so that data is stored in the order requested by an external device.

[0008] In an embodiment, a data storage device may include: a storage device; a buffer memory device configured to temporarily store write data and a mapping table; and a memory controller configured to control the storage device to program the write data. The memory controller is configured to: when a write command including a logical address is received from the outside, store the logical address by mapping the logical address to a physical address sequentially stored in the mapping table in the order in which the write command is received, and when a programming operation corresponding to a first write command fails, invalidate first mapping information corresponding to the first write command and update the first mapping information by allocating a new physical address to the logical address included in the first write command in response to a reprogramming command generated for the first write command.

[0009] In an embodiment, an operation method of a data storage device may include: in response to a write command including a logical address received from the outside, temporarily storing write data and a mapping table in a buffer memory device by using a memory controller; storing the logical address by using the memory controller by mapping the logical address to a physical address sequentially stored in the mapping table in the order in which the write command is received; controlling, by the memory controller, a storage device to program the write data; invalidating, by the memory controller, first mapping information corresponding to a first write command according to a determination result that a programming operation corresponding to the first write command fails; and updating, by the memory controller, the first mapping information by allocating a new physical address to the logical address included in the first write command in response to a reprogramming command generated for the first write command.

[0010] In an embodiment, a data storage device may include: a storage device including a plurality of storage blocks; a buffer memory device configured to temporarily store first write data and second write data; a buffer manager configured to manage the buffer memory device in a scatter-gather manner; and a memory controller. The memory controller is configured to: control the storage device to program the first write data and the second write data provided in sequence, invalidate first mapping information corresponding to the first write data when programming of the first write data fails and programming of the second write data succeeds, and update the first mapping information by allocating a new storage block into which the first write data will be reprogrammed.

[0011] According to an embodiment of the present disclosure, only a failed programming operation can be selectively executed again, and the programming order requested by an external device can also be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a configuration of a data storage device according to an embodiment of the present disclosure.

[0013] Figures 2A to 2C is a diagram for describing a buffer management method using a scatter-gather buffer method according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram showing a configuration of a memory controller according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram for describing a buffer management method using a multi-buffer method according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram for describing a method of managing a mapping table according to an embodiment of the present disclosure.

[0017] Figure 6 is a diagram showing the configuration of a memory controller according to an embodiment of the present disclosure.

[0018] Figures 7A to 7D is a diagram for describing the operation of a reprogramming circuit according to an embodiment of the present disclosure.

[0019] Figures 8 to 10 is a flowchart for describing a method of operating a data storage device according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a diagram showing the configuration of a data storage device 10 according to an embodiment of the present disclosure.

[0022] Referring to Figure 1 , the data storage device 10 may include a memory controller 100 and a storage device 200. The data storage device 10 may be electrically connected to an external device such as a host, and may exchange data with the external device.

[0023] The external device may be selected from various types of computing systems such as: personal computers, laptop computers, server computers, workstations, tablet PCs, drones, advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, image display devices, measurement devices, Internet of Things (IoT) devices.

[0024] The storage device 200 may include at least one of a volatile memory device and a non-volatile memory device. The storage device 200 may be coupled to the memory controller 100 through a plurality of channels CH1, CH2, CH3 to CHm, and may include a plurality of memory chips CHIP or a plurality of packages. The memory chip CHIP may include a plurality of memory dies. Each memory die may include one or more planes. Each plane may include one or more storage blocks. Each storage block may be composed of a plurality of pages. Physical addresses may be assigned to the memory regions constituting the storage device 200, such as pages, blocks, planes, or dies.

[0025] The memory controller 100 may control the storage device 200 in response to an external request. For example, the memory controller 100 may program data into the storage device 200 in response to a write request from the outside. The memory controller 100 may read the data written in the storage device 200 and provide the read data to the outside in response to a read request from the outside.

[0026] The memory controller 100 may include at least one processor 111, an external interface 113, a storage interface 115, a buffer manager 117, a first memory device 121, and a second memory device 123. The first memory device 121 and the second memory device 123 may be collectively referred to as a buffer memory device 120.

[0027] The processor 111 may be configured to operate in hardware when the processor 111 runs firmware or software provided for various operations of the data storage device 10. The processor 111 may be implemented in a form combining hardware and firmware or software running on the hardware. In an embodiment, the processor 111 may execute functions for managing a flash translation layer (FTL) of the storage device 200, such as address mapping, block management, garbage collection, or wear leveling.

[0028] Under the control of the processor 111, the external interface 113 may receive commands and clock signals from an external device, and provide a communication channel for controlling input and output of data. Specifically, the external interface 113 may provide a physical connection between the external device and the data storage device 10.

[0029] Under the control of the processor 111, the external interface 113 may temporarily store write data provided by an external device in the buffer memory device 120, which is selected from the first memory device 121 and the second memory device 123. In addition, the external interface 113 may provide read data read from the storage device 200 and temporarily stored in the buffer memory device 120 to the external device.

[0030] In an embodiment, the external interface 113 may communicate with an external device based on an interface using at least one of various communication standards or interfaces such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High-Speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocol, System Management Bus (SMBus) protocol, Inter-Integrated Circuit (I2C) protocol, and Improved Inter-Integrated Circuit (I3C) protocol.

[0031] The storage interface 115 may provide a communication channel for transmitting and receiving signals between the memory controller 100 and the storage device 200. The storage interface 115 may write the data temporarily stored in the buffer memory device 120 to the storage device 200 under the control of the processor 111. In addition, the storage interface 115 may temporarily store the read data in the buffer memory 120 by passing the read data read from the storage device 200 to the buffer memory device 120 under the control of the processor 111.

[0032] The buffer manager 117 may be configured to control the buffer memory device 120 under the control of the processor 111.

[0033] The buffer manager 117 may divide the buffer memory device 120 into a plurality of regions (or slots), and may allocate or release each region for temporarily storing data. Allocating a region may refer to a state in which data is stored in the corresponding region or a state in which the data stored in the corresponding region is valid. Releasing a region may refer to a state in which data is not stored in the corresponding region or a state in which the data stored in the corresponding region is invalid. In the following description, deleting the data stored in the buffer memory device 120 and releasing the slot of the buffer memory device 120 may be regarded as having the same meaning.

[0034] The first memory device 121 may be disposed inside the memory controller 100. The second memory device 121 may be disposed outside the memory controller 100. In an embodiment, one of the first memory device 121 and the second memory device 123 may be SRAM and the other may be DRAM. However, the configuration of the buffer memory device 120 is not limited to the above configuration.

[0035] Figures 2A to 2C is a diagram for describing a buffer management method using a scatter-gather buffer method according to an embodiment of the present disclosure.

[0036] Representative examples of the manner (i.e., mode or method) of managing the buffer memory device 120 may include a circular buffer method and a scatter-gather method.

[0037] When programming the data requested to be written by an external device into the storage device 200, the data for which programming fails may remain in the buffer memory device 120. According to the manner of managing the buffer memory device 120, the normally programmed data may or may not remain in the buffer memory device 120.

[0038] For example, if the buffer memory device 120 is managed in a circular buffer manner, when the data cached in the buffer memory device 120 is normally programmed into the storage device 200, the memory controller 100 may release the slot storing the cached data in the buffer memory device 120. However, the memory controller 100 may release the slots in the order in which the data is cached in the buffer memory device 120. That is, in the circular buffer mode, when the programming of the data cached in the buffer memory device 120 fails, the memory controller 100 may keep (i.e., retain) the data with programming failure and the data subsequently cached in the buffer memory device 120 in a valid state regardless of whether the programming is successful.

[0039] For example, if the buffer memory device 120 is managed in a scatter-gather manner, the memory controller 100 may delete the normally programmed data from the buffer memory device 120 and may keep the data with programming failure in the buffer memory device 120.

[0040] Figure 2A A scatter-gather buffer memory device 1251 and a status table 1253 of the scatter-gather buffer memory device 1251 are shown.

[0041] Exemplarily, the scatter-gather buffer memory device 1251 may include regions corresponding to a first index INDEX1 to an eighth index INDEX8 respectively. The memory controller 100 may cache first data DATA1 to eighth data DATA8 into the scatter-gather buffer memory device 1251.

[0042] The memory controller 100 may divide the regions of the scatter-gather buffer memory device 1251 to indicate the regions as indexes INDEX. The memory controller 100 may write status information STATUS and data information DATA in the status table 1253, where the status information STATUS indicates whether data is cached in the region corresponding to each index INDEX, and the data information DATA is related to the data cached in the region corresponding to the index INDEX. For example, if data is cached in the region corresponding to the index INDEX, the memory controller 100 may write the value "1" in the status information STATUS, and if data is not cached in the region corresponding to the index INDEX, the memory controller 100 may write the value "0" in the status information STATUS.

[0043] Refer to Figure 2A, after caching the first data DATA1 to the eighth data DATA8 into the regions corresponding to the first index INDEX1 to the eighth index INDEX8 in the scatter-gather buffer memory device 1251 respectively, the memory controller 100 may write the value "1" into all the status information STATUS corresponding to the first index INDEX1 to the eighth index INDEX8 in the status table 1253 respectively. In addition, the memory controller 100 may write the first data DATA1 to the eighth data DATA8 cached in the regions corresponding to the first index INDEX1 to the eighth index INDEX8 in the scatter-gather buffer memory device 1251 into the data information DATA corresponding to the first index INDEX1 to the eighth index INDEX8 in the status table 1253.

[0044] Figure 2B FIG. shows the scatter-gather buffer memory device 1261 and the status table 1263 after the programming of the cached data is executed normally.

[0045] When the storage device 200 programs the data cached in the scatter-gather buffer memory device 1261 normally regardless of the order of the data cached in the scatter-gather buffer memory device 1261, the memory controller 100 may delete the normally programmed data from the scatter-gather buffer memory device 1261.

[0046] Refer to Figure 2B , if the programming operation of the first data DATA1 cached in the region corresponding to the first index INDEX1 in the scatter-gather buffer memory device 1261 fails, and the programming operation of the second data DATA2 cached in the region corresponding to the eighth index INDEX8 in the scatter-gather buffer memory device 1261 succeeds, the memory controller 100 may delete the successfully programmed second data DATA2 from the scatter-gather buffer memory device 1261, although the second data DATA2 is cached after the first data DATA1, and the memory controller 100 may keep (i.e., retain) the first data DATA1 with the failed programming operation in the scatter-gather buffer memory device 1261. The memory controller 100 may change the status information STATUS corresponding to the eighth index INDEX8 in the status table 1263 to the value "0", and may change the data information DATA corresponding to the eighth index INDEX8 in the status table 1263 to the NULL value.

[0047] Figure 2C FIG. shows the scatter-gather buffer memory device 1271 and the status table 1273 after the new data provided by the external device is cached after the cached data is deleted.

[0048] After deleting the second data DATA2, the memory controller 100 may cache the ninth data DATA9, i.e., new data provided by an external device, into a region corresponding to the eighth index INDEX in the scatter-gather buffer memory device 1271. The memory controller 100 may update the status table 1273 by changing the data information DATA corresponding to the eighth index INDEX8 in the status table 1273 to the ninth data DATA9 and changing the status information STATUS corresponding to the eighth index INDEX8 in the status table 1273 to the value "1".

[0049] In the case of the circular buffer mode, data subsequently cached into the buffer memory device 120 is held in the buffer memory device 120 until the data previously cached into the buffer memory device 120 is successfully programmed, regardless of whether the programming operation for the subsequently cached data is successful.

[0050] In the case of the scatter-gather mode, limited buffer space can be effectively managed because data that has been successfully programmed is deleted from the buffer memory device 120 and data that has failed to be programmed is held in the buffer memory device 120 without considering the order of the buffered data.

[0051] The controller 100 may be configured to reprogram data that has failed to be programmed by using only the data held in the buffer memory device 120 based on the order requested by the external device.

[0052] Figure 3 is a diagram showing the configuration of a memory controller 100-1 according to an embodiment of the present disclosure.

[0053] Referring to Figure 3 , the memory controller 100-1 may include a command conversion circuit 151, a buffer manager 117, a mapping table manager 153, and a buffer memory device 120-1.

[0054] The command conversion circuit 151 may assign a sequence number to commands received from an external device in the order in which the commands are received, and may classify the commands based on the attributes of the commands.

[0055] In an embodiment, a multi-buffer mode may be adopted to manage the buffer memory device 120-1, in which the buffer memory device 120-1 is divided into a plurality of buffer spaces. The commands classified by the command conversion circuit 151 may be cached into buffer spaces corresponding to the attributes of the commands.

[0056] Attributes of the command may include normal attributes corresponding to a normal write operation and write enhancement attributes corresponding to an operation of preferentially storing data or storing data at a faster speed than other data, but embodiments of the present disclosure are not limited thereto.

[0057] The buffer manager 117 may divide the buffer memory device 120-1 into a first buffer 310, a second buffer 320, and a mapping table 330. The first buffer 310 and the second buffer 320 may be collectively referred to as a write buffer.

[0058] In an embodiment, the memory controller 100-1 may control the first buffer 310 to cache write data having normal attributes, and may control the second buffer 320 to cache write data having write enhancement attributes. Mapping data, that is, a set of mapping information between a logical address used by an external device and a physical address used by the storage device 200, may be cached in the mapping table 330.

[0059] The mapping information may represent a pair consisting of a physical address and a logical address corresponding to the physical address. The mapping data may represent a set of multiple pieces of mapping information.

[0060] When a set flush event is triggered, the buffer manager 117 may flush the write data stored in the first buffer 310 or the second buffer 320 or the mapping data stored in the mapping table 330 to the storage device 200.

[0061] Events for flushing write data may include a case where one of the first buffer 310 or the second buffer 320 is full, a case where a logical address has been mapped to all physical addresses included in the mapping table 330, and a case where a write command for write data having a capacity greater than the remaining capacity of the buffer memory device 120-1 is received from an external device.

[0062] After the start of a write operation, the mapping table manager 153 may load mapping data onto the mapping table 330, the mapping data including information on physical addresses of open blocks allocated to the storage device 200. The mapping table manager 153 may update the mapping table 330 by mapping logical addresses to physical addresses stored in order in the mapping table 330 in the order in which write commands are received from an external device.

[0063] That is, when a write command is received, the mapping table manager 153 may map logical addresses to the write commands in the order in which the mapping table 330 receives the write commands, where the mapping table 330 includes physical addresses stored in order.

[0064] Figure 4It is a diagram for describing a buffer management method using a multi-buffer method according to an embodiment of the present disclosure.

[0065] Referring to Figure 4 , the command conversion circuit 151 can classify the command CMD based on the attribute of the command CMD received from an external device, and can add a flag 0 or 1 to the command based on the classified attribute. For example, the command conversion circuit 151 can classify the attribute of writing data into a normal attribute and a write enhancement attribute, can assign the flag "0" to the write data with the normal attribute, and can assign the flag "1" to the write data with the write enhancement attribute.

[0066] The buffer manager 117 can control the buffer memory device 120-1 so that the data classified by the command conversion circuit 151 is stored in the corresponding buffer space. For example, the buffer manager 117 can control the buffer memory device 120-1 so that the write data 71 whose attribute corresponds to the flag "0" is stored in the first buffer 310, and the write data 72 whose attribute corresponds to the flag "1" is stored in the second buffer 320.

[0067] The command conversion circuit 151 can assign a sequence number Seq to each command CMD in the order in which the command CMD is received from an external device. In this case, the sequence number Seq can represent the order of the commands input to the memory controller 100, and can be used to divide old data and new data. Figure 4 Ten commands respectively assigned sequence numbers Seq from "0" to "9" are shown. The command CMD with the sequence number Seq of "0" can be a command CMD that is input to the memory controller 100 earlier than the command with the sequence number Seq of "9".

[0068] Figure 5 It is a diagram for describing a method of managing a mapping table according to an embodiment of the present disclosure.

[0069] Referring to Figure 5 , the mapping table 330 can be divided into multiple sections SECT.

[0070] When a write command CMD is received from an external device, the mapping table manager 153 can load mapping data onto the mapping table 330 in which the physical addresses PPN1 to PPN10 of open blocks are stored in sequence, and the mapping table manager 153 can sequentially assign the sections SECT of the mapping table 330 to the physical addresses PPN1 to PPN10 in the order in which the write command CMD is received. The mapping information to which the logical addresses LBA 1 to LBA 10 respectively corresponding to the write command CMD are mapped can be stored in the physical addresses PPN1 to PPN10 of the corresponding sections SECT.

[0071] The mapping table manager 153 may sequentially assign the sections SECT of the mapping table 330 to the sequence numbers Seq such that the sections SECT correspond to the sequence of the sequence numbers Seq assigned to the command CMD.

[0072] As described above, when the write command CMD and the logical addresses LBA 1 to LBA 10 corresponding to the write command CMD are received from an external device, the memory controller 100 may update the mapping table 330 by mapping the received logical addresses LBA 1 to LBA 10 to the physical addresses PPN1 to PPN10, respectively.

[0073] The mapping table 330 may have a physical address to logical address (P2L) form, including information about the corresponding logical addresses LBA1 to LBA 10 in the order of the physical addresses PPN1 to PPN10.

[0074] In an embodiment, when the write data cached in the first buffer 310 and / or the second buffer 320 is flushed to the storage device 200, the mapping table manager 513 may back up the mapping data corresponding to the flushed write data to the storage device 200.

[0075] For example, when the first buffer 310 storing the write data corresponding to the command with the attribute of "0" is to be flushed, the mapping table manager 153 may back up the mapping data with the sequence numbers Seq of "0", "3", "4", "6", "7", "8" stored in the first buffer 310 to the storage device 200.

[0076] Figure 6 It is a diagram showing the configuration of the memory controller 100-2 according to an embodiment of the present disclosure.

[0077] Referring to Figure 6 , the memory controller 100-2 may include a command conversion circuit 151, a buffer manager 117, a mapping table manager 153, a reprogramming circuit 155, and a buffer memory device 120-1.

[0078] The command conversion circuit 151, the buffer manager 117, the mapping table manager 153, and the buffer memory device 120-1 may be constructed the same as or similarly to the corresponding components described with reference to Figure 3 .

[0079] The command conversion circuit 151 may assign a sequence number to the commands received from an external device in the order of the received commands, and may classify the commands based on the attributes of the commands.

[0080] When a write command is received, the mapping table manager 153 may load mapping information onto the mapping table 330, which includes the physical addresses of open blocks allocated for writing data, and the mapping table manager 153 may update the mapping table 330 by mapping logical addresses to the physical addresses of the mapping table 330 in the order in which the write commands are received.

[0081] When a flush event is triggered, the buffer manager 117 may control the storage device 200 such that the storage device 200 programs the write data by flushing the write data cached in the buffer memory device 120-1 to the storage device 200.

[0082] The storage device 200 may program the write data and send information on whether the programming is successful to the memory controller 100-2 as a response.

[0083] When the programming is successful, the mapping table manager 153 may back up the mapping data corresponding to the flushed write data to the storage device 200.

[0084] When the programming fails, error handling operations may be performed by the reprogramming circuit 155.

[0085] The reprogramming circuit 155 may reprogram the write data for which the programming has failed into the storage device 200.

[0086] When the storage device 200 reports a programming failure, the reprogramming circuit 155 may back up the mapping data, i.e., a set of invalid mapping information cached in the mapping table 300 and related to the failed write command, to the storage device 200.

[0087] The reprogramming circuit 155 may generate a reprogramming command based on the failed write command. Thus, an open block may be allocated, and the write data corresponding to the failed write command will be programmed into the open block. The reprogramming circuit 155 may update the mapping information of the mapping table 330 based on the physical address corresponding to the allocated open block and may request programming from the storage device 200 based on the updated mapping information.

[0088] Thus, the mapping data matching the order in which the write commands are received may be stored in the mapping table 330.

[0089] Figures 7A to 7D is a diagram for describing the operation of a reprogramming circuit according to an embodiment of the present disclosure.

[0090] Refer to Figure 7A, the first write data DATA11 to the fourth write data DATA14 can be cached in buffer 310 or 320 in the order in which the write commands are received. The mapping data P2L, that is, a set of mapping information corresponding to the first write data DATA11 to the fourth write data DATA14, can be stored in the mapping table 330.

[0091] The mapping data P2L of the mapping table 330 can be generated by updating the logical addresses LBA 11 to LBA 14 in the order in which the write commands are received for the physical addresses PPN 11 to PPN 14 of the open blocks in which the write data is to be programmed.

[0092] When a flush event is triggered, the write data in buffer 310 or 320 can be flushed to the storage device 200. The storage device 200 can send information on whether the programming was successful to the memory controller 100 as a response.

[0093] In this case, the programming of the write data DATA11, DATA13, and DATA14 can be successful, and the programming of the write data DATA12 can be failed.

[0094] Refer to Figure 7B , the buffer manager 117 can release the slots in buffer 310 or 320 corresponding to the write data DATA11, DATA13, and DATA14 for which the programming was successful, and can hold (i.e., retain) the write data DATA12 for which the programming was failed in buffer 310 or 320.

[0095] The reprogramming circuit 155 can invalidate (INV) the mapping information corresponding to the write command for which the programming was failed, and can back up the mapping data including the invalid mapping information in the mapping table 330 to the mapping block 210 of the storage device 200.

[0096] The reprogramming circuit 155 can generate and run a reprogramming command for the write data DATA12 for which the programming was failed so that an open block can be allocated.

[0097] Refer to Figure 7C , the reprogramming circuit 155 can load the mapping data from the mapping block 210 to the mapping table 330. In addition, the reprogramming circuit 155 can update the mapping information in the mapping table 330 by storing the physical address new PPN of the open block allocated for reprogramming according to the invalid logical address LBA 12.

[0098] The reprogramming circuit 155 can request reprogramming REPGM from the storage device 200 based on the updated mapping data.

[0099] When the reprogramming of the second data DATA12 is successful, as Figure 7D shown, the slot in buffer 310 or 320 that stores the second data DATA12 can be released, and the updated mapping data can be backed up to the mapping block 210.

[0100] Therefore, the mapping data that matches the order in which the write commands are received can be stored in the mapping block 210.

[0101] Figures 8 to 10 is a flowchart for describing an operation method of a data storage device according to an embodiment of the present disclosure.

[0102] Figure 8 is a flowchart for describing a write method according to an embodiment of the present disclosure.

[0103] When a write command is received from an external device (S101), the memory controller 100 may request a programming operation from the storage device 200 by processing the write command (S103). The process S103 of processing the write command will be described later with reference to Figure 9 described.

[0104] The memory controller 100 may check whether the programming operation according to the processing of the write command is successful (S105). When the programming operation is successful (i.e., "Yes" in S105), the memory controller 100 may back up the mapping data of the mapping table 330 to the storage device 200 (S107). In addition, the memory controller 100 may release the slot in the buffer that stores the write data for which the programming operation is successful.

[0105] When the programming operation fails (i.e., "No" in S105), the memory controller 100 may hold the write data for which the programming operation fails in the buffer slot, may reprogram the write data (S109), and may check whether the programming operation for the write data is successful (S105).

[0106] The reprogramming process S109 will be described later with reference to Figure 10 described.

[0107] Figure 9 is a flow for describing a process of processing a write command according to an embodiment of the present disclosure.

[0108] The memory controller 100 may analyze the write command received from the external device. For example, the memory controller 100 may assign a sequence number to each command in the order in which the commands are received, and may classify the commands based on the attributes of the commands (S201).

[0109] Commands corresponding to write commands can be cached in buffer spaces corresponding to classification attributes based on their sequence numbers (S203).

[0110] The memory controller 100 can allocate an open block in which write data will be programmed and can update the mapping table 330 (S205). In an embodiment, the memory controller 100 can load mapping data including information about the physical address of the allocated open block onto the mapping table 330 and can update the mapping table 330 by storing logical addresses in the mapping table 330 in the order in which write commands are received.

[0111] The memory controller 100 can determine whether an event to flush write data is triggered (S207).

[0112] The event to flush write data can include a case where one of the first buffer 310 or the second buffer 320 is full, a case where a logical address has been mapped to all physical addresses included in the mapping table 330, and a case where a write command for write data having a capacity greater than the remaining capacity of the buffer memory device 120-1 is received from an external device.

[0113] When the event to flush write data is triggered (i.e., "Yes" in S207), the memory controller 100 can flush the write data to the storage device 200, that is, can request programming from the storage device 200 (S209) and can check whether the programming is successful (S105).

[0114] When the event to flush write data is not triggered (i.e., "No" in S207), the state of the memory controller 100 can transition to a standby state (S211).

[0115] Figure 10 is a flowchart for describing a reprogramming process according to an embodiment of the present disclosure.

[0116] When the storage device 200 reports that a programming operation of write data has failed, the memory controller 100 can invalidate mapping information corresponding to the failed programming operation (S301).

[0117] The controller 100 can back up mapping data including invalid mapping information in the mapping table 330 to the storage device 200 (S303).

[0118] The memory controller 100 can generate a reprogramming command for write data for which a programming operation has failed and can determine whether the write data is in a state where the write data can be reprogrammed (S307). For example, the memory controller 100 can determine whether the memory controller 100 is in an idle state.

[0119] When the written data is not in a state where the written data can be reprogrammed (i.e., "No" in S307), the memory controller 100 can continue to monitor the written data (S307). When the written data is in a state where the written data can be reprogrammed (i.e., "Yes" in S307), the memory controller 100 can update the mapping table 330 by allocating an open block that will perform the reprogramming (S309).

[0120] To update the mapping table 330, the memory controller 100 can load the mapping data of the storage device 200 onto the mapping table 330, and can change the mapping information of the mapping table 330 based on the physical address of the open block allocated for reprogramming.

[0121] The memory controller 100 can request reprogramming from the storage device 200 based on the updated mapping information (S311). In addition, the memory controller 100 can check whether the programming is successful (S105).

[0122] When the reprogramming is successful, the memory controller 100 can back up the mapping data including the updated mapping information to the storage device 200. Therefore, the mapping data matching the order in which the write commands are received can be stored in the storage device 200.

[0123] In a scatter-gather buffer manner configured to release the write buffer corresponding to the write command with successful programming, the memory controller 100 can map the write commands to physical addresses in the order in which the write commands are received.

[0124] When the data in the write buffer is emptied, if the programming operation of a certain written data fails, the mapping table can be updated as described above. Therefore, only the failed programming operations can be selectively reprogrammed, and the programming order requested by the external device can be guaranteed.

[0125] As described above, those skilled in the art to which the present technology pertains can understand that the present technology can be implemented in various other forms without departing from the technical spirit or basic characteristics of the present technology. Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive. The scope of the present technology is defined by the appended claims rather than the specific embodiments, and all modifications or variations derived from the meaning and scope of the claims and their equivalent forms should be understood to be included within the scope of the present technology. In addition, the embodiments can be combined to form other embodiments.

Claims

1. A data storage device comprising: Storage device; A buffer memory device temporarily stores write data and a mapping table; as well as a memory controller, controlling the storage device to program the write data, Wherein, the memory controller: When a write command including a logical address is received from the outside, the logical address is stored by mapping the logical address to physical addresses sequentially stored in the mapping table in the order in which the write command is received, and When a programming operation corresponding to a first write command fails, first mapping information corresponding to the first write command is invalidated, and the first mapping information is updated by allocating a new physical address to a logical address included in the first write command in response to a reprogramming command generated for the first write command.

2. The data storage device according to claim 1, wherein: The memory controller: invalidating the successfully written data of the programming operation in the buffer memory device, and The write data that failed the programming operation is retained in the buffer memory device.

3. The data storage device according to claim 1, wherein: The memory controller retains only the write data that failed the programming operation in the buffer memory device regardless of the order in which the write commands were received.

4. The data storage device according to claim 1, wherein: The memory controller includes a reprogramming circuit, the reprogramming circuit: When a programming operation corresponding to the first write command fails, invalidating the first mapping information, storing first mapping data including the invalidated first mapping information in the storage device, and The first mapping information is updated with the new physical address by loading the first mapping data onto the mapping table in response to the reprogram command.

5. The data storage device according to claim 1, wherein: The memory controller includes a buffer manager that controls the buffer memory device in a scatter-gather manner.

6. A method for operating a data storage device, comprising: In response to a write command including a logical address received from the outside, temporarily storing the write data and the mapping table in the buffer memory device using the memory controller; storing the logical addresses by mapping the logical addresses to physical addresses sequentially stored in the mapping table using the memory controller in the order in which the write commands are received; Using the memory controller to control a storage device to program the write data; invalidating, using the memory controller, first mapping information corresponding to the first write command according to a determination result that a program operation corresponding to the first write command has failed; as well as The first mapping information is updated, with the memory controller, by assigning a new physical address to a logical address included in the first write command in response to a reprogram command generated for the first write command.

7. The operating method according to claim 6, further comprising: The memory controller is used to invalidate the write data of the successful programming operation in the buffer memory device, and to retain the write data of the failed programming operation in the buffer memory device.

8. The operating method according to claim 6, further comprising: Only write data that failed a programming operation is retained in the buffer memory device using the memory controller, taking into account the order in which the write commands were received.

9. The operating method according to claim 6, further comprising: In the event that the programming operation corresponding to the first write command fails: invalidating the first mapping information using the memory controller; storing first mapping data including the invalidated first mapping information in the storage device; loading the first mapping data onto the mapping table in response to the reprogramming command; as well as The first mapping information is updated using the new physical address.

10. The operating method according to claim 6, further comprising: The buffer memory device is controlled in a scatter-gather manner using the memory controller.

11. A data storage device comprising: A storage device, comprising a plurality of storage blocks; a buffer memory device for temporarily storing the first write data and the second write data; a buffer manager for managing the buffer memory device in a scatter-gather manner; as well as Memory Controller: controlling the storage device to program first write data and second write data provided in sequence, When programming of the first write data fails and programming of the second write data succeeds, invalidating first mapping information corresponding to the first write data, and The first mapping information is updated by allocating a new storage block, and the first write data will be reprogrammed into the new storage block.

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