Memory device, memory system, method of operating memory system, and method of controlling memory device

Abstract

A memory device, a memory system, a method of operating the memory system, and a method of controlling the memory device are provided. The memory device includes: a memory bank including a plurality of memory cells; and a bank register corresponding to the memory bank. The memory bank includes: a main data area storing user data; and a metadata area storing metadata corresponding to the user data. The memory bank register includes: a metadata register that caches metadata to be stored in a metadata region; and a dirty bitmap including location information in which the metadata is to be stored in the metadata region.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0170332, filed with the Korean Intellectual Property Office on November 30, 2023, and Korean Patent Application No. 10-2024-0005379, filed with the Korean Intellectual Property Office on January 12, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure relate to a memory device and an operation method thereof. Background Art

[0003] Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. When the power is interrupted, a volatile memory device loses the data stored therein. Among volatile memory devices, a dynamic random access memory (DRAM) is used in various fields such as mobile systems, servers, graphics units, etc. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory device capable of supporting a metadata mode with enhanced functions.

[0005] In the memory device according to the present disclosure, dirty metadata and information about a position where the dirty metadata will be stored in a metadata area are managed separately. Accordingly, the performance of the metadata mode is enhanced.

[0006] According to an aspect of the present disclosure, a memory device may include: a memory bank including a plurality of memory cells; and a bank register corresponding to the memory bank, wherein the memory bank may include: a main data area configured to store user data; and a metadata area configured to store metadata corresponding to the user data. The bank register may include: a metadata register configured to cache metadata to be stored in the metadata area; and a dirty bitmap including position information indicating a position where the metadata will be stored in the metadata area.

[0007] The metadata register may include a plurality of sub-registers configured to store a plurality of metadata corresponding to a plurality of user data, and the dirty bitmap may include a plurality of dirty bits corresponding to the plurality of sub-registers.

[0008] A plurality of different columns of the memory bank may be allocated for user data, and the same column among the plurality of different columns may be allocated for metadata corresponding to the user data.

[0009] The memory device may further include a storage management circuit configured to: cache dirty metadata in a sub-register selected from the plurality of sub-registers in response to a write command; and change a bit value of a dirty bit corresponding to the selected sub-register storing the dirty metadata among the plurality of bits included in a dirty bitmap.

[0010] The storage management circuit is further configured to: store the dirty metadata cached in the selected sub-register in response to a store dirty command.

[0011] The storage management circuit is configured to: prevent data cached in unselected sub-registers among the plurality of sub-registers from being stored in a metadata area in response to a store dirty command.

[0012] The storage management circuit is further configured to: initialize the bit value of the dirty bit corresponding to the selected sub-register after the metadata cached in the selected sub-register is stored in the metadata area.

[0013] The storage management circuit is further configured to: store the dirty metadata cached in the selected sub-register and the data cached in unselected sub-registers not selected from the plurality of sub-registers in the metadata area in response to a store command.

[0014] The storage management circuit is further configured to: initialize the bit value of the dirty bit corresponding to the selected sub-register after the dirty metadata cached in the selected sub-register and the data cached in the unselected sub-registers.

[0015] The memory device may further include a load management circuit configured to: load the metadata stored in the metadata area into the plurality of sub-registers in response to a load command; and load the clean metadata stored in the metadata area into unselected sub-registers not selected from the plurality of sub-registers.

[0016] The load management circuit may be configured to: prevent the metadata stored in the metadata area from being loaded into the selected sub-register caching the dirty metadata.

[0017] The load management circuit may be configured to: maintain the bit value of the dirty bit corresponding to the selected sub-register after the clean metadata stored in the metadata area is loaded into the unselected sub-registers.

[0018] According to another aspect of the present disclosure, a memory system may include: a memory device configured to store user data and metadata corresponding to the user data; and a memory controller configured to control the memory device. The memory device may include: a memory bank including a plurality of memory cells; and a bank register corresponding to the memory bank. The memory bank may include: a main data area configured to store user data; and a metadata area configured to store metadata corresponding to the user data. The bank register may include: a metadata register configured to cache the metadata to be stored in the metadata area; and a dirty bitmap including position information indicating positions where the metadata will be stored in the metadata area.

[0019] The memory controller may include: a dirty register bitmap including information on whether dirty metadata is stored in the metadata register; and a scheduler configured to schedule commands to be provided to the memory controller based on the dirty register bitmap.

[0020] The scheduler may also be configured to send a store dirty command to the memory device when the dirty metadata is cached in the metadata register and a load command has not been previously sent to the memory device.

[0021] The metadata register may include a plurality of sub-registers configured to store a plurality of metadata corresponding to the user data, and the memory device may also be configured to, in response to the store dirty command, store the dirty metadata cached in a sub-register selected from the plurality of sub-registers in the metadata area and prevent data cached in sub-registers not selected from the sub-registers from being stored in the metadata area.

[0022] The scheduler may be configured to send a store command to the memory device when the dirty metadata is cached in the metadata register and a load command has been previously sent to the memory device.

[0023] The metadata register may include a plurality of sub-registers configured to store a plurality of metadata corresponding to a plurality of user data, and the memory device may also be configured to, in response to the store command, store the dirty metadata cached in a sub-register selected from the plurality of sub-registers and the metadata cached in sub-registers not selected among the plurality of sub-registers in the metadata area.

[0024] The scheduler may be configured to omit sending the store dirty command and the store command when the dirty metadata is not cached in the metadata register.

[0025] According to another aspect of the present disclosure, a method of operating a memory system, the memory system including a memory device and a memory controller controlling the memory device, the method includes: enabling the memory controller to send an activation command to the memory device to activate a selected row of a selected memory bank; enabling the memory controller to send a write command to store user data in the selected memory bank; enabling the memory controller to selectively send a store dirty command or a store command to the memory device based on whether dirty metadata is stored in a metadata register storing metadata of the user data and whether the memory controller has previously sent a load command to the memory device; and enabling the memory controller to send a precharge command to the memory device.

[0026] According to another aspect of the present disclosure, a method of controlling a memory device, the memory device including a plurality of memory cells constituting a memory bank and a bank register corresponding to the memory bank, the method includes: activating a selected row of the memory bank based on an activation command; and after the selected row of the memory bank is activated, performing a write operation in a metadata mode without performing a load operation of loading metadata from the memory bank to the bank register, wherein the write operation in the metadata mode may include: based on a dirty bitmap indicating a position of dirty metadata stored in a metadata area of the memory bank, writing only the dirty metadata cached in the register to the metadata area of the memory bank. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by referring to the embodiments of the present disclosure described in detail with reference to the drawings.

[0028] Figure 1 is a block diagram showing a memory system according to one or more embodiments of the present disclosure.

[0029] Figure 2 is a diagram showing an operation of a metadata mode according to one or more embodiments of the present disclosure.

[0030] Figure 3 is a block diagram showing a memory system according to one or more embodiments of the present disclosure.

[0031] Figure 4 is a block diagram showing a memory bank according to one or more embodiments of the present disclosure.

[0032] Figure 5 is a conceptual diagram showing a memory bank including a metadata area allocated by a column division scheme according to one or more embodiments of the present disclosure.

[0033] Figure 6is a diagram showing data stored in the metadata area of a memory bank of a Figure 5 .

[0034] Figure 7 is a block diagram showing a memory device according to one or more embodiments of the present disclosure.

[0035] Figure 8 is a diagram showing memory cells included in a memory bank array according to one or more embodiments of the present disclosure.

[0036] Figure 9 is a diagram showing a bank register according to one or more embodiments of the present disclosure.

[0037] Figure 10 and Figures 11A to 11C is a diagram showing Figure 9 of the first bank register.

[0038] Figure 12 is a flowchart showing a write operation in metadata mode according to one or more embodiments of the present disclosure.

[0039] Figure 13 is a flowchart showing the operation of a memory device when receiving a write command according to one or more embodiments of the present disclosure.

[0040] Figure 14 and Figure 15 is a diagram showing an example of processing metadata and user data according to one or more embodiments of the present disclosure.

[0041] Figure 16 is a flowchart showing the operation of a memory device when receiving a store dirty command according to one or more embodiments of the present disclosure.

[0042] Figures 17 to 19 is a diagram showing an example of processing metadata and dirty bits when receiving a store dirty command according to one or more embodiments of the present disclosure.

[0043] Figure 20 is a flowchart showing the operation of a memory device when receiving a store command according to one or more embodiments of the present disclosure.

[0044] Figures 21 to 23 is a diagram showing an example of processing metadata and dirty bits when receiving a store command according to one or more embodiments of the present disclosure.

[0045] Figure 24 is a block diagram showing a memory system according to one or more embodiments of the present disclosure.

[0046] Figure 25is a block diagram showing a memory device according to one or more embodiments of the present disclosure.

[0047] Figure 26 is a flowchart showing operations of a memory device according to one or more embodiments of the present disclosure when a load command is received.

[0048] Figures 27 to 29 is a diagram showing loading metadata when a load command is received according to one or more embodiments of the present disclosure.

[0049] Figure 30 is a conceptual diagram showing a memory bank including a metadata area allocated by a row division scheme according to one or more embodiments of the present disclosure.

[0050] Figure 31 is a block diagram showing a memory system according to one or more embodiments of the present disclosure.

[0051] Figure 32 and Figure 33 is a diagram showing in detail a dirty bitmap register according to one or more embodiments of the present disclosure.

[0052] Figure 34 is a flowchart showing a method of scheduling commands according to one or more embodiments of the present disclosure.

[0053] Figures 35A to 35C is a diagram showing a method of scheduling commands according to one or more embodiments of the present disclosure. Detailed Description

[0054] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0055] In the following description, even in different drawings, the same reference numerals are used for the same elements. Matters defined in the description (such as detailed configurations and elements) are provided to help a comprehensive understanding of example embodiments. However, it is clear that example embodiments can be practiced without those specific defined matters. In addition, well-known functions or configurations will not be described in detail since they would obscure the description with unnecessary detail.

[0056] In the present disclosure, the expression “restricted data is stored” may include an embodiment in which one or more items in the data are stored while at least one item in the data is not stored, and another embodiment in which no data is stored.

[0057] [Memory System with Separate Management of Dirty Metadata] Figure 1 is a block diagram showing a memory system 10 according to one or more embodiments of the present disclosure.

[0058] Memory system 10 may support a metadata mode. In the present disclosure, the metadata mode may represent a mode of storing both user data and metadata in memory device 200. The metadata may be used to improve the performance of the memory device or enhance the security of the memory device. For example, the metadata may be an error correction code or parity data for performing an error correction operation, a memory address, a control signal, and information for managing data storage. User data may represent the main information that a user or an application intends to read or write in the memory device. User data may be the main content that the memory device is configured to store and manage, and the metadata serves a supporting role in improving the performance and security of the memory device.

[0059] In addition, memory system 10 according to the present disclosure may cache dirty metadata in a bank register. In addition, memory system 10 may separately manage the dirty metadata and the location information where the dirty metadata will be stored in the metadata area of the memory bank. Dirty metadata may represent the metadata among the metadata stored in the metadata area for which a change is requested. For example, the metadata that has been modified and temporarily stored in the bank register but not yet permanently stored in the memory bank of memory system 10 may be referred to as dirty metadata. Thus, memory system 10 may effectively perform an operation of storing the dirty metadata cached in the bank register into the metadata area of the memory bank or an operation of loading the metadata stored in the metadata area of the memory bank into the bank register in the metadata mode.

[0060] Referring to Figure 1 , memory system 10 may include memory controller 100 and memory device 200.

[0061] Memory controller 100 may control memory device 200. As an example, memory controller 100 may control memory device 200 in response to a request from a processor that supports various applications such as server applications, personal computer (PC) applications, mobile applications, etc. For example, memory controller 100 may be a part of a host including a processor and may control memory device 200 in response to a request from the processor. Memory controller 100 may be implemented through a system on chip (SoC).

[0062] Memory controller 100 may send commands and / or addresses to memory device 200 to control memory device 200. Memory controller 100 may send an activate command, a write command, a read command, and a precharge command to memory device 200. In addition, memory controller 100 may send, for example, the store command, the store dirty command, and the load command described below to memory device 200.

[0063] The memory controller 100 may send data to the memory device 200 or may receive data from the memory device 200.

[0064] As an example, during a write operation, the memory controller 100 may send user data and metadata corresponding to the user data to the memory device 200. As an example, during a read operation, the memory controller 100 may receive user data and metadata corresponding to the user data from the memory device 200.

[0065] As an example, when the metadata is error correction code (ECC) parity data and the ECC engine is implemented in the memory device 200, the metadata may be sent and received between the metadata region MR of the memory device 200 and the bank register corresponding to the metadata region MR, but the metadata is not sent and received between the memory controller 100 and the memory device 200.

[0066] The memory device 200 may receive data from the memory controller 100 and may store the data. The memory device 200 may read out the stored data in response to a request from the memory controller 100 and may send the read-out data to the memory controller 100.

[0067] According to one or more embodiments, the memory device 200 may be a memory device including volatile memory cells. As an example, the memory device 200 may be various DRAM devices (such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, LPDDR6 SDRAM, graphics double data rate synchronous graphics random access memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, etc.).

[0068] In addition, according to one or more embodiments, the memory device 200 may be a memory device in which DRAM dies are stacked (such as high bandwidth memory (HBM), HBM2, HBM3, etc.).

[0069] In addition, according to one or more embodiments, the memory device 200 may be a memory module (such as a dual in-line memory module (DIMM)). For example, the memory device 200 may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, this is only an example. According to one or more embodiments, the memory device 200 may be any other memory module (such as a single in-line memory module (SIMM)).

[0070] In addition, according to one or more embodiments, the memory device 200 may be a static random access memory (SRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a thyristor random access memory (TRAM) device, a magnetic random access memory (MRAM) device, etc.

[0071] The memory device 200 may include a memory cell array 310 and a bank register group 500.

[0072] The memory cell array 310 may include a plurality of memory banks, and each of the memory banks may include memory cells for storing data. In the present disclosure, for ease of explanation, it is assumed that each memory bank includes DRAM cells. However, this is only an example. According to one or more embodiments, each of the memory banks may be implemented to include volatile memory cells instead of DRAM cells. In addition, the memory banks may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0073] Each of the memory banks may include a metadata region MR. The metadata region MR may represent a region among the regions included in the memory bank that is allocated for storing metadata.

[0074] As an example, the first memory bank 310_1 may include a plurality of columns, and a part of the plurality of columns may be allocated to the metadata region MR. In this case, it can be referred to that some carved columns are used as the metadata region MR. According to one or more embodiments, the first memory bank 310_1 may include a plurality of rows, and a part of the plurality of rows may be allocated to the metadata region MR. In this case, it can be referred to that some carved rows are used as the metadata region MR.

[0075] The bank register group 500 may include a plurality of bank registers. Each bank register may cache metadata to be stored in the metadata area of the corresponding memory bank. In addition, each bank register may cache metadata loaded from the metadata area of the corresponding memory bank. In the present disclosure, the expression "caching metadata" may mean "temporarily storing metadata".

[0076] As an example, the first bank register 500_1 may correspond to the first memory bank 310_1, and may cache metadata to be stored in the metadata area MR of the first memory bank 310_1 or metadata loaded from the metadata area MR of the first memory bank 310_1.

[0077] According to one or more embodiments, each of the bank registers may include a dirty bitmap. The dirty bitmap may include position information of dirty metadata to be stored in the metadata area MR of the memory bank. In other words, the dirty bitmap may be used to manage the position information of dirty metadata to be stored in the metadata area MR of the memory bank. Each bit in the dirty bitmap may represent a block or a segment of the memory device 200. For example, in the dirty bitmap, a bit set to 1 may indicate that the corresponding block is dirty (i.e., a bit that has been modified and temporarily stored but not yet saved to the memory bank or the permanent storage device), and a bit set to 0 may indicate that the corresponding block is clean (i.e., a bit that matches the data stored in the memory bank or the permanent storage device).

[0078] As an example, the first bank register 500_1 may include a dirty bitmap 521, and the dirty bitmap 521 may include position information of dirty metadata cached in the first bank register 500_1 to be stored in the metadata area MR of the first memory bank 310_1.

[0079] The memory device 200 according to the present disclosure may effectively perform a write operation in the metadata mode or a load operation in the metadata mode using the dirty bitmap. In this embodiment, the write operation in the metadata mode may represent an operation of storing dirty metadata cached in the bank register in the metadata area MR of the memory bank. The load operation in the metadata mode may represent an operation of loading metadata stored in the metadata area MR of the memory bank into the corresponding bank register.

[0080] The memory device 200 may perform a store dirty operation of storing only dirty metadata in the metadata area by using a dirty bitmap among the metadata cached in the bank registers. As an example, as described below, when at least one bit of the dirty bitmap is 1 and the operation of loading metadata from the metadata area MR into the bank register has not been previously performed, the memory system 10 may perform the store dirty operation.

[0081] In this case, among the metadata cached in the bank registers, only the metadata marked as "dirty" (e.g., bits set to "1") by the dirty bitmap may be stored in the metadata area MR. The metadata not marked as dirty (e.g., bits set to "0") by the dirty bitmap may not be stored in the metadata area MR. Since only the dirty metadata is selectively stored in the metadata area MR by using the dirty bitmap, the store dirty operation may be referred to as a masked write operation.

[0082] In addition, the memory device 200 may perform a store operation of storing the metadata cached in the bank registers in the metadata area MR by using the dirty bitmap. As an example, as described below, when at least one bit of the dirty bitmap is 1 and the operation of loading metadata from the metadata area MR into the bank register has been previously performed, the memory system 10 may perform the store operation.

[0083] In this case, the metadata cached in the bank registers may be stored in the metadata area MR of the memory bank. That is, the metadata marked as dirty and the metadata not marked as dirty by the dirty bitmap may be stored in the metadata area MR of the memory bank.

[0084] In addition, the memory device 200 may omit the store dirty operation or the store operation. As an example, during a write operation, the memory device 200 may store user data in the memory bank and may cache the metadata corresponding to the user data in the bank register, and then the memory device 200 may terminate the write operation. As an example, as described below, when all bits of the dirty bitmap are "0", the memory system 10 may omit the store dirty operation or the store operation.

[0085] In addition, the memory system 10 may perform a load clean operation of loading only clean metadata among the metadata stored in the metadata area by using the dirty bitmap. In this case, the clean metadata may represent the metadata that has not been requested to be changed among the metadata stored in the metadata area MR.

[0086] In this case, only the clean metadata among the metadata stored in the metadata region MR of the memory bank can be loaded into the bank register. That is, among the metadata stored in the metadata region MR of the memory bank, the metadata stored in the positions marked as dirty metadata by the dirty bitmap may not be loaded into the bank register, and among the metadata stored in the metadata region MR of the memory bank, only the clean metadata stored in the positions not marked as dirty metadata by the dirty bitmap can be loaded into the bank register. Since only clean metadata is selectively loaded from the metadata region MR into the bank register using the dirty bitmap, the clean load operation can be referred to as a masked load operation.

[0087] As described above, the memory system 10 according to the present embodiment can support the metadata mode and can separately manage the dirty metadata and the position information where the dirty metadata will be stored in the metadata region MR of the memory bank. Therefore, the memory system 10 can effectively perform a write operation in the metadata mode or a load operation in the metadata mode.

[0088] Figure 2 is a diagram showing operations in the metadata mode according to one or more embodiments of the present disclosure. As an example, Figure 2 shows a write operation in the metadata mode. For ease of explanation, it is assumed that both the relevant memory device and the memory device 200 according to the present embodiment (refer to Figure 1 ) receive an activation command ACT at a first time point t1.

[0089] Refer to Figure 2 , during the write operation in the metadata mode, the relevant memory device may receive an activation command ACT at the first time point t1. Then, the relevant memory device may sequentially receive a load command LD, a write command WR, a store command ST, and a precharge command PRE.

[0090] As Figure 2 shown, the relevant memory device may need to receive a load command LD before receiving the write command WR. That is, before performing the write operation, the relevant memory device may need to perform a load operation of loading the metadata stored in the memory bank into the bank register.

[0091] More specifically, the size of the metadata is generally smaller than the size of the user data. Therefore, multiple metadata corresponding to different user data are stored together.

[0092] As an example, for ease of explanation, assume that 32 bytes of data are stored in a memory cell corresponding to a row and a column. Further, assume that the size of user data is 32 bytes and the size of metadata is 2 bytes. In this case, 16 metadata corresponding to 16 different user data can be stored together in a memory cell corresponding to a row and a column.

[0093] Therefore, when there is a request to change the metadata corresponding to a user data, it is necessary to load the metadata to be changed together with other stored metadata into the bank register before the write operation. In the case of not performing the load operation and performing the write operation, other metadata stored together with the metadata to be changed may be corrupted due to being overwritten by invalid data.

[0094] Therefore, as Figure 2 shown, the related memory device may receive a load command LD after receiving an activation command ACT. Therefore, it takes a first time T1 to perform the load operation. Further, the related storage device may receive a write command WR after receiving the load command LD. Therefore, it takes a second time T2 to convert the load operation to the write operation. Therefore, the related memory device requires a relatively long time for the write operation in the metadata mode.

[0095] However, according to an embodiment, Figure 1 the memory device 200 shown in may separately manage the position information of the dirty metadata stored in the metadata area MR using a dirty bitmap.

[0096] The memory device 200 may use the position information about the dirty metadata to support the store dirty operation. As an example, the memory device 200 may store user data in a corresponding memory bank in response to a write command WR, and may perform a store dirty operation of only overwriting the dirty metadata in the metadata area MR in response to a store dirty command STD. Therefore, compared with the related memory device, the memory device 200 according to the embodiment does not require the first time T1 and the second time T2 to perform the write operation. Therefore, the time required to perform the write operation can be reduced by a third time T3.

[0097] Further, the memory device 200 according to the embodiment may receive a store command ST instead of the store dirty command STD, and may perform a store operation. Further, the memory device 200 according to the embodiment may omit the store dirty operation or the store operation. Therefore, the time required to perform the write operation in the metadata mode can also be reduced.

[0098] Hereinafter, various embodiments of the memory system according to the present embodiment will be described in detail.

[0099] Memory device performing a write operation in an execution metadata mode Figure 3 is a block diagram showing a memory system 10A according to one or more embodiments of the present disclosure. Figure 3 The memory system 10A of Figure 1 is similar to the memory system 10 of Figure 3 Therefore, in Figure 1 the same / similar reference numerals denote the same / similar elements in

[0100] Referring to Figure 3 , the memory system 10A may include a memory controller 100A and a memory device 200A. The memory device 200A may include a memory cell array 310, a bank register group 500, and a storage management circuit 600.

[0101] The memory cell array 310 may include a plurality of memory banks, and each of the memory banks may include a metadata region MR. The metadata region MR may correspond to some of the plurality of rows or some of the plurality of columns of the memory bank.

[0102] The bank register group 500 may include a plurality of bank registers, and each of the bank registers may include a dirty bitmap. The dirty bitmap may include position information where dirty metadata will be stored in the metadata region MR.

[0103] The storage management circuit 600 may control an operation of storing metadata stored in each bank register into the metadata region MR of the corresponding memory bank.

[0104] According to one or more embodiments, during a write operation in the metadata mode, the memory device 200A may receive a write command WR from the memory controller 100A. The memory device 200A may store user data into a corresponding memory bank in response to the write command WR.

[0105] During a write operation in the metadata mode, the memory device 200A may receive a store dirty command STD from the memory controller 100A. In response to the store dirty command STD, the storage management circuit 600 may control the memory device 200A to perform a store dirty operation. In this case, the storage management circuit 600 may control the memory device 200A with reference to the dirty bitmap such that only the dirty metadata cached in the bank register is stored in the corresponding metadata region MR.

[0106] During a write operation in the metadata mode, the memory device 200A may receive a store command ST from the memory controller 100A. In response to the store command ST, the storage management circuit 600 may control the memory device 200A to perform a storage operation. In this case, the storage management circuit 600 may refer to the dirty bitmap to control the memory device 200A to store the dirty metadata cached in the bank register and the metadata other than the dirty metadata in the metadata region MR.

[0107] During a write operation in the metadata mode, the memory device 200A may not receive a store dirty command STD or a store command ST from the memory controller 100A. That is, during the corresponding write operation in the metadata mode, the store dirty operation or the store operation may be omitted. In this case, the dirty metadata may continue to be temporarily stored in the bank register.

[0108] As described above, the memory system 10A according to an embodiment may use the dirty bitmap to separately manage the position information where the dirty metadata will be stored in the metadata region MR of the memory bank. Therefore, a write operation can be effectively performed in the metadata mode.

[0109] Figure 4 is a block diagram showing a memory bank 310_1 according to one or more embodiments of the present disclosure. Figure 4 The memory bank 310_1 of Figure 3 corresponds to the first memory bank 310_1 of

[0110] Referring to Figure 4 , the first memory bank 310_1 may include a first memory bank array 311_1, a row decoder 260_1, and a column decoder 270_1.

[0111] The first memory bank array 311_1 may include a plurality of memory cells. The first memory bank array 311_1 may include a main data region MDR and a metadata region MR.

[0112] The main data region MDR may represent a region in the first memory bank array 311_1 that is allocated for storing user data (or user-generated data) and / or application-specific data. According to one or more embodiments, the main data region MDR may represent a region in the first memory bank array 311_1 that excludes the region allocated to the metadata region MR.

[0113] The metadata region MR may represent a region in the first memory bank array 311_1 that is allocated for storing metadata. The metadata region MR may include a first metadata region MR1 to a k-th metadata region MRk (where k is an integer greater than 1).

[0114] The row decoder 260_1 may activate one of a plurality of rows ROW1 to ROWm (where m is an integer greater than 1) in response to a row address RA. As an example, each of the rows ROW1 to ROWm may correspond to a word line.

[0115] The column decoder 270_1 may activate one of a plurality of columns COL1 to COLn (where n is an integer greater than 1) in response to a column address CA. As an example, each of the columns COL1 to COLn may correspond to a column select line (hereinafter referred to as CSL). However, this is merely an example, and according to one or more embodiments, each of the columns COL1 to COLn may correspond to a bit line.

[0116] According to one or more embodiments, the metadata region MR may be allocated by a column partitioning scheme. That is, some of the columns COL1 to COLn may be allocated to the metadata region MR.

[0117] As an example, when it is assumed that the sixty-first column COL61 to the sixty-fourth column COL64 are allocated to the metadata region MR, the memory cells corresponding to the sixty-first column COL61 may be defined as the first metadata region MR1. Similarly, the memory cells corresponding to the sixty-second column COL62 to the sixty-fourth column COL64 may be respectively allocated to the second metadata region MR2 to the fourth metadata region MR4.

[0118] According to one or more embodiments, the metadata region MR may be allocated by a row carved-out scheme. That is, some of the rows ROW1 to ROWm may be allocated to the metadata region MR.

[0119] As an example, when it is assumed that the sixty-first row ROW61 to the sixty-fourth row ROW64 are allocated to the metadata region MR, the memory cells corresponding to the sixty-first row ROW61 may be defined as the first metadata region MR1. Similarly, the memory cells corresponding to the sixty-second row ROW62 to the sixty-fourth row ROW64 may be respectively defined as the second metadata region MR2 to the fourth metadata region MR4.

[0120] In the present embodiment, for ease of explanation, it is assumed that the metadata region MR is allocated by a column partitioning scheme.

[0121] Figure 5 is a conceptual diagram of a memory bank including a metadata region allocated by a column partitioning scheme according to one or more embodiments of the present disclosure. Figure 6 is a diagram showing Figure 5 the data stored in the metadata region of the memory bank. Refer to Figure 5 andFigure 6 The described memory bank 310_1 may correspond to a first memory bank 310_1 such as Figure 3 and Figure 4 .

[0122] In Figure 5 and Figure 6 , for ease of explanation, it is assumed that the first memory bank 310_1 includes first column selection lines CSL1 to CSL64 and memory cells corresponding to the sixty-first column selection line CSL61 to the sixty-fourth column selection line CSL64 are assigned to the first metadata region MR1 to the fourth metadata region MR4. In addition, it is assumed that 32 bytes of user data are stored in the memory cells selected by a word line and a column selection line. In addition, it is assumed that 2 bytes of metadata correspond to 32 bytes of user data.

[0123] Referring to Figure 5 , the first memory bank 310_1 may include a first memory bank array 311_1, a row decoder 260_1, and a column decoder 270_1.

[0124] The first memory bank array 311_1 may be electrically connected to a plurality of word lines WL1 to WLm and the first column selection lines CSL1 to CSL64, and may include memory cells. The word lines WL1 to WLm may be defined as rows ROW1 to ROWm, and the column selection lines CSL1 to CSL64 may be defined as columns COL1 to COL64.

[0125] A part of the first memory bank array 311_1 may be assigned to the main data region MDR, and other parts of the first memory bank array 311_1 may be assigned to the metadata region MR.

[0126] As an example, as shown in Figure 5 , the memory cells corresponding to the first column COL1 to the sixtieth column COL60 may be assigned to the main data region MDR. User data may be stored in the memory cells assigned to the main data region MDR.

[0127] Referring to Figure 5 and Figure 6 , in the main data region MDR, 32 bytes of user data may be stored in the memory cells corresponding to a row and a column.

[0128] As an example, 32 bytes of user data can be stored in the memory cell corresponding to the first row ROW1 and the first column COL1. Similarly, among the memory cells corresponding to the first row ROW1, 32 bytes of user data can be stored in each of the memory cells corresponding to the second column COL2 to the sixtieth column COL60. Similarly, among the memory cells corresponding to the second row ROW2, 32 bytes of user data can be stored in each of the memory cells corresponding to the first column COL1 to the sixtieth column COL60.

[0129] In addition, as an example, as Figure 5 shown, the memory cells corresponding to the sixty-first column COL61 to the sixty-fourth column COL64 can be allocated to the metadata area MR. As an example, the memory cell corresponding to the sixty-first column COL61 can be allocated to the first metadata area MR1. In addition, the memory cells corresponding to the sixty-second column COL62 to the sixty-fourth column COL64 can be respectively allocated to the second metadata area MR2 to the fourth metadata area MR4. Metadata can be stored in the memory cells allocated to the metadata area MR.

[0130] Referring to Figure 5 and Figure 6 in the metadata area MR, 32 bytes of metadata can be stored in the memory cell corresponding to one row and one column. In other words, 16 metadata corresponding to 16 different user data can be stored together in the memory cell corresponding to one row and one column. For example, multiple different columns of the first memory bank array 311_1 are allocated for storing user data, and each of the columns of the first memory bank array 311_1 other than the multiple different columns is allocated for storing metadata corresponding to a part of the user data.

[0131] As an example, 16 metadata can be stored in the memory cell corresponding to the first row ROW1 and the sixty-first column COL61. The 16 metadata can be the 16 metadata corresponding to the 16 user data stored in the memory cells corresponding to the first column COL1 to the sixteenth column COL16 among the memory cells corresponding to the first row ROW1. That is to say, the metadata corresponding to the user data of the first row ROW1 and the first column COL1 to the metadata corresponding to the user data of the first row ROW1 and the sixteenth column COL16 can be stored together in the memory cell corresponding to the first row ROW1 and the sixty-first column COL61.

[0132] In this case, among the memory cells corresponding to the sixty-first column COL61, the metadata corresponding to the user data of the first column selection line CSL1, the metadata corresponding to the user data of the second column selection line CSL2, ……, the metadata corresponding to the user data of the fifteenth column selection line CSL15, and the metadata corresponding to the user data of the sixteenth column selection line CSL16 can be stored in the first part, the second part, ……, the fifteenth part, and the sixteenth part respectively. As an example, the 32-byte memory cells assigned to the sixty-first column COL61 can be divided into 16 parts (e.g., the first part to the sixteenth part), and each of the 16 parts is assigned 2 bytes. The 2-byte memory cells assigned to each of the first part to the sixteenth part can be set to store the metadata related to the corresponding user data.

[0133] Similarly, the metadata corresponding to the user data from the first row ROW1 and the seventeenth column COL17 to the metadata corresponding to the user data of the first row ROW1 and the thirty-second column COL32 can be stored together in the memory cells corresponding to the first row ROW1 and the sixty-second column COL62. In addition, the metadata corresponding to the user data from the first row ROW1 and the thirty-third column COL33 to the metadata corresponding to the user data of the first row ROW1 and the forty-eighth column COL48 can be stored together in the memory cells corresponding to the first row ROW1 and the sixty-third column COL63. In addition, the metadata corresponding to the user data from the first row ROW1 and the forty-ninth column COL49 to the metadata corresponding to the user data of the first row ROW1 and the sixtieth column COL60 can be stored together in the memory cells corresponding to the first row ROW1 and the sixty-fourth column COL64.

[0134] In this embodiment, among the memory cells corresponding to the sixty-fourth column COL64, the metadata corresponding to the user data of the forty-ninth column selection line CSL49, the metadata corresponding to the user data of the fiftieth column selection line CSL50, ……, the metadata corresponding to the user data of the fifty-ninth column selection line CSL59, and the metadata corresponding to the user data of the sixtieth column selection line CSL60 can be stored in the first part, the second part, ……, the eleventh part, and the twelfth part respectively.

[0135] In this case, among the memory cells corresponding to the sixty-fourth column COL64, the metadata may not be stored in the thirteenth part to the sixteenth part. That is to say, the metadata may not be stored in the parts of the memory cells corresponding to the sixty-fourth column COL64. As an example, the thirteenth part to the sixteenth part of the memory cells corresponding to the sixty-fourth column COL64 can be set as spare registers.

[0136] Similarly, metadata corresponding to user data from the second row ROW2 and the first column COL1 to metadata corresponding to user data from the second row ROW2 and the sixteenth column COL16 can be stored together in a memory cell corresponding to the second row ROW2 and the sixty-first column COL61.

[0137] According to the above scheme, user data can be stored in a memory cell corresponding to a row and a column in the main data region MDR. In addition, metadata corresponding to the user data can be stored in a memory cell corresponding to a row and a column in the metadata region MR.

[0138] In addition, for ease of explanation, Figure 5 a structure is shown in which columns corresponding to the main data region MDR are arranged adjacent to each other and columns corresponding to the metadata region MR are arranged adjacent to each other. However, this is only an example, and the present disclosure should not be limited to this or restricted thereby. As an example, the physical arrangement of the main data region MDR and the metadata region MR can be different from Figure 5 the conceptual diagram. According to an embodiment, columns corresponding to the main data region MDR can be arranged to be physically spaced apart from each other. According to one or more embodiments, columns corresponding to the metadata region MR can be arranged to be physically spaced apart from each other.

[0139] Figure 7 is a block diagram showing a memory device 200A according to one or more embodiments of the present disclosure. Figure 7 The memory device 200A can correspond to Figure 3 the memory device 200A. For ease of explanation, it is assumed that the metadata region MR is allocated by a column division scheme similar to Figure 5 and Figure 6 . In addition, it is assumed that the metadata is ECC parity data.

[0140] Referring to Figure 7 , the memory device 200A can include a control logic circuit 210, an address register 220, a memory bank control logic 230, a refresh control circuit 400, a row address multiplexer (RA Mux) 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a memory bank array group 311, a sense amplifier group 285, an input / output (I / O) strobe circuit 290, an ECC engine 350, a data I / O buffer 320, a bank register group 500, and a storage management circuit 600.

[0141] The memory bank array group 311 can include a plurality of memory bank arrays 311_1 to 311_n. Each of the memory bank arrays 311_1 to 311_n can include memory cells. As an example, each of the memory cells can be formed at a point where a corresponding word line intersects a corresponding bit line.

[0142] The row decoder group 260 may include a plurality of row decoders 260_1 to 260_n. Each of the row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the memory bank arrays 311_1 to 311_n.

[0143] The sense amplifier group 285 may include a plurality of sense amplifiers 285_1 to 285_n. Each of the sense amplifiers 285_1 to 285_n may be connected to a corresponding memory bank array among the memory bank arrays 311_1 to 311_n.

[0144] The column decoder group 270 may include a plurality of column decoders 270_1 to 270_n. Each of the column decoders 270_1 to 270_n may be connected to a corresponding memory bank array among the memory bank arrays 311_1 to 311_n via a corresponding sense amplifier.

[0145] The address register 220 may receive an address ADDR including a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100 or 100A (refer to Figure 1 , Figure 3 ). The address register 220 may provide the received memory bank address BANK_ADDR to the memory bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0146] The memory bank control logic 230 may generate a memory bank control signal in response to the memory bank address BANK_ADDR. As an example, the row decoder corresponding to the memory bank address BANK_ADDR among the row decoders 260_1 to 260_n may be activated in response to the memory bank control signal. The column decoder corresponding to the memory bank address BANK_ADDR among the column decoders 270_1 to 270_n may be activated in response to the memory bank control signal.

[0147] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and may receive the refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the row decoders 260_1 to 260_n.

[0148] The refresh control circuit 400 may sequentially increase or decrease the refresh row address REF_ADDR in response to a refresh signal from the control logic circuit 210.

[0149] Among the row decoders 260_1 to 260_n, the row decoder selected by the memory bank control logic 230 may activate the word line corresponding to the row address RA output from the row address multiplexer 240. As an example, the selected row decoder may apply a word line drive voltage to the word line corresponding to the row address.

[0150] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. Further, for example, in burst mode, the column address latch 250 may gradually increase the received column address COL_ADDR. The column address latch 250 may apply the column address CA obtained by temporarily storing or gradually increasing the column address COL_ADDR to each of the column decoders 270_1 to 270_n.

[0151] Among the column decoders 270_1 to 270_n, the column decoder activated by the memory bank control logic 230 may activate the sense amplifiers 285_1 to 285_n corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the I / O strobe circuit 290.

[0152] The I / O strobe circuit 290 may include a circuit for strobing I / O data. Further, the I / O strobe circuit 290 may include a data latch for storing the data output from the memory bank arrays 311_1 to 311_n and a write driver for writing data into the memory bank arrays 311_1 to 311_n.

[0153] The data I / O buffer 320 may convert a data signal DQ into user data during a write operation and may provide the user data to the ECC engine 350. The data I / O buffer 320 may convert the user data provided from the ECC engine 350 into a data signal DQ during a read operation. For example, the data I / O buffer 320 may output a data strobe signal DQS.

[0154] The ECC engine 350 may perform an ECC encoding operation on user data during a write operation and may generate metadata as ECC parity data. As an example, the ECC engine 350 may provide the metadata to the bank register bank 500 during a write operation. As an example, the ECC engine 350 may perform an ECC decoding operation on user data and metadata during a read operation.

[0155] The bank register group 500 may include bank registers, and metadata may be cached in corresponding bank registers among the bank registers.

[0156] Each of the bank registers may include a dirty bitmap. The dirty bitmap may include position information where dirty metadata will be stored in the metadata region MR of the memory bank. As an example, the first bank register 500_1 may include a dirty bitmap 521, and the dirty bitmap 521 may include position information where the dirty metadata cached in the first bank register 500_1 will be stored in the metadata region MR of the first memory bank 310_1 (refer to Figure 3 ).

[0157] The control logic circuit 210 may control the operation of the memory device 200A. As an example, the control logic circuit 210 may generate control signals for allowing the memory device 200A to perform write operations, read operations, store dirty operations, and store operations.

[0158] The control logic circuit 210 may include a command decoder 211 and a mode register bank 212. The command decoder 211 decodes a command CMD applied to it from the memory controller 100A (refer to Figure 3 ), and the mode register bank 212 sets the operation mode of the memory device 200A (refer to Figure 3 ).

[0159] The command decoder 211 may decode a command CMD (such as an active command ACT, a precharge command PRE, a write command WR, etc.), and may generate internal command signals (such as an internal activation signal IACT, an internal precharge signal IPRE, an internal write signal IWR, etc.).

[0160] In addition, the command decoder 211 may decode a command CMD (such as a store dirty command STD, a store command ST, etc.), and may generate internal command signals (such as an internal store dirty signal ISTD, an internal store signal IST, etc.).

[0161] The storage management circuit 600 may control the operation of storing the metadata stored in the bank register group 500 into the metadata region MR.

[0162] The storage management circuit 600 may receive the internal store dirty signal ISTD. The storage management circuit 600 may control the column decoder group 270 and the bank register group 500 to perform a store dirty operation in response to the internal store dirty signal ISTD. As an example, the storage management circuit 600 may control the column decoder group 270 and the bank register group 500 with reference to the dirty bitmap to store only the dirty metadata of the data in the bank register group 500 in the metadata region MR.

[0163] The storage management circuit 600 may receive an internal storage signal IST. In response to the internal storage signal IST, the storage management circuit 600 may control the column decoder group 270 and the bank register group 500 to perform a storage operation. As an example, the storage management circuit 600 may control the column decoder group 270 with reference to a dirty bitmap to store the dirty metadata of the bank register group 500 and the metadata excluding the dirty metadata of the bank register group 500 in the metadata region MR.

[0164] Figure 8 is a diagram showing memory cells included in a memory bank array according to one or more embodiments of the present disclosure.

[0165] Referring to Figure 8 , the first memory bank array 311_1 may include a plurality of word lines WL0 to WLm, a plurality of bit lines BL0 to BLn, and a plurality of memory cells MC, and the plurality of memory cells MC are located at the intersection points of the word lines WL0 to WLm and the bit lines BL0 to BLn.

[0166] Each memory cell MC may be a DRAM cell. As an example, each of the memory cells MC may include a cell transistor connected to the word line and the bit line and a cell capacitor connected to the cell transistor.

[0167] Figure 9 is a diagram showing a bank register according to one or more embodiments of the present disclosure. Figure 9 The bank register 500_1 of Figure 3 may correspond to the first bank register 500_1 such as

[0168] Referring to Figure 9 , the first bank register 500_1 may cache the metadata to be stored in the metadata region MR of the first memory bank 310_1 (refer to Figure 3 ), or may cache the metadata loaded from the metadata region MR of the first memory bank 310_1.

[0169] The first bank register 500_1 may include a plurality of metadata registers 511 to 51m and a plurality of dirty bitmaps 521 to 52m.

[0170] Each of the metadata registers 511 to 51m may correspond to a predetermined position in the metadata region MR. As an example, each of the metadata registers 511 to 51m may correspond to the memory cells selected by a row and a column in the metadata region MR, and may cache the metadata to be stored in the memory cells.

[0171] The dirty bitmaps 521 to 52m may correspond to the metadata registers 511 to 51m. As an example, the first dirty bitmap 521 may correspond to the first metadata register 511, and the second dirty bitmap 522 may correspond to the second metadata register 512.

[0172] Each of the dirty bitmaps 521 to 52m may manage the state of the metadata stored in the corresponding metadata register. As an example, when some of the metadata stored in the first metadata register 511 are dirty metadata, the first dirty bitmap 521 may set the bit value of the dirty bit corresponding to the dirty metadata to "1". As an example, when performing a store dirty operation, only the dirty metadata marked as dirty by the first dirty bitmap 521 among the metadata of the first metadata register 511 may be stored in the metadata area MR.

[0173] Figure 10 and Figures 11A to 11C is a diagram showing in detail Figure 9 the first bank register 500_1. Figure 10 Showing in more detail Figure 9 an example of the first bank register 500_1 in. Figures 11A to 11C Showing in more detail each metadata register and the dirty bitmap corresponding to the metadata register.

[0174] For ease of explanation, similar to Figure 5 and Figure 6 , it is assumed that the first memory bank 310_1 may include the first column COL1 to the sixty-fourth column COL64, the memory cells corresponding to the first column COL1 to the sixtieth column COL60 are assigned to the main data area MDR, and the memory cells corresponding to the sixty-first column COL61 to the sixty-fourth column COL64 are assigned to the first metadata area MR1 to the fourth metadata area MR4. In addition, it is assumed that 32 bytes of data are stored in the memory cell selected by one row and one column and 2 bytes of metadata correspond to 32 bytes of user data.

[0175] Referring to Figure 10 and Figures 11A to 11C , the first bank register 500_1 may include the first metadata register 511 to the fourth metadata register 514 and the first dirty bitmap 521 to the fourth dirty bitmap 524.

[0176] The first metadata register 511 to the fourth metadata register 514 may respectively correspond to the first metadata region MR1 to the fourth metadata region MR4. Each of the first metadata register 511 to the fourth metadata register 514 may include a first sub-register SR1 to a sixteenth sub-register SR16. Each of the first sub-register SR1 to the sixteenth sub-register SR16 may cache metadata corresponding to the corresponding user data.

[0177] Each of the first dirty bitmap 521 to the fourth dirty bitmap 524 may display the status of the metadata stored in the corresponding sub-register. As an example, when the metadata stored in the sub-register is dirty metadata, the dirty bit corresponding to the dirty metadata in the dirty bitmap may be set to "1".

[0178] More specifically, as Figure 11A shown, the first metadata register 511 may include a first sub-register SR1 to a sixteenth sub-register SR16. The metadata corresponding to the user data to be stored in the first column COL1 may be stored in the first sub-register SR1. Similarly, the metadata corresponding to the user data to be stored in the second column COL2 to the sixteenth column COL16 may be respectively stored in the second sub-register SR2 to the sixteenth sub-register SR16.

[0179] The first dirty bitmap 521 may include a first dirty bit DB1 to a sixteenth dirty bit DB16. The first dirty bit DB1 to the sixteenth dirty bit DB16 may respectively display the status of the metadata stored in the first sub-register SR1 to the sixteenth sub-register SR16.

[0180] As an example, in the case where there is a request to change the metadata regarding the user data stored in the first column COL1 through the memory controller 100A, the metadata to be changed upon request or the metadata that has been changed according to the request may be cached in the first sub-register SR1. In this case, the metadata stored in the first sub-register SR1 may be regarded as dirty metadata, and the first dirty bit DB1 of the first dirty bitmap 521 may change from "0" to "1".

[0181] As described above, the first dirty bitmap 521 may be used to display and manage the status of the metadata stored in the first metadata register 511.

[0182] In addition, the second metadata register 512 to the fourth metadata register 514 and the second dirty bitmap 522 to the fourth dirty bitmap 524 may be implemented similar to the first metadata register 511 and the first dirty bitmap 521.

[0183] As an example, as Figure 11BAs shown, the second metadata register 512 may include first to sixteenth sub-registers SR1 to SR16, and metadata corresponding to user data to be stored in seventeenth to thirty-second columns COL17 to COL32 may be stored in first to sixteenth sub-registers SR1 to SR16 respectively. The second dirty bitmap 522 may include first to sixteenth dirty bits DB1 to DB16, and first to sixteenth dirty bits DB1 to DB16 may respectively indicate the status of metadata cached in first to sixteenth sub-registers SR1 to SR16.

[0184] In addition, as Figure 11C shown, the fourth metadata register 514 may include first to sixteenth sub-registers SR1 to SR16, and metadata corresponding to user data to be stored in forty-ninth to sixtieth columns COL49 to COL60 may be cached in first to twelfth sub-registers SR1 to SR12. The fourth dirty bitmap 524 may include first to twelfth dirty bits DB1 to DB12, and first to twelfth dirty bits DB1 to DB12 may respectively indicate the status of metadata cached in first to twelfth sub-registers SR1 to SR12. In this case, the fourth metadata register 514 may include unused thirteenth to sixteenth sub-registers SR13 to SR16, and thirteenth to sixteenth sub-registers SR13 to SR16 may be set as spare registers. As an example, thirteenth to sixteenth sub-registers SR13 to SR16 may correspond to thirteenth to sixteenth parts of memory cells corresponding to sixty-fourth column COL64 (refer to Figure 5 and Figure 6 ) in which no metadata is stored.

[0185] In Figures 11A to 11C , although dirty bits Figure 1 to dirty bit Figure 3 only include zero (0) as the bit value, these are only examples, and different bit values may be used to indicate the status of metadata. For example, the bit value 0 may be used to indicate clean metadata, while the bit value 1 may be used to indicate dirty metadata.

[0186] Figure 12 is a flowchart showing a write operation in a metadata mode according to one or more embodiments of the present disclosure.

[0187] In operation S110, the memory device 200A (refer to Figure 3 ) may receive a command CMD and an address ADDR corresponding to the command CMD from the memory controller 100A (refer to Figure 3 ).

[0188] In operation S120, the memory device 200A may determine whether the received command CMD is a write command WR.

[0189] When it is determined that the received command CMD is a write command WR, operation S130 may be executed. In operation S130, the memory device 200A may cache the metadata in a sub-register of the corresponding metadata register, and may set the dirty bit of the dirty bitmap corresponding to the sub-register to "1". Then, in operation S140, the memory device 200A may store the user data in the main data region MDR.

[0190] In addition, when it is determined that the received command CMD is not a write command WR, operation S150 may be executed.

[0191] In operation S150, the memory device 200A may determine whether the received command CMD is a store dirty command STD.

[0192] When it is determined that the received command CMD is a store dirty command STD, operation S160 may be executed. In operation S160, the memory device 200A may store only the dirty metadata among the metadata cached in the metadata register in the metadata region MR. In addition, when it is determined that the received command CMD is not a store dirty command STD, operation S170 may be executed.

[0193] In operation S170, the memory device 200A may determine whether the received command CMD is a store command ST.

[0194] When it is determined that the received command CMD is a store command ST, operation S180 may be executed. In operation S180, the memory device 200A may store all the metadata stored in the metadata register in the metadata region MR.

[0195] In addition, when it is determined that the received command CMD is not a store command ST, the store operation and the store dirty operation may be omitted. In this case, the memory device 200A may receive a precharge command, and thus, the write operation in the metadata mode may be completed.

[0196] Meanwhile, the above description is only an example, and the present disclosure should not be limited to this or restricted thereby. According to an embodiment, the order of operation S120 for determining whether the received command is a write command WR, operation S150 for determining whether the received command is a store dirty command STD, and operation S170 for determining whether the received command is a store command ST may be changed, or operation S120, operation S150, and operation S170 may be omitted.

[0197] In addition, according to an embodiment, operations of receiving and processing a write command WR, operations of receiving and processing a store dirty command STD, and operations of receiving and processing a store command ST may be independently performed.

[0198] Hereinafter, operations of receiving and processing a write command WR, operations of receiving and processing a store dirty command STD, and operations of receiving and processing a store command ST will be described in more detail.

[0199] Figures 13 to 15 is a diagram showing operations of a memory device when a write command WR is received. Specifically, Figure 13 is a flowchart showing operations of a memory device when a write command WR is received, and Figure 14 and Figure 15 is a diagram showing an example of processing metadata and user data.

[0200] For ease of explanation, it is assumed that the first metadata register 511 includes sixteen sub-registers SR1 to SR16 similar to Figure 10 and FIG. 11. In addition, it is assumed that user data is stored in memory cells corresponding to the first column COL1 and the first row ROW1.

[0201] Referring to Figure 13 , in operation S210, the memory device 200A may receive a write command WR, an address ADDR, user data, and metadata. In this case, the received address ADDR may include a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR of a memory cell storing the user data.

[0202] In operation S220, the memory device 200A may store the user data in a main data region MDR.

[0203] As an example, as shown in Figure 15 , the memory device 200A may store 32 bytes of user data in memory cells corresponding to the first column COL1 and the first row ROW1 of the main data region MDR.

[0204] In operation S230, the memory device 200A may cache the received metadata in a sub-register of a corresponding register, and may set a dirty bit of a dirty bitmap corresponding to the sub-register to "1".

[0205] As an example, referring to Figure 14, the first sub-register SR1 of the first metadata register 511 may correspond to the metadata regarding the user data to be stored in the first column COL1. Thus, the memory device 200A may cache the received metadata in the first sub-register SR1 of the first metadata register 511. Then, the memory device 200A may change the first dirty bit DB1 of the first dirty bitmap 521 corresponding to the first sub-register SR1 from "0" to "1".

[0206] In addition, for ease of explanation, it is assumed that in the description with reference to Figure 13 , the operation S220 of storing user data in the main data region MDR is performed earlier than the operation S230. However, the present disclosure should not be limited to this or restricted thereby. As an example, the operation S220 of storing user data in the main data region MDR may be performed after the operation S230, or may be performed in parallel with the operation S230.

[0207] Figures 16 to 19 is a diagram showing the operation of the memory device when a store dirty command STD is received. Specifically, Figure 16 is a flowchart showing the operation of the memory device when a store dirty command STD is received, and Figures 17 to 19 is a diagram showing an example of processing metadata and dirty bits when a store dirty command STD is received.

[0208] For ease of explanation, similar to Figures 13 to 15 , it is assumed that the data stored in the first sub-register SR1 of the first metadata register 511 is dirty metadata.

[0209] Referring to Figure 16 , in operation S310, the memory device 200A may receive a store dirty command STD and an address ADDR.

[0210] As an example, the received address ADDR may be the address ADDR of the user data, and may include the memory bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR of the user data. In response to the received store dirty command STD, the memory device 200A may store the dirty metadata among the metadata of the metadata register corresponding to the address ADDR of the user data in the memory cells of the metadata region MR corresponding to the address ADDR of the user data.

[0211] As an example, the received address ADDR may be the address ADDR of the metadata and may include the memory bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR of the metadata. In response to the received store dirty command STD, the memory device 200A may store the dirty metadata among the metadata of the metadata register corresponding to the address ADDR of the metadata in the memory cells of the metadata region MR corresponding to the address ADDR of the metadata.

[0212] As an example, when at least one bit of the dirty bitmap is “1” and the operation of loading metadata from the metadata region MR has not been previously performed, the memory device 200A may receive the store dirty command STD.

[0213] That is, since the operation of loading metadata from the metadata region MR has not been previously performed, the corresponding metadata register may include a first sub-register SR1 storing metadata corresponding to user data and other sub-registers SR2 to SR16 storing invalid data. Thus, when the memory device 200A receives the store dirty command STD, the memory device 200A may store only the metadata of the first sub-register SR1 in the corresponding memory cells based on the value of the corresponding dirty bitmap. However, this is only an example, and the present disclosure should not be limited to this or be restricted thereby. For example, the storage management circuit 600 of the memory device 200A may store the dirty metadata cached in the sub-register selected from among the plurality of sub-registers in the metadata region MR in response to the store dirty command STD. For example, the storage management circuit 600 of the memory device 200A may prevent the metadata cached in the unselected sub-registers among the plurality of sub-registers from being stored in the metadata region MR in response to the store dirty command STD. According to an embodiment, even when the operation of loading metadata is performed, when the store dirty command STD is received, the memory device 200A may store only the metadata of a specific sub-register in the memory cells based on the dirty bitmap.

[0214] In operation S320, the memory device 200A may store the dirty metadata in the metadata region MR based on the dirty bitmap.

[0215] As an example, as Figure 17As shown, the first dirty bit DB1 of the first dirty bitmap 521 may be "1". Accordingly, the memory device 200A may determine that the metadata cached in the first sub-register SR1 of the first metadata register 511 is dirty metadata. In other words, the memory device 200A may store only the metadata cached in the first sub-register SR1 of the first metadata register 511 in the corresponding memory cell based on the fact that the first dirty bit DB1 of the first dirty bitmap 521 is "1", and the invalid data stored in the other sub-registers SR2 to SR16 of the first metadata register 511 may not be stored in the corresponding memory cell.

[0216] Then, the memory device 200A may store the dirty metadata cached in the first sub-register SR1 of the first metadata register 511 in the memory cell corresponding to the first row ROW1 and the sixty-first column COL61. As an example, the dirty metadata cached in the first sub-register SR1 of the first metadata register 511 may be stored in the first portion corresponding to the first sub-register SR1 of the first metadata register 511 among the memory cells corresponding to the first row ROW1 and the sixty-first column COL61.

[0217] Accordingly, as Figure 18 shown, the metadata of the user data regarding the first row ROW1 and the first column COL1 may be updated. As an example, the metadata of the user data regarding the first row ROW1 and the first column COL1 may be updated in the memory cell corresponding to the first portion of the first sub-register SR1 of the first metadata register 511 among the memory cells corresponding to the first row ROW1 and the sixty-first column COL61.

[0218] Meanwhile, the other metadata stored together in the first row ROW1 and the sixty-first column COL61 may not be changed. That is, the other metadata stored in the memory cells of the other portions (e.g., the second portion to the sixteenth portion) that do not correspond to the first sub-register SR1 of the first metadata register 511 among the memory cells corresponding to the first row ROW1 and the sixty-first column COL61 may not be changed.

[0219] In operation S330, the memory device 200A may initialize the dirty bits of the dirty bitmap.

[0220] As an example, as Figure 19 shown, the memory device 200A may change the first dirty bit DB1 of the first dirty bitmap 521 from "1" to "0".

[0221] Figures 20 to 23 is a diagram illustrating the operation of the memory device when a store command ST is received. Specifically,Figure 20 is a flowchart showing the operation of the memory device when a store command ST is received, and Figures 21 to 23 is a diagram showing an example of processing metadata and dirty bits when a store command ST is received.

[0222] For ease of explanation, similar to Figures 13 to 15 , it is assumed that the data stored in the first sub-register SR1 of the first metadata register 511 is dirty metadata.

[0223] Referring to Figure 20 , in operation S410, the memory device 200A may receive a store command ST and an address ADDR.

[0224] As an example, when at least one bit of the dirty bitmap is "1" and the operation of loading metadata from the metadata region MR has been previously performed, the memory device 200A may receive a store command ST.

[0225] As an example, the received address ADDR may be the address ADDR of user data and may include the memory bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR of the user data. In response to the received store command ST, the memory device 200A may store the metadata of the metadata register corresponding to the address ADDR of the user data in the memory cell of the metadata region MR corresponding to the address ADDR of the user data based on the received address ADDR of the user data.

[0226] As an example, the received address ADDR may be the address ADDR of metadata and may include the memory bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR of the metadata. In response to the received store command ST, the memory device 200A may store the metadata of the metadata register corresponding to the address ADDR of the metadata in the memory cell of the metadata region MR corresponding to the address ADDR of the metadata based on the received address ADDR of the metadata.

[0227] In operation S420, the memory device 200A may store all the metadata cached in the metadata register in the metadata region MR with reference to the dirty bitmap.

[0228] As an example, as shown in Figure 21 , the memory device 200A may store all the metadata cached in the first sub-register SR1 of the first metadata register 511 in the memory cell corresponding to the first row ROW1 and the sixty-first column COL61 regardless of the value of the dirty bit of the first dirty bitmap 521. Thus, as Figure 22As shown, the metadata of the user data regarding the first row ROW1 and the first column COL1 can be updated.

[0229] In addition, since the metadata stored in the memory cells of the first row ROW1 and the sixty - first column COL61 has been previously loaded into the first metadata register 511, the metadata of the user data regarding the first row ROW1 and the second column COL2 to the metadata of the user data regarding the first row ROW1 and the sixteenth column COL16 can be substantially unchanged. That is, even if all the metadata stored in the first sub - register SR1 of the first metadata register 511 is stored in the memory cells corresponding to the first row ROW1 and the sixty - first column COL61, only the dirty metadata can be updated, and the other metadata can be substantially the same.

[0230] In operation S430, the memory device 200A can initialize the dirty bits of the dirty bitmap.

[0231] As an example, as Figure 23 shown, the memory device 200A can change the bit value of the first dirty bit DB1 of the first dirty bitmap 521 from "1" to "0".

[0232] As described above with reference to Figures 3 to 23 the memory device 200A according to the present disclosure can support write operations in the metadata mode and can separately manage the dirty metadata and the location information where the dirty metadata will be stored in the metadata region MR. Therefore, the memory device 200A can effectively perform the operation of storing the dirty metadata cached in the bank register in the metadata region MR in the metadata mode.

[0233] Meanwhile, referring to Figures 3 to 23 the embodiments that effectively perform write operations in the metadata mode are described. However, this is only an example, and the present disclosure can be applied to load operations in the metadata mode. Hereinafter, embodiments that effectively perform load operations in the metadata mode will be described in detail.

[0234] [Memory Device Performing Load Operation in Metadata Mode] Figure 24 is a block diagram showing a memory system according to one or more embodiments of the present disclosure. Figure 24 The memory system 10B of Figure 3 is similar to Figure 24 the memory system 10A of Figure 3 In

[0235] Referring to Figure 24, the memory system 10B may include a memory controller 100B and a memory device 200B. The memory device 200B may include a memory cell array 310, a bank register group 500, a storage management circuit 600, and a load management circuit 700.

[0236] When compared with Figure 3 the memory device 200A of Figure 24 the memory device 200B of

[0237] The load management circuit 700 may control an operation of loading metadata stored in a metadata area MR of a memory bank into each bank register.

[0238] According to one or more embodiments of the present disclosure, during a load operation in a metadata mode, the memory device 200B may receive a load command LD from the memory controller 100B. In response to the load command LD, the load management circuit 700 may control the memory device 200B to load the metadata stored in the metadata area MR into the corresponding bank register.

[0239] Specifically, the load management circuit 700 may use a dirty bitmap to control the memory device 200B to load only clean metadata excluding dirty metadata among the metadata stored in the metadata area MR into the bank register. In this case, the clean metadata may represent the metadata among the metadata stored in the metadata area MR that has not been requested to be changed.

[0240] As described above, since only clean metadata is selectively loaded from the metadata area MR of the bank into the bank register using the dirty bitmap, the dirty metadata cached in the bank register can be protected from being overwritten. In other words, during the load operation, the dirty metadata may not be damaged or destroyed by the data loaded from the memory bank into the bank register, thereby enhancing the efficiency of the load operation.

[0241] Figure 25 is a block diagram showing a memory device 200B according to one or more embodiments of the present disclosure. Figure 25 The memory device 200B of Figure 24 corresponds to

[0242] Figure 25 The memory device 200B of Figure 7 is similar to Figure 25 the memory device 200A of Figure 7, assume that the metadata area MR is allocated by a column splitting scheme, and the metadata is ECC parity data.

[0243] Refer to Figure 25 , the memory device 200B may include a control logic circuit 210, an address register 220, a memory bank control logic 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a memory bank array group 311, a sense amplifier group 285, an I / O strobe circuit 290, an ECC engine 350, a data I / O buffer 320, a bank register group 500, a storage management circuit 600, and a load management circuit 700.

[0244] The control logic circuit 210 may receive a load command LD. A command decoder 211 may decode the load command LD and may generate an internal load signal ILD.

[0245] The load management circuit 700 may control the operation of loading the metadata stored in the metadata area MR into the bank register group 500.

[0246] The load management circuit 700 may receive the internal load signal ILD. The load management circuit 700 may control the column decoder group 270 and the bank register group 500 in response to the internal load signal ILD to perform a load clean operation. The load clean operation may represent an operation of loading only the clean metadata excluding the dirty metadata among the metadata stored in the metadata area MR into the bank register.

[0247] As described above, since the load clean operation is performed using the dirty bitmap, the dirty metadata cached in the bank register may not be damaged during the load operation.

[0248] Figures 26 to 29 is a diagram showing the operation of the memory device when a load command LD is received. Figure 26 is a flowchart showing the operation of the memory device when a load command LD is received, and Figures 27 to 29 is a diagram showing the loading of metadata when a load command LD is received.

[0249] For ease of explanation, assume that a load command LD is received to load the metadata corresponding to the user data read out after a read command RD is received. In addition, assume that the dirty metadata is stored in the first sub-register SR1 of the first metadata register 511. In addition, assume that the read command RD is a command requesting a read operation on the user data stored in the memory cell corresponding to the first row ROW1 and the first column COL1, and the metadata corresponding to the user data is stored in the memory cell corresponding to the first row ROW1 and the sixty-first column COL61.

[0250] Referring to Figure 26 , in operation S510, the memory device 200B may receive a read command RD and an address ADDR. In this case, the received address ADDR may include a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR of a memory cell storing user data to be read out. As an example, the address ADDR may include a row address and a column address, the row address may correspond to the first row ROW1, and the column address may correspond to the first column COL1.

[0251] In operation S520, the memory device 200B may read out user data in response to the read command RD.

[0252] As an example, as shown in Figure 27 , the memory device 200B may read out user data stored in a memory cell corresponding to the first row ROW1 and the first column COL1.

[0253] In operation S530, the memory device 200B may receive a load command LD and an address ADDR. In this case, the received address ADDR may include a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR of a memory cell storing metadata to be loaded. As an example, the address ADDR may include a row address and a column address, the row address may correspond to the first row ROW1, and the column address may correspond to the sixty-first column COL61.

[0254] In operation S540, the memory device 200B may load only clean metadata excluding dirty metadata based on a dirty bitmap.

[0255] As an example, as shown in Figure 28 , the memory device 200B may determine based on the first dirty bitmap 521 that dirty metadata is stored in the first sub-register SR1 of the first metadata register 511. That is, the memory device 200B may determine that the dirty metadata stored in the first sub-register SR1 is valid metadata regarding the user data of the first row ROW1 and the first column COL1.

[0256] In addition, the memory device 200B may determine based on the first dirty bitmap 521 that among the metadata stored in the first row ROW1 and the sixty-first column COL61 of the metadata region MR, the metadata corresponding to the first column COL1 is invalid metadata, and the metadata corresponding to the second column COL2 to the sixteenth column COL16 is clean metadata as valid metadata.

[0257] Then, as shown in Figure 29As shown, the memory device 200B may load only clean metadata into the first metadata register 511. As an example, the clean metadata corresponding to the second column COL2 to the sixteenth column COL16 may be loaded into the second sub-register SR2 to the sixteenth sub-register SR16 of the first metadata register 511. As described above, since only clean metadata is loaded and data is not loaded into the first sub-register SR1 that stores dirty metadata, the dirty metadata cached in the first sub-register SR1 can be stably maintained without being damaged or rewritten.

[0258] Meanwhile, since the dirty metadata has not been stored in the metadata area MR, the first dirty bit DB1 of the first dirty bitmap 521 may continue to have a value of "1".

[0259] As referred to Figures 24 to 29 As described, the memory device 200B according to the present disclosure may support a load operation in the metadata mode. Specifically, the memory device 200B may support a load clean operation of loading only clean metadata into the bank register based on the dirty bitmap. Therefore, the memory device 200B can stably perform the load operation without damaging the dirty metadata cached in the sub-register.

[0260] In addition, referring to Figures 5 to 29 the described embodiment is based on the assumption that the metadata area MR is allocated by a column division scheme. However, this is only an example, and the present disclosure should not be limited to this or restricted thereby. As an example, the metadata area MR may be allocated by a row division scheme.

[0261] Figure 30 is a conceptual diagram showing a first memory bank 310_1 including a metadata area MR allocated by a row division scheme.

[0262] Figure 30 The first memory bank 310_1 of Figure 5 is similar to the first memory bank 310_1 of Figure 30 Therefore, in Figure 5 the same or similar reference numerals represent the same or similar elements in

[0263] Referring to Figure 30 the first memory bank 310_1 may include a first memory bank array 311_1, a row decoder 260_1, and a column decoder 270_1.

[0264] The metadata area MR can be allocated by a row segmentation scheme. As an example, the memory cells corresponding to the first row ROW1 can be allocated to the first metadata area MR1, and the memory cells corresponding to the second row ROW2 can be allocated to the second metadata area MR2.

[0265] In this case, the storage management circuit according to the present disclosure can control the row decoder 260_1 to perform a storage dirty operation or a storage operation. The load management circuit according to the present disclosure can control the row decoder 260_1 to perform a load clean operation.

[0266] As described above, even if the metadata area MR is allocated by a row segmentation scheme, the operation of storing the dirty metadata cached in the bank register in the metadata area of the memory bank or the operation of loading the metadata stored in the metadata area of the memory bank into the bank register can be effectively performed.

[0267] [Memory Controller for Effectively Scheduling Commands] Figure 31 is a block diagram showing a memory system 10C according to one or more embodiments of the present disclosure. Figure 31 The memory system 10C of Figure 1 is similar to the memory system 10 of Figure 3 the memory system 10A and Figure 24 the memory system 10B of Figure 31 Therefore, in Figure 1 、 Figure 3 and Figure 24 the same or similar reference numerals denote the same or similar elements in

[0268] Referring to Figure 31 , the memory system 10C may include a memory controller 100C and a memory device 200C. The memory device 200C may include a memory cell array 310, a bank register group 500, a storage management circuit 600, and a load management circuit 700.

[0269] The memory controller 100C may include a memory bank scheduler group 800. The memory bank scheduler group may include a plurality of memory bank schedulers.

[0270] The memory bank scheduler may correspond to multiple memory banks of the memory device 200C respectively, and each memory bank scheduler may schedule commands sent to the corresponding memory bank. As an example, the first memory bank scheduler 810 may correspond to the first memory bank 310_1, and may schedule the activation command ACT, write command WR, store command ST, store dirty command STD, and precharge command PRE to be sent to the first memory bank 310_1.

[0271] Each of the memory bank schedulers may include a dirty register bitmap. The dirty register bitmap may include dirty metadata information about the corresponding bank register group. As an example, the dirty register bitmap 811 of the first memory bank scheduler 810 may use a bitmap to manage information about the metadata registers among the metadata registers of the first bank register 500_1 that include dirty metadata.

[0272] According to one or more embodiments of the present disclosure, each of the memory bank schedulers may schedule commands based on the corresponding dirty register bitmap. As an example, each of the memory bank schedulers may send one of the store command ST and the store dirty command STD based on the corresponding dirty register bitmap, or may not send the store command ST and the store dirty command STD.

[0273] As described above, when commands are scheduled based on the dirty register bitmap, the performance of the metadata mode provided by the memory system 10C may be improved.

[0274] Figure 32 and Figure 33 are diagrams showing in detail the dirty bitmap register according to one or more embodiments of the present disclosure. Specifically, Figure 32 shows the dirty register bitmap 811 included in the first memory bank scheduler 810 as a representative example. Figure 33 shows the dirty register bitmap 811 as a representative example. The dirty register bitmap 811 shows the status of the metadata registers included in the first bank register 500_1. For ease of explanation, similar to Figure 10 it is assumed that the first bank register 500_1 includes four metadata registers.

[0275] Referring to Figure 32 and Figure 33 the first memory bank scheduler 810 may include a dirty register bitmap 811, and the dirty register bitmap 811 may include a first dirty register bit, a second dirty register bit, a third dirty register bit, and a fourth dirty register bit DRB1 to DRB4.

[0276] The first dirty register bit DRB1 to the fourth dirty register bit DRB4 can correspond to the first metadata register, the second metadata register, the third metadata register, and the fourth metadata registers 511 to 514 respectively. Each of the first dirty register bit DRB1 to the fourth dirty register bit DRB4 can indicate whether the dirty metadata is stored in the corresponding metadata register.

[0277] As an example, the first dirty register bit DRB1 of the dirty register bitmap 811 can correspond to the first metadata register 511. When at least one dirty metadata is stored in the first metadata register 511, the bit value of the first dirty register bit DRB1 can be set to "1". When at least one dirty metadata is not stored in the first metadata register 511, the bit value of the first dirty register bit DRB1 can be set to "0".

[0278] Similarly, the second dirty register bit DRB2 to the fourth dirty register bit DRB4 of the dirty register bitmap 811 can correspond to the second metadata register 512 to the fourth metadata register 514 respectively, and can include information on whether the dirty metadata is stored in the second metadata register 512 to the fourth metadata register 514.

[0279] As described above, the memory controller 100C can determine whether the dirty metadata is stored in the bank register based on the dirty register bitmap, and can effectively schedule commands.

[0280] Figure 34 is a flowchart showing a method of scheduling commands according to one or more embodiments of the present disclosure. Figures 35A to 35C is a diagram showing a method of scheduling commands according to an embodiment of the present disclosure. For ease of explanation, Figure 34 and Figures 35A to 35C show a method of scheduling commands for a write operation in the metadata mode.

[0281] In operation S610, the memory controller 100C (refer to Figure 31 ) can calculate an address to process a write request from the outside.

[0282] In operation S620, the memory controller 100C can send an activation command ACT for activating a selected row of a selected memory bank to the memory device 200C (refer to Figure 31 ).

[0283] In operation S630, the memory controller 100C can send a write command WR to store user data in the memory device 200C.

[0284] In operation S640, the memory controller 100C may determine, based on the dirty register bitmap, whether the bit value of the dirty register bit DRB of the metadata register having metadata corresponding to the user data in the cache is "1".

[0285] When the dirty register bit DRB is "1", operation S650 may be executed.

[0286] In operation S650, the memory controller 100C may determine whether a load operation has been previously performed on the metadata register having metadata corresponding to the user data in the cache. That is, determine whether a load command LD has been sent.

[0287] When it is determined that the load command LD has not been sent previously, operation S660 may be executed. In operation S660, the memory controller 100C may send a store dirty command STD.

[0288] As Figure 35A shown, when the bit value of the dirty register bit DRB1 corresponding to the first metadata register 511 (refer to Figure 33 ) is "1", the memory controller 100C may determine that dirty metadata is included in the first metadata register 511. In addition, in the case where the load command LD has not been sent previously, invalid metadata may be included in the first metadata register 511.

[0289] In this case, the memory controller 100C may send the store dirty command STD to the memory device 200C to allow only the dirty metadata to be stored in the metadata area MR. Thus, the valid metadata stored in the metadata area MR can be prevented from being corrupted by the invalid metadata of the first metadata register 511.

[0290] In the case where the load command LD has been sent previously, operation S670 may be executed. In operation S670, the memory controller 100C may send a store command ST.

[0291] As Figure 35B shown, in the case where the bit value of the dirty register bit DRB1 corresponding to the first metadata register 511 is "1", the memory controller 100C may determine that dirty metadata is included in the first metadata register 511. In addition, in the case where the load command LD has been sent previously, it is determined that the metadata excluding the dirty metadata of the first metadata register 511 is valid metadata that is substantially the same as the metadata stored in the metadata area MR.

[0292] In this case, the memory controller 100C may send a store command ST to the memory device 200C. Accordingly, valid metadata including dirty metadata cached in the first metadata register 511 may be stored in the metadata region MR. In this case, the metadata may be stored in the metadata region MR faster than when performing a store dirty operation.

[0293] In addition, when the bit value of the dirty register bit DRB is "0", the operation of sending a store dirty command STD or a store command ST may be omitted. As an example, as Figure 35C shown, when the bit value of the first dirty register bit DRB1 is "0", the memory controller 100C may not send a store dirty command STD or a store command ST.

[0294] Then, in operation S680, the memory controller 100C may send a precharge command PRE to the memory device 200C. Accordingly, the write operation in the metadata mode may be completed.

[0295] As referred to Figure 31 and Figures 35A to 35C above, the memory controller 100C according to the present disclosure may effectively schedule commands based on a dirty register bit map, and thus, the performance of the metadata mode may be improved.

[0296] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: a memory bank including a plurality of memory cells; as well as Bank registers, corresponding to memory banks, The memory storage body includes: A master data area configured to: store user data; and The metadata area is configured to: store metadata corresponding to the user data, and Among them, the memory bank registers include: a metadata register configured to: cache metadata to be stored in the metadata area; and A dirty bitmap including location information indicating a location in the metadata area where metadata is to be stored.

2. The memory device of claim 1, wherein: The metadata register includes a plurality of sub-registers configured to store a plurality of metadata corresponding to a plurality of user data, and the dirty bitmap includes a plurality of dirty bits corresponding to the plurality of sub-registers.

3. The memory device of claim 2, wherein: A plurality of different columns of a memory bank are allocated for storing user data, and Wherein, each of the columns of the memory bank other than the plurality of different columns is allocated for storing metadata corresponding to a portion of the user data.

4. The memory device of claim 2, further comprising a storage management circuit, the storage management circuit being configured to: caching dirty metadata in a subregister selected from the plurality of subregisters in response to a write command; and A bit value of a first dirty bit among the plurality of dirty bits is changed, the first dirty bit corresponding to the selected sub-register storing the dirty metadata.

5. The memory device of claim 4, wherein: The storage management circuit is further configured to, in response to a store dirty command, store dirty metadata cached in the selected sub-register in the metadata area.

6. The memory device of claim 5, wherein: The storage management circuit is further configured to, in response to a store dirty command, restrict metadata cached in unselected sub-registers among the plurality of sub-registers from being stored in the metadata area.

7. The memory device of claim 5, wherein: The storage management circuit is further configured to initialize a bit value of a first dirty bit corresponding to the selected subregister after the dirty metadata cached in the selected subregister is stored in the metadata area.

8. The memory device of claim 4, wherein: The storage management circuit is further configured to, in response to a storage command, store dirty metadata cached in the selected subregister and metadata cached in unselected subregisters that are not selected from the plurality of subregisters in the metadata area.

9. The memory device of claim 8, wherein: The storage management circuit is further configured to initialize a bit value of a first dirty bit corresponding to the selected subregister after dirty metadata cached in the selected subregister and metadata cached in unselected subregisters are stored in the metadata area.

10. The memory device according to any one of claims 4 to 9, further comprising a load management circuit, the load management circuit being configured to: In response to a load command, loading metadata stored in the metadata area into the plurality of sub-registers; and Clean metadata stored in the metadata area is loaded to unselected sub-registers that are not selected from the plurality of sub-registers.

11. The memory device of claim 10, wherein: The load management circuit is further configured to restrict clean metadata stored in the metadata area from being loaded into selected sub-registers of the cache having dirty metadata.

12. The memory device of claim 11, wherein: The load management circuit is further configured to maintain a bit value of a first dirty bit corresponding to the selected sub-register after clean metadata stored in the metadata area is loaded into the unselected sub-register.

13. A memory system comprising: A memory device configured to: store user data and metadata corresponding to the user data; as well as A memory controller configured to: control the memory device, Wherein, the memory device comprises: a memory bank comprising a plurality of memory cells; and Bank registers, corresponding to memory banks, The memory storage body includes: a main data area configured to store user data; and a metadata area configured to store metadata corresponding to the user data, and Among them, the memory bank registers include: a metadata register configured to: cache metadata to be stored in the metadata area; and A dirty bitmap including location information indicating a location in the metadata area where metadata is to be stored.

14. The memory system of claim 13, wherein: The memory controller includes: a dirty register bitmap including information about whether dirty metadata is stored in the metadata register; and A scheduler is configured to schedule commands to be provided to the memory controller based on the dirty register bitmap.

15. The memory system of claim 14, wherein: The scheduler is further configured to send a store dirty command to the memory device when dirty metadata is cached in the metadata register and a load command has not been previously sent to the memory device.

16. The memory system of claim 15, wherein: The metadata register includes a plurality of sub-registers configured to store a plurality of metadata corresponding to a plurality of user data, and The memory device is also configured to: in response to a store dirty command, store dirty metadata cached in a subregister selected from the multiple subregisters in the metadata area, and restrict metadata cached in a subregister not selected from the multiple subregisters from being stored in the metadata area.

17. The memory system of claim 14, wherein: The scheduler is further configured to send a store command to the memory device when dirty metadata is cached in the metadata register and a load command has been previously sent to the memory device.

18. The memory system of claim 17, wherein: The metadata register includes a plurality of sub-registers configured to store a plurality of metadata corresponding to a plurality of user data, and The memory device is further configured to store, in response to a store command, dirty metadata cached in a subregister selected from the plurality of subregisters and metadata cached in unselected subregisters among the plurality of subregisters in the metadata area.

19. The memory system of claim 14, wherein: The scheduler is further configured to omit sending of the store dirty command and the store command when the dirty metadata is not cached in the metadata register.

20. A method of operating a memory system, the memory system comprising a memory device and a memory controller for controlling the memory device, the method comprising: sending, by the memory controller, an activate command to the memory device to activate a selected row of a selected memory bank; sending a write command via a memory controller to store user data in the selected memory bank; selectively sending, by the memory controller, a store dirty command or a store command to the memory device, the store dirty command being sent based on dirty metadata being stored in a metadata register, metadata about the user data being stored in the metadata register, and the store command being sent based on the memory controller having previously sent a load command to the memory device; as well as A precharge command is sent to the memory device by the memory controller.

Images