Cluster parity for NAND data placement mode

Abstract

The invention relates to cluster parity for NAND data placement mode. In some examples, improvements to data placement architectures in NAND are disclosed that provide additional data protection by allowing for an improved NAND data placement mode that recovers from certain fault cases. The invention diagonally adds fringes to data across page lines and planes to enhance data protection. A parity is stored in the SLC block for additional protection until a block write is completed, and the parity may then be deleted.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is a patent application for invention titled "Cluster Parity for NAND Data Placement Patterns" with an application date of March 15, 2019, an application number of 201980029446.8.

[0003] Priority application

[0004] This application claims the priority benefits of U.S. Provisional Application No. 62 / 675,451 filed on May 23, 2018 and U.S. Provisional Application No. 62 / 644,282 filed on March 16, 2018, the entire texts of which are incorporated herein by reference. BACKGROUND OF THE INVENTION

[0005] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory.

[0006] Volatile memory requires power to store its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc.

[0007] Non-volatile memory can retain stored data without power and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistive change memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint TM memory, etc.

[0008] Flash memory is used as non-volatile memory for various electronic applications. Flash memory devices typically include one or more groups of single-transistor, floating gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption.

[0009] Two common types of flash memory array architectures include NAND and NOR architectures, named in a logical form based on the configuration of the basic memory cells of each. The memory cells of a memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string are coupled in series (source to drain) between a source line and a bit line.

[0010] Both NOR and NAND architecture semiconductor memory arrays are accessed by a decoder that activates a particular memory cell by selecting the word line coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell can place its data value on the bit line, causing different currents to flow depending on the state of the particular cell that is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the source side select gate (SGD) line. The word lines coupled to the gates of each group of unselected memory cells are driven with a specified pass voltage (e.g., Vpass) to operate each group of the unselected memory cells as transfer transistors (e.g., to transfer current in a manner not limited by their stored data values). Then, current flows from the source line to the bit line through each series-coupled group limited only by the selected memory cells of each group to place the current-encoded data value of the selected memory cells on the bit line.

[0011] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or jointly to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0) to represent one data bit.

[0012] However, a flash memory cell can also represent one of more than two programming states, thus allowing for the fabrication of higher density memories without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In some examples, an MLC can refer to a memory cell that can store two data bits (e.g., one of four programming states), a three-level cell (TLC) can refer to a memory cell that can store three data bits (e.g., one of eight programming states), and a four-level cell (QLC) can store four data bits per cell. MLC is used in a broader context herein, i.e., can refer to any memory cell that can store more than one data bit per cell (i.e., can represent more than two programming states).

[0013] Traditional memory arrays are two-dimensional (2D) structures disposed on the surface of a semiconductor substrate. To increase the memory capacity within a given area and reduce costs, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells and thus the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures (such as 3D NAND architecture semiconductor memory devices) are being developed to further increase memory density and reduce memory costs.

[0014] Such 3D NAND devices typically include a memory cell string coupled in series (e.g., drain to source) between one or more source side select gates (SGS) proximate to the source and one or more drain side select gates (SGD) proximate to the bit line. In an example, the SGS or SGD may include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through a plurality of vertically spaced layers containing respective word lines. A semiconductor structure (such as a polysilicon structure) may extend adjacent to a string of memory cells to form the channel of the memory cells of the string. In an example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be “folded” and thus arranged relative to a U-shaped column. In other examples, a plurality of vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0015] Memory arrays or devices may be combined together to form a bank of a memory system, such as a solid state drive (SSD), universal flash storage (UFS TM ) device, multimedia card (MMC) solid state storage device, embedded MMC device (eMMC TM ) etc. SSDs are particularly useful as a primary storage device for a computer that has advantages over traditional hard drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, an SSD may have reduced seek time, latency, or other delays (such as electromechanical, etc.) associated with a disk drive. SSDs use non-volatile memory cells (such as flash memory cells) to eliminate the requirement for an internal battery supply, thereby allowing the drive to be more versatile and smaller.

[0016] An SSD may include several memory devices (including several dies or logical units such as logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logical functions required to operate the memory devices or interface with an external system. Such an SSD may include one or more flash memory dies that include several memory arrays and peripheral circuitry thereon. The flash memory arrays may include several blocks of memory cells organized into several physical pages. In many instances, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands associated with memory operations from a host, such as read or write operations that transfer data (such as user data and associated integrity data such as error data and address data, etc.) between the memory device and the host, or an erase operation that erases data from the memory device. SUMMARY OF THE INVENTION

[0017] One aspect of the present application relates to a NAND memory device, which includes: a NAND memory cell array organized into multiple planes and addressable by multiple page rows; and a controller configured to: store a received data item in the array such that a first part, a second part, and a third part of the received data item are stored on different page rows; calculate a parity value of the received data item using the first part, the second part, and the third part; assign the parity value to a first position within a parity cluster; calculate a combined parity value by combining the parity value with a second parity value from a second parity cluster, the second parity value occupying the same first position in the second parity cluster; erase the parity value and the second parity value; and store the combined parity value.

[0018] Another aspect of the present application relates to a method, which includes: at a memory controller: storing a received data item in a NAND array such that a first part, a second part, and a third part of the received data item are stored on different page rows; calculating a parity value of the received data item using the first part, the second part, and the third part; assigning the parity value to a first position within a parity cluster; calculating a combined parity value by combining the parity value with a second parity value from a second parity cluster, the second parity value occupying the same first position in the second parity cluster; erasing the parity value and the second parity value; and storing the combined parity value.

[0019] Another aspect of the present application relates to a non-transitory machine-readable medium storing instructions that, when executed, cause a controller of a memory device to perform operations including: storing a received data item in a NAND array of the memory device such that a first portion, a second portion, and a third portion of the received data item are stored on different page rows; calculating a parity value of the received data item using the first portion, the second portion, and the third portion; assigning the parity value to a first position within a parity cluster; calculating a combined parity value by combining the parity value with a second parity value from a second parity cluster, the second parity value occupying the same first position in the second parity cluster; erasing the parity value and the second parity value; and storing the combined parity value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the drawings, which are not necessarily to scale, the same numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not by way of limitation, the various embodiments discussed in the present invention.

[0021] Figure 1 An example of an environment including a memory device is illustrated.

[0022] Figures 2 to 3 A schematic diagram of an example of a 3D NAND architecture semiconductor memory array is illustrated.

[0023] Figure 4 An example block diagram of a memory module is illustrated.

[0024] Figure 5 The possible effects of a programming failure of a NAND are illustrated.

[0025] Figure 6 The possible effects of an asynchronous power loss during programming of a NAND are illustrated.

[0026] Figure 7 AND 8 An improved NAND data placement pattern of data on a TLC NAND array according to some examples of the present invention is illustrated.

[0027] Figure 9 The logical placement of parity pages in volatile memory of a controller or other components of a NAND according to some examples of the present invention is illustrated.

[0028] Figure 10 A schematic diagram of parity value storage for storing parity pages in non-volatile NAND is illustrated.

[0029] Figure 11 Flowchart of method 1100 for storing data on a NAND die of a NAND device by applying an improved NAND data placement pattern according to some examples of the present invention.

[0030] Figure 12 Examples of uncorrectable errors in NAND according to some examples of the present invention.

[0031] Figure 13 Description of the storage of multiple parity values arranged in multiple clusters according to some examples of the present invention.

[0032] Figure 14 Description of the storage of multiple compressed parity values according to some examples of the present invention.

[0033] Figure 15 Flowchart of a method for clustering parity values in an improved NAND data placement pattern of a NAND device according to some examples of the present invention.

[0034] Figure 16 Schematic diagram of a memory controller according to some examples of the present invention.

[0035] Figure 17 Is a block diagram of an example of a machine on which one or more embodiments may be implemented. Detailed Description

[0036] In some examples, a method of organizing data written to a memory device (such as a NAND memory device) to protect against certain types of failures is disclosed. For example, a first portion is programmed on a first page row and a first plane, a second portion is programmed on a second page row and a second plane, a third portion is programmed on a third page row and a third plane, and a fourth portion is programmed on a fourth page row and a fourth plane. The first page row, the second page row, the third page row, the first plane, the second plane, and the third plane are selected such that the first portion, the second portion, and the third portion are stored in memory cells on different page rows and different planes relative to each other.

[0037] Electronic devices such as mobile electronic devices (such as smartphones, tablet computers, etc.), electronic devices for automotive applications (such as automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected devices or apparatuses (such as Internet of Things (IoT) devices, etc.) have different storage requirements that particularly depend on the type of the electronic device, the usage environment, the performance expectations, etc.

[0038] An electronic device can be divided into several main components: a processor (such as a central processing unit (CPU) or other main processor), a memory (such as one or more volatile or non-volatile random access memory (RAM) memory devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.) and a storage device (such as a non-volatile memory (NVM) device, such as a flash memory, read-only memory (ROM), SSD, MMC or other memory card structures or assemblies, etc.). In some instances, the electronic device can include a user interface (such as a display, touch screen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc.

[0039] Figure 1 An example of an environment 100 is described that includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 can be included in various products 150 (such as Internet of Things (IoT) devices (such as refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.)) to support the processing, communication or control of the product 150.

[0040] The memory device 110 includes a memory controller 115 and a memory array 120, and the memory array 120 includes (for example) several individual memory dies (such as a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, stacked vertical structures are used to increase the number of layers and physical pages and accordingly increase the density of the memory device (such as a storage device). In an instance, the memory device 110 can be a discrete memory or a storage device component of the host device 105. In other instances, the memory device 110 can be a part of an integrated circuit (such as a system-on-chip (SOC), etc.) stacked with or otherwise included with one or more other components of the host device 105.

[0041] One or more communication interfaces can be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC TM interface or one or more other connectors or interfaces. The host device 105 can include a host system, an electronic device, a processor, a memory card reader or one or more other electronic devices external to the memory device 110. In some instances, the host 105 can be a machine that has some or all of the components discussed with reference Figure 17 to the machine 1700.

[0042] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to transfer (e.g., write or erase) data to and / or transfer (e.g., read) data from one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. The memory controller 115 may particularly include circuitry or firmware that includes one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and to provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to and from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0043] The memory manager 125 may particularly include circuitry or firmware, such as several components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host) into device commands (e.g., commands associated with the operation of the memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., for accomplishing various memory management functions).

[0044] The memory manager 125 may include a set of management tables 130 configured to store various information associated with one or more components of the memory device 110 (e.g., various information associated with the memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 may include information about the block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In some instances, a bit error may be referred to as an uncorrectable bit error if the number of detected errors in one or more of the error counts is above a threshold. The management tables 130 may particularly store the counts of correctable or uncorrectable bit errors.

[0045] The array controller 135 may in particular include circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory operations may be based on, for example, host commands received from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

[0046] The array controller 135 may include an error correction code (ECC) component 140, which may in particular include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to, or reading data from, one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to actively detect error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data and recover from the error occurrences while maintaining the integrity of the data transmitted between the host 105 and the memory device 110 or maintaining the integrity of the stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) faulty memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0047] In some instances, a memory array may include several NAND dies, and one or more functions of the memory controller 115 for a particular NAND die may be implemented on a die - on - controller on the particular die. Other organizations and partitioning of control functionality may also be utilized, such as a controller for each die, plane, super - block, block, page, and the like.

[0048] The memory array 120 may include a number of memory cells arranged as (e.g.) several devices, semiconductor dies, planes, sub - blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may include 18,592 data bytes (B) (16,384 + 2208 bytes) per page, 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two data bits per cell (i.e., 4 programmable states)) may include 18,592 data bytes (B) (16,384 + 2208 bytes) per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the write time and twice the program / erase (P / E) cycles required of the corresponding TLC memory device. Other examples may include other numbers or arrangements. In some instances, a memory device or a portion thereof may selectively operate in SLC mode or a desired MLC mode (e.g., TLC, QLC, etc.).

[0049] In operation, data is typically written to or read from the NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (such as read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as needed. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0050] Although a page of data can contain several bytes of user data (such as a data payload containing several data sectors) and its corresponding metadata, the size of a page typically only refers to the number of bytes used to store the user data. As an example, a page of data with a page size of 4KB can contain 4KB of user data (such as 8 sectors presenting a sector size of 512B) and metadata corresponding to the user data (such as 32B, 54B, 224B, etc.), such as integrity data (such as error detection or correction code data), address data (such as logical address data, etc.) or other metadata associated with the user data.

[0051] Different types of memory cells or memory arrays 120 can provide different page sizes or require different amounts of metadata associated with them. For example, different memory device types can have different error rates, which can result in different amounts of metadata required to ensure the integrity of data pages (e.g., a memory device with a higher error rate requires more error correction code data bytes than a memory device with a lower error rate). As an example, a multi-level cell (MLC) NAND flash device can have a higher error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, the MLC device requires more metadata bytes for error data than the corresponding SLC device.

[0052] Figure 2 Illustrate a number of string memory cells (such as the first to third A 0 201A 0 and sub-block A n 201A n and sub-block B 0 201B 0 and sub-block B n 201B n etc.) organized into blocks (such as block A 201A, block B 201B, etc.) and sub-blocks (such as sub-block A 0 memory strings 205A 0 to 207A 0 and the first to third A n memory strings 205A n to 207A n and the first to third B0 Memory string 205B 0 to 207B 0 , first to third B n Memory string 205B n to 207B n An example schematic diagram of a 3D NAND architecture semiconductor memory array 200 (such as). The memory array 200 represents a part of a larger number of similar structures commonly found in blocks, devices, or other units of a memory device.

[0053] Each string of memory cells includes a number of layers of charge storage transistors (such as floating gate transistors, charge trapping structures, etc.) stacked in the Z direction (source to drain) on a source line (SRC) 235 or a source side select gate (SGS) (such as first to third A 0 SGS231A 0 to 233A 0 , first to third A n SGS231A n to 233A n , first to third B 0 SGS231B 0 to 233B 0 , first to third B n SGS231B n -233B n , etc.) and a drain side select gate (SGD) (such as first to third A 0 SGD 226A 0 to 228A 0 , first to third A n SGD 226A n to 228A n , first to third B 0 SGD 226B 0 to 228B 0 , first to third B n SGD 226B n to 228B n etc.). Each string of memory cells in the 3D memory array can be arranged as data lines (such as bit lines (BL) BL0 to BL2 220 to 222) in the X direction and as physical pages in the Y direction.

[0054] Within a physical page, each layer represents a row of memory cells, and each string of memory cells represents a column. A sub-block may represent one or more physical pages. A block may contain several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although described herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having eight layers of memory cells, in other instances, the memory array 200 may include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or layers. For example, each string of memory cells may include more or fewer layers (e.g., 16, 32, 64, 128, etc.) and one or more additional semiconductor material layers above or below the charge storage transistors (e.g., select gates, data lines, etc.). As an example, a 48GB TLC NAND memory device may include 18,592 data bytes (B) per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and four or more planes per device.

[0055] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically or otherwise operably connected to) an access line (e.g., word line (WL) WL0 0 through WL7 0 210A through 217A, WL0 1 through WL7 1 210B through 217B, etc.), and the access lines may commonly couple the control gates (CG) across a particular layer or a portion of a layer as needed. A particular memory cell in a particular layer and correspondingly in a string in the 3D memory array may be accessed or controlled using the corresponding access line. The select gate group may be accessed using various select lines. For example, the first through third A 0 SGD 226A 0 through 228A 0 may be accessed using the A 0 SGD line SGDA 0 225A 0 The first through third A n SGD 226A n through 228A n may be accessed using the A n SGD line SGDA n 225A n The first through third B 0 SGD 226B 0 through 228B 0 may be accessed using the B 0 SGD line SGDB 0 225B 0Access, and the first to third B n SGD 226B n to 228B n can be used B n SGD line SGDB n 225B n Access. The first to third A 0 SGS231A 0 to 233A 0 and the first to third A n SGS231A n to 233A n can use the gate selection line SGS 0 230A access, and the first to third B 0 SGS231B 0 to 233B 0 and the first to third B n SGS231B n to 233B n can use the gate selection line SGS 1 230B access.

[0056] In an example, the memory array 200 may include several layers of semiconductor material (such as polysilicon, etc.) configured to couple the control gates (CG) or select gates (or portions of the CG or select gates) of the respective memory cells of the array. A particular string of memory cells in the array can be accessed, selected, or controlled using a combination such as bit lines (BL) and select gates, and a particular memory cell at one or more layers in a particular string can be accessed, selected, or controlled using one or more access lines (such as word lines).

[0057] Figure 3 An example schematic diagram showing a portion of a NAND architecture semiconductor memory array 300 including a two-dimensional array of a plurality of memory cells 302 and sense amplifiers or devices 360 arranged in strings (such as the first to third strings 305 to 307) and layers (such as the respective word lines (WL) WL0 to WL7 310 to 317, drain side select gate (SGD) lines 325, source side select gate (SGS) lines 330, etc.). For example, the memory array 300 may illustrate, for example Figure 2 an example schematic diagram of a portion of a physical page of the memory cells of a 3D NAND architecture semiconductor memory device as described in

[0058] Each string of memory cells is coupled to a source line (SRC) using a respective source-side select gate (SGS) (e.g., first to third SGSs 331 to 333), and is coupled to a respective data line (e.g., first to third bit lines (BL) BL0 to BL2 320 to 322) using a respective drain-side select gate (SGD) (e.g., first to third SGDs 326 to 328). Although in the example of Figure 3 eight layers (e.g., using word lines (WL) WL0 to WL7 310 to 317) and three data lines (BL0 to BL2 326 to 328) are illustrated, other examples may include strings of memory cells having more or fewer layers or data lines as needed.

[0059] In a NAND architecture semiconductor memory array (e.g., example memory array 300), the state of a selected memory cell 302 can be accessed by sensing a change in current or voltage associated with a particular data line containing the selected memory cell. The memory array 300 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In an example, one or more drivers can activate the particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates depending on the type of operation to be performed on the particular memory cell or group of memory cells.

[0060] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) can be applied to a selected word line (e.g., WL4) and thus to the control gate of each memory cell coupled to the selected word line (e.g., first to third control gates (CG) 341 to 343 of the memory cells coupled to WL4). The programming pulse can (e.g.) start at 15V or near 15V and can increase in magnitude during the application of each programming pulse in some examples. When the program voltage is applied to the selected word line, a potential such as ground potential (e.g., Vss) can be applied to the data line (e.g., bit line) and the substrate (and thus the channel between the source and drain) of the memory cell intended for programming, resulting in a charge transfer from the channel to the floating gate of the target memory cell (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0061] In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells not intended for programming, or a prohibit voltage (such as Vcc) may be applied to data lines (such as bit lines) having memory cells not intended for programming to (for example) prohibit charge transfer from the channel to the floating gates of such non-target memory cells. The pass voltage may (for example) vary depending on the proximity of the applied pass voltage to the word lines intended for programming. The prohibit voltage may include a supply voltage (Vcc) with respect to a ground potential (such as Vss), for example, a voltage from an external source or supply (such as a battery, an AC to DC converter, etc.).

[0062] As an example, if a programming voltage (such as 15V or greater) is applied to a specific word line (such as WL4), a pass voltage of 10V may be applied to one or more other word lines (such as WL3, WL5, etc.) to prohibit programming of non-target memory cells or to maintain the values stored in such memory cells not intended for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to inhibit programming of the non-target memory cells may decrease. For example, when a programming voltage of 15V is applied to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the pass voltage or the number of word lines, etc. may be higher or lower or more or less.

[0063] A sense amplifier 360 coupled to one or more of the data lines (such as the first, second, or third bit lines (BL0 to BL2) 320 to 322) may detect the state of each memory cell in the corresponding data line by sensing the voltage or current on a specific data line.

[0064] Between the application of one or more programming pulses (such as Vpgm), a verification operation may be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it may be prohibited from further programming. If the selected memory cell has not reached its intended programmed state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programmed state after a specific number (such as a maximum number) of programming pulses, the selected memory cell or the string, block, or page associated with the selected memory cell may be marked as defective.

[0065] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) can be applied to the substrate (and thus the channel between the source and drain) of the memory cells intended for erasure (e.g., using one or more bit lines, select gates, etc.), while keeping the word line of the target memory cell at a potential such as ground potential (e.g., Vss), thereby causing charge transfer from the floating gate of the target memory cell to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0066] Figure 4 An example block diagram illustrating a memory device 400 that includes a memory array 402 having a plurality of memory cells 404 and one or more circuits or components for providing communication with or performing one or more memory operations on the memory array 402. The memory device 400 can include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, an input / output (I / O) circuit 426, and a memory control unit 430.

[0067] The memory cells 404 of the memory array 402 can be arranged in blocks, such as a first block 402A and a second block 402B. Each block can include sub-blocks. For example, the first block 402A can include a first sub-block 402A 0 and a second sub-block 402A n , and the second block 402B can include a first sub-block 402B 0 and a second sub-block 402B n . Each sub-block can include a number of physical pages, and each page includes a number of memory cells 404. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 404, in other examples, the memory array 402 can include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 404 can be arranged in a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using (e.g.) access lines 406, a first data line 410, or one or more select gates, source lines, etc.

[0068] The memory control unit 430 can control the memory operations of the memory device 400 based on one or more signals or instructions received on a control line 432 (e.g., including one or more clock signals or control signals indicating a desired operation (e.g., write, read, erase, etc.)) or an address signal (A0 to AX) received on one or more address lines 416. One or more devices external to the memory device 400 can control the values of the control signals on the control line 432 or the address signals on the address lines 416. Examples of devices external to the memory device 400 can include (but are not limited to) Figure 4Hosts, memory controllers, processors, or one or more circuits or components not described therein.

[0069] Memory device 400 can use access lines 406 and first data lines 410 to transfer (e.g., write or erase) data to or from one or more of the memory cells 404 (e.g., read). The row decoder 412 and column decoder 414 can receive and decode address signals (A0 to AX) from the address lines 416, can determine which of the memory cells 404 should be accessed, and can provide signals to one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0 to WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0 to BLn)), as described above.

[0070] Memory device 400 can include sensing circuitry, such as sense amplifiers 420, configured to determine the value of data on the memory cells 404 (e.g., read) or determine the value of data written to the memory cells 404. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 can read the logic level of the selected memory cell 404 in response to a read current flowing into the memory array 402, through the selected string, and to the data lines 410.

[0071] One or more devices external to the memory device 400 can communicate with the memory device 400 using I / O lines (DQ0 to DQN) 408, address lines 416 (A0 to AX), or control lines 432. The input / output (I / O) circuit 426 can use the I / O lines 408 to transfer data values into or out of the memory device 400 according to (e.g.) the control lines 432 and address lines 416, e.g., transfer into or out of the page buffer 422 or the memory array 402. The page buffer 422 can store data received from one or more devices external to the memory device 400 before programming the data into the relevant part of the memory array 402, or can store data read from the memory array 402 before transmitting the data to one or more devices external to the memory device 400.

[0072] The column decoder 414 can receive address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSELn). The selector 424 (e.g., selection circuit) can receive the column select signals (CSEL1 to CSELn) and select data representing the value of data read from or programmed into the memory cells 404 in the page buffer 422. The selected data can be transferred between the page buffer 422 and the I / O circuit 426 using the second data line 418.

[0073] The memory control unit 430 may receive positive and negative supply signals from an external source or supplier, such as an internal or external battery, an AC to DC converter, etc., such as a supply voltage (Vcc) 434 and a negative supply (Vss) 436 (e.g., ground potential). In some instances, the memory control unit 430 may include a regulator 428 that internally provides positive or negative supply signals.

[0074] ECC and other techniques have significantly improved the reliability of NAND devices. However, there are specific scenarios where additional protection against data loss is desired. For example, as Figure 5 shown, a write operation with a programming failure when programming page row X 510 can corrupt many pages within the plane. As Figure 5 shown, all pages in a plane (e.g., plane 1) have been corrupted due to the programming failure of page row X 510. Similarly, and as Figure 6 shown, an asynchronous power loss (power loss to the NAND device, without warning) during the programming of the first page row X 607 can also corrupt a different page row Z 605.

[0075] As used herein, a page row is a logical construct that identifies a group of pages including pages at the same location in each plane within a plane group. Thus, for example, the first page in planes 0 to 3 is identified by page row 0. A page is composed of memory cells belonging to the same word line. A block is a group of pages, i.e., all NAND strings (a NAND string is a group of NAND cells connected in series) that share the same group of word lines. In some NAND configurations, a block is the smallest erasable unit. A page is the smallest addressable unit for reading and writing. A plane is a group of physical blocks on a single NAND die, which is configured for operation such that physical blocks from each of multiple planes can be erased in parallel (i.e., during a given time interval, physical blocks can be erased substantially simultaneously or overlapping each other), but only a single physical block in any individual plane can be erased at any given time. There can be multiple planes per NAND die. As Figures 5 to 8 shown in 10 and 12 to 14, a plane is represented by a single physical block (selected from the list of physical blocks of the plane), and thus, for example, in Figure 5 a plane depicts a list of pages in the selected physical block, but there are additional physical blocks not shown for clarity.

[0076] In some instances, improvements to NAND devices are disclosed, which are achieved by allowing from Figure 5 and Figure 6An improved NAND data placement pattern for the fault case recovery described in [reference] is used to provide additional data protection. The present invention stripes data across page rows and planes to ensure that a power failure or programming error affecting an entire page row or plane does not corrupt an entire data item and at most corrupts a single portion of the data item. In some instances, parity information may be calculated and stored until programming is complete. This parity information can be used to recover the corruption of a portion of the data item.

[0077] For example, the NAND may receive a data item from a host device. This data item may be divided into several parts. For the purposes of this description, an example will be used in which the received data item is divided into four parts. Those skilled in the art who benefit from the present invention should readily understand that the received data item can be divided into fewer or more parts. The first part may be programmed at a first location in the NAND, the second part at a second location, the third part at a third location, and the fourth part at a fourth location. The first location, second location, third location, and fourth location may be selected such that the first part, second part, third part, and fourth part are stored in memory cells on different page rows and different planes relative to each other. The different locations of the first, second, third, and fourth parts may include different planes, pages, dies, blocks, and the like. In some instances, the first, second, third, and fourth parts may be stored on the same die. The first, second, third, and fourth parts may be coupled to one or more other parts in various relationships. For example, in some instances, the first and second parts may be stored adjacent to each other according to being stored in adjacent page rows and adjacent planes (e.g., as Figure 7 shown in [reference]). As used herein, "adjacent" means the next page row and / or plane in sequence. In some instances, the second and third parts may be stored adjacent to each other according to being stored in adjacent page rows and adjacent planes. In some instances, the third and fourth parts may be stored adjacent to each other according to being stored in adjacent page rows and adjacent planes. See, for example, Figure 7 710, 715, 720, and 725 in [reference] (discussed in more detail below). Thus, the parts of the data are stored such that a corruption in a single plane or a single word line corrupts at most a single part of the data. This enables the NAND to reconstruct the corrupted part using parity data. In some instances, each of the first, second, and third parts may be the next page, an additional page, and the upper page relative to each other. In these instances, the fourth part may be a copy of one of the first, second, and third parts.

[0078] Figure 7 and 8 show an improved NAND data placement pattern of data on a TLC NAND array 700 having four planes and 216 page rows (page rows 24 to 203 are not shown for clarity). Figure 8It is the display page line 204 to 215 Figure 7 In some examples, TLC NAND array 700 may be on a single die having four planes. Figure 7 In FIG. 1 , the page rows of NAND are represented by rows, and the planes of NAND are represented by columns. The data items to be programmed (denoted by P n ) is divided into several parts: the first P n 、Second P n 、Third P n and the fourth P n , where n indicates different data items. For example, the first data item received by the host can be divided into several parts: the first P 1 、Second P 1 、Third P 1 and the fourth P 1 The data item can be a page, word, block, or any other unit of data sent by the host.

[0079] The example portion may include a lower page, an upper page, and additional pages of a TLC programming page corresponding to the data item. In some examples, for pages 0 to 3, the first P n Can be the next page, second page n It can be an extra page, and the third P n The fourth page may be the upper page, thus corresponding to the programming order of TLC memory. n Can be the first P n A copy of the fourth P n can be written the same as writing to the first P n For QLC NAND, the fourth P n It can be the fourth programming page. Figure 7 In one example improved NAND data placement pattern, the portion is diagonally striped so that a particular data item P x Each portion of is on a different plane and on a different page relative to the other portions. In some examples, data item P x Each portion of may be placed in a page row and on a plane that is one greater than the previous portion. Thus, the first portion may be placed at location (page row X, plane Y), the second portion may be placed at location (page row X+1, plane Y+1), the third portion may be placed at location (page row X+2, plane Y+2), and the fourth portion may be placed at location (page row X+3, plane Y+3). It should be appreciated that the "first," "second," "third," and "fourth" portions are merely convenient descriptors for different portions of the data.

[0080] When the part is placed, the plane can be folded back to the first plane. Figure 7 In the display, P 3The first part is placed in plane 2 (page 0), the second part can be placed in plane 3 (page 1), and the third part can be folded back and placed in plane 0 (page 2), and the fourth part can be placed in plane 1 (page 3). This data placement scheme ensures that Figure 5 and Figure 6 the error conditions shown in n will affect at most only a single part of data item P. As shown, parts such as the first part (e.g., at 725) can be repeated.

[0081] In some instances, data is written to NAND in groups of four data items P 1 to P 4 across four page rows (page rows 0 to 3) and four plane rows (plane 0 to 3). It should be understood that each page row (represented as Figure 7 and 8 the rows in 1 can store the same part of different data items (e.g., the first parts of data items P 2 P 3 P 4 are written to page 0 in planes 0, 1, 2, and 3 respectively). It should be understood that each plane can store different parts of different data items, i.e., each plane stores the first part, the second part, the third part, and the fourth part, but each part belongs to a different P x . For each consecutive next page row, different parts of the data items are written and the data items are shifted one bit to the right (in the case of a wrap-around process) to prevent the second part of the same data item from being written to the same plane. Thus, page row 1 can store the second parts of data items P 1 P 2 P 3 and P 4 but are written to planes that are one more than the previous page, and thus are written to planes 1, 2, 3, and 0 respectively.

[0082] In some instances, the first parts of the first group of four data items (e.g., the first P 1 the first P 2 the first P 3 the first P 4 ) can correspond to the next page of the SLC NAND, the second parts (the second P 1 the second P 2 the second P 3 the second P 4 ) can correspond to an additional page, the third parts (the third P 1 the third P 2 the third P 3 the third P 4 ) can correspond to the previous page, and the fourth parts (the fourth P1 , Fourth P 2 , Fourth P 3 , Fourth P 4 ) may correspond (in TLC NAND) to a copy of the first part (next page).

[0083] In some instances, for all groups of data items, the mapping between the pages and parts shown in the figure may be the same. A group is represented by a dashed box in Figure 7 and includes four data items of a group in Figure 7 . For example, for group 2 (page rows 4 to 7), the first part may be the next page, the second part may be the upper page, the third part may be an additional page, and the fourth part may be a copy of the next page. It should be understood that larger or smaller group sizes may be utilized. Thus, a group may include 8 data items P 1 to P 8 and may span 8 planes and 8 pages.

[0084] In other instances, rather than the first part of all groups storing the next page, the second part storing the additional page, the third part storing the upper page, and the fourth part storing a copy of the first part, the parts stored by each group may be shifted. For example, for group 2 (page rows 4 to 7), the mapping between the parts and the pages may be changed such that the first part may store the additional page, the second part may store the upper page, the third part may store the next page, and the fourth part may be a copy of the first part (additional page). For group 3 (pages 8 to 11), the mapping between the parts and the pages may be shifted again. Thus, the first part may be the upper page, the second part may be the next page, the third part may be the additional page, and the fourth part may be the same as the first part (upper page). For group 4 (pages 12 to 15), the programmed pages assigned to each part may be shifted again to be the same as the programmed pages in pages 0 to 3, and so on. Thus, the cycle is:

[0085] Page line Plane (0…3) 0 Lower 1 Extra 2 Upper 3 Lower 4 Extra 5 Upper 6 Lower 7 Extra 8 Upper 9 Lower 10 Extra 11 Upper … …

[0086] In addition to the diagonal part placement scheme, parity pages may be calculated from the data item parts. For example, the parity page may be the XOR of the data in the first part, the second part, the third part, and the fourth part. For example:

[0087]

[0088] where is the XOR operator.

[0089] The parity check value can be calculated and temporarily stored in a volatile memory (such as RAM), and then it is periodically stored in non-volatile storage in a NAND block separate from the user data. The diagonal placement of parts of the page data ensures that the remaining data can be recovered when there are programming defects or an asynchronous power loss erases the entire page or entire plane, because at most only one part of a data item will be lost, and because of the XOR parity check data, it is recoverable.

[0090] Figure 9 Illustrate the logical placement of parity check pages in the volatile memory of the controller or other components of the NAND according to some examples of the present invention. Figure 9 The parity check pages shown in Figure 7 and 8 are parity check pages calculated for the n data items. When programming the data items into the Figure 7 NAND in 1 to 12 the parity check can be calculated and stored in a volatile memory (such as random access memory). At a first time T0, parts of the data items Figure 9 shown in

[0091] from 13 to 24 can be written to page rows 0 to 11 and planes 0 to 3 of die 700. At the same time, the parity check values 902 to 924 of these data items can be calculated and stored in a volatile storage device such as RAM, as Figure 9 shown. In some examples, the parity check values 902 to 924 are overwritten by the parity check values 926 to 948. In some examples, the parity check values 902 to 924 can be written to the NAND before they are overwritten, for example, written to a reliable SLC block. Similarly, at time T1, the parity check values of pages 12 to 23 can be calculated and the parity check bits are stored in the RAM when these pages are written, as

[0092] Figure 10 A schematic diagram of a parity check page storage 1000 for storing parity check pages in non-volatile NAND is shown. In the Figure 10 example, the parity check page storage 1000 can be configured as an SLC block to improve reliability. Figure 10 The parity check page storage 1000 shown in Figure 7in the separated locations of the TLC NAND array 700. In other instances, parity pages may be stored on the same die as the user data from which they are generated. Parity pages 1 to 12 are stored at time T0. The cleared page row count (FPC) indicates the number of page rows of programmed user data (e.g., on die 700). Parity pages 13 to 24 are stored at time T1, and so on, until parity pages 205 to 216 are stored at time T17.

[0093] The parity data stored in the RAM or SLC 1000 can be used to recover user data pages. Returning to Figure 7 , if plane 1 is damaged (as Figure 5 shown), then only a single part of the P n data item will be damaged due to the failure on plane 1. The system can utilize the parity data to recover these parts. Individual parts of the user data can be recovered by applying an XOR operation to the remaining pages and the parity pages. For example, if plane 1 is damaged, then the second part 715 of the P 1 data item will be damaged. This part can be recovered by applying an XOR operation to the first part 710 of P 1 , the third part 720 of P 1 , the fourth part of P 1 , and the parity 902 of P1. Similarly, if a page row is damaged as Figure 6 shown, then only a single part of the user data page will be lost. For example, if Figure 7 only one of page rows 0 to 3 of 1 is damaged, then only a single part of a particular user page will be lost. For example, if the page on page row 1 is damaged, then the second part 715 of P

[0094]

[0095] is damaged, but the first, second, and fourth parts are not damaged and thus the third part can be reconstructed using the parity values. For example, by:

[0096] Figure 11A flowchart of method 1100 for storing data on a NAND die of a NAND device using an improved NAND data placement pattern according to some examples of the present invention is shown. A host device may send a data item to be written to the NAND. This data item may be programmed into the following several parts of the NAND: a first part, a second part, a third part, and a fourth part. The example parts may correspond to the upper page, lower page, and extra page of a TLC NAND. In other examples, the data item may be divided into only two parts (corresponding to the lower page and upper page of an MLC NAND) or four parts (corresponding to the lower page, upper page, middle page, and extra page of a QLC NAND). In other examples, the parts may not correspond to the programming stages of the NAND, but may be divided in other ways (such as most significant bits, least significant bits, and the like). In some examples, the programmed pages of the NAND corresponding to the parts may be shifted based on the data item grouping. Thus, in the first grouping of data items, the lower page is written on the first page row of the group, and in a later grouping of the data items, the extra page may be written on the first page row of the group, and so on.

[0097] At operation 1102, the controller may program the first part of the received data to the first page row and the first plane in the NAND array. At operation 1104, the controller may program the second part of the received data to the second page row and the second plane in the NAND array. At operation 1106, the controller may program the third part of the received data to the third page row and the third plane in the NAND array. At operation 1107, the controller may program the fourth part of the received data to the fourth page row and the fourth plane in the NAND array. In some examples, the fourth part may be a copy of one of the first, second, third, or fourth parts. For example, the fourth part may be a copy of the part first written for the group (such as the first part). The first page row, second page row, third page row, fourth page row, first plane, second plane, third plane, and fourth plane may be selected such that the first part, second part, third part, and fourth part of a particular data item are programmed into memory cells on different page rows and different planes relative to each other. In some examples, all the locations are on the same die. At operation 1108, the NAND memory device may calculate a parity value of the data item using the first, second, and third parts. This parity value may be stored in volatile or non-volatile memory.

[0098] While the above data placement pattern minimizes data loss by strategically placing data and using parity values, once the NAND blocks corresponding to the parity data are programmed, the parity values can be discarded. Although this saves the overhead of storing parity data, this parity data can be used with the same data placement pattern to recover from uncorrectable error correction code (UECC) situations where NAND cannot recover data using traditional ECC. For example, as Figure 12 shown, there may be unrecoverable ECC errors in plane 1, page rows Z to Z + 5.

[0099] By storing data using the improved NAND data placement pattern described above, the loss of individual parts of the data can be recovered using parity values. From the perspective of the additional overhead for storing parity values, this cost may be high. In some instances, methods, systems, memory devices, and machine-readable media for cluster parity storage of NAND devices that utilize the improved data placement pattern disclosed above are disclosed. Instead of storing each parity value, XOR operations can be used to combine parity values from multiple data items and store them in a compressed form to reduce the reserved space for saving parity values. The compressed parity values can be a combination of multiple parity values, for example, an XOR combination of two or more parity values.

[0100] For example, Figure 13 shows SLC NAND block 1300 storing multiple parity values arranged in multiple clusters. In Figure 13 , it is arranged in 16 clusters of 54 page rows for each of the four planes of each cluster. Thus, each cluster contains 216 parity values. Each parity value corresponds to a data item (e.g., from Figure 10 ). The first compressed parity value can be created by performing an XOR operation on the parity values in the same position in each different cluster. For example, the compressed parity value can be created from the XOR of parity value 1, parity value 217, and so on up to parity value 3241. This is represented by the dark line in Figure 13 . The second compressed parity value can be created by performing an XOR operation on the second parity values in each cluster (e.g., parity 2, parity 218, and so on up to parity value 3242). Clusters 2 to 14 included in the XOR calculation are not shown for brevity and clarity.

[0101] More generally, a set of compressed parity values can be created. The relative position in the cluster can be used to reference each parity value in each cluster using the following notation: (cluster, page, plane). For example, Figure 13The parity value 1 in [it] can be (0, 0, 0), which indicates that this parity value is in cluster 0, page 0, and plane 0. The page value can be relative to the cluster. That is, parity 3241 can be addressed by (15, 0, 0) because it is in the first page and the first plane of cluster 15, even though it is generally in page row 810. The compressed parity value can be calculated by performing an XOR operation on the parity values at the same relative position for all clusters. For example:

[0102]

[0103] As Figure 13 shown, the value of X is in the range of 0 to 53, and the value of Y is in the range of 0 to 3.

[0104] As Figure 14 shown, these compressed parity values can be stored in NAND and can be labeled as PARITYX a . In some instances, the compressed parity value and / or the uncompressed parity value can be stored in the original NAND block before closing the original block. Then, the uncompressed value can be deleted and the space can be freed for other values (such as the compressed parity value). The data item P n for calculating the parity value used to calculate the compressed parity value can be called the group of compressed parity data items G n . For example, if Figure 13 shows the parity value corresponding to the data item P Figure 7 from n , then all parts of the data items for the constituent parity values (such as parity 1, parity 217, etc. up to parity 3241) used to generate the first compressed parity value can be parts of the group of compressed parity data items G 1 . For parity value 1, the part of the data item can include the first P Figure 7 from 1 , the second P 1 , the third P 1 , and the fourth P 1 .

[0105] If an uncorrectable ECC error occurs (such as Figure 12 shown), then the NAND device can use the compressed parity value to reconstruct the damaged part of the data item. By performing an XOR operation on the compressed parity value and the values of the parts of the data items in group G n (excluding the damaged part, of course), the damaged part of the data item can be recovered. For example, in the data item P Figure 7 from ( 1In the first part of the non-recoverable situation, the system can perform an XOR operation on the compressed parity value PARITYX1 and the group G except for the data item P 1 in the first part to 1 recover the data item P 1 in the data part (including the second, third, and fourth parts of the data item P 1 ) in the group G

[0106] Figure 15 A flowchart illustrating a method of clustering parity values according to some examples of the present invention is shown. At operation 1502, incoming data can be stored according to the disclosed improved NAND data placement pattern. For example, the received data item is stored in a memory cell of a NAND array such that the first, second, third, and fourth parts of the data item are stored in memory cells on different page rows and different planes relative to each other in the array, as Figure 7 illustrated. At operation 1504, a parity value of the received data item can be calculated and stored in a volatile or non-volatile storage device. As mentioned, the parity value can be an XOR of parts of the data item. At operation 1506, the NAND device can assign the parity value calculated at operation 1504 to a position (e.g., the first position of the parity cluster) in the parity cluster. At operation 1508, the same position in each of the clusters can be used to calculate a compressed parity value, for example, by applying an XOR operator to the parity values in the same position in each parity value cluster.

[0107] This compressed parity value can be used to recover the data part as previously described. For example, a damaged data part can be recovered by performing an XOR operation on the data part (except for the damaged data part) in the group of compressed parity data items and the compressed parity.

[0108] For example, if there is the following data item P n belonging to the first parity value in each parity value cluster (e.g., the first page row and the first plane):

[0109] <![CDATA[P n > First part Second part Third part Fourth part <![CDATA[Parity n > 1 010 111 000 010 111 54 101 001 110 101 111 810 000 110 010 000 100

[0110] Then, the P n in the table 1 The compressed parity of the group of data items (G 54For the second part, the system calculates the XOR of 010, 111, 000, 010, 101, 110, 101, 000, 110, 010, 000, and 100 (which is the compressed parity check). This result is: 001, which is the correction value. It should be noted that the example table and the above examples simplify by only having three P values (1, 54, and 810) and leaving the P 1 values in the group G 108 as shown in Figure 13 .

[0111] Figure 16 Schematic diagram illustrating a memory controller 1615 according to some examples of the present invention. Memory controller 1615 is an example of memory controller 115, memory manager 1625 is an example of memory manager 125, and management table 1630 may be an example of management table 130. Controller 1635 and ECC 1640 may be Figure 1 examples of controller 135 and ECC 140 of Figure 7 . In some examples, the pattern controller 1642 included in controller 1635 can determine the location of the portion of the stored data item. In some examples, the positioning is according to the NAND data placement pattern disclosed herein. For example, the first portion of the received data item is placed at the first page row of a plurality of page rows of NAND in the array and the first plane of a plurality of planes; the second portion of the received data item is programmed to the second page row of the plurality of page rows in the array and the second plane of the plurality of planes; the third portion of the received data item is programmed to the third page row of the plurality of page rows in the array and the third plane of the plurality of planes; the parity value of the data item is calculated using the first portion, the second portion, and the third portion; and wherein the first page row, the second page row, the third page row, the first plane, the second plane, and the third plane are selected such that the first portion, the second portion, and the third portion are stored in memory cells on different page rows and different planes relative to each other. For example, the pattern controller 1642 can position the data in the NAND as shown in 8 .

[0112] In some examples, the pattern controller 1642 can also calculate one or more parity values. In some examples, the parity value can be calculated by a hardware XOR processor.

[0113] The pattern controller 1642 can allocate and assign the parity value to a volatile memory location (as shown in Figure 9 ) or a non-volatile memory location (as shown in Figure 10shown) and analogs. The pattern controller 1642 can assign parity values to the clusters and create a compressed parity value using the parity values from each cluster, and can store the compressed parity value. The parity values utilized from each cluster can be selected based on a formula or other pattern. For example, each parity value can be assigned to a relative position in each cluster (e.g., the first parity value, the second parity value, etc. in the cluster), and the same position in each cluster can be used to create the compressed parity value. The pattern controller 1642 can store the compressed parity value in volatile or non-volatile memory (e.g., as Figure 14 shown). The pattern controller 1642 can implement Figure 11 and Figure 15 methods.

[0114] Figure 17 A block diagram of an example machine 1700 on which any one or more of the techniques (e.g., methods) discussed herein may be executed. In alternative embodiments, machine 1700 may operate as a stand-alone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1700 may act as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1700 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1700 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, an IoT device, an automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specify actions to be taken by that machine. Further, although only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0115] As described herein, an instance may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuitry is a collection (e.g., a group of circuits) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may vary flexibly over time and with underlying hardware variability. A circuitry includes members that may perform particular tasks individually or in combination when operating. In an instance, the hardware of a circuitry may be designed immutably to perform a particular operation (e.g., hardwired). In an instance, the hardware of a circuitry may include physically components with variable connections (e.g., execution units, transistors, simple circuits, etc.) that include computer-readable media encoded with instructions to perform a particular operation by being physically modified (e.g., magnetically, electrically, movable placement of immovable mass particles, etc.). When connecting the physical components, the underlying electrical property (e.g.) of the hardware composition changes from an insulator to a conductor, or vice versa. The instructions enable the participating hardware (e.g., execution units or load mechanisms) to create members of the circuitry in the hardware via variable connections to perform parts of a particular task in operation. Thus, when the device is operating, the computer-readable media is communicatively coupled to other components of the circuitry. In an instance, any of the physical components may be used in more than one member of more than one circuitry. For example, in operation, an execution unit may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry or a third circuit in a second circuitry at a different time.

[0116] A machine (e.g., a computer system) 1700 (e.g., a host device 105, a memory device 110, etc.) may include a hardware processor 1702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller 115, etc.), a main memory 1704, and a static memory 1706, some or all of which may communicate with each other via an interconnect (e.g., a bus) 1708. The machine 1700 may further include a display unit 1710, an alphanumeric input device 1712 (e.g., a keyboard), and a user interface (UI) navigation device 1714 (e.g., a mouse). In an instance, the display unit 1710, the input device 1712, and the UI navigation device 1714 may be a touch screen display. Additionally, the machine 1700 may include a storage device (e.g., a drive unit) 1716, a signal generation device 1718 (e.g., a speaker), a network interface device 1720, and one or more sensors 1716, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1700 may include an output controller 1728, such as a serial (e.g., a universal serial bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0117] The storage device 1716 may include a machine-readable medium 1722 having stored thereon one or more sets of data structures or instructions 1724 (e.g., software) embodying any one or more of the techniques or functions described herein or utilized by any one or more of the techniques or functions described herein. The instructions 1724 may also reside, completely or at least partially, within the main memory 1704, within the static memory 1706, or within the hardware processor 1702 during execution thereof by the machine 1700. In an example, one or any combination of the hardware processor 1702, the main memory 1704, the static memory 1706, or the storage device 1716 may constitute the machine-readable medium 1722.

[0118] Although the machine-readable medium 1722 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database or associated caches and servers) configured to store one or more instructions 1724.

[0119] The term "machine-readable medium" may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 1700 and that causes the machine 1700 to perform any one or more of the techniques of the present invention or that is capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid state memories and optical and magnetic media. In an example, a massed machine-readable medium includes a machine-readable medium having a plurality of particles with invariant (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transitory propagated signal. Specific examples of massed machine-readable media may include: non-volatile memories such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0120] Instruction 1724 (such as software, program, operating system (OS), etc.) or other data is stored on storage device 1721 and can be accessed by memory 1704 for use by processor 1702. Memory 1704 (such as DRAM) is generally faster but volatile, and thus is a different type of storage from storage device 1721 (such as SSD), which is suitable for long-term storage (including under "cut-off" conditions). Instructions 1724 or data used by user or machine 1700 are generally loaded into memory 1704 for use by processor 1702. When memory 1704 is full, virtual space from storage device 1721 can be allocated to supplement memory 1704; however, since storage device 1721 is generally slower than memory 1704 and the write speed is generally at least 2 times slower than the read speed, using virtual memory can significantly degrade the user experience due to storage device latency (compared to memory 1704, such as DRAM). In addition, using storage device 1721 for virtual memory can significantly reduce the available lifespan of storage device 1721.

[0121] Compared to virtual memory, virtual memory compression (such as the kernel feature "ZRAM") uses a portion of the memory as a compressed block storage device to avoid paging to storage device 1721. Paging occurs within the compressed block until this data needs to be written to storage device 1721. Virtual memory compression increases the available size of memory 1704 while reducing wear on storage device 1721.

[0122] Storage devices optimized for mobile electronic devices or mobile storage devices typically include MMC solid-state storage devices (such as micro Secure Digital (microSD TM ) cards, etc.). MMC devices include several parallel interfaces (such as an 8-bit parallel interface) with the host device and are generally removable and separable components from the host device. In contrast, eMMC TM devices are attached to the circuit board and are regarded as components of the host device, which have a read speed comparable to that of SSD devices based on Serial ATA TM (Serial AT (Advanced Technology) Attachment or SATA). However, the requirements for mobile device performance are constantly increasing, such as fully enabling virtual or augmented reality devices, leveraging increased network speeds, etc. In response to this requirement, storage devices have switched from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) use a Low-Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths to communicate with the host device, thereby further increasing the read / write speed.

[0123] Instruction 1724 can be further transmitted or received via a communication network 1726 using a transmission medium through a network interface device 1720 that utilizes any one of several transport protocols (such as Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks can include local area networks (LANs), wide area networks (WANs), packet data networks (such as the Internet), mobile telephone networks (such as cellular networks), plain old telephone service (POTS) networks, and wireless data networks (such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards (referred to as ), IEEE 802.16 series standards (referred to as ), IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, etc.). In an example, the network interface device 1720 can include one or more physical jacks (such as Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1726. In an example, the network interface device 1720 can include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be considered to include any non-transitory medium that is capable of storing, encoding, or carrying instructions executed by the machine 1700, and includes digital or analog communication signals or other non-transitory media that facilitate such software communication.

[0124] The detailed description above includes references to the accompanying drawings that form a part of the detailed description. The drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples can include elements in addition to those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. In addition, the inventors also contemplate examples (or aspects thereof) that use any combination or arrangement of elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0125] In the present invention, as is common in patent filings, the term "a" or "an" is used to include one or more, independent of any other instances or uses of "at least one" or "one or more". In the present invention, the term "or" is used to refer to "exclusive or", such that "A or B" can include "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as the ordinary English equivalents of the corresponding terms "including" and "wherein". Also, in the appended claims, the terms "comprising" and "including" are open-ended, i.e., a system, apparatus, article, or process that includes elements other than those listed after this term in the claim is still considered to fall within the scope of the claim. Further, in the appended claims, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0126] In various instances, the components, controllers, processors, units, engines, or tables described herein may specifically include physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as (but not limited to) a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry (including processor groups or multi-core devices).

[0127] The term "horizontal" as used in the present invention is defined as a plane parallel to the conventional plane or surface of the substrate (e.g., the plane under the wafer or die), independent of the actual orientation of the substrate at any given point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. The prepositions (e.g., "on", "above", and "below") are defined with respect to the conventional plane or surface on the top or exposed surface of the substrate, independent of the orientation of the substrate; and "on" is intended to indicate direct contact of one structure with another structure that is "on" it (in the absence of an express contrary indication); the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which expressly includes (but is not limited to) direct contact between the identified structures, unless expressly identified otherwise. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, because if a structure is the outermost part of the construct being discussed at a given point in time, it can be "above" the reference structure, even if this structure extends vertically rather than horizontally with respect to the reference structure.

[0128] The terms "wafer" and "substrate" are generally used herein to refer to any structure on which an integrated circuit is formed, and also to such structures during various stages of integrated circuit fabrication. Accordingly, the following detailed description should not be considered limiting, and the scope of the various embodiments is defined only by the appended claims and the full scope of equivalents authorized by such claims.

[0129] Memories in accordance with the present invention and various embodiments described herein include memories that utilize a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cells are formed (i.e., the vertical structure will be considered to extend away from the substrate surface, the bottom end of the vertical structure will be considered the end closest to the substrate surface, and the top end of the vertical structure will be considered the end furthest from the substrate surface).

[0130] As used herein, directional adjectives (e.g., horizontal, vertical, normal, parallel, etc.) may refer to relative orientation and are not intended to require strict adherence to a particular geometric property, unless otherwise specified. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of the substrate, but may be generally perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 degrees and 120 degrees, etc.).

[0131] In some embodiments described herein, different doping profiles may be applied to the source side select gate (SGS), the control gate (CG), and the drain side select gate (SGD), where each of these may be formed of polysilicon or at least contain polysilicon in this instance, such that these layers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etchant solution. For example, during the process of forming a monolithic pillar in a 3D semiconductor device, the SGS and CG may form recesses, while the SGD may remain less recessed or even not recessed. Accordingly, these doping profiles are capable of selectively etching different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device by using an etchant solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0132] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of bringing a memory cell into an intended state is referred to herein as "programming" and may include both writing to the memory cell and erasing from the memory cell (e.g., a memory cell may be programmed to an erased state).

[0133] According to one or more embodiments of the present invention, a memory controller (such as a processor, a controller, firmware, etc.) located inside or outside the memory device is capable of determining (such as selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) the number of wear cycles or the wear state (such as recording wear cycles, counting the operations of the memory device as they occur, tracking the operations of the memory device from which it starts, evaluating the memory device characteristics corresponding to the wear state, etc.).

[0134] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to the memory device with each memory operation. The memory device control circuitry (such as control logic) may be programmed to compensate for the memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operation parameters (such as values, characteristics) in response to the wear cycle information.

[0135] It should be understood that when an element is referred to as being "on another element", "connected to another element", or "coupled to another element", it may be directly on the other element, directly connected to the other element, or directly coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly on another element", "directly connected to another element", or "directly coupled to another element", there are no intervening elements or layers. If two elements are shown in a diagram as being connected by a line between them, then the two elements may be coupled or directly coupled, unless otherwise indicated.

[0136] The method examples described herein may be at least partially implemented by a machine or a computer. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include (but are not limited to) hard disks, removable disks, removable optical disks (such as optical discs and digital video discs), cassette tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid state drives (SSD), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0137] The foregoing description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. For instance, one of ordinary skill in the art may use other embodiments after reviewing the foregoing description. It should be understood that when submitted, it is not intended to interpret or limit the scope or meaning of the claims. Also, in the foregoing detailed description, various features may be grouped together to simplify the invention. This should not be construed as wishing that unclaimed disclosed features are essential to any claim. Rather, the subject matter of the invention may not have all of the features of a particular disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment, and such embodiments may be combined or arranged with each other in various combinations or permutations. The scope of the embodiments should be determined with reference to the appended claims and the full scope of equivalents authorized by such claims.

[0138] Other Notes and Examples

[0139] Example 1 is a NAND memory device that includes: a NAND memory cell array organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations including: programming a first portion of a received data item to a first page row of the multiple page rows and a first plane of the multiple planes in the array; programming a second portion of the received data item to a second page row of the multiple page rows and a second plane of the multiple planes in the array; programming a third portion of the received data item to a third page row of the multiple page rows and a third plane of the multiple planes in the array.

[0140] In Example 2, the subject matter of Example 1, wherein the operations include storing a parity value by applying an XOR operator to the first portion, second portion, and third portion.

[0141] In Example 3, the subject matter of Example 2, wherein the operations further include storing the parity value in the NAND memory cell array.

[0142] In Example 4, the subject matter of Example 3, wherein the parity value is stored in a location of the NAND memory cell array configured as single-level cell (SLC) memory cells.

[0143] In Example 5, the subject matter of any one of Examples 3 to 4, wherein the first portion, second portion, and third portion are programmed to locations of the NAND memory cell array configured as three-level cell (TLC) memory cells.

[0144] In Example 6, the subject matter according to any one of Examples 2 to 5, wherein the operations include: determining that one of the first part, the second part, or the third part is damaged; and recovering the one of the first part, the second part, or the third part by utilizing the parity value.

[0145] In Example 7, the subject matter according to any one of Examples 2 to 6, which includes a volatile memory communicating with the controller; and wherein the operations further include: first storing the parity value in the volatile memory; and moving the parity value to the NAND memory cell array.

[0146] In Example 8, the subject matter according to any one of Examples 1 to 7, wherein the operations further include: programming a fourth part of the received data item to a fourth page row among the plurality of page rows and a fourth plane among the plurality of planes in the array.

[0147] In Example 9, the subject matter according to any one of Examples 1 to 8, wherein the first part, the second part, and the third part include individual bits within the received data.

[0148] In Example 10, the subject matter according to any one of Examples 1 to 9, wherein the third page row and the third plane are larger than the second page row and the second plane, and the second page row and the second plane are larger than the first page row and the first plane.

[0149] Example 11 is a method of storing data on a NAND device, the NAND device including a NAND memory cell array organized into a plurality of planes and addressable by a plurality of page rows, the method including: programming a first part of a received data item to a first page row among the plurality of page rows and a first plane among the plurality of planes in the array; programming a second part of the received data item to a second page row among the plurality of page rows and a second plane among the plurality of planes in the array; programming a third part of the received data item to a third page row among the plurality of page rows and a third plane among the plurality of planes in the array.

[0150] In Example 12, the subject matter according to Example 11, which includes storing a parity value by applying an XOR operator to the first part, the second part, and the third part.

[0151] In Example 13, the subject matter according to Example 12, which includes storing the parity value in the NAND memory cell array.

[0152] In example 14, the subject matter of example 13, wherein the parity value is stored in a location of the NAND memory cell array configured as single-level cell (SLC) memory cells.

[0153] In example 15, the subject matter of any of examples 13 to 14, wherein the first portion, the second portion, and the third portion are programmed into locations of the NAND memory cell array configured as triple-level cell (TLC) memory cells.

[0154] In example 16, the subject matter of any of examples 12 to 15, comprising: determining that one of the first portion, the second portion, or the third portion is corrupted; and recovering the one of the first portion, the second portion, or the third portion by utilizing the parity value.

[0155] In example 17, the subject matter of any of examples 12 to 16, comprising: first storing the parity value in volatile memory; and moving the parity value to the NAND memory cell array.

[0156] In example 18, the subject matter of any of examples 11 to 17, comprising programming a fourth portion of the received data item into a fourth page row of the plurality of page rows in the array and a fourth plane of the plurality of planes.

[0157] In example 19, the subject matter of any of examples 11 to 18, wherein the first portion, the second portion, and the third portion comprise individual bits within the received data.

[0158] In example 20, the subject matter of any of examples 11 to 19, wherein the third page row and the third plane are larger than the second page row and the second plane, and the second page row and the second plane are larger than the first page row and the first plane.

[0159] Example 21 is a machine-readable medium that includes instructions that, when executed by a machine, cause the machine to perform operations including: programming a first portion of a received data item into a first page row of a plurality of page rows of a NAND array and a first plane of a plurality of planes of the NAND array; programming a second portion of the received data item into a second page row of the plurality of page rows of the array and a second plane of the plurality of planes; programming a third portion of the received data item into a third page row of the plurality of page rows of the array and a third plane of the plurality of planes.

[0160] In Example 22, the subject matter of Example 21, wherein the operation includes storing a parity value by applying an XOR operator to the first part, the second part, and the third part.

[0161] In Example 23, the subject matter of Example 22, wherein the operation further includes storing the parity value in the NAND memory cell array.

[0162] In Example 24, the subject matter of Example 23, wherein the parity value is stored in a location of the NAND memory cell array configured as single-level cell (SLC) memory cells.

[0163] In Example 25, the subject matter of any one of Examples 23 to 24, wherein the first part, the second part, and the third part are programmed into locations of the NAND memory cell array configured as triple-level cell (TLC) memory cells.

[0164] In Example 26, the subject matter of any one of Examples 22 to 25, wherein the operation includes: determining that one of the first part, the second part, or the third part is corrupted; and recovering the one of the first part, the second part, or the third part by utilizing the parity value.

[0165] In Example 27, the subject matter of any one of Examples 22 to 26, which includes a volatile memory communicating with the controller; and wherein the operation further includes: first storing the parity value in the volatile memory; and moving the parity value to the NAND memory cell array.

[0166] In Example 28, the subject matter of any one of Examples 21 to 27, wherein the operation further includes: programming a fourth part of the received data item into a fourth page row of the plurality of page rows in the array and a fourth plane of the plurality of planes.

[0167] In Example 29, the subject matter of any one of Examples 21 to 28, wherein the first part, the second part, and the third part include individual bits within the received data.

[0168] In Example 30, the subject matter of any one of Examples 21 to 29, wherein the third page row and the third plane are larger than the second page row and the second plane, and the second page row and the second plane are larger than the first page row and the first plane.

[0169] Example 31 is a NAND memory device that includes: a NAND memory cell array organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations, the controller including means for programming a first portion of a received data item to a first page row of the multiple page rows and a first plane of the multiple planes in the array, means for programming a second portion of the received data item to a second page row of the multiple page rows and a second plane of the multiple planes in the array, and means for programming a third portion of the received data item to a third page row of the multiple page rows and a third plane of the multiple planes in the array.

[0170] In Example 32, the subject matter according to Example 31 includes means for storing a parity value by applying an XOR operator to the first portion, second portion, and third portion.

[0171] In Example 33, the subject matter according to Example 32 includes means for storing the parity value in the NAND memory cell array.

[0172] In Example 34, the subject matter according to Example 33, wherein the parity value is stored in a location of the NAND memory cell array configured as single-level cell (SLC) memory cells.

[0173] In Example 35, the subject matter according to any one of Examples 33 to 34, wherein the first portion, second portion, and third portion are programmed to locations of the NAND memory cell array configured as triple-level cell (TLC) memory cells.

[0174] In Example 36, the subject matter according to any one of Examples 32 to 35 includes means for determining that one of the first portion, second portion, or third portion is corrupted and means for restoring the one of the first portion, second portion, or third portion by using the parity value.

[0175] In Example 37, the subject matter according to any one of Examples 32 to 36 includes means for first storing the parity value in volatile memory and means for moving the parity value to the NAND memory cell array.

[0176] In Example 38, the subject matter according to any one of Examples 31 to 37 includes means for programming a fourth portion of the received data item to a fourth page row of the multiple page rows and a fourth plane of the multiple planes in the array.

[0177] In instance 39, the subject matter according to any one of instances 31 to 38, wherein the first part, the second part, and the third part comprise individual bits within the received data.

[0178] In instance 40, the subject matter according to any one of instances 31 to 39, wherein the third page row and the third plane are greater than the second page row and the second plane, and the second page row and the second plane are greater than the first page row and the first plane.

[0179] Instance 41 is a NAND memory device, comprising: a NAND memory cell array organized into a plurality of planes and addressable by a plurality of page rows; and a controller configured to perform operations including: storing a received data item in a memory cell of the NAND array such that a first part, a second part, and a third part of the data item are stored in memory cells in different page rows and different planes relative to each other in the array; calculating a parity value of the received data item using the first part, the second part, and the third part; assigning the parity value of the received data item to a first position of a parity cluster among a plurality of parity clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0180] In instance 42, the subject matter according to instance 41, wherein the operation of calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster comprises selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches a relative position of the parity value in the first parity cluster.

[0181] In instance 43, the subject matter according to any one of instances 41 to 42, wherein the parity value is stored in a block of the NAND memory cells.

[0182] In instance 44, the subject matter according to any one of instances 42 to 43, wherein the operation comprises storing the compressed parity value in a block of the NAND memory cells.

[0183] In instance 45, the subject matter according to any one of instances 43 to 44, wherein the operation comprises overwriting the parity value with the compressed parity value.

[0184] In example 46, a subject matter according to any one of examples 41 to 45, wherein the operations include: calculating the second parity value based on first, second, and third portions of a second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array fails an error correction code check; and recovering the first portion using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item.

[0185] In example 47, a subject matter according to any one of examples 41 to 46, wherein the operation of calculating the compressed parity value includes applying an XOR operation to the parity value and the second parity value.

[0186] In example 48, a subject matter according to any one of examples 41 to 47, wherein the operation of calculating the parity value of the received data item using the first portion, the second portion, and the third portion includes applying an XOR operator to the first portion, the second portion, and the third portion.

[0187] Example 49 is a machine-readable medium that includes instructions that, when executed by a machine, cause the machine to perform operations including: storing a received data item in memory cells of a NAND array such that first, second, and third portions of the data item are stored in memory cells in different page rows and different planes relative to each other in the array; calculating a parity value of the received data item using the first portion, the second portion, and the third portion; assigning the parity value of the received data item to a first location of a parity cluster among a plurality of parity clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0188] In example 50, a subject matter according to example 49, wherein the operation of calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster includes selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches a relative position of the parity value in the first parity cluster.

[0189] In example 51, a subject matter according to any one of examples 49 to 50, wherein the parity value is stored in a block of the NAND memory cells.

[0190] In instance 52, the subject matter according to any one of instances 50 to 51, wherein the operation further comprises storing the compressed parity value in a block of the NAND memory cells.

[0191] In instance 53, the subject matter according to any one of instances 51 to 52, wherein the operation further comprises overwriting the parity value with the compressed parity value.

[0192] In instance 54, the subject matter according to any one of instances 49 to 53, wherein the operation further comprises: calculating the second parity value based on first, second, and third portions of a second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array fails an error correction code check; and recovering the first portion using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item.

[0193] In instance 55, the subject matter according to any one of instances 49 to 54, wherein the operation of calculating the compressed parity value comprises applying an XOR operation to the parity value and the second parity value.

[0194] In instance 56, the subject matter according to any one of instances 49 to 55, wherein the operation of calculating the parity value of the received data item using the first, second, and third portions comprises applying an XOR operator to the first, second, and third portions.

[0195] Instance 57 is a method of storing data on a NAND device, the NAND device comprising an array of NAND memory cells organized into a plurality of planes and addressable by a plurality of page rows, the method comprising: storing a received data item in a memory cell of the NAND array such that first, second, and third portions of the data item are stored in memory cells in different page rows and different planes of the array relative to each other; calculating a parity value of the received data item using the first, second, and third portions; assigning the parity value of the received data item to a first location of a parity check cluster of a plurality of parity check clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity check cluster of the plurality of parity check clusters.

[0196] In instance 58, the subject matter according to instance 57, wherein calculating the compressed parity value based on the parity value and the second parity value of the second parity check cluster includes selecting the second parity value from the second parity check cluster based on the relative position of the second parity value in the second parity check cluster that matches the relative position of the parity value in the first parity check cluster.

[0197] In instance 59, the subject matter according to any one of instances 57 to 58, wherein the parity value is stored in a block of the NAND memory cells.

[0198] In instance 60, the subject matter according to any one of instances 58 to 59, which includes storing the compressed parity value in a block of the NAND memory cells.

[0199] In instance 61, the subject matter according to any one of instances 59 to 60, which includes overwriting the parity value with the compressed parity value.

[0200] In instance 62, the subject matter according to any one of instances 57 to 61, which includes: calculating the second parity value based on first, second, and third portions of a second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array fails an error correction code check; using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item to recover the first portion.

[0201] In instance 63, the subject matter according to any one of instances 57 to 62, wherein calculating the compressed parity value includes applying an XOR operation to the parity value and the second parity value.

[0202] In instance 64, the subject matter according to any one of instances 57 to 63, wherein calculating the parity value of the received data item using the first portion, second portion, and third portion includes applying an XOR operator to the first portion, second portion, and third portion.

[0203] Example 65 is a NAND memory device that includes: a NAND memory cell array organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations, the controller including components for storing a received data item in memory cells of the NAND array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells in the array that are in different page rows and different planes relative to each other, components for calculating a parity value of the received data item using the first portion, the second portion, and the third portion, components for assigning the parity value of the received data item to a first location of a parity cluster among a plurality of parity clusters, and components for calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0204] In example 66, the subject matter of example 65, wherein the components for calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster include components for selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches a relative position of the parity value in the first parity cluster.

[0205] In example 67, the subject matter of any one of examples 65 to 66, wherein the parity value is stored in a block of the NAND memory cells.

[0206] In example 68, the subject matter of any one of examples 66 to 67, which includes components for storing the compressed parity value in a block of the NAND memory cells.

[0207] In example 69, the subject matter of any one of examples 67 to 68, which includes components for overwriting the parity value with the compressed parity value.

[0208] In example 70, the subject matter of any one of examples 65 to 69, which includes components for calculating the second parity value based on first, second, and third portions of a second data item, components for receiving an indication that a first portion of the data item read from the NAND memory cell array fails an error correction code check, and components for recovering the first portion using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item.

[0209] In example 71, the subject matter according to any one of examples 65 to 70, wherein the component for calculating the compressed parity value includes a component for applying an XOR operation to the parity value and the second parity value.

[0210] In example 72, the subject matter according to any one of examples 65 to 71, wherein the component for calculating the parity value of the received data item using the first part, the second part, and the third part includes a component for applying an XOR operator to the first part, the second part, and the third part.

[0211] Example 73 is at least one machine-readable medium that includes instructions that, when executed by a processing circuitry, cause the processing circuitry to perform operations to implement any one of examples 1 to 72.

[0212] Example 74 is a device that includes components for implementing any one of examples 1 to 72.

[0213] Example 75 is a system for implementing any one of examples 1 to 72.

[0214] Example 76 is a method for implementing any one of examples 1 to 72.

Claims

1. A NAND memory device, which comprises: A NAND memory cell array, which is organized into multiple planes and can be addressed by multiple page rows; and A controller, which is configured to: Store the received data item in the array such that a first part, a second part, and a third part of the received data item are stored on different page rows; Calculate a parity check value of the received data item using the first part, the second part, and the third part; Assign the parity check value to a first position within a parity check cluster; Calculate a combined parity check value by combining the parity check value with a second parity check value from a second parity check cluster, the second parity check value occupying the same first position in the second parity check cluster; Erase the parity check value and the second parity check value; and Store the combined parity check value.

2. The NAND memory device according to claim 1, wherein the operations performed by the controller further include receiving an indication that the first part of the received data item read from the NAND memory cell array during a read operation fails an error correction code check.

3. The NAND memory device according to claim 2, wherein the operations performed by the controller further include using the combined parity check value, the second part and the third part of the received data item, and other parts of other data items corresponding to the combined parity check value to recover the first part.

4. The NAND memory device according to claim 1, wherein the operation of calculating the combined parity check value based on the parity check value and the second parity check value of the second parity check cluster includes performing an XOR operation on the parity check value and the second parity check value.

5. The NAND memory device according to claim 1, wherein the second parity check value is a parity check value of a first part, a second part, and a third part of second data items stored in second memory cells in the NAND memory cell array that are in different page rows and different planes relative to each other.

6. The NAND memory device according to claim 1, wherein the operations performed by the controller further include storing the combined parity check value in a cell configured as a single-level cell (SLC) memory cell.

7. The NAND memory device according to claim 1, wherein the first part, the second part, and the third part respectively include an upper page, a lower page, and an extra page.

8. A method, which comprises: At a memory controller: Store the received data item in a NAND array such that a first part, a second part, and a third part of the received data item are stored on different page rows; Calculate a parity check value of the received data item using the first part, the second part, and the third part; Assign the parity check value to a first position within a parity check cluster; Calculate a combined parity value by combining the parity value with a second parity value from a second parity cluster, the second parity value occupying the same first position in the second parity cluster; Erase the parity value and the second parity value; And Store the combined parity value.

9. The method according to claim 8, wherein the method further comprises receiving an indication that the first portion of the received data item read from the NAND memory cell array during a read operation fails an error correction code check.

10. The method according to claim 9, wherein the method further comprises using the combined parity value, the second portion and the third portion of the received data item, and other portions of other data items corresponding to the combined parity value to recover the first portion.

11. The method according to claim 8, wherein calculating the combined parity value based on the parity value and the second parity value of the second parity cluster comprises performing an XOR operation on the parity value and the second parity value.

12. The method according to claim 8, wherein the second parity value is a parity value of a first portion, a second portion, and a third portion of second data items stored in second memory cells in the NAND array that are in different page rows and different planes relative to each other.

13. The method according to claim 8, further comprising storing the combined parity value in a cell configured as a single-level cell (SLC) memory cell.

14. The method according to claim 8, wherein the first portion, the second portion, and the third portion respectively comprise an upper page, a lower page, and an extra page.

15. A non-transitory machine-readable medium storing instructions that, when executed, cause a controller of a memory device to perform operations including: Store a received data item in the NAND array of the memory device such that a first portion, a second portion, and a third portion of the received data item are stored on different page rows; Calculate a parity value of the received data item using the first portion, the second portion, and the third portion; Assign the parity value to a first position within a parity cluster; Calculate a combined parity value by combining the parity value with a second parity value from a second parity cluster, the second parity value occupying the same first position in the second parity cluster; Erase the parity value and the second parity value; And Store the combined parity value.

16. The non-transitory machine-readable medium according to claim 15, wherein the operations further comprise receiving an indication that the first portion of the received data item read from the NAND memory cell array during a read operation fails an error correction code check.

17. The non-transitory machine-readable medium according to claim 16, wherein the operation further comprises using the combined parity value, the second portion and the third portion of the received data item, and other portions of other data items corresponding to the combined parity value to recover the first portion.

18. The non-transitory machine-readable medium according to claim 15, wherein the operation of calculating the combined parity value based on the parity value and the second parity value of the second parity check cluster comprises performing an XOR operation on the parity value and the second parity value.

19. The non-transitory machine-readable medium according to claim 15, wherein the operation further comprises storing the combined parity value in a cell configured as a single-level cell (SLC) memory cell.

20. The non-transitory machine-readable medium according to claim 15, wherein the first portion, the second portion, and the third portion respectively comprise a front page, a back page, and an extra page.

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