Performance test method and device for data reading program

Abstract

The embodiment of the invention provides a performance test of a data reading program, and the method comprises the steps: receiving a target test request sent by a host device, the target test request being used for requesting to test the data access performance of a target data access program in a manner of performing data access on a memory; converting a target operation instruction for the target data access program according to access information carried by the target test request and storage information of a memory; in the process of calling the target data access program to execute the target operation instruction, monitoring data access information of the target data access program; and generating target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program. Through the data reading program performance testing method and device, the problem that the performance testing efficiency of the data reading program is low in the prior art is solved, and then the effect of improving the performance testing efficiency of the data reading program is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more particularly, to a method and device for performance testing of a data reading program. Background Art

[0002] The main control chip on a storage device is a key component in the storage device. By designing a data access program on the main control chip, the main control chip can be capable of being responsible for accessing the memory in the storage device and IO processing. Before the design of the main control chip of the storage device is completed and ready for production, verifying the reliability of the operation logic of the data access program in the main control chip is a key step to ensure that the performance of the storage device meets the expected requirements. In related technologies, the performance of the data access program designed on the main control chip is usually tested by means of simulation verification, that is, the data access program on the main control chip of the storage device is burned on a simulation test platform, and the performance of the data access program of the main control chip is tested by running the data access program. However, compared with the main control chip, the simulation test platform has the shortcoming of limited space. Therefore, the simulation test platform may not be able to effectively run the data access program. In order to effectively test the performance of the data access program, in related technologies, a high-scale simulation verification platform is usually sought to simulate a chip closer to the finished product, so as to complete the performance test of the data access program. Although this method can improve the accuracy of the performance test by simulating a chip closer to the finished product, finding a high-scale simulation verification platform requires a large amount of time and cost, resulting in a low test efficiency of the performance of the data access program. Summary of the Invention

[0003] The embodiments of the present application provide a method and device for performance testing of a data reading program, so as to at least solve the problem of low test efficiency for the performance of the data reading program in related technologies.

[0004] According to an embodiment of the present application, a method for performance testing of a data reading program is provided. The target test system includes a host device, a target test platform, and a memory. The target test platform is connected between the host device and the memory. The data access program deployed on the main control chip of the storage device is burned on the target test platform. The method is applied to the target test platform and includes:

[0005] Receiving a target test request sent by the host device, where the target test request is used to request to test the data access performance of the target data access program by accessing the memory;

[0006] Convert a target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory, where the target operation instruction is used to indicate the amount of data accessed from each of multiple storage areas of the memory, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage areas of the memory;

[0007] During the process of calling the target data access program to execute the target operation instruction, monitor the data access information of the target data access program, where the data access information is used to indicate the transmission delay situation of data transmitted between the host device and the memory;

[0008] Generate the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program, where the conversion delay is used to indicate the time consumption of the target data access program to convert the storage location of the data requested to be accessed by the target test request in the memory.

[0009] Optionally, the converting a target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory includes:

[0010] Allocate the target data volume of the data to be accessed in each storage area according to the total data volume of the data requested to be accessed by the target test request and the storage information, where the access information includes the total data volume;

[0011] Generate the target operation instruction for requesting to extract the target data volume of data from each storage area.

[0012] Optionally, the allocating the target data volume of the data to be accessed in each storage area according to the total data volume of the data requested to be accessed by the target test request and the storage information includes:

[0013] Calculate the target proportion of the target storage capacity of each storage area in the total capacity of the multiple storage areas, where the storage information includes the target storage capacity corresponding to each storage area;

[0014] Allocate the total data volume according to the target proportion to obtain the target data volume of the data to be accessed in each storage area.

[0015] Optionally, the generating the target operation instruction for requesting to extract the target data volume of data from each storage area includes:

[0016] Obtain the access address information of each of the storage areas.

[0017] Add the access address information and the target data volume to corresponding positions in the access instruction template to obtain a target access instruction, where the target operation instruction includes the target access instruction corresponding to each of the storage areas.

[0018] Optionally, after receiving the target test request sent by the host device, the method further includes:

[0019] Obtain the operation type of the data access operation requested to be executed by the target test request.

[0020] In the case where the operation type indicates a data read operation on the memory, write preset data to all storage positions in each of the storage areas.

[0021] Optionally, after obtaining the operation type of the data access operation requested to be executed by the target test request, the method further includes:

[0022] In the case where the operation type indicates a data write operation on the memory, detect the data storage status in each of the storage areas.

[0023] In the case where the data storage status is used to indicate that there is data stored in the storage area, clear the data stored in the storage area.

[0024] Optionally, the monitoring of the data access information of the target data access program includes:

[0025] Determine a target waveform from the data transmission waveform of the target test platform, where the data transmission waveform is used to characterize the data transmission situation between the host device and the memory of the target test platform, and the target waveform is used to indicate the data transmission situation between the host device and the memory of the target test platform in response to the target test request.

[0026] Determine the duration of the target waveform as the reference transmission delay of the target test platform, where the reference transmission delay is used to indicate the time situation required for the target test platform to call the target data access program to transmit the total data volume requested to be accessed by the target test request, and the data access information includes the reference transmission delay.

[0027] The generating the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program includes:

[0028] Calculate a reference ratio of a first main frequency of the main control chip and a second main frequency of the target test platform, where the first main frequency is used to characterize the operating speed of the main control chip, and the second main frequency is used to characterize the operating speed of the target test platform;

[0029] Calculate a target transmission delay for the main control chip to call the target data access program to transmit the total data volume according to the reference ratio and the reference transmission delay;

[0030] Calculate a sum value of the target transmission delay and the conversion delay to obtain a total delay;

[0031] Calculate a quotient value of the total data volume and the total delay to obtain a data access rate of the target data access program on the main control chip, where the target data access performance includes the data access rate.

[0032] According to another embodiment of the present application, there is provided a performance testing device for a data reading program. The target test system includes a host device, a target test platform, and a memory. The target test platform is connected between the host device and the memory. A data access program deployed on the main control chip of the storage device is burned on the target test platform. The device is applied to the target test platform and includes:

[0033] A receiving module, configured to receive a target test request sent by the host device, where the target test request is used to request to test the data access performance of the target data access program by accessing the memory;

[0034] A conversion module, configured to convert a target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory, where the target operation instruction is used to indicate the quantity of data to be accessed from each of multiple storage areas of the memory by the target data access program, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage areas of the memory;

[0035] A monitoring module, configured to monitor the data access information of the target data access program during the process of calling the target data access program to execute the target operation instruction, where the data access information is used to indicate the transmission delay situation of data transmission between the host device and the memory;

[0036] A generation module, configured to generate target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program, where the conversion delay is used to indicate the time consumption of the target data access program for converting the storage location of the data requested to be accessed by the target test request in the memory.

[0037] According to another embodiment of the present application, there is also provided a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0038] According to another embodiment of the present application, there is also provided an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0039] Through the present application, a host device, a target test platform, and a memory are configured in a target test system. The target data access program to be tested is burned on the target test platform. Then, when testing the data access performance of the target data access program in response to a target test request, according to the access information carried in the target test request and the storage information of the memory, the total amount of data accessed by the host device in the memory and the configuration of the storage areas of the memory are determined. Further, according to the access information and the storage information of the memory, the data access program deployed on the main control chip of the storage device burned on the target test platform is called to determine the amount of data accessed in each storage area of the memory. It is not necessary to call the target data access program to convert the storage location of the data requested to be accessed by the target test request in the memory. Instead, the total amount of data requested to be accessed by the target test request is directly allocated to each storage area for storage. On the one hand, this can reduce the running efficiency of the target storage platform for the target data program. On the other hand, since there is data access traffic in each storage area, the extreme performance when the target data access program accesses data can be tested, and the data access information indicating the time delay situation for transmitting data between the host device and the memory is monitored during the call process, so as to obtain the time consumption situation required for accessing data. Finally, the target data access performance is generated according to the time delay situation indicated by the data access information and the conversion time delay indicating the time consumption situation of converting the data requested to be accessed by the target test request by the target data access program into the storage location in the memory. Through the above method, on the one hand, it is possible to avoid converting the storage location of the data requested to be accessed by the target test request in the memory by running the target access program, thereby reducing the running space consumption of the target test platform and accelerating the program running speed. On the other hand, the extreme performance when the data access program accesses data can be tested. Therefore, the problem of low performance test efficiency for data reading programs in the related art can be solved, and the effect of improving the performance test efficiency for data reading programs can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a hardware structure block diagram of a server device for a method for testing the performance of a data reading program according to an embodiment of the present application;

[0041] Figure 2 is a flowchart of a method for testing the performance of a data reading program according to an embodiment of the present application;

[0042] Figure 3 is a schematic diagram for testing the performance of a data reading program according to an embodiment of the present application;

[0043] Figure 4 is a schematic diagram of the hierarchical organization relationship of each level of a memory according to an embodiment of the present application;

[0044] Figure 5A flowchart of a random read test according to an embodiment of the present application;

[0045] Figure 6 It is a structural block diagram of a performance test device for a data reading program according to an embodiment of the present application. Detailed implementation manners

[0046] In the following, embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0047] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence.

[0048] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 It is a hardware structural block diagram of a server device for a performance test method of a data reading program according to an embodiment of the present application. As Figure 1 shown, the server device may include one or more ( Figure 1 only one is shown in Figure 1 the processor 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Among them, the above-mentioned server device may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown in Figure 1 is only schematic and does not limit the structure of the above-mentioned server device. For example, the server device may further include more or fewer components than

[0049] shown in

[0050] Figure 1 shown, or have a different configuration from

[0049] The memory 104 can be used to store computer programs. For example, software programs and modules of application software, such as the computer program corresponding to the performance test method of the data reading program in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above-mentioned method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely provided with respect to the processor 102, and these remote memories can be connected to the server device through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and their combinations.

[0050] The transmission device 106 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, abbreviated as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0051] In this embodiment, a method for performance testing of a data reading program is provided. Figure 2 It is a flowchart of a method for performance testing of a data reading program according to an embodiment of the present application. The target test system includes a host device, a target test platform, and a memory. The target test platform is connected between the host device and the memory. A data access program deployed on the main control chip of the storage device is burned on the target test platform. The method is applied to the target test platform, as Figure 2 shown, this process includes the following steps:

[0052] Step S202, receiving a target test request sent by the host device, where the target test request is used to request to test the data access performance of a target data access program by accessing data in the memory;

[0053] Step S204, converting a target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory, where the target operation instruction is used to indicate the quantity of data to be accessed from each of multiple storage areas of the memory by the target data access program, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage areas of the memory;

[0054] Step S206, during the process of calling the target data access program to execute the target operation instruction, monitoring the data access information of the target data access program, where the data access information is used to indicate the transmission delay situation of data transmitted between the host device and the memory;

[0055] Step S208, generating the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program, where the conversion delay is used to indicate the time consumption situation of the target data access program for converting the storage location of the data requested to be accessed by the target test request in the memory.

[0056] Through the above steps,

[0057] Configure the host device, the target test platform, and the memory in the target test system, burn the target data access program to be tested on the target test platform. Then, when testing the data access performance of the target data access program in response to a target test request, determine the total amount of data accessed by the host device in the memory and the configuration of the storage areas of the memory according to the access information carried in the target test request and the storage information of the memory. Furthermore, according to the access information and the storage information of the memory, call the data access program deployed on the main control chip of the storage device burned on the target test platform to determine the amount of data accessed in each storage area of the memory. There is no need to call the target data access program to convert the storage location of the data requested by the target test request in the memory. Instead, directly allocate the total amount of data requested by the target test request to each storage area for storage. On the one hand, this can reduce the running efficiency of the target storage platform for the target data program. On the other hand, since there is data access traffic in each storage area, the extreme performance when the target data access program accesses data can be tested, and monitor the data access information indicating the latency situation for data transmission between the host device and the memory during the call process, so as to obtain the time consumption for accessing data. Finally, generate the target data access performance according to the latency situation indicated by the data access information and the conversion latency indicating the time consumption for converting the data requested by the target test request by the target data access program to the storage location in the memory. Through the above method, on the one hand, it can avoid converting the storage location of the data requested by the target test request in the memory by running the target access program, thereby reducing the running space consumption of the target test platform and accelerating the program running speed. On the other hand, it can test the extreme performance when the data access program accesses data. Therefore, it can solve the problem of low performance test efficiency of the data reading program in the related art and achieve the effect of improving the performance test efficiency of the data reading program.

[0058] Optionally, in the embodiment of the present application, the target test platform is used to provide a running environment for the data access program deployed in the main control chip, so as to implement the access verification of the data access program in the main control chip. The target test platform can be an FPGA (Field Programmable Gate Array)-based simulation test platform or an ASIC (Application Specific Integrated Circuit)-based access test platform. This solution does not make any limitations in this regard.

[0059] Optionally, in the embodiments of the present application, the memory is used to provide a data storage space, so as to simulate the data access environment of the data access program of the host chip in the storage device. The memory includes multiple storage areas for storing data. The memory can be, but is not limited to, NAND (Not AND), that is, a NAND flash memory, or can be an eMMC (Embedded Multi Media Card), or a UFS (Universal Flash Storage). This solution does not make any limitations in this regard.

[0060] Optionally, in the embodiments of the present application, the host chip of the storage device is burned on the target test platform. Among them, the storage device can be, but is not limited to, an SSD (Solid State Drive). This solution does not make any limitations in this regard.

[0061] In the embodiment provided in the above step S202, the host device can test the data access performance of the target data access program by requesting the target test platform to run the target data access program to perform data access on the memory. That is, the target test request can be a test request used to indicate that the data stored at the target storage location in the target memory needs to be accessed. That is, the target test request carries both the information of the target storage location in the target memory that needs to be accessed and the information of the target data that needs to be accessed at the target storage location. However, when testing the target data access program, in order to avoid the problem of the consumption of the running space by the conversion algorithm module in the target data access program, the conversion operation of the storage location can be not performed using the algorithm module, that is, the access location of the data requested by the target test request is not considered, and only the total amount of data to be accessed is considered. The total amount of data to be accessed is evenly distributed to each storage location of the memory. On the one hand, this avoids the operation of the algorithm module and saves the running space. On the other hand, it can also test the extreme performance of the target data access program.

[0062] Optionally, in the embodiments of the present application, Figure 3 is a schematic diagram of the performance test of a data reading program according to the embodiments of the present application. As Figure 3 shown, the host device sends the target test request to the target test platform, and the target test platform allocates the target data volume to each memory according to the target test request sent by the host device. Among them, the target test request is used to request to test the data access performance of the target data access program by performing data access on the memory. The way of performing data access on the memory can be to read data from the memory or write data to the memory. This solution does not make any limitations in this regard.

[0063] In the embodiment provided in step S204 above, the access information is used to indicate the total amount of data requested to be accessed in the memory. The total amount of data accessed in the memory can be the total amount of data read or the total amount of data written. This solution does not limit this.

[0064] Optionally, in the embodiments of the present application, the storage information is used to indicate the configuration of the storage area requested by the memory. The configuration of the storage area can include, but is not limited to, the number of storage areas, the size of the storage areas, and can also include the data storage status of the storage areas. This solution does not limit this.

[0065] Optionally, in the embodiments of the present application, the storage information can be, but is not limited to, the number of storage areas included in the memory and the data storage amount in each storage area. Furthermore, the way to convert the target operation instruction according to the access information and the memory information can be to evenly distribute the total amount of data requested to be accessed by the target test request to each storage area, that is, to evenly divide the total amount of data by the number of storage areas included in the memory, so as to obtain the amount of data to be accessed in each storage area. Then, a reference operation instruction for requesting to access the data of the amount to be accessed from the storage area is generated. Furthermore, the reference operation instructions corresponding to each storage area in multiple storage areas constitute the target operation instruction. In the embodiments of the present application, the total amount of data can also be distributed according to the number of storage areas and the data storage amount in each storage area, that is, calculate the ratio of the data storage amounts of each storage area, and distribute the total amount of data according to the ratio of the data storage amounts to obtain the amount of data to be accessed in each storage area. Then, a reference operation instruction for requesting to access the data of the amount to be accessed from the storage area is generated. Furthermore, the reference operation instructions corresponding to each storage area in multiple storage areas constitute the target operation instruction.

[0066] In the embodiment provided in step S206 above, to evaluate the data access performance of the target data access program, it is necessary to know the time required for the memory to transfer data to the host device after accessing the data. Therefore, it is necessary to monitor the transmission delay situation of data transmission between the host device and the memory. The way to monitor the transmission delay can be to configure a timing program on the target test platform and run the timing program while the target test platform executes the target operation instruction. When the target test platform receives the data transmitted by the memory, the timing program stops timing. At this time, the time displayed by the timing program is the transmission delay.

[0067] In the embodiment provided in the above step S208, since under normal circumstances, it is necessary to first obtain the storage location of the requested access data in the memory and then access the data. In order to more accurately evaluate the data access performance of the target data access program, it is necessary to reserve the time consumption for the target data access program to convert the storage location of the requested access data in the memory. The method of generating the target data access performance according to the latency indicated by the data access information and the conversion latency can be to add the latency indicated by the data access information and the conversion latency to obtain the comprehensive latency of data access, and then evaluate the target data access performance according to the comprehensive latency.

[0068] As an alternative embodiment, the converting the target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory includes:

[0069] Allocating the target data volume of the data to be accessed in each storage area according to the total data volume of the data requested to be accessed in the target test request and the storage information, where the access information includes the total data volume;

[0070] Generating the target operation instruction for requesting to extract the data of the target data volume from each storage area.

[0071] Optionally, in the embodiments of the present application, the target data volume of the data to be accessed allocated to each storage area may be the same or different, and this solution does not limit this.

[0072] Optionally, in the embodiments of the present application, corresponding reference operation instructions may be generated for each storage area according to the target quantity extracted from each storage area, where the reference operation instruction is used to indicate accessing the data of the target quantity from the corresponding storage area, and then each reference operation instruction is constructed into the target operation instruction.

[0073] Through the above content, by allocating the target data volume to be accessed to each storage area according to the storage information and the total data volume of the data to be accessed, the task is dynamically allocated according to the storage situation of the storage area, thereby optimizing the test efficiency of the target data access program.

[0074] As an alternative embodiment, the allocating the target data volume of the data to be accessed in each storage area according to the total data volume of the data requested to be accessed in the target test request and the storage information includes:

[0075] Calculating the target ratio of the target storage capacity of each storage area in the total capacity of the multiple storage areas, where the storage information includes the target storage capacity corresponding to each storage area;

[0076] Allocate the total data volume according to the target ratio to obtain the target data volume of the data to be accessed in each storage area.

[0077] Optionally, in the embodiments of the present application, the method for calculating the target storage capacity of a storage area may, but is not limited to, subtracting the used storage capacity from the total storage capacity of the storage area.

[0078] Optionally, in the embodiments of the present application, allocating the total data volume according to the target ratio may be to evenly allocate the data volume to each storage area. In this case, the allocation method may be to use the minimum target storage capacity among multiple storage areas as the target data volume for each storage area; it may also be to allocate according to the proportion of each storage area in multiple storage areas. In this case, the allocation method may be to multiply the total data volume by the target ratio of each storage area to obtain the target data volume of each storage area. This solution does not limit this.

[0079] Through the above content, by allocating the target data volume of the data to be accessed in each storage area according to the total data volume of the requested accessed data and the storage information, it can be ensured that each storage area can be allocated data, and the allocation situation can be flexibly adjusted according to the configuration of the storage area, avoiding the situation of data access failure due to insufficient storage space, achieving the maximization of the data access performance of the test target data access program, and improving the accuracy of the data access performance test.

[0080] As an optional embodiment, the generating the target operation instruction for requesting to extract the target data volume from each storage area includes:

[0081] Obtain the access address information of each storage area,

[0082] Add the access address information and the target data volume to the corresponding positions in the access instruction template to obtain a target access instruction, where the target operation instruction includes the target access instruction corresponding to each storage area.

[0083] Optionally, in the embodiments of the present application, the access address information is the address information of the storage area, and the access address information may, but is not limited to, include total_lun (address increment variable), channel (channel number), ce (pin number), lun (logical unit number), block (data block number), plane (structural unit). The meanings of each variable are as follows:

[0084] total_lun: Message address increment variable, incremented by 1 for each received message;

[0085] ch: The channel number of the current message. NFC_CH_NUM is the number of channels, that is, the number of channels managed by the current NAND controller;

[0086] ce: The CE number of the current message. BE_CHAN_CE_NUM is the number of CEs owned by NAND on one channel;

[0087] lun: The LUN number of the current message. NAND_LUN_PLN_NUM is the number of LUNs owned by one CE;

[0088] blk: The block number of the current message. NAND_LUN_PLN_NUM is the number of planes owned by one LUN.

[0089] Figure 4 It is a schematic diagram of the hierarchical organization relationship of a memory according to an embodiment of the present application. As Figure 4 shown, after the target test platform receives the read message, according to the pre-written PBA (Physical Block Address) address, it distributes the message to the NAND (memory) from channel, CE, LUN, and plane in the order of large first rotation. The specific rotation method is as follows: according to the following calculation method, the message is evenly distributed to the NAND from large (ch) to small (plane):

[0090] total_lun = (total_lun + 1) % (NFC_CH_NUM * BE_CHAN_CE_NUM * NAND_CE_LUN_NUM * NAND_LUN_PLN_NUM);

[0091] ch = total_lun % NFC_CH_NUM;

[0092] ce = (total_lun / NFC_CH_NUM) % BE_CHAN_CE_NUM;

[0093] lun = (total_lun / (NFC_CH_NUM * BE_CHAN_CE_NUM)) % NAND_LUN_PLN_NUM;

[0094] blk = total_lun / (NFC_CH_NUM * BE_CHAN_CE_NUM * NAND_LUN_PLN_NUM).

[0095] As an optional embodiment, after receiving the target test request sent by the host device, the method further includes:

[0096] Obtain the operation type of the data access operation requested by the target test request;

[0097] When the operation type indicates that a data read operation is to be performed on the memory, write preset data to all storage locations in each of the storage areas.

[0098] Optionally, in the embodiments of the present application, the operation type of the data access operation requested by the target test request may be reading data, writing data, or deleting data, and this solution does not limit this.

[0099] Optionally, in the embodiments of the present application, when the operation type indicates that a data read operation is to be performed on the memory, preset data is written to the storage locations of each storage area. In this embodiment, preset data may be written to all storage locations of the storage area, or only to some storage locations. Writing preset data to all storage locations of the storage area may be: the memory traverses all the luns (logical units) of the hard disk, and writes one wordline to each lun; writing data only to some storage locations may be: according to the amount of data to be read in each storage area, determine the number of storage locations in the storage area where the data to be read is located, and randomly select the corresponding number of free storage locations to write preset data.

[0100] Through the above content, by writing preset data to the storage locations of each storage area when the operation type indicates that a data read operation is to be performed on the memory, it can be ensured that when data needs to be read from the storage area, there is data in each storage area that can be read, thus avoiding the situation where data reading fails due to no data to read in the storage area.

[0101] As an optional embodiment, after obtaining the operation type of the data access operation requested by the target test request, the method further includes:

[0102] When the operation type indicates that a data write operation is to be performed on the memory, detect the data storage status in each of the storage areas;

[0103] When the data storage status is used to indicate that there is data stored in the storage area, clear the data stored in the storage area.

[0104] Optionally, in the embodiments of the present application, the data storage status in the storage area is used to reflect the data storage situation in the storage area, and the data storage status may be an occupied state or an idle state, and this solution does not limit this.

[0105] Optionally, in the embodiments of the present application, when the data storage state is used to indicate that there is data stored in the storage area, the data stored in the storage area is cleared. In this embodiment, all the data stored in the storage area can be cleared, or only part of the data in the storage area can be cleared. Clearing only part of the data in the storage area can be to determine the number of storage positions in the storage area that need to be written with data according to the amount of data to be written in each storage area, and randomly select the corresponding number of storage positions to clear the data therein.

[0106] Through the above content, when the operation type indicates that a data writing operation is to be performed on the memory and the data storage state is used to indicate that there is data stored in the storage area, clearing the data stored in the storage area can ensure that when data needs to be written to the storage area, there are idle storage positions available for writing data in each storage area, thereby avoiding the situation where data writing fails due to no idle storage positions in the storage area.

[0107] As an alternative embodiment, the monitoring of the data access information of the target data access program includes:

[0108] Determining a target waveform from the data transmission waveform of the target test platform, where the data transmission waveform is used to characterize the data transmission situation between the host device and the memory of the target test platform, and the target waveform is used to indicate the data transmission situation between the host device and the memory when the target test platform responds to the target test request;

[0109] Determining the duration of the target waveform as the reference transmission delay of the target test platform, where the reference transmission delay is used to indicate the time situation required for the target test platform to call the target data access program to transmit the total amount of data requested by the target test request, and the data access information includes the reference transmission delay;

[0110] The generating of the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program includes:

[0111] Calculating a reference ratio of the first main frequency of the main control chip and the second main frequency of the target test platform, where the first main frequency is used to characterize the operating speed situation of the main control chip, and the second main frequency is used to characterize the operating speed situation of the target test platform;

[0112] Calculating the target transmission delay for the main control chip to call the target data access program to transmit the data of the total amount of data according to the reference ratio and the reference transmission delay;

[0113] Calculate the sum of the target transmission delay and the conversion delay to obtain the total delay;

[0114] Calculate the quotient of the total data volume and the total delay to obtain the data access rate of the target data access program on the main control chip, where the target data access performance includes the data access rate.

[0115] Optionally, in the embodiments of the present application, in order to more accurately reflect the performance of the chip, the performance can be analyzed through waveforms, and then the calculated performance can be converted into the performance under the formal chip frequency, so as to evaluate the performance of the formal chip. The method of using the target waveform to evaluate the target data access performance can be: after the environment runs normally for a period of time, capture the data transmission waveform from the target test platform, and calculate the performance by statistically counting the frequency of cq returned per unit time (for random read, bs is 4K, the host device issues a read command, and after the storage device main control chip finishes reading the data, it needs to inform the host device and send the completion message to the nvme queue of the corresponding host device. This completion message is called a cq). For example, if 30 cqs are received on the waveform under 10,000 ticks, that is, 30 4K reads are completed. Assuming a tick period of 1 ns, the random read performance at this time is 3000 Kips.

[0116] Optionally, in the embodiments of the present application, Figure 5 For a random read test flow chart according to the embodiments of the present application, as Figure 5 shown, the specific implementation process is as follows:

[0117] (1) The FPGA simulation environment (target test platform) loads the software and hardware versions, the front-end core starts, establishes a connection with the host (host device), and the host recognizes the disk.

[0118] (2) After the back-end core starts, the nand (memory) initialization is completed, and the back-end starts pre-writing, and completes a write for each word lun of each lun of each nand.

[0119] (3) fio issues random reads with the maximum pressure, Fio bs 4K; lodepth 256; Numjob 8. To test the random read performance limit of the chip, as much read pressure as possible needs to be given at the host end. And it is necessary to ensure that the reads issued by the host are evenly distributed on each lun, and a certain amount of data needs to be guaranteed. For example, 256 luns require 48M of data. The specific calculation method is related to the reading strategy. If not all luns can be fully utilized, the performance will be inaccurate.

[0120] (4) After the front end receives the NVMe command of fio, it allocates hardware resources and context resources, converts the read command into the read command format for back-end interaction, ensuring uniform channels. Before sending the message to the back end, it sets a dynamically adjustable delay point, which can be used to make up for the reduction in software time consumption after removing the algorithm.

[0121] (5) After the back end receives the read message, according to the pre-written PBA address, it rotates from the largest among channel, CE, LUN, and plane (enable AIPR) and sends it to NAND.

[0122] (6) After NAND finishes reading the data, it sends the data to the host through DMA, then triggers the return to CQ. The back end returns the completion to the front end, and the front end releases the resources.

[0123] (7) After the I / O is stable, for example, when the read is completed by 10% (fio does not reach the maximum performance at the beginning and needs to wait for stability), start capturing the waveform, take the average of 1024 read samples, analyze the waveform, and obtain the performance data. Generally, according to experience, as long as the hardware limit is reached, the waveform generally shows a certain regularity.

[0124] Through the above content, by capturing and analyzing the data transmission waveform to analyze the target data access performance, converting it proportionally to the performance of the formal main control chip, and adding the conversion delay on the basis of the transmission delay, the time consumption under the formal firmware can be more accurately simulated, so that the true performance of the chip can be more accurately simulated, ensuring the reliability of the results.

[0125] In the above embodiment, we know that the traditional SSD firmware architecture consists of three parts: the front end, the algorithm module, and the back end. The front end is responsible for docking with the host through PCIe, handling NVMe host messages, system management, etc.; the algorithm is responsible for functions such as address conversion, garbage collection, and wear leveling; the back end manages NAND particles and is responsible for specific read and write message command processing and scheduling.

[0126] Generally, for a complete SSD firmware driver, during the process of implementing functions, a large amount of time is spent optimizing the firmware performance, adjusting the code and algorithms of each part to make the performance optimal. However, it is not very suitable to do this optimization on the FPGA simulation platform before tape-out. One reason is that the FPGA platform runs slowly, resulting in low efficiency. Another reason is that the hardware chip problems are not cleared, resulting in the coupling of software and hardware problems and being difficult to locate. Therefore, this traditional architecture is no longer suitable for system performance verification on FPGA. For the performance test of chip random read and the limit performance test of related accelerators, a more efficient firmware driver is needed.

[0127] This more efficient firmware requires the simplest software structure, but it can traverse the entire system process, utilize the appropriate acceleration, be flexible and adjustable, and be close to the actual usage scenario to measure the ultimate performance of the hardware and chip problems. According to the above requirements, we adjusted the firmware architecture for the random read performance test and evaluation on the FPGA simulation platform before tape-out. The main ideas are as follows:

[0128] 1. Completely remove the algorithm module, no longer perform address conversion operations, directly allocate PBA (Physical Block Address), and simplify a large amount of software computing power consumption.

[0129] 2. The front-end functions remain unchanged. An interaction module with the back-end needs to be added to directly send read messages to the back-end, without paying attention to the erase / write functions, reducing the interaction consumption between modules. Also, simplify the message content for the interaction between modules, from 16 dwords to 4 dwords, only transmitting the necessary content (such as PBA, message ID, and host address). Other information in the message is completed in their respective usage modules, reducing software memory access and configuration consumption. However, due to the omission of the algorithm module, in order to more accurately simulate the consumption in the actual environment and flexibly verify, when the front-end sends commands to the back-end, a tunable algorithm processing delay needs to be reserved.

[0130] 3. Only retain the read-related IO operations in the back-end process. After the disk starts, the back-end core pre-writes NAND, writing one word line for each LUN. This operation can eliminate the front-end and FTL's handling of host write / erase. After that, directly perform fio reads, reducing the firmware complexity. Due to the simplification of the messages between cores, the back-end needs to complete and send other read information by itself. For example, the PBA address needs to be evenly distributed to each concurrent unit according to the written address to ensure the maximum concurrency of NAND. Do not pay attention to various read errors, and still transmit data after errors, simplifying the error process handling.

[0131] After the above firmware process adjustment, it ensures the message processing of the necessary steps in the complete random read process, and the software is greatly simplified. The firmware computing power is no longer a bottleneck for performance testing, and the pressure can be directly applied to the hardware to reflect the true performance of the hardware.

[0132] In this embodiment, since the io trigger source on the host of the FPGA platform may not be of the same frequency as the FPGA, in order to more accurately reflect the performance of the chip, we generally analyze the performance through waveforms and then convert the calculated performance into the performance at the frequency of the formal chip, so as to evaluate the performance of the formal chip. The evaluation method for random read is as follows: after the io is stable, that is, after the environment has been running normally for a period of time, capture the waveforms of the front end and the back end, and calculate the performance by counting the frequency of cq returned per unit time (for random read, bs is 4K. When the host issues a read command, after the SSD finishes reading the data, it needs to inform the host and send the completion message to the nvme queue of the corresponding host. This completion message is called a cq). For example, if 30 cqs are received on the waveform in 10000 ticks, that is, 30 4K reads are completed. Assuming a tick period of 1ns, the random read performance at this time is 3000Kips.

[0133] After the above process is adjusted, there are the following advantages:

[0134] Remove the algorithm module. In the firmware processing, the algorithm consumes the most computing power. Since the read process does not involve functions such as maintaining the address translation table, kernel garbage collection, and wear leveling, removing it does not affect the entire read process. The address conversion function is removed and directly issued by the front end. As long as the channel number is correct, the pba address is automatically allocated at the back end, greatly simplifying the read process.

[0135] After the back-end core starts, it automatically pre-writes a word line in each lun. The entire IO process can omit the erase and write operations at the front end and the algorithm, greatly simplifying the process.

[0136] When reading at the back end, the addresses are automatically and evenly distributed. The distribution index of the nand addresses, from largest to smallest, is channel, ce, lun, plane (when aipr is enabled). Rotate in order from the largest first. After traversing, rotate to the lower layer. For example, when reading a message, first traverse the channel, and at this time ce / lun / plane are all 0; after all channels are traversed, then traverse ce. This ensures that the messages can be evenly sent to the nand, achieving an optimal concurrency and thus obtaining an optimal nand performance. The specific algorithm will be introduced in the detailed steps. The above traversal is implemented according to the Nand organization method.

[0137] Since the algorithm module is omitted, the delay of the algorithm can be added between the front end and the back end to more accurately simulate the time consumption under the formal firmware, verify more flexibly, and the computing power optimization target of the algorithm can be evaluated by adjusting this delay.

[0138] The subtracted interaction messages are reduced from 16 dwords to 4 dwords, and only the necessary content (such as pba, message ID, and host address) is transmitted. Other messages are completed in the processing module, reducing the memory access and configuration consumption of the software.

[0139] Finally, the performance is calculated through the waveform and scaled to the performance of the formal chip in proportion to ensure the reliability of the results.

[0140] In summary, by trimming and adjusting the traditional firmware architecture of the SSD through the process, software bottlenecks can be eliminated to the greatest extent, chip problems can be exposed in advance, and risks can be released.

[0141] Through the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) and includes several instructions for causing a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0142] In this embodiment, a performance testing device for a data reading program is also provided. The device is used to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0143] Figure 6 is a structural block diagram of a performance testing device for a data reading program according to an embodiment of the present application, as Figure 6As shown in the figure, the device includes: a receiving module 62 for receiving a target test request sent by the host device, where the target test request is used to request testing the data access performance of a target data access program by accessing data in the memory; a conversion module 64 for converting a target operation instruction for the target data access program according to the access information carried in the target test request and the storage information of the memory, where the target operation instruction is used to indicate the quantity of data accessed from each of multiple storage areas of the memory by the target data access program, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage areas of the memory; a monitoring module 66 for monitoring the data access information of the target data access program during the process of calling the target data access program to execute the target operation instruction, where the data access information is used to indicate the transmission delay situation of data transmitted between the host device and the memory; and a generating module 68 for generating the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program, where the conversion delay is used to indicate the time consumption of the target data access program for converting the storage locations in the memory of the data requested to be accessed by the target test request.

[0144] Through the above steps, by receiving the target test request sent by the host device, and then according to the access information carried in the target test request and the storage information of the memory, the total amount of data accessed by the host device in the memory and the configuration of the storage areas of the memory are determined. Then, according to the access information and the storage information of the memory, the data access program deployed on the main control chip of the storage device burned on the target test platform is called to determine the quantity of data accessed from each storage area in the memory, thereby ensuring that there is a data access service in each storage area of the memory. During the calling process, the data access information indicating the delay situation of data transmitted between the host device and the memory is monitored, so as to obtain the time consumption for accessing the data. At the same time, the time consumption for the target data access program to convert the storage locations in the memory of the data requested to be accessed is calculated to obtain the conversion delay. Finally, the target data access performance is comprehensively evaluated according to the delay situation indicated by the data access information and the conversion delay. In this way, on the one hand, the operation of the algorithm module can be avoided, thereby reducing the storage space consumption of the target test platform. On the other hand, the extreme performance of the data access program when accessing data can be tested. Therefore, the problem of low performance test efficiency of the data reading program in the related technology can be solved, and the effect of improving the performance test efficiency of the data reading program can be achieved.

[0145] Optionally, the conversion module includes:

[0146] An allocation unit, configured to allocate a target data volume of data to be accessed in each of the storage areas according to the total data volume of the data requested to be accessed by the target test request and the storage information, where the access information includes the total data volume;

[0147] A generation unit, configured to generate the target operation instruction for requesting to extract the data of the target data volume from each of the storage areas.

[0148] Optionally, the allocation unit is further configured to:

[0149] Calculate a target ratio of the target storage capacity of each of the storage areas in the total capacity of the multiple storage areas, where the storage information includes the target storage capacity corresponding to each of the storage areas;

[0150] Allocate the total data volume according to the target ratio to obtain the target data volume of the data to be accessed in each of the storage areas.

[0151] Optionally, the generation unit is further configured to:

[0152] Obtain the access address information of each of the storage areas,

[0153] Add the access address information and the target data volume to corresponding positions in the access instruction template to obtain a target access instruction, where the target operation instruction includes the target access instruction corresponding to each of the storage areas.

[0154] Optionally, the device further includes:

[0155] An acquisition module, configured to acquire the operation type of the data access operation requested to be executed by the target test request after receiving the target test request sent by the host device;

[0156] A writing module, configured to write preset data to all storage positions in each of the storage areas when the operation type indicates that a data reading operation is to be performed on the memory.

[0157] Optionally, the device further includes:

[0158] A detection module, configured to detect the data storage status in each of the storage areas after acquiring the operation type of the data access operation requested to be executed by the target test request, when the operation type indicates that a data writing operation is to be performed on the memory;

[0159] An emptying module, configured to empty the data stored in the storage area when the data storage status indicates that there is data stored in the storage area.

[0160] Optionally, the monitoring module includes:

[0161] A first determination unit, configured to determine a target waveform from the data transmission waveform of the target test platform, where the data transmission waveform is used to characterize the data transmission situation between the host device and the memory of the target test platform, and the target waveform is used to indicate the data transmission situation between the host device and the memory when the target test platform responds to the target test request;

[0162] A second determination unit, configured to determine the target waveform duration as the reference transmission delay of the target test platform, where the reference transmission delay is used to indicate the time required for the target test platform to call the target data access program to transmit the total data volume requested by the target test request, and the data access information includes the reference transmission delay.

[0163] Optionally, the generation module includes:

[0164] A first calculation unit, configured to calculate a reference ratio of the first main frequency of the main control chip and the second main frequency of the target test platform, where the first main frequency is used to characterize the operating speed of the main control chip, and the second main frequency is used to characterize the operating speed of the target test platform;

[0165] A transmission unit, configured to calculate a target transmission delay for the main control chip to call the target data access program to transmit the total data volume according to the reference ratio and the reference transmission delay;

[0166] A second calculation unit, configured to calculate the sum of the target transmission delay and the conversion delay to obtain a total delay;

[0167] A third calculation unit, configured to calculate a quotient of the total data volume and the total delay to obtain the data access rate of the target data access program on the main control chip, where the target data access performance includes the data access rate.

[0168] It should be noted that the above-mentioned various modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned various modules are respectively located in different processors in any combination form.

[0169] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0170] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), external hard drives, magnetic disks, or optical discs.

[0171] An embodiment of the present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0172] In an exemplary embodiment, the above electronic device may further include a transmission device and input / output devices. Among them, the transmission device is connected to the above processor, and the input / output devices are connected to the above processor.

[0173] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above method embodiments.

[0174] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above method embodiments.

[0175] An embodiment of the present application also provides a computer program. The computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in any one of the above method embodiments.

[0176] Specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be repeated here.

[0177] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present application can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a sequence different from that here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0178] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included within the protection scope of the present application.

Claims

1. A performance testing method for a data reading program, characterized in that: The target test system includes a host device, a target test platform and a memory, wherein the target test platform is connected between the host device and the memory, and a data access program deployed on a main control chip of a storage device is burned on the target test platform. The method is applied to the target test platform, and the method includes: receiving a target test request sent by the host device, wherein the target test request is used to request to test data access performance of a target data access program by accessing data to the memory; Converting a target operation instruction for the target data access program according to the access information carried by the target test request and the storage information of the memory, wherein the target operation instruction is used to indicate the amount of data accessed by the target data access program from each of the multiple storage areas of the memory, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage area of ​​the memory; In the process of calling the target data access program to execute the target operation instruction, monitoring data access information of the target data access program, wherein the data access information is used to indicate a transmission delay of data transmitted between the host device and the memory; The target data access performance of the target data access program is generated based on the data access information and the conversion delay of the target data access program, wherein the conversion delay is used to indicate the time consumed by the target data access program to convert the storage location of the data requested to be accessed by the target test request in the memory.

2. The method according to claim 1, characterized in that The converting the target operation instruction for the target data access program according to the access information carried by the target test request and the storage information of the memory includes: Allocating a target data volume of data to be accessed in each of the storage areas according to the total data volume of data requested to be accessed by the target test request and the storage information, wherein the access information includes the total data volume; The target operation instruction for requesting to extract a target data amount of data from each of the storage areas is generated.

3. The method according to claim 2, characterized in that The allocating a target data volume of data to be accessed in each storage area according to the total data volume of the data requested to be accessed by the target test request and the storage information comprises: Calculating a target proportion of a target storage capacity of each storage area to a total capacity of the plurality of storage areas, wherein the storage information includes the target storage capacity corresponding to each storage area; The total data volume is allocated according to the target ratio to obtain the target data volume of the data required to be accessed by each storage area.

4. The method according to claim 2, characterized in that: The generating of the target operation instruction for requesting to extract the target data amount from each of the storage areas comprises: Obtaining access address information of each of the storage areas, The access address information and the target data volume are added to corresponding positions in an access instruction template to obtain a target access instruction, wherein the target operation instruction includes the target access instruction corresponding to each of the storage areas.

5. The method according to claim 1, characterized in that After receiving the target test request sent by the host device, the method further includes: Obtaining an operation type of the data access operation requested to be performed by the target test request; In a case where the operation type indicates that a data read operation is performed on the memory, preset data is written into all storage locations of each of the storage areas.

6. The method according to claim 5, characterized in that After obtaining the operation type of the data access operation requested to be executed by the target test request, the method further includes: In a case where the operation type indicates that a data write operation is to be performed on the memory, detecting a data storage state in each of the storage areas; When the data storage state indicates that data is stored in the storage area, the data stored in the storage area is cleared.

7. The method according to claim 1, characterized in that The monitoring of the data access information of the target data access program includes: Determine a target waveform from the data transmission waveform of the target test platform, wherein the data transmission waveform is used to characterize the data transmission status between the host device and the memory of the target test platform, and the target waveform is used to indicate the data transmission status between the host device and the memory of the target test platform in response to the target test request; Determine the target waveform duration as a reference transmission delay of the target test platform, wherein the reference transmission delay is used to indicate the time required for the target test platform to call the target data access program to transmit the total amount of data requested to be accessed by the target test request, and the data access information includes the reference transmission delay; The step of generating the target data access performance of the target data access program according to the data access information and the conversion delay of the target data access program includes: Calculating a reference ratio of a first main frequency of the main control chip to a second main frequency of the target test platform, wherein the first main frequency is used to characterize the operating speed of the main control chip, and the second main frequency is used to characterize the operating speed of the target test platform; Calculate the target transmission delay for the main control chip to call the target data access program to transmit the total amount of data according to the reference ratio and the reference transmission delay; Calculating the sum of the target transmission delay and the conversion delay to obtain a total delay; The quotient of the total data volume and the total delay is calculated to obtain a data access rate of the target data access program on the main control chip, wherein the target data access performance includes the data access rate.

8. A performance testing device for a data reading program, characterized in that: The target test system includes a host device, a target test platform and a memory, wherein the target test platform is connected between the host device and the memory, and a data access program deployed on a main control chip of a storage device is burned on the target test platform. The device is applied to the target test platform, and the device includes: a receiving module, configured to receive a target test request sent by the host device, wherein the target test request is used to request to test the data access performance of a target data access program by accessing data to the memory; a converting module, configured to convert a target operation instruction for the target data access program according to the access information carried by the target test request and the storage information of the memory, wherein the target operation instruction is used to indicate the amount of data accessed by the target data access program from each of the multiple storage areas of the memory, the access information is used to indicate the total amount of data requested to be accessed in the memory, and the storage information is used to indicate the configuration of the storage area of ​​the memory; A monitoring module, used for monitoring data access information of the target data access program during the process of calling the target data access program to execute the target operation instruction, wherein the data access information is used to indicate the transmission delay of data transmitted between the host device and the memory; A generation module is used to generate the target data access performance of the target data access program based on the data access information and the conversion delay of the target data access program, wherein the conversion delay is used to indicate the time consumed by the target data access program to convert the data requested to be accessed by the target test request to a storage location in the memory.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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