A performance verification system, method, terminal and storage medium for a matrix vector processor

Abstract

The present invention belongs to the technical field of computer hardware detection, and particularly relates to a performance verification system, method, terminal and storage medium for a matrix vector processor, including an excitation data storage RAM, a test point setting module, an excitation data acquisition module, a verification execution FSM state machine, an excitation signal transmission module, a calculation result capture module, a result data storage RAM, a result comparison and discrimination module, a plurality of input signal clusters and a plurality of output signal clusters. By adopting the signal cluster design, the present invention effectively reduces the wiring complexity and the usage amount of LUT resources, and the verification excitation and response comparison data adopt a preset storage mode, without the need to generate excitation signals in real time, which greatly improves the verification efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer hardware detection, and particularly relates to a performance verification system, method, terminal and storage medium for a matrix vector processor. Background Art

[0002] With the rapid development of modern computer systems and embedded systems, matrix-vector processors play an increasingly important role in various high-performance computing tasks. By optimizing matrix and vector operations, matrix-vector processors can significantly improve computing efficiency and are widely used in fields such as artificial intelligence, image processing, and scientific computing. However, with the increasing complexity of processor architectures, how to ensure the correctness and efficiency of their designs has become a key issue. Performance verification is an important link in the processor design process, which ensures the correctness, efficiency, and reliability of the architecture design before the chip enters the detailed design (RTL coding) and physical implementation (tape-out).

[0003] Existing matrix-vector processor verification architectures are usually very complex, especially in multi-core collaborative processor architectures. This complexity leads to a large consumption of on-chip resources, such as lookup table (LUT) resources, during the verification process. For example, a typical multi-core matrix-vector processor may contain multiple coprocessors and a complex memory hierarchy, and verifying the collaborative work of these modules requires a large amount of resources, which not only increases the hardware cost but also may lead to resource waste.

[0004] In a multi-core collaborative matrix-vector processor, the verification process usually requires real-time generation of stimulus signals, which makes it difficult to achieve a high level of path coverage in a short time. For example, a system containing multiple matrix and vector coprocessors may take hours or even days to complete a full verification, which seriously affects the verification efficiency and user experience. Summary of the Invention

[0005] Aiming at the defect that in a multi-core collaborative matrix-vector processor in the prior art, the verification process usually requires real-time generation of stimulus signals, which makes it difficult to achieve a high level of path coverage in a short time, the present invention provides a performance verification system, method, terminal and storage medium for a matrix vector processor to solve the above technical problems.

[0006] In a first aspect, the present invention provides a performance verification system for a matrix vector processor, including:

[0007] A number of input signal clusters and a number of output signal clusters, with a number of input signal lines connected to each input signal cluster. One end of each input signal line away from the input signal cluster corresponds to a test point in the matrix vector processor to be verified. A number of output signal lines are connected to each output signal cluster. One end of each output signal line away from the output signal cluster corresponds to a test response point in the matrix vector processor to be verified;

[0008] The excitation data storage RAM is used to store the excitation data for verification;

[0009] The test point setting module is used to receive the input signal cluster code involved in the target verification module / module combination in the matrix vector processor to be verified, the ID of the target input signal line for sending the excitation signal on this input signal cluster, the output signal cluster code involved in the current target verification module / module combination, and the ID of the target output signal line for receiving the data processing result on this output signal cluster. It is used to generate the corresponding excitation data hash address according to the input signal cluster code and the ID of the target input signal line, and generate the corresponding result data hash address according to the output signal cluster code and the ID of the target output signal line;

[0010] The excitation data acquisition module is used to read the target excitation data from the corresponding position in the excitation data storage RAM according to the excitation data hash address and send it to the verification execution FSM state machine;

[0011] The verification execution FSM state machine is used to perform format conversion on the received target excitation data to generate an excitation signal;

[0012] The excitation signal transmitting module is used to send the excitation signal generated by the verification execution FSM state machine to the target verification module according to the input signal cluster corresponding to the input signal cluster code and the input signal line corresponding to the ID of the target input signal line;

[0013] The calculation result capturing module is used to receive the data processing result feedback from the target verification module according to the output signal cluster corresponding to the output signal cluster code and the output signal line corresponding to the ID of the target output signal line;

[0014] The result data storage RAM is used to store the theoretical verification calculation result corresponding to the current excitation data in the target verification module / module combination;

[0015] The result comparison and identification module is used to read the theoretical verification calculation result from the corresponding position in the result data storage RAM according to the result data hash address, compare the data processing result received by the calculation result capturing module with the theoretical verification calculation result, and send the comparison result to the verification execution FSM state machine.

[0016] A further improvement of this technical solution is that it further includes a coverage rate recording module, which is used to record the function coverage rate, code coverage rate, and assertion coverage rate of all function points that pass the verification in the target verification module calculated by the verification execution FSM state machine according to the comparison result.

[0017] A further improvement of this technical solution is that it further includes a key information setting module, which is used to receive the key information input by the user. The key information includes the clock frequency required for this verification and the excitation signal transmission bandwidth, and sends it to the verification execution FSM state machine.

[0018] A further improvement of this technical solution is that it further includes a verification report generation module, which is used to integrate the clock frequency, excitation signal transmission bandwidth, and calculated coverage rate involved in the current verification into a verification report and send it to the user terminal.

[0019] A further improvement of this technical solution is that it further includes a process detection and recording module, which is used to record the execution stage of this verification in real time. The execution stage includes excitation signal generation, excitation signal transmission, calculation result reception, coverage rate calculation, result comparison and identification, and verification report generation.

[0020] A further improvement of this technical solution is that it further includes a management information configuration module, which is used to perform parameter configuration on the excitation data storage RAM, test point setting module, excitation data acquisition module, verification execution FSM state machine, excitation signal transmission module, calculation result capture module, result data storage RAM, result comparison and identification module, coverage rate recording module, key information setting module, verification report generation module, and process detection and recording module.

[0021] In a second aspect, the present invention provides a verification method for a performance verification system of a matrix vector processor based on any one of the above, including:

[0022] S1. Generate a corresponding excitation data hash address according to the target input signal cluster encoding and target input signal line ID input by the user, and generate a corresponding result data hash address according to the target output signal cluster encoding and target output signal line ID input by the user;

[0023] S2. Read the pre-stored target excitation data from the corresponding position in the excitation data storage RAM according to the excitation data hash address and send it to the verification execution FSM state machine;

[0024] S3. The verification execution FSM state machine performs format conversion on the received target excitation data to generate an excitation signal;

[0025] S4. Encoding the corresponding input signal cluster and the input signal line corresponding to the target input signal line ID according to the input signal cluster, and sending the excitation signal generated by the verification execution FSM state machine to the target verification module in the matrix vector processor to be verified;

[0026] S5. Receiving the data processing result fed back by the target verification module according to the output signal cluster encoding the corresponding output signal cluster and the output signal line corresponding to the target output signal line ID;

[0027] S6. Reading the pre-stored theoretical verification calculation result from the corresponding position of the result data storage RAM according to the result data hash address, comparing the data processing result with the theoretical verification calculation result, and sending the comparison result to the verification execution FSM state machine;

[0028] S7. The verification execution FSM state machine calculates the function coverage rate, code coverage rate, and assertion coverage rate of all functional points passed in the target verification module according to the comparison result;

[0029] S8. Generating a verification report including the function coverage rate, code coverage rate, and assertion coverage rate, and sending it to the user terminal.

[0030] A further improvement of this technical solution is that before step S1, it also includes receiving the clock frequency and excitation signal transmission bandwidth required for this verification input by the user, and sending them to the verification execution FSM state machine.

[0031] In a third aspect, the present invention provides a terminal, including:

[0032] A processor and a memory, wherein,

[0033] The memory is used to store a computer program,

[0034] The processor is used to call and run the computer program from the memory, so that the terminal executes the method of the above terminal.

[0035] In a fourth aspect, the present invention provides a computer storage medium, and instructions are stored in the computer-readable storage medium. When it runs on a computer, it causes the computer to execute the methods described in the above aspects.

[0036] The beneficial effects of the present invention are as follows:

[0037] Efficient resource utilization: By adopting the "signal cluster" design, the verification system of the present invention can effectively reduce the wiring complexity and the usage amount of LUT resources. For example, a typical multi-core matrix-vector processor may consume a large amount of LUT resources to implement complex signal transmission and processing in the existing verification methods. However, through the multiplexing and optimized design of signal lines, the present invention significantly reduces resource consumption and hardware costs. The present invention supports flexible configuration of the verification requirements for different modules, and can dynamically adjust resource allocation according to actual needs, further improving the resource utilization efficiency.

[0038] Significantly improved verification efficiency: The verification stimulus and response comparison data adopt a preset storage mode, and there is no need to generate stimulus signals in real time, which greatly improves the verification efficiency. For example, in the existing methods, generating stimulus signals in real time may make it difficult to reach a high level of path coverage in a short time. However, through preset stimulus data, the present invention can quickly generate stimulus signals and conduct verification, significantly shortening the verification time. The architecture of the performance verification system adopts a modular design, optimizing the balance of multi-stream collaboration such as stimulus signal control, response result comparison, and coverage calculation, avoiding the inefficiency problem caused by complex verification processes. For example, a system containing multiple matrix and vector coprocessors may take hours or even days to complete a full verification in the existing methods. However, through modular design and optimized collaboration mechanisms, the present invention can significantly improve the verification efficiency and enhance the user experience.

[0039] In addition, the design principle of the present invention is reliable, the structure is simple, and it has a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a schematic block diagram of the performance verification part of the system.

[0042] Figure 2 It is a schematic block diagram of the matrix-vector processor to be verified in the system.

[0043] Figure 3 It is a schematic flow chart of the method according to an embodiment of the present invention.

[0044] Figure 4 It is a schematic structural diagram of a terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] To make the objectives, features, and advantages of the present invention more obvious and understandable, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the accompanying drawings in the specific embodiments. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0047] The following explains the key terms that appear in the present invention.

[0048] RAM, Random Access Memory, random access memory; is a storage device that allows data to be randomly read and written at any location, has a fast access speed, and is commonly used as the main memory of a computer system or on-chip storage.

[0049] FSM, Finite State Machine, finite state machine; is a mathematical model used to describe the states of a system and the transitions between states. In hardware design, FSM is commonly used in the design of control logic to manage different operating states of the system.

[0050] RoCC interface, Rocket Chip Custom Coprocessor Interface, rocket chip custom coprocessor interface; is an interface protocol used to connect the main processor and the coprocessor, allowing the coprocessor to work efficiently with the main processor, and is commonly used in the processor design of the RISC-V architecture.

[0051] L2 main memory, Level 2 Main Memory, secondary main memory; usually refers to the secondary cache (L2 Cache) in the processor, which has a larger capacity than the primary cache (L1 Cache) but a slightly higher access latency. It is used to store data and instructions frequently accessed by the processor to reduce the number of accesses to the main memory.

[0052] L1 cache, Level 1 Cache, primary cache; is a high-speed cache inside the processor, located near the processor core, with extremely low access latency and a small capacity. It is used to store the data and instructions most frequently accessed by the processor to improve system performance.

[0053] LUS, Load / Store Unit, is a functional module in a processor responsible for performing data load (reading data from memory into registers) and store (writing data from registers into memory) operations.

[0054] AXI4 bus, Advanced eXtensible Interface 4, is a high-performance on-chip bus protocol used to connect a processor to memory or other peripherals. It supports multiple data transfer modes and features high bandwidth and low latency.

[0055] Icache, Instruction Cache, is a dedicated cache in a processor used to store instructions to be executed. It improves the instruction fetch speed and reduces the latency of the processor fetching instructions from main memory.

[0056] Dcache, Data Cache, is a dedicated cache in a processor used to store data accessed by the processor. It improves the data fetch speed and reduces the latency of the processor fetching data from main memory.

[0057] ALU, Arithmetic Logic Unit, is a functional module in a processor responsible for performing arithmetic operations (such as addition, subtraction, multiplication, division) and logical operations (such as AND, OR, NOT).

[0058] FPU, Floating Point Unit, is a functional module in a processor specifically used to perform floating-point operations such as addition, subtraction, multiplication, division, etc.

[0059] SFU, Special Function Unit, is a functional module in a processor used to perform specific complex operations such as vector operations, matrix operations, etc., typically used in high-performance computing and graphics processing.

[0060] LD, Load, refers to the operation of reading data from memory into registers.

[0061] ST, Store, refers to the operation of writing data from registers into memory.

[0062] These terms are very important in computer architecture and hardware design, as they describe the key components of a processor and memory and their functions.

[0063] Such as Figure 1As shown in the figure, the present invention provides a performance verification system for a matrix vector processor, including a matrix vector processor to be verified and a performance verification part of the matrix vector processor to be verified. The performance verification part of the matrix vector processor to be verified includes an excitation data storage RAM, a test point setting module, an excitation data acquisition module, a verification execution FSM state machine, an excitation signal transmitting module, a calculation result capturing module, a result data storage RAM, a result comparison and discrimination module, a plurality of input signal clusters and a plurality of output signal clusters. A plurality of input signal lines are connected to each input signal cluster, and one end of each input signal line far away from the input signal cluster correspondingly connects to a test point in the matrix vector processor to be verified. A plurality of output signal lines are connected to each output signal cluster, and one end of each output signal line far away from the output signal cluster correspondingly connects to a test response point in the matrix vector processor to be verified.

[0064] In the system of the present invention, by adopting the "signal cluster" design, the wiring complexity is significantly reduced, and the usage amount of lookup table (LUT) resources is decreased. Each input / output signal cluster supports data transmission multiplexing of multiple signal lines through a high-transmission-bandwidth communication bus, which means that limited hardware resources can be utilized more efficiently during the verification process. Due to the introduction of the excitation data storage RAM and the result data storage RAM, the verification excitation and response comparison data do not need to be generated in real time, but a preset storage mode is adopted. This way avoids the overhead caused by dynamically allocating and releasing resources during the verification process, and further improves the resource utilization efficiency.

[0065] This system supports flexible configuration of the verification requirements for different modules. Users can easily specify the module or module combination to be verified, as well as the corresponding input / output signal clusters and signal lines through the test point setting module. This high flexibility enables the verification system to adapt to the verification requirements of matrix vector processors with different scales and complexities. In addition, the system also supports dynamically adjusting the resource allocation according to actual needs, such as adjusting the number of input / output signal clusters and the connection of signal lines, to optimize the verification process and results.

[0066] Since the excitation data required for verification is pre-stored in the excitation data storage RAM, the verification execution FSM state machine can quickly generate excitation signals and send them to the module to be verified, without generating excitation signals in real time. This way greatly shortens the verification preparation time and improves the verification efficiency. The system adopts a modular design, optimizing the balance in aspects of multi-stream coordination such as excitation signal control, response result comparison, and coverage rate calculation. Each module works in cooperation to jointly complete the entire verification process from excitation signal generation to verification report generation, avoiding the problem of low efficiency in complex verification processes.

[0067] In addition, the setting method of the input signal cluster and the output signal cluster in the matrix vector processor to be verified is as Figure 2As shown in the figure. The matrix vector processor to be verified includes a main processor, a Matrix co-processor, a Vector co-processor, and a processor L2 main memory; the Matrix co-processor and the Vector co-processor are connected to the main processor through a RoCC interface in a one-hangs-two mode; the main processor's main processor L1 cache, the Matrix LUS unit (which is the storage unit of the Matrix co-processor) of the Matrix co-processor, and the Vector LUS unit (which is the storage unit of the Vector co-processor) of the Vector co-processor are connected to the processor L2 main memory through the AXI4 bus to achieve storage data exchange.

[0068] The main processor is designed with a five-stage pipeline, including an instruction fetch stage, a decoding stage, an issue stage, an execution stage, a result collection and write-back stage, a total of five stages. The main processor L1 cache includes an instruction cache Icache and a data cache Dcache; the main processor also includes an instruction fetch module, a warp allocation module, a decoding module, an issue cache module, a first scoreboard module, a main processor register file module, a task issue module, a main processor computing unit (including ALU, FPU, SFU, etc.), a co-processor task scheduling module, a computing result write-back module, and a second scoreboard module and other main modules. The main processor is mainly responsible for the calculation of some RISC-V conventional instructions, and completes the necessary preliminary decoding and scheduling for the Matrix matrix calculation in the Matrix co-processor and the Vector vector calculation in the Vector co-processor.

[0069] The Vector co-processor is designed with a three-stage pipeline, including secondary decoding-scheduling, execution, result collection and write-back, a total of three stages. The storage unit of the Vector co-processor includes a Vector LUS unit, an LD read unit, an ST write unit, and a multi-core data exchange module responsible for exchanging storage information with other cores; the Vector co-processor includes a Decode secondary decoding module, a Schedule secondary scheduling module, a data distribution unit, a process monitoring distribution unit, and multiple Vector process groups (each group contains 32 Vector computing units, and the number of Vector process groups can be arbitrarily expanded according to actual application requirements). The Vector co-processor is responsible for executing Vector vector calculations and needs to write the calculation results back to the processor L2 main memory through the Vector LUS unit in a timely manner.

[0070] The Matrix matrix co - processor is designed with a three - stage pipeline, including three stages: secondary decoding - scheduling, execution, and result collection and write - back. The storage unit of the Matrix matrix co - processor includes Matrix LUS units, LD read units, ST write units, and a multi - core data exchange module responsible for exchanging storage information with other cores; the Matrix matrix co - processor includes a Decode secondary decoding module, a Schedule secondary scheduling module, a data distribution unit, a process monitoring and distribution unit, and multiple Matrix process groups (each group contains 32 Matrix computing units, and the number of Matrix process groups can be arbitrarily expanded according to actual application requirements). The Matrix matrix co - processor is responsible for executing Matrix matrix calculations and needs to write the calculation results back to the processor L2 main memory via the Matrix LUS units in a timely manner.

[0071] One or more related functional modules of the main processor / Matrix matrix co - processor / Vector vector co - processor use the input excitation signal as the input signal and execute the corresponding calculation functions in a pipeline manner.

[0072] The input signal clusters include the main - processor input signal cluster, the Matrix matrix - co - processor input signal cluster, and the Vector vector - co - processor input signal cluster; the output signal clusters include the main - processor output signal cluster, the Matrix matrix - co - processor output signal cluster, and the Vector vector - co - processor output signal cluster.

[0073] To ensure the verification accuracy, the following signal sampling points, including test points and test response points, are deployed for the key modules of each processor. An input signal line (i.e., excitation emission signal line) is set between each test point and the input signal cluster, and an output signal line (i.e., response reception signal line) is set between each test response point and the output signal cluster.

[0074] Specifically, the test points corresponding to the main - processor input signal cluster include: the input ports of the instruction fetch module, the warp distribution module, the decoding module, the scoreboard module, the task emission module, the main - processor computing unit, the co - processor task scheduling module input port, and the calculation result write - back module input port, etc.; the test response points corresponding to the main - processor input signal cluster include: the output ports of the instruction fetch module, the warp distribution module, the decoding module, the scoreboard module, the task emission module, the main - processor computing unit, the co - processor task scheduling module output port, and the calculation result write - back module output port, etc.

[0075] The test points corresponding to the input signal clusters of the Matrix matrix co-processor include: the input ports of the multi-core data exchange module, the input ports of process group 1, the input ports of process group n, the input ports of the secondary decoding and scheduling module, the input ports of the data distribution unit, and the input ports of the process monitoring and distribution unit, etc.; the test response points corresponding to the output signal clusters of the Matrix matrix co-processor include: the output ports of the multi-core data exchange module, the output ports of process group 1, the output ports of process group n, the output ports of the secondary decoding and scheduling module, the output ports of the data distribution unit, and the output ports of the process monitoring and distribution unit; similarly, the input signal clusters of the Vector vector co-processor are also provided with test points and corresponding test response points; all the above signal sampling points can be adjusted and expanded arbitrarily according to the actual situation of the matrix-vector processor to be verified, and the application is convenient and efficient.

[0076] The input / output signal clusters of different processors are a high-transmission-bandwidth communication bus, which can support data transmission to multiple corresponding excitation emission signal lines / response reception signal lines and support data transmission multiplexing of multiple signal lines. For example, the input signal cluster of the main processor can send relevant excitation data to the excitation emission signal lines 1 to 8 at the sampling points of the corresponding modules of the main processor; the output signal cluster of the Vector vector co-processor supports feedback of the response data of relevant excitations from the response reception signal lines 1 to 6 at the sampling points of the corresponding modules in the Vector vector co-processor and transmits it back to the performance verification part of the matrix-vector processor to be verified.

[0077] Through the design of the input signal cluster and the output signal cluster, the excitation signal and the response data can be efficiently transmitted to each module of the matrix vector processor to be verified during the verification process. Each signal cluster supports the data transmission multiplexing of multiple signal lines, greatly improving the data transmission bandwidth and efficiency. By connecting the L1 cache of the main processor, the Matrix LUS unit of the Matrix matrix coprocessor, and the Vector LUS unit of the Vector vector coprocessor to the L2 main memory of the processor through the AXI4 bus, fast data exchange is achieved, ensuring the timeliness and accuracy of the data during the verification process. The present invention supports the verification of the module pipeline composed of a single module or multiple modules in the main processor, the Matrix matrix coprocessor, and the Vector vector coprocessor. This flexibility enables the verification system to adapt to verification requirements of different scales and complexities, improving the pertinence and effectiveness of the verification. The collaborative work among the main processor, the Matrix matrix coprocessor, and the Vector vector coprocessor is realized through the RoCC interface and the AXI4 bus in the one-hang-two mode, ensuring seamless docking and efficient collaboration among the modules during the verification process. The main processor, the Matrix matrix coprocessor, and the Vector vector coprocessor all adopt the pipeline design, enabling the computing tasks to be processed in parallel and improving the computing efficiency. Through the refined pipeline stage division, the computing status and output results of each stage can be monitored more accurately, providing detailed data support for performance verification. The introduction of the pipeline design also enables the verification system to better simulate the actual operation scenario, improving the reliability and practicality of the verification results. The input signal cluster sends the excitation signal to the relevant functional modules of the matrix vector processor to be verified, and these modules execute the corresponding computing functions in a pipeline manner. In this way, the computing functions and performance of each module can be accurately verified, ensuring the correctness and efficiency of the architecture design. The output signal cluster receives and transmits the response data of the computing results, enabling the verification system to compare the actual computing results with the theoretical expected results in real time, and timely discover and correct potential design defects or errors.

[0078] Among them, the stimulus data storage RAM is used to store the stimulus data for verification; the test point setting module is used to receive the input signal cluster code involved in the target verification module / module combination in the matrix vector processor to be verified, the target input signal line ID for sending the stimulus signal on the input signal cluster, the output signal cluster code involved in the current target verification module / module combination, and the target output signal line ID for receiving the data processing result on the output signal cluster, and is used to generate the corresponding stimulus data hash address according to the input signal cluster code and the target input signal line ID, and is used to generate the corresponding result data hash address according to the output signal cluster code and the target output signal line ID; the stimulus data acquisition module is used to read the target stimulus data from the corresponding position in the stimulus data storage RAM according to the stimulus data hash address, and send it to the verification execution FSM state machine; the verification execution FSM state machine is used to receive the target stimulus data from the received target The target excitation data is formatted and an excitation signal is generated; an excitation signal transmitting module is used to send the excitation signal generated by the verification execution FSM state machine to the target verification module according to the input signal cluster corresponding to the input signal cluster code and the input signal line corresponding to the target input signal line ID; a calculation result capture module is used to receive the data processing result fed back by the target verification module according to the output signal cluster corresponding to the output signal cluster code and the output signal line corresponding to the target output signal line ID; a result data storage RAM is used to store the theoretical verification calculation result corresponding to the current excitation data in the target verification module / module combination; a result comparison and identification module is used to read the theoretical verification calculation result from the corresponding position of the result data storage RAM according to the result data hash address, and compare the data processing result received by the calculation result capture module with the theoretical verification calculation result, and send the comparison result to the verification execution FSM state machine.

[0079] Specifically, the performance verification part of the matrix-vector processor to be verified includes four on-chip RAM memories, among which RAM1, RAM2, and RAM3 are stimulus data storage RAMs, and RAM4 is result data storage RAM; RAM1, RAM2, and RAM3 respectively store the verification stimulus data involved in the modules to be verified (also called target verification modules) inside the main processor, Matrix coprocessor, and Vector coprocessor, which can be directly read and applied after the sampling points are determined; RAM4 stores the corresponding output response data (also called theoretical verification calculation results) of the input verification stimulus data of all modules involved in the matrix-vector processor to be verified, which can be directly read and applied as a control after the sampling points are determined and the response of the target verification module is received.

[0080] Furthermore, the performance verification part of the matrix vector processor to be verified also includes a coverage recording module, a key information setting module, a verification report generating module, a process detection recording module and a management information configuration module.

[0081] Specifically, a coverage recording module is used to record the functional coverage, code coverage, and assertion coverage of all functional points that pass the verification in the target verification module calculated by the verification execution FSM state machine according to the comparison result. A key information setting module is used to receive the key information input by the user. The key information includes the clock frequency and the excitation signal transmission bandwidth required for this verification, and send it to the verification execution FSM state machine. A verification report generation module is used to integrate the clock frequency, excitation signal transmission bandwidth, and calculated coverage involved in the current verification into a verification report and send it to the user terminal. A process detection recording module is used to record the execution stage of this verification in real time. The execution stage includes excitation signal generation, excitation signal transmission, calculation result reception, coverage calculation, result comparison and identification, and verification report generation. A management information configuration module is used to configure parameters for the excitation data storage RAM, test point setting module, excitation data acquisition module, verification execution FSM state machine, excitation signal transmission module, calculation result capture module, result data storage RAM, result comparison and identification module, coverage recording module, key information setting module, verification report generation module, and process detection recording module.

[0082] In the present invention, the excitation data storage RAM adopts three independent excitation data storage RAMs (RAM1, RAM2, and RAM3) to store the verification excitation data of the main processor, the Matrix matrix coprocessor, and the Vector vector coprocessor respectively. This modular storage method makes the management of excitation data clearer and more efficient. During the verification process, the corresponding excitation data can be directly read according to the sampling points without real-time generation, greatly improving the verification efficiency. The test point setting module can automatically generate the excitation data hash address and the result data hash address by receiving the input signal cluster encoding, the target input signal line ID, the output signal cluster encoding, and the target output signal line ID input by the user, realizing the fast positioning and reading of the excitation data and the theoretical verification calculation results. The excitation data acquisition module quickly reads the target excitation data from the excitation data storage RAM according to the excitation data hash address and sends it to the verification execution FSM state machine, ensuring the accuracy and timeliness of the excitation signal. The verification execution FSM state machine performs format conversion on the received target excitation data to generate an excitation signal that meets the requirements of the module to be verified, further improving the flexibility and adaptability of the verification. The excitation signal transmission module accurately sends the generated excitation signal to the target verification module according to the input signal cluster encoding and the target input signal line ID, ensuring the smooth progress of the verification process. The calculation result capture module quickly receives the data processing result feedback from the target verification module according to the output signal cluster encoding and the target output signal line ID, providing data support for the subsequent result comparison. The result data storage RAM stores the corresponding output response data (theoretical verification calculation results) of all modules of the matrix vector processor to be verified for the input verification excitation data, providing an accurate reference basis for the result comparison. The result comparison and identification module reads the theoretical verification calculation results from the result data storage RAM according to the result data hash address and compares them with the actually received data processing results to quickly discover potential design defects or errors, improving the accuracy and reliability of the verification. The coverage rate recording module records the function coverage rate, code coverage rate, and assertion coverage rate calculated by the verification execution FSM state machine according to the comparison results, providing strong support for evaluating the integrity and effectiveness of the verification. The verification report generation module integrates the clock frequency, excitation signal transmission bandwidth, and calculated coverage rate involved in the current verification into a verification report and sends it to the user terminal for the user to view and evaluate the verification results conveniently. The process detection and recording module records the execution stage of this verification in real time, including excitation signal generation, excitation signal transmission, calculation result reception, coverage rate calculation, result comparison and identification, and verification report generation, providing the user with a detailed log of the verification process for easy problem tracking and debugging. The management information configuration module configures parameters for each module, enabling the verification system to be flexibly adjusted according to different verification requirements, improving the adaptability and scalability of the verification system.

[0083] This system supports the verification of a single module in a processor, as well as the pipelined verification of a module composed of multiple modules within a single processor, and also supports the pipelined verification of modules between cross-processors (main processor - coprocessor (including Matrix matrix coprocessor and Vector vector coprocessor)) (the pipelined verification is performed according to the sorting of multiple groups of excitation data included in the excitation signal, and the pipelined verification here is a prior art and will not be elaborated here).

[0084] If it is necessary to verify a single module (target verification module) in the processor, only need to emit an excitation signal through the performance verification part of the matrix-vector processor to be verified. The corresponding input signal cluster of the processor (main processor or coprocessor) is sent to the target verification module through relevant signal points; after the target verification module finishes processing the excitation signal, the output signal of the target verification module is sent to the performance verification part of the matrix-vector processor to be verified through the corresponding output signal line and the corresponding output signal cluster of the processor, and wait for verification.

[0085] Similarly, if it is necessary to perform pipelined verification on a module composed of multiple modules within a single processor (i.e., the target verification module combination, such as Module A - Module B - Module C), then emit an excitation signal through the performance verification part of the matrix-vector processor to be verified. The corresponding input signal cluster of the processor is sent to Module A through relevant signal points; after Module B and Module C finish pipelining the processing of the excitation signal, the output signal of Module C is sent to the performance verification part of the matrix-vector processor to be verified through the corresponding output signal line of Module C and the corresponding output signal cluster of the processor, and wait for verification.

[0086] Similarly, if it is necessary to perform pipelined verification on the cross-processor modules of the main processor - coprocessor (for example, Module A - Module B - Module C - Module D), then emit an excitation signal through the performance verification part of the matrix-vector processor to be verified. The corresponding input signal cluster of the main processor is sent to Module A through relevant signal points; after Module B, Module C, and Module D finish pipelining the processing of the excitation signal, the output signal of Module D is sent to the performance verification part of the matrix-vector processor to be verified through the signal line and the corresponding output signal cluster of the coprocessor, and wait for verification.

[0087] The system in the present invention supports independent verification of a single module in a processor. This function enables designers to conduct detailed performance tests and fault troubleshooting for specific modules, ensuring that each module can meet the expected performance indicators. The system also supports verification of the module pipeline composed of multiple modules within a single processor, which enables designers to evaluate the collaborative working ability between modules and ensure the performance and stability of the entire processor. Particularly importantly, the system supports cross-processor (main processor - coprocessor) module pipeline verification, which greatly expands the scope of verification and enables designers to comprehensively evaluate the overall performance of the processor system, including data transfer efficiency and collaborative working ability between different processors. The system emits excitation signals through the performance verification part of the matrix vector processor to be verified and communicates with the target verification module or module combination via the corresponding input signal cluster and output signal cluster of the processor. This design makes the verification process more concise and efficient. Whether it is single-module verification, multi-module pipeline verification, or cross-processor pipeline verification, the system can automatically execute according to the preset process without manual intervention, greatly improving the automation degree and efficiency of verification.

[0088] As Figure 3 shown, the present invention provides a verification method for a performance verification system of a matrix vector processor based on any one of the above, including:

[0089] S1. Generate a corresponding excitation data hash address according to the target input signal cluster encoding and target input signal line ID input by the user, and generate a corresponding result data hash address according to the target output signal cluster encoding and target output signal line ID input by the user;

[0090] S2. Read the pre-stored target excitation data from the corresponding position in the excitation data storage RAM according to the excitation data hash address and send it to the verification execution FSM state machine;

[0091] S3. The verification execution FSM state machine performs format conversion on the received target excitation data to generate an excitation signal;

[0092] S4. Send the excitation signal generated by the verification execution FSM state machine to the target verification module in the matrix vector processor to be verified according to the input signal cluster corresponding to the input signal cluster encoding and the input signal line corresponding to the target input signal line ID;

[0093] S5. Receive the data processing result feedback from the target verification module according to the output signal cluster corresponding to the output signal cluster encoding and the output signal line corresponding to the target output signal line ID;

[0094] S6. Read the pre - stored theoretical verification calculation result from the corresponding position in the result data storage RAM according to the result data hash address, compare the data processing result with the theoretical verification calculation result, and send the comparison result to the verification execution FSM state machine;

[0095] S7. The verification execution FSM state machine calculates the function coverage rate, code coverage rate, and assertion coverage rate of all the function points that pass the verification in the target verification module according to the comparison result;

[0096] S8. Generate a verification report including the function coverage rate, code coverage rate, and assertion coverage rate, and send it to the user terminal.

[0097] Specifically, if the data processing result is the same as the theoretical verification calculation result, it indicates that the corresponding function verification of the target verification module passes; otherwise, the corresponding function verification of the target verification module fails, and it is sent to the verification execution FSM state machine. Then, the verification execution FSM state machine calculates the function coverage rate, code coverage rate, and assertion coverage rate of all the function points that pass the verification in the target verification module according to the comparison result (the calculation of the coverage rate here is prior art and will not be elaborated further).

[0098] Further, before step S1, it also includes receiving the clock frequency and excitation signal transmission bandwidth required for this verification input by the user, and sending them to the verification execution FSM state machine.

[0099] Through the user - defined clock frequency and excitation signal transmission bandwidth, the verification system of the present invention can adapt to verification tasks under different application scenarios and performance requirements. This flexibility makes the verification process closer to the actual usage environment, improving the practicality and reliability of the verification results. The clock frequency and excitation signal transmission bandwidth are key factors affecting the performance of the processor. Considering these factors during the verification process can more accurately simulate the actual operating state of the processor, thereby more precisely evaluating its performance. This helps to discover potential performance bottlenecks and optimization spaces, providing strong support for the design and optimization of the processor. According to the clock frequency and excitation signal transmission bandwidth input by the user, the verification execution FSM state machine can dynamically adjust the resource allocation and utilization strategy. For example, in the case of a higher clock frequency or a larger excitation signal transmission bandwidth, more resources can be invested to improve the verification efficiency; conversely, fewer resources can be invested to save costs. This optimization strategy helps to improve the overall performance and resource utilization rate of the verification system.

[0100] Figure 4 It is a schematic structural diagram of a terminal 400 provided by an embodiment of the present invention. The terminal 400 can be used to execute the performance verification method of the matrix - vector processor provided by the embodiment of the present invention.

[0101] Among them, the terminal 400 may include: a processor 410, a memory 420, and a communication module 430. These components communicate via one or more buses. Those skilled in the art can understand that the structure of the server shown in the figure does not constitute a limitation on the present invention. It can be a bus structure, a star structure, and may also include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0102] Among them, the memory 420 can be used to store the execution instructions of the processor 410. The memory 420 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disc. When the execution instructions in the memory 420 are executed by the processor 410, the terminal 400 is enabled to execute some or all of the steps in the above method embodiments.

[0103] The processor 410 is the control center of the storage terminal, connecting various parts of the entire electronic terminal through various interfaces and lines. By running or executing the software programs and / or modules stored in the memory 420, and calling the data stored in the memory, it executes various functions of the electronic terminal and / or processes data. The processor may be composed of an integrated circuit (IC), for example, it may be composed of a single packaged IC, or may be composed of multiple packaged ICs with the same or different functions connected. For example, the processor 410 may only include a central processing unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core or may include multiple operation cores.

[0104] The communication module 430 is used to establish a communication channel, so that the storage terminal can communicate with other terminals. It receives user data sent by other terminals or sends user data to other terminals.

[0105] The present invention also provides a computer storage medium. Among them, the computer storage medium can store a program, and when the program is executed, it may include some or all of the steps in the embodiments provided by the present invention. The storage medium may be a magnetic disk, an optical disc, a read-only memory (ROM), or a random access memory (RAM), etc.

[0106] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solutions in the embodiments of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc, etc., various media that can store program codes, including several instructions for causing a computer terminal (which can be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0107] For the same and similar parts among the various embodiments in this specification, reference can be made to each other. In particular, for the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the descriptions in the method embodiments.

[0108] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there can be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of systems or modules can be in electrical, mechanical, or other forms.

[0109] The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they can be located in one place, or they can be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, in each embodiment of the present invention, the functional modules can be integrated in a processing module, or each module can exist physically alone, or two or more modules can be integrated in one module.

[0111] Although the present invention has been described in detail by referring to the accompanying drawings and in conjunction with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions should all be within the scope of the present invention. / Any person skilled in the art within the technical scope disclosed by the present invention can easily conceive of changes or substitutions, which should all be covered by the protection scope of the present invention.

Claims

1. A performance verification system for a matrix vector processor, characterized in that Including: A number of input signal clusters and a number of output signal clusters. A number of input signal lines are connected to each input signal cluster. One end of each input signal line far from the input signal cluster corresponds to and is connected to a test point in the matrix vector processor to be verified. A number of output signal lines are connected to each output signal cluster. One end of each output signal line far from the output signal cluster corresponds to and is connected to a test response point in the matrix vector processor to be verified; An excitation data storage RAM for storing the excitation data for verification; A test point setting module, which is used to receive the input signal cluster code involved in the target verification module / module combination in the matrix vector processor to be verified, the ID of the target input signal line for sending the excitation signal on this input signal cluster, the output signal cluster code involved in the current target verification module / module combination, and the ID of the target output signal line for receiving the data processing result on this output signal cluster. It is used to generate the corresponding excitation data hash address according to the input signal cluster code and the ID of the target input signal line, and generate the corresponding result data hash address according to the output signal cluster code and the ID of the target output signal line; An excitation data acquisition module, which is used to read the target excitation data from the corresponding position in the excitation data storage RAM according to the excitation data hash address and send it to the verification execution FSM state machine; A verification execution FSM state machine, which is used to perform format conversion on the received target excitation data to generate an excitation signal; An excitation signal transmission module, which is used to send the excitation signal generated by the verification execution FSM state machine to the target verification module according to the input signal cluster corresponding to the input signal cluster code and the input signal line corresponding to the ID of the target input signal line; A calculation result capture module, which is used to receive the data processing result fed back by the target verification module according to the output signal cluster corresponding to the output signal cluster code and the output signal line corresponding to the ID of the target output signal line; A result data storage RAM for storing the theoretical verification calculation result corresponding to the current excitation data in the target verification module / module combination; A result comparison and discrimination module, which is used to read the theoretical verification calculation result from the corresponding position in the result data storage RAM according to the result data hash address, compare the data processing result received by the calculation result capture module with the theoretical verification calculation result, and send the comparison result to the verification execution FSM state machine.

2. The performance verification system of the matrix vector processor according to claim 1, characterized in that It further includes a coverage rate recording module, which is used to record the function coverage rate, code coverage rate, and assertion coverage rate of all functional points passed in the target verification module calculated by the verification execution FSM state machine according to the comparison result.

3. The performance verification system of the matrix vector processor according to claim 2, characterized in that, It further includes a key information setting module, which is used to receive the key information input by the user. The key information includes the clock frequency and excitation signal transmission bandwidth required for this verification, and send them to the verification execution FSM state machine.

4. The performance verification system of the matrix vector processor according to claim 3, characterized in that, It further includes a verification report generation module, which is used to integrate the clock frequency, excitation signal transmission bandwidth, and calculated coverage rate involved in the current verification into a verification report and send it to the user terminal.

5. The performance verification system of the matrix vector processor according to claim 4, wherein It further includes a process detection record module for recording the execution stage of this verification in real time. The execution stage includes excitation signal generation, excitation signal transmission, calculation result reception, coverage rate calculation, result comparison and identification, and verification report generation.

6. The performance verification system of the matrix vector processor according to claim 5, characterized in that It further includes a management information configuration module for performing parameter configuration on the excitation data storage RAM, test point setting module, excitation data acquisition module, verification execution FSM state machine, excitation signal transmission module, calculation result capture module, result data storage RAM, result comparison and identification module, coverage rate record module, key information setting module, verification report generation module, and process detection record module.

7. A verification method for a performance verification system of a matrix vector processor according to any one of claims 1-6, characterized in that, It includes: S1. Generate a corresponding excitation data hash address according to the target input signal cluster encoding and target input signal line ID input by the user, and generate a corresponding result data hash address according to the target output signal cluster encoding and target output signal line ID input by the user; S2. Read the pre-stored target excitation data from the corresponding position in the excitation data storage RAM according to the excitation data hash address, and send it to the verification execution FSM state machine; S3. The verification execution FSM state machine performs format conversion on the received target excitation data to generate an excitation signal; S4. Send the excitation signal generated by the verification execution FSM state machine to the target verification module in the matrix vector processor to be verified according to the input signal cluster corresponding to the input signal cluster encoding and the input signal line corresponding to the target input signal line ID; S5. Receive the data processing result feedback from the target verification module according to the output signal cluster corresponding to the output signal cluster encoding and the output signal line corresponding to the target output signal line ID; S6. Read the pre-stored theoretical verification calculation result from the corresponding position in the result data storage RAM according to the result data hash address, compare the data processing result with the theoretical verification calculation result, and send the comparison result to the verification execution FSM state machine; S7. The verification execution FSM state machine calculates the function coverage rate, code coverage rate, and assertion coverage rate of all functional points passed in the target verification module according to the comparison result; S8. Generate a verification report including the function coverage rate, code coverage rate, and assertion coverage rate, and send it to the user terminal.

8. The verification method according to claim 7, wherein Before step S1, it further includes receiving the clock frequency and excitation signal transmission bandwidth required for this verification input by the user, and sending them to the verification execution FSM state machine.

9. A terminal, characterized in that, It includes: A processor; A memory for storing the execution instructions of the processor; Wherein, the processor is configured to execute the method according to any one of claims 7-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the program is executed by the processor, it implements the method according to any one of claims 7-8.

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