Data processing method and device, electronic equipment and computer readable storage medium

Abstract

The invention discloses a data processing method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of data processing.The method comprises the steps that a processor obtains a read command; the read command comprises an initial logic block address and the number of logic blocks; on the basis of the initial logic block address, sequentially carrying out continuity judgment on the read command and commands in a plurality of preset different-sequence data read command streams; when it is judged that the read command is continuous with the command in the target sequential data read command stream, adding one to the matching coincidence frequency of the target sequential data read command stream; if the cumulative value of the matching coincidence times of the target sequence data reading command stream is greater than a first threshold value, pre-reading data in the flash memory unit based on the initial logic block address and the number of logic blocks, and storing the pre-read data in the cache unit, so that when a next reading command is obtained, the pre-read data in the flash memory unit are stored in the cache unit; and the data corresponding to the next read command can be searched from the cache unit.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a data processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] Due to its delicate size, excellent data throughput and random performance, and low power consumption, solid-state drives based on flash memory technology, such as NAND flash memory technology, are widely used. However, when reading data from a solid-state drive based on flash memory technology, there is a preparation time of dozens of microseconds in the flash memory cells, which occupies most of the latency of the read command. Currently, by classifying the read commands in the read command queue and determining whether the first n read commands have been read for each type of read command, the prefetching of the data corresponding to the (n + 1)-th read command and subsequent read commands can be triggered sequentially, so as to reduce the latency of reading data from the solid-state drive for multiple different types of sequential data read command streams. However, in this method, if the solid-state drive based on flash memory technology processes read commands through multiple processors, the order of each type of read command received by each processor will be distorted, so that the data prefetching operation cannot be triggered and started, resulting in the latency of obtaining data for the read command and reducing the user experience. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a data processing method, apparatus, electronic device, and computer-readable storage medium.

[0004] According to a first aspect of the present application, an embodiment of the present application provides a data processing method, which is applied to a solid-state drive. The solid-state drive includes flash memory cells, multiple processors, and a cache unit. The method includes: A processor obtains a read command; the read command includes a starting logical block address and a logical block number; Based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a preset plurality of different sequential data read command streams; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching count of the target sequential data read command stream is incremented by one; If the cumulative value of the matching count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the logical block number, the data in the flash memory cells is prefetched, and the prefetched data is stored in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0005] Optionally, determining that the read command is continuous with the commands in the target sequential data read command stream includes: If the ratio of the difference between the starting logical block address of a read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream is less than a second threshold, it is determined that the read command and the commands in the target sequential data read command stream are consecutive.

[0006] Optionally, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory cells, including: Based on the starting logical block address and the number of logical blocks, determine the starting logical block address of the pre-read data and the amount of pre-read data; Based on the starting logical block address of the pre-read data and the amount of pre-read data, pre-read the data in the flash memory cells.

[0007] Optionally, based on the starting logical block address and the number of logical blocks, determine the starting logical block address of the pre-read data and the amount of pre-read data, including: Perform a first weighted processing on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; Perform a second weighted processing on the number of logical blocks based on a second coefficient to obtain the amount of pre-read data.

[0008] Optionally, the data processing method further includes: Save the starting logical block address, amount, and physical address in the cache unit of the pre-read data; Based on the starting logical block address of the pre-read data, update the maximum logical block address corresponding to the cache unit.

[0009] Optionally, the data processing method further includes: If it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and amount of the pre-read data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; Based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out.

[0010] Optionally, determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and amount of the pre-read data stored in the cache unit, includes: If the number of pre-read data stored in the cache unit is greater than the third threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, based on the starting logical block address, the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit, determine that the target data corresponding to the read command is stored in the cache unit.

[0011] Optionally, based on the starting logical block address, the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit, determining that the target data corresponding to the read command is stored in the cache unit includes: Based on the starting logical block address and the number of logical blocks, determine the first logical block address range corresponding to the read command; Based on the starting logical block address and the number of the pre-read data stored in the cache unit, determine the second logical block address range corresponding to the pre-read data stored in the cache unit; If the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0012] According to the second aspect of the present application, an embodiment of the present application provides a data processing device, which is applied to a solid-state drive. The solid-state drive includes flash memory cells, multiple processors, and a cache unit. The device includes: An acquisition module, configured to acquire a read command; the read command includes a starting logical block address and the number of logical blocks; A determination module, configured to sequentially determine the continuity of the read command with the commands in a preset plurality of different-order data read command streams based on the starting logical block address; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, increment the matching compliance count of the target-order data read command stream by one; A pre-reading module, configured to, if the cumulative value of the matching compliance count of the target-order data read command stream is greater than the first threshold, pre-read the data in the flash memory cells based on the starting logical block address and the number of logical blocks, and store the pre-read data in the cache unit, so that when the next read command is acquired, the data corresponding to the next read command can be found in the cache unit.

[0013] Optionally, the determination module is configured to determine that the read command is continuous with the commands in the target-order data read command stream if the ratio of the difference between the starting logical block addresses between the read command and the commands in the target-order data read command stream to the number of logical blocks corresponding to the commands in the target-order data read command stream is less than the second threshold.

[0014] Optionally, the pre-reading module is configured to determine the starting logical block address of the pre-read data and the number of the pre-read data based on the starting logical block address and the number of logical blocks; Based on the starting logical block address of the pre-read data and the quantity of the pre-read data, pre-read the data in the flash memory cells.

[0015] Optionally, the pre-reading module is used to perform a first weighting process on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; Based on a second coefficient, perform a second weighting process on the number of logical blocks to obtain the quantity of the pre-read data.

[0016] Optionally, the data processing device further includes: An update module, configured to save the starting logical block address, quantity of the pre-read data, and the physical address in the cache unit; Based on the starting logical block address of the pre-read data, update the maximum logical block address corresponding to the cache unit.

[0017] Optionally, the data processing device further includes: A data reading module, configured to, if it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and quantity of the pre-read data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; Based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out.

[0018] Optionally, the data reading module is configured to, if the quantity of the pre-read data stored in the cache unit is greater than a second threshold and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and quantity of the pre-read data stored in the cache unit.

[0019] Optionally, the data reading module is configured to determine a first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks; Based on the starting logical block address and quantity of the pre-read data stored in the cache unit, determine a second logical block address range corresponding to the pre-read data stored in the cache unit; If the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0020] According to the third aspect of the present application, an embodiment of the present application provides a solid-state drive, including: Flash memory cells, multiple processors, and a cache unit; The processor is used to obtain a read command; the read command includes a starting logical block address and a number of logical blocks; based on the starting logical block address, the read command is successively determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching compliance count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory unit and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0021] According to a fourth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the data processing method as described in the first aspect or any implementation manner of the first aspect.

[0022] According to a fifth aspect of the present application, an embodiment of the present application provides a computer program product including a computer program or instructions, which when executed by a processor, implement the data processing method as described in the first aspect or any implementation manner of the first aspect.

[0023] The data processing method, device, electronic device, and computer-readable storage medium provided by the embodiments of the present application obtain a read command through a processor; the read command includes a starting logical block address and a number of logical blocks; based on the starting logical block address, the read command is successively determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching compliance count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory unit and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash technology processes read commands through multiple processors, each processor can accurately identify whether the read command is a sequential data read command, and when it is recognized that the read command is a sequential data read command, trigger and start the data pre-reading operation, so that the solid-state drive can identify multiple sequential data read command streams and perform data pre-reading through multiple processors, which can reduce the read latency of sequential data of the solid-state drive, improve the read performance of the solid-state drive, and improve the user experience.

[0024] The above description is only an overview of the technical solution of this application. In order to understand the technical means of this application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of this application more obvious and understandable, the following specifically illustrates the specific implementation manners of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic flowchart of a data processing method in an embodiment of this application; Figure 2 It is a schematic diagram showing that the multi-processor load imbalance in the solid-state drive in the embodiment of this application causes the distortion of the arrival order of different-order data read command streams to the firmware; Figure 3 It is a schematic diagram showing that the interference between different read command streams in the embodiment of this application causes the distortion of the arrival order of different-order data stream command streams to the firmware; Figure 4 It is a schematic flowchart of the continuity determination process in the embodiment of this application; Figure 5 It is a schematic flowchart of another data processing method in the embodiment of this application; Figure 6 It is a schematic structural diagram of a data processing device in the embodiment of this application; Figure 7 It is a schematic hardware structure diagram of a solid-state drive in the embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] To make the objectives, technical solutions and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0027] The embodiment of this application provides a data processing method, which is applied to a solid-state drive. The solid-state drive includes flash memory units, multiple processors and a cache unit. As Figure 1 shown, the method includes: S101, a processor obtains a read command; the read command includes a starting logical block address and a logical block number.

[0028] In this embodiment, the flash memory units are used to store data. The processor runs firmware to implement functions such as address mapping and data prefetching. The cache unit serves as a data cache area of the solid-state drive and is used to store pre-fetched data. Multiple processors share the cache unit.

[0029] In this embodiment, the solid-state drive pre-reads data for the received read commands through multiple processors.

[0030] In this embodiment, the host can generate multiple sequential data read command streams based on tasks and then send multiple sequential data read command streams to the solid-state drive simultaneously. Each sequential data read command stream is composed of multiple read commands, and the read range of each read command is composed of the starting logical block address ( , LPA) and the number of logical blocks ( ). Since the solid-state drive contains multiple processors, even if the sequential data read command streams sent by the host are strictly continuous, that is , represents the i-th read command. However, when the solid-state drive receives the read command stream, it is not strictly continuous inside. As Figure 2 shows, in the figure, the host issues 3 sequential data read command streams (Job1, Job2, and Job3), which access different lba ranges respectively. When the solid-state drive receives the read commands of Job1, due to the existence of multiple processors in the solid-state drive to allocate read commands, the order in which different read command streams reach the processor firmware becomes discontinuous, and the same is true for the read commands of Job2 and Job3. When the queue depth of the sequential data read command stream of the host is larger, this discontinuous phenomenon is more obvious.

[0031] Secondly, the host starts to issue sequential data read command streams at different times, and the time overlap and timing gap between the issued sequential data read command streams cause the multiple sequential data read command streams to interleave with each other in the firmware. As shown in the appendix Figure 3 , the read commands of Job1, Job2, and Job3 interleave to form the order of the read commands actually received by the firmware.

[0032] After the solid-state drive receives the read commands, it can first be parsed by the firmware in the processor to obtain information such as the logical address range to be read and the corresponding physical address.

[0033] S102, based on the starting logical block address, sequentially determine the continuity of the read commands with the commands in multiple preset different sequential data read command streams; and when it is determined that the read commands are continuous with the commands in the target sequential data read command stream, increment the matching count of the target sequential data read command stream by one.

[0034] In this embodiment, a prefetch data buffer and a prefetch management structure can be set for the prefetch of each sequential data command stream. The prefetch data buffer is located in the cache unit of the solid-state drive. The prefetch management structure can be stored in the processor memory. Each processor can manage the prefetch management structure. The prefetch management structure can include historical commands in the sequential data command stream or the corresponding historical read ranges of the commands, the number of matching times, the number of non-matching times, a valid data bitmap, the LPA of the prefetch data in the cache unit, the physical address (PBA) of the prefetch data, and the maximum LPA of the prefetch data. The historical commands in the sequential data command stream or the corresponding historical read ranges of the commands are used to determine the continuity of the read commands. The number of matching times is the trigger condition for prefetch, and the number of non-matching times is one of the interruption conditions for prefetch. The starting logical block address, physical address, valid data bitmap (recording whether the data is ready), and the maximum LPA of the prefetch data corresponding to each prefetch data are used to determine the hit of the prefetch.

[0035] In this embodiment, when the processor obtains a read command, the read command can be sequentially compared with the historical commands in the sequential data command stream in each prefetch management structure for continuity determination.

[0036] In some embodiments, for example, the solid-state drive is a solid-state drive based on NAND technology. The overall process of continuity determination is as shown in Figure 4 shown. The number of consecutive times is also the number of matching times, and the number of non-consecutive times is also the number of non-matching times. If it is consecutive with the command in the target sequential data read command stream, for example, consecutive with the historical read command in the prefetch management structure 3, then the number of matching times of the prefetch management structure 3 is incremented by one, and the number of non-matching times is cleared. Then enter the NAND data prefetch process. If the historical read commands in all prefetch management structures are not consecutive with the current read command, the continuity determination fails, the prefetch is interrupted, the prefetch process is exited, and data is read from the NAND flash unit.

[0037] In some embodiments, if the read command is consecutive with the command in the target sequential data read command stream, the read command can be updated to the command in the target sequential data read command stream to update the historical commands in the target sequential data read command stream.

[0038] In some embodiments, if the cumulative value of the number of mismatches in a certain sequential data read command stream is greater than a fourth threshold, it is considered that the data in the prefetch data buffer corresponding to the current prefetch management structure is no longer suitable for the host's sequential data read command stream, and the corresponding prefetch management structure can be re-initialized. The historical commands or the historical read ranges corresponding to the commands in the sequential data command stream in the prefetch management structure, the LPA of the prefetch data in the cache unit, the physical address (PBA) of the prefetch data, and the maximum LPA of the prefetch data are all set to invalid values; the number of match conformances, the number of mismatch conformances, and the valid data bitmap are all set to 0. Thus, the prefetch management structure becomes a prefetch management structure corresponding to an invalid historical read command.

[0039] In some embodiments, if the historical read commands in all prefetch management structures are not consecutive with the current read command, it can be determined whether there is a prefetch management structure corresponding to an invalid historical read command. If so, the read command is updated to the prefetch management structure corresponding to the invalid historical read command.

[0040] S103. If the cumulative value of the number of match conformances of the target sequential data read command stream is greater than a first threshold, prefetch the data in the flash memory unit based on the starting logical block address and the number of logical blocks, and store the prefetch data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0041] In this embodiment, if the cumulative value of the number of match conformances of the target sequential data read command stream is greater than a first threshold, it is considered that the current solid-state drive has received a sequential data read command stream request, enters the prefetch process, prefetch the data in the flash memory unit based on the starting logical block address and the number of logical blocks, and store the prefetch data in the cache unit.

[0042] The data processing method provided by the embodiment of the present application obtains a read command through a processor; the read command includes a starting logical block address and the number of logical blocks; based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching compliance count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory unit and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash memory technology processes read commands through multiple processors, each processor can accurately identify whether the read command is a sequential data read command, and when it is recognized that the read command is a sequential data read command, trigger the start of the data pre-reading operation, so that the solid-state drive can identify multiple sequential data read command streams and perform data pre-reading through multiple processors, which can reduce the read latency of sequential data in the solid-state drive, improve the read performance of the solid-state drive, and improve the user experience.

[0043] In an alternative embodiment, in step S102, determining that the read command is continuous with the commands in the target sequential data read command stream includes: If the ratio of the difference in the starting logical block address between the read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream is less than a second threshold, it is determined that the read command is continuous with the commands in the target sequential data read command stream.

[0044] Specifically, the following formula can be used to sequentially determine the continuity of the read command with the commands in a plurality of preset data read command streams in different orders: ; where is the initial logical block address of the read command, is the initial logical block address corresponding to the jth command in the mth sequential data read command stream; is the number of logical blocks corresponding to the jth command in the mth sequential data read command stream; is the second threshold.

[0045] In this embodiment, if the read range of the read command and the commands in a sequential data read command stream satisfies the above formula, the read command passes the continuity determination, and this sequential data read command stream is the target sequential data read command stream.

[0046] In this embodiment, by comparing the ratio of the difference in the starting logical block address between the read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream with a second threshold value, it is possible to quickly determine whether the read command is consecutive with the commands in the target sequential data read command stream.

[0047] In an alternative embodiment, in step S103, pre-reading the data in the flash memory cells based on the starting logical block address and the number of logical blocks includes: Determining the starting logical block address of the pre-read data and the amount of pre-read data based on the starting logical block address and the number of logical blocks; pre-reading the data in the flash memory cells based on the starting logical block address of the pre-read data and the amount of pre-read data.

[0048] In this embodiment, there should be a certain interval between the starting logical block address of the pre-read data and the reading range of the current read command, such that when the next read command arrives, the pre-read data is just ready in the buffer. Therefore, based on the starting logical block address and the number of logical blocks, as well as a preset waiting coefficient for pre-reading and a multiple coefficient for pre-reading, the starting logical block address of the pre-read data and the amount of pre-read data can be determined.

[0049] In this embodiment, after determining the starting logical block address and range of the pre-read data, the solid-state drive sequentially reads the data from the flash memory cells into the cache cells.

[0050] In some embodiments, it is also possible to save the starting logical block address, amount, and physical address in the cache cell of the pre-read data; update the maximum logical block address corresponding to the cache cell based on the starting logical block address of the pre-read data.

[0051] Specifically, during implementation, the starting logical block address, amount, and PBA of each pre-read data can be saved in the pre-read management structure, and at the same time, the maximum LPA of the pre-read data stored in the current cache cell can be updated for hit determination. After the pre-read data storage is completed, the corresponding valid data position in the pre-read management structure is set to 1.

[0052] In some embodiments, determining the starting logical block address of the pre-read data and the amount of pre-read data based on the starting logical block address and the number of logical blocks includes: Performing a first weighting process on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; performing a second weighting process on the number of logical blocks based on a second coefficient to obtain the amount of pre-read data.

[0053] In specific implementation, accuracy and coverage are used to measure the performance of the prefetching algorithm. The accuracy of prefetching is defined as the ratio of the correctly prefetched data to all the prefetched data, and the coverage is defined as the ratio of the correctly prefetched data to all the prefetched data. To ensure the accuracy and coverage of the prefetching algorithm, the starting logical block address of the prefetched data can be set to: ; The quantity of the prefetched data can be set to: ; wherein, is the waiting coefficient of prefetching, that is, the first coefficient; is the multiple coefficient of prefetching, that is, the second coefficient. The starting logical block address of the prefetched data; is the starting logical block address corresponding to the read command, the number of logical blocks.

[0054] In this embodiment, based on the number of logical blocks and the first coefficient, a first weighting process is performed on the starting logical block address to obtain the starting logical block address of the prefetched data; based on the second coefficient, a second weighting process is performed on the number of logical blocks to obtain the quantity of the prefetched data; the accuracy and coverage of the prefetched data can be improved by adjusting the first coefficient and the second coefficient, and the overall read interference of the solid-state drive can be reduced.

[0055] In an alternative embodiment, as Figure 5 shown, the data processing method further includes: S104, if it is determined, based on the starting logical block address and the number of logical blocks, and the starting logical block address and the quantity corresponding to the prefetched data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit, determining the physical address of the target data corresponding to the read command in the cache unit; S105, reading the target data from the cache unit based on the physical address of the target data in the cache unit and sending it out.

[0056] In some implementation manners, in step S104, determining, based on the starting logical block address and the number of logical blocks, and the starting logical block address and the quantity corresponding to the prefetched data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit includes: If the quantity of the prefetched data stored in the cache unit is greater than a third threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, determining, based on the starting logical block address and the number of logical blocks, and the starting logical block address and the quantity corresponding to the prefetched data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit.

[0057] In the present embodiment, before determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number corresponding to the pre-read data stored in the cache unit, by determining whether the number of pre-read data stored in the cache unit is greater than a third threshold, and determining whether the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, it can be timely determined whether there is sufficient data in the cache unit and whether the target data corresponding to the read command exists in the cache unit, avoiding a useless data search process.

[0058] In some embodiments, in step S104, determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number corresponding to the pre-read data stored in the cache unit, includes: Determining a first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks; determining a second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and the number corresponding to the pre-read data stored in the cache unit; if the second logical block address range is greater than or equal to the first logical block address range, determining that the target data corresponding to the read command is stored in the cache unit.

[0059] Specifically, when a read command arrives, if it passes the sequential data read naming stream determination, it enters the pre-read hit determination process.

[0060] 1. Determine whether there is a sufficient amount of data in the cache unit. Since reading data from the flash memory unit takes a delay of dozens of microseconds, while transmitting data from the cache unit to the host only takes a few microseconds, in order to ensure continuous pre-read hits, the firmware needs to check the number of valid data in the cache unit. When the number of valid data is greater than a third threshold, proceed to the next step; otherwise, exit the pre-read process.

[0061] 2. Determine whether the LPA of the current read command is within the LPAs corresponding to the pre-read data. Compare the LPA of the current read command with the maximum LPA of the valid data in the cache. If the LPA of the current read command is greater than or equal to the maximum LPA of the valid data in the cache, there is no target data of the current read command in the cache unit, triggering a pre-read interrupt; if the LPA of the current read command is less than the maximum LPA of the valid data in the cache, the target data corresponding to the current read command may exist in the cache unit, and proceed to the next step.

[0062] 3. Locate the position of the target data corresponding to the read command in the cache unit. According to the LPA of each pre-read data saved, use the binary search method to find the position of the current read command LPA in the cache unit, and determine whether all the logical block addresses (LBAs) of the read command are hit. If all are hit, proceed to the next step; otherwise, consider the pre-read to fail and exit the pre-read process.

[0063] 4. Based on the position of the matching LBA in the cache unit and the PBA of each saved data, determine whether all the PBAs at the LBA hit positions match. If they match, determine that the pre-read is a hit, notify the host to fetch the corresponding part of the data in the cache unit, and clear the corresponding valid data bits to 0. If they do not match, determine that the hit fails and exit the pre-read process.

[0064] In this embodiment, if it is determined, based on the starting logical block address, the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out; in this way, the response to the read command can be quickly realized, the target data corresponding to the read command can be sent out, and the read latency of the solid-state drive can be reduced.

[0065] An embodiment of the present application provides a data processing device, which is applied to a solid-state drive. The solid-state drive includes flash memory units, multiple processors, and a cache unit, as Figure 6 shown. The device includes: An acquisition module 61, configured to acquire a read command; the read command includes a starting logical block address and the number of logical blocks.

[0066] A determination module 62, configured to, based on the starting logical block address, sequentially determine the continuity between the read command and the commands in a preset plurality of different-order data read command streams; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, increment the matching count of the target-order data read command stream by one.

[0067] A pre-read module 63, configured to, if the cumulative value of the matching count of the target-order data read command stream is greater than a first threshold, pre-read the data in the flash memory unit based on the starting logical block address and the number of logical blocks, and store the pre-read data in the cache unit, so that when the next read command is acquired, the data corresponding to the next read command can be found in the cache unit.

[0068] The data processing device provided by the embodiment of the present application obtains a read command through a processor; the read command includes a starting logical block address and the number of logical blocks; based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching compliance count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory unit and store the pre-read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash memory technology processes read commands through multiple processors, each processor can accurately identify whether the read command is a sequential data read command, and when it is recognized that the read command is a sequential data read command, trigger the start of the data pre-reading operation, so that the solid-state drive can identify multiple sequential data read command streams and perform data pre-reading through multiple processors, which can reduce the read latency of sequential data in the solid-state drive, improve the read performance of the solid-state drive, and improve the user experience.

[0069] In some embodiments, the determination module is configured to determine that the read command is continuous with the commands in the target sequential data read command stream if the ratio of the difference between the starting logical block addresses of the read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream is less than a second threshold.

[0070] In some embodiments, the pre-reading module is configured to determine the starting logical block address and the number of pre-read data based on the starting logical block address and the number of logical blocks; and pre-read the data in the flash memory unit based on the starting logical block address and the number of pre-read data.

[0071] In some embodiments, the pre-reading module is configured to perform a first weighting process on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; and perform a second weighting process on the number of logical blocks based on a second coefficient to obtain the number of pre-read data.

[0072] In some embodiments, the data processing device further includes: An update module, configured to save the starting logical block address, the number, and the physical address in the cache unit of the pre-read data; and update the maximum logical block address corresponding to the cache unit based on the starting logical block address of the pre-read data.

[0073] In some embodiments, the data processing device further includes: A data reading module, which is configured to determine that the target data corresponding to a read command is stored in the cache unit if, based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit, and to determine the physical address of the target data corresponding to the read command in the cache unit; and to read the target data from the cache unit based on the physical address of the target data in the cache unit and send it out.

[0074] In some embodiments, the data reading module is configured to determine that the target data corresponding to a read command is stored in the cache unit if the number of the pre-read data stored in the cache unit is greater than a second threshold and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit.

[0075] In some embodiments, the data reading module is configured to determine a first logical block address range corresponding to a read command based on the starting logical block address and the number of logical blocks; to determine a second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and the number of the pre-read data stored in the cache unit; and to determine that the target data corresponding to the read command is stored in the cache unit if the second logical block address range is greater than or equal to the first logical block address range.

[0076] According to an embodiment of the present application, the present application further provides a solid-state drive, including flash memory cells, a plurality of processors, and a cache unit. The processor is configured to obtain a read command; the read command includes a starting logical block address and the number of logical blocks; to sequentially determine the continuity of the read command with the commands in a plurality of preset data read command streams in different orders based on the starting logical block address; and to increment the matching count of the target sequential data read command stream by one when it is determined that the read command is continuous with the commands in the target sequential data read command stream; if the cumulative value of the matching count of the target sequential data read command stream is greater than a first threshold, pre-read the data in the flash memory cells based on the starting logical block address and the number of logical blocks, and store the pre-read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0077] Figure 7 A schematic block diagram of an exemplary solid-state drive that can be used to implement the embodiments of the present application is shown.

[0078] As Figure 7As shown, the solid-state drive includes a solid-state drive controller (SSD controller), flash memory cells 804, and a cache unit 808. The SSD controller includes a plurality of processors 801, which can perform various appropriate actions and processes according to a computer program stored in a static random access memory (SRAM) 802. The processors 801, a DRAM controller 803, and the static random access memory 802 are connected to each other through a bus 805. A host interface 806 and a flash memory interface 807 are also connected to the bus 805. The flash memory cells 804, such as a memory, are connected to the flash memory interface 807. The cache unit 808 can be a double data rate synchronous dynamic random access memory (DDR) and is connected to the DRAM controller 803.

[0079] The host interface 806 can serve as an input / output interface.

[0080] The processors 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processors 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processors 801 execute the various methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as the static random access memory 802. In some embodiments, part or all of the computer program can be loaded and / or installed on the solid-state drive. When the computer program is executed by the processors 801, one or more steps of the data processing method described above can be executed. Alternatively, in other embodiments, the processors 801 can be configured to execute the data processing method in any other appropriate manner (e.g., by means of firmware).

[0081] The various embodiments of the systems and technologies described above in this article can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs, the one or more computer programs can be executed and / or interpreted on a programmable system including at least one programmable processor, the programmable processor can be a special or general-purpose programmable processor, can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0082] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the machine, partially on the machine, executed partially on the machine and partially on a remote machine as an independent software package, or executed entirely on a remote machine or server.

[0083] Embodiments of the present application provide a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, such that the computer device executes the data processing method described above in the embodiments of the present application.

[0084] Embodiments of the present application provide a computer-readable storage medium storing executable instructions, where the executable instructions, when executed by a processor, will cause the processor to execute the data processing method provided in the embodiments of the present application.

[0085] In some embodiments, the computer-readable storage medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can be a machine-readable signal medium or a machine-readable storage medium. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of the computer-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0086] In some embodiments, the executable instructions can be in the form of a program, software, a software module, a script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as an independent program or being deployed as a module, a component, a subroutine, or other unit suitable for use in a computing environment.

[0087] As an example, executable instructions can, but do not necessarily have to, correspond to files in a file system, can be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or, stored in multiple cooperating files (e.g., files that store one or more modules, subroutines, or code portions).

[0088] As an example, executable instructions can be deployed to execute on one computing device, or on multiple computing devices at one location, or, on multiple computing devices distributed at multiple locations and interconnected by a communication network.

[0089] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0090] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0091] A computer system can include a client and a server. The client and the server are generally far apart from each other and typically interact through a communication network. The client - server relationship is created by computer programs that run on the respective computers and have a client - server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server that incorporates blockchain.

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in the present application can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions disclosed in the present application can be achieved, and no limitation is imposed herein.

[0093] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0094] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A data processing method, applied to a solid state drive, wherein the solid state drive comprises a flash memory unit, a plurality of processors and a cache unit, wherein: The method comprises: The processor obtains a read command; the read command includes a starting logical block address and a logical block quantity; Based on the starting logical block address, sequentially comparing the read command with commands in a plurality of preset different sequential data read command streams for continuity; and when it is determined that the read command is continuous with commands in a target sequential data read command stream, increasing the number of matching matches of the target sequential data read command stream by one; If the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, the data in the flash memory unit is pre-read based on the starting logical block address and the number of logical blocks, and the pre-read data is stored in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

2. The data processing method according to claim 1, characterized in that: Determining that the read command is continuous with commands in a target sequential data read command stream comprises: If the ratio of the starting logical block address difference between the read command and the command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than a second threshold, it is determined that the read command and the command in the target sequential data read command stream are continuous.

3. The data processing method according to claim 1, characterized in that: Pre-reading data in the flash memory unit based on the starting logical block address and the number of logical blocks includes: Based on the starting logical block address and the number of logical blocks, determining a starting logical block address of pre-read data and the number of pre-read data; The data in the flash memory unit is pre-read based on the starting logical block address of the pre-read data and the amount of the pre-read data.

4. The data processing method according to claim 3, characterized in that: Based on the starting logical block address and the number of logical blocks, determining the starting logical block address of pre-read data and the number of pre-read data includes: Based on the number of logical blocks and the first coefficient, performing a first weighted processing on the starting logical block address to obtain a starting logical block address of the pre-read data; Based on the second coefficient, a second weighting process is performed on the number of logic blocks to obtain the number of pre-read data.

5. The data processing method according to claim 3, characterized in that: Also includes: Saving the starting logical block address, quantity and physical address of the pre-read data in the cache unit; Based on the starting logical block address of the pre-read data, the maximum logical block address corresponding to the cache unit is updated.

6. The data processing method according to claim 1, characterized in that: Also includes: If it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number corresponding to the pre-read data stored in the cache unit, the physical address of the target data corresponding to the read command in the cache unit is determined; Based on the physical address of the target data in the cache unit, the target data is read from the cache unit and sent out.

7. The data processing method according to claim 6, characterized in that: Determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of pre-read data stored in the cache unit, includes: If the amount of pre-read data stored in the cache unit is greater than a second threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, based on the starting logical block address and the number of logical blocks, and the starting logical block address and number corresponding to the pre-read data stored in the cache unit, it is determined that the target data corresponding to the read command is stored in the cache unit.

8. The data processing method according to claim 6, characterized in that: Determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of pre-read data stored in the cache unit, includes: Determine a first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks; Determine a second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and the number of the pre-read data stored in the cache unit; If the second logical block address range is greater than or equal to the first logical block address range, it is determined that the target data corresponding to the read command is stored in the cache unit.

9. A data processing device, applied to a solid state hard disk, the solid state hard disk comprising a flash memory unit, a plurality of processors and a cache unit, characterized in that: The device comprises: An acquisition module, used to acquire a read command; the read command includes a starting logical block address and a logical block quantity; a determination module, configured to determine the continuity of the read command with commands in a plurality of preset different sequential data read command streams in sequence based on the starting logical block address; and when determining that the read command is continuous with commands in a target sequential data read command stream, increase the number of matching times of the target sequential data read command stream by one; A pre-read module is used to pre-read the data in the flash memory unit based on the starting logical block address and the number of logical blocks if the cumulative value of the matching times of the target sequential data read command stream is greater than a first threshold, and store the pre-read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found from the cache unit.

10. The data processing device according to claim 9, characterized in that: The determination module is used to determine that the read command and the command in the target sequential data read command stream are continuous if the ratio of the starting logical block address difference between the read command and the command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than a second threshold.

11. The data processing device according to claim 9, characterized in that: The pre-reading module is used to determine the starting logical block address of the pre-read data and the amount of the pre-read data based on the starting logical block address and the amount of the logical blocks; The data in the flash memory unit is pre-read based on the starting logical block address of the pre-read data and the amount of the pre-read data.

12. The data processing device according to claim 11, characterized in that: The pre-reading module is used for performing a first weighted processing on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; Based on the second coefficient, a second weighting process is performed on the number of logic blocks to obtain the number of pre-read data.

13. The data processing device according to claim 11, characterized in that: Also includes: An update module, used for storing the starting logical block address, quantity and physical address of the pre-read data in the cache unit; Based on the starting logical block address of the pre-read data, the maximum logical block address corresponding to the cache unit is updated.

14. The data processing device according to claim 9, characterized in that: Also includes: a data reading module, configured to determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of pre-read data stored in the cache unit, and to determine the physical address of the target data corresponding to the read command in the cache unit; Based on the physical address of the target data in the cache unit, the target data is read from the cache unit and sent out.

15. The data processing device according to claim 14, characterized in that: The data reading module is used to determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and number corresponding to the pre-read data stored in the cache unit if the number of pre-read data stored in the cache unit is greater than a third threshold and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address.

16. The data processing device according to claim 14, characterized in that: The data reading module is used to determine a first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks; Determine a second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and the number of the pre-read data stored in the cache unit; If the second logical block address range is greater than or equal to the first logical block address range, it is determined that the target data corresponding to the read command is stored in the cache unit.

17. A solid state hard disk, characterized in that: include: a flash memory unit, a plurality of processors and a cache unit; The processor is used to obtain a read command; the read command includes a starting logical block address and a logical block quantity; Based on the starting logical block address, sequentially comparing the read command with commands in a plurality of preset different sequential data read command streams for continuity; and when it is determined that the read command is continuous with commands in a target sequential data read command stream, increasing the number of matching matches of the target sequential data read command stream by one; If the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, the data in the flash memory unit is pre-read based on the starting logical block address and the number of logical blocks, and the pre-read data is stored in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the data processing method according to any one of claims 1 to 8.

19. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the data processing method according to any one of claims 1 to 8 is implemented.

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