PCIE interrupt affinity remapping method, system and device and storage medium

Abstract

The PCIE interrupt affinity remapping method provided by the invention comprises the following steps: creating a trap configuration, creating the trap configuration by a Hypervisor aiming at a register interception operation of a first interrupt affinity, starting a virtual machine through the Hypervisor, writing a register, configuring the first interrupt affinity, intercepting a register writing operation by the Hypervisor, and replacing virtual CPU ID information in the first interrupt affinity into physical CPU ID information. According to the method, the MSI / MSIX interrupt of the PCIE peripheral can be received by the virtual machine, the second interrupt affinity is generated, the second interrupt affinity is written into the hardware register by the Hypervisor, and when the CPU is virtualized, the virtual machine can also receive the MSI / MSIX interrupt of the PCIE peripheral under the condition that the virtual CPU and the virtual CPU are inconsistent.

Description

Technical Field

[0001] The present invention belongs to the field of embedded virtualization, and particularly relates to a PCIE interrupt affinity remapping method, system, device and storage medium. Background Art

[0002] In modern computing environments, virtualization technology has become an essential part of data centers and cloud computing platforms. The Hypervisor (Virtual Machine Monitor) is responsible for managing virtual machines (VMs) and providing an abstraction layer between the physical hardware and the virtual machines. With the development of virtualization technology, especially in high-performance and low-latency application scenarios, the access to hardware resources by virtual machines has become increasingly important. In this process, MSI (Message Signaled Interrupts) as a modern interrupt handling mechanism plays a crucial role. However, when a virtual machine in a virtualized environment needs to handle MSI, how to correctly configure the MSI affinity and its remapping problem has become a technical challenge.

[0003] MSI is a mechanism that notifies the processor through message passing rather than traditional electrical interrupt signals, and is widely used to support interrupt requests of high-performance devices. Different from the traditional interrupt handling method, MSI allows devices to trigger interrupts by directly sending memory write operations, thus reducing the complexity of the traditional interrupt controller and improving system performance. In a virtualized environment, each virtual machine is usually configured to access the hardware resources allocated by the virtualization platform. The interrupt signals of these resources also need to be virtualized and forwarded to the corresponding virtual machines. In the MSI mechanism, there is an affinity problem in the MSI interrupt handling of virtual machines.

[0004] To solve the MSI affinity configuration and remapping problems in a virtualized environment, modern Hypervisors have adopted some technical means, such as device passthrough (PCIPassthrough), interrupt affinity setting and optimization, etc.

[0005] If CPU virtualization is performed, there will be a situation where the physical CPU virtualization and the virtual CPU are inconsistent. At this time, if there is a PCI controller and its peripherals in the system, the virtual machine will use the virtual CPU number to set the MSI / MSIX interrupt affinity of the PCIE peripherals, which will cause the virtual machine to be unable to receive the MSI / MSIX interrupts of the PCIE peripherals.

[0006] This solution solves this problem by intercepting and remapping the MSI / MSIX affinity configuration of virtual machines in the hypervisor. Summary of the Invention

[0007] To solve the above technical problems, the present invention provides a method, system, device and storage medium for PCIE interrupt affinity remapping.

[0008] The present invention is achieved through the following technical solutions.

[0009] The PCIE interrupt affinity remapping method provided by the present invention includes the following steps:

[0010] Create a trap configuration. The Hypervisor creates a trap configuration for the register interception operation of the first interrupt affinity.

[0011] Start the virtual machine through the Hypervisor.

[0012] Write to the register to configure the first interrupt affinity.

[0013] The Hypervisor intercepts the write register operation and replaces the virtual CPU ID information in the first interrupt affinity with the physical CPU ID information to generate the second interrupt affinity.

[0014] The Hypervisor writes the second interrupt affinity to the hardware register.

[0015] Furthermore, both the generation methods of the first interrupt and the second interrupt are MSI or MSI-X.

[0016] Furthermore, the trap configuration includes the register address and register length of the first interrupt affinity. When performing the trap configuration, the Hypervisor performs read, write, execution, and cache attributes on the register of the first interrupt affinity.

[0017] Furthermore, configuring the first interrupt affinity includes CPU serial number information.

[0018] The present invention also provides a PCIE interrupt affinity remapping system, including a virtual machine, a Hypervisor, and hardware. The Hypervisor is provided with an init module and a trap module, and the Hypervisor communicates with the virtual machine and the hardware respectively.

[0019] Furthermore, creating the trap configuration occurs in the init module, and communication occurs between the init module and the trap module.

[0020] The present invention also provides a PCIE interrupt affinity remapping device, including a module for executing the method described in any one of the above, and characterized by including a processor and an interface circuit. The interface circuit is used to receive signals from other devices outside the device that executes the kernel state command and transmit them to the processor, or send signals from the processor to other devices outside the device that executes the kernel state command. The processor uses logic circuits or executes code instructions to implement the method described in any one of the above.

[0021] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method described in any one of the above is implemented.

[0022] The beneficial effect of the present invention is that when CPU virtualization occurs and there is a mismatch between physical CPU virtualization and virtual CPUs, virtual machines can also receive MSI / MSIX interrupts from PCIE peripherals. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic flowchart of the method of the present invention;

[0024] Figure 2 is a system connection relationship diagram of the present invention;

[0025] Figure 3 is a schematic flowchart of the method of an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The technical solution of the present invention will be further described below, but the scope of protection is not limited thereto.

[0027] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Embodiment

[0029] In this embodiment, based on the rockchip rk3568 rock3a single board, the rockchip rk3568 chip is an ARM architecture chip, and its interrupt controller is a GICV3 interrupt controller. The MSI / MSIX interrupts for PCIE peripherals will ultimately be converted into LPI interrupts and processed by the ITS module in the GICV3 interrupt controller.

[0030] In the scenario of the rock3a single board, the implementation method is as follows:

[0031] Step 1: The initialization module of the Hypervisor will establish trap configurations to intercept write operations to the ITS registers for the MSI / MSIX affinity of PCIE peripherals;

[0032] Step 2, the Hypervisor starts the virtual machine;

[0033] When the virtual machine starts, it will set the MSI / MSIX affinity information of the PCIE peripheral to the ITS register with the virtual CPU serial number information;

[0034] Step 4, the Hypervisor intercepts the write operation of the ITS register and changes the virtual CPU serial number information in the MSI / MSIX affinity of the PCIE peripheral to the physical CPU serial number information;

[0035] Step 5, the Hypervisor writes the modified MSI / MSIX affinity of the PCIE peripheral into the ITS register.

[0036] The above embodiments are the preferred solutions for the implementation of the present invention. It should be noted that any obvious replacement and minor changes are within the protection scope of the present invention without departing from the concept of the present invention.

Claims

1. PCIE interrupt affinity remapping method, characterized in that The following steps are involved: Create a trap configuration. The Hypervisor creates a trap configuration for the register interception operation of the first interrupt affinity. Start the virtual machine through the Hypervisor; Write register to configure the first interrupt affinity; The Hypervisor intercepts the register write operation and replaces the virtual CPUID information in the first interrupt affinity with the physical CPUID information to generate a second interrupt affinity; The hypervisor writes the second interrupt affinity to the hardware register.

2. The method according to claim 1, characterized in that: The first interrupt and the second interrupt are both generated in MSI or MSI-X.

3. The method according to claim 1, characterized in that: The trap configuration includes a register address of the first interrupt affinity and a register length of the first interrupt affinity. When performing the trap configuration, the Hypervisor reads, writes, executes, and caches the register of the first interrupt affinity.

4. The method according to claim 1, characterized in that: Configuring the first interrupt affinity includes CPU sequence number information.

5. PCIE interrupt affinity remapping system, characterized by: It includes virtual machines, Hypervisor, and hardware. The Hypervisor is equipped with init module and trap module. The Hypervisor communicates with the virtual machines and hardware respectively.

6. The system according to claim 1, characterized in that: Creating the trap configuration occurs in the init module, and the init module communicates with the trap module.

7. A PCIE interrupt affinity remapping device, comprising a module for executing the method according to any one of claims 1 to 4, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other devices other than the device for executing kernel mode commands and transmit them to the processor or send signals from the processor to other devices other than the device for executing kernel mode commands, and the processor is used to implement the method as described in any one of claims 1 to 4 through logic circuits or execution code instructions.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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