Power grid dispatching instruction sequence anomaly detection method and system

Abstract

The invention provides a power grid dispatching instruction sequence anomaly detection method and system, and relates to the technical field of data processing. The method comprises the following steps: firstly, determining an interference scheduling instruction sequence corresponding to a to-be-detected scheduling instruction sequence; secondly, potential feature mining is carried out on a to-be-detected scheduling instruction sequence, and a corresponding to-be-detected instruction vector is output; then, according to a to-be-detected instruction vector, performing interference removal operation on the interference scheduling instruction sequence, and outputting a corresponding interference removal instruction sequence; and finally, according to a sequence matching parameter between the to-be-detected scheduling instruction sequence and the interference removal instruction sequence, outputting abnormal detection data corresponding to the to-be-detected scheduling instruction sequence. On the basis of the content, the problem that in the prior art, the reliability of power grid dispatching instruction sequence anomaly detection is relatively low can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular, to a method and system for detecting anomalies in power grid dispatching instruction sequences. Background Art

[0002] Power grid dispatching instruction sequences are instructions generated during the dispatching process of a power system, usually including load dispatching, equipment start / stop, power regulation, etc. These instructions may be affected by multiple factors, such as equipment failures, network problems, or human operation errors. Therefore, identifying abnormal dispatching instructions is crucial for ensuring the safety and stability of the power grid. However, in the prior art, generally, the power grid dispatching instruction sequence is compared and analyzed with a preset sequence. For example, when there is an anomaly in the preset sequence, if the power grid dispatching instruction sequence is consistent with the preset sequence, it can be considered that the power grid dispatching instruction sequence also has an anomaly; conversely, if the power grid dispatching instruction sequence is inconsistent with the preset sequence, it can be considered that the power grid dispatching instruction sequence does not have an anomaly. This simple comparison and analysis are difficult to effectively cover the anomalies in the power grid dispatching instruction sequence, resulting in relatively low reliability of anomaly analysis. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method and system for detecting anomalies in power grid dispatching instruction sequences to improve the relatively low reliability of anomaly detection in power grid dispatching instruction sequences existing in the prior art.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions: A method for detecting anomalies in a power grid dispatching instruction sequence, comprising: Determining an interference dispatching instruction sequence corresponding to the to-be-detected dispatching instruction sequence, wherein the to-be-detected dispatching instruction sequence includes a plurality of to-be-detected power grid dispatching instructions, and the interference dispatching instruction sequence is formed by applying interference information to the to-be-detected dispatching instruction sequence, and the way of applying interference information includes at least one of adjusting the instruction order, deleting instructions, adding instructions, and replacing instructions for the plurality of to-be-detected power grid dispatching instructions; Mining potential features of the to-be-detected dispatching instruction sequence and outputting a corresponding to-be-detected instruction vector, wherein the to-be-detected instruction vector is used to reflect the potential semantic features of the plurality of to-be-detected power grid dispatching instructions in the to-be-detected dispatching instruction sequence; Based on the to-be-detected instruction vector, performing an interference removal operation on the interference dispatching instruction sequence and outputting a corresponding interference-removed instruction sequence; Output the anomaly detection data corresponding to the to-be-detected scheduling instruction sequence according to the sequence matching parameter between the to-be-detected scheduling instruction sequence and the interference removal instruction sequence, where the anomaly detection data is used to reflect whether there is an abnormal to-be-detected power grid scheduling instruction in the to-be-detected scheduling instruction sequence.

[0005] In a preferred selection of the present invention, in the above method for anomaly detection of power grid scheduling instruction sequences, the step of performing potential feature mining on the to-be-detected scheduling instruction sequence and outputting the corresponding to-be-detected instruction vector includes: Perform an embedding operation on the to-be-detected scheduling instruction sequence, output the corresponding scheduling instruction embedding vector, and perform a vector compression operation on the scheduling instruction embedding vector to output the corresponding scheduling instruction compression vector; Perform multi-level potential feature mining on the scheduling instruction compression vector to output a corresponding plurality of scheduling instruction potential vectors, where the a-th scheduling instruction potential vector is formed by performing potential feature mining on the b-th scheduling instruction potential vector, and the plurality of scheduling instruction potential vectors respectively correspond to different potential feature levels, a = b + 1, and b is greater than or equal to 1; Perform a vector expansion operation on at least one of the plurality of scheduling instruction potential vectors to output the corresponding at least one scheduling instruction expansion vector, where the vector expansion operation and the vector compression operation are two mutually inverse operations; Determine the corresponding to-be-detected instruction vector based on the at least one scheduling instruction expansion vector.

[0006] In a preferred selection of the present invention, in the above method for anomaly detection of power grid scheduling instruction sequences, the step of performing a vector expansion operation on at least one of the plurality of scheduling instruction potential vectors to output the corresponding at least one scheduling instruction expansion vector includes: Perform a vector aggregation operation on at least two of the plurality of scheduling instruction potential vectors to output the corresponding first scheduling instruction aggregation vector; Perform a vector expansion operation on the first scheduling instruction aggregation vector to output the corresponding scheduling instruction expansion vector.

[0007] In a preferred selection of the present invention, in the above method for anomaly detection of power grid scheduling instruction sequences, the at least two scheduling instruction potential vectors include the x-th scheduling instruction potential vector and the y-th scheduling instruction potential vector, the x-th scheduling instruction potential vector includes z first local potential vectors, and the y-th scheduling instruction potential vector includes z second local potential vectors; The step of performing a vector aggregation operation on at least two of the multiple scheduling instruction latent vectors and outputting a corresponding first scheduling instruction aggregation vector includes: Performing a convolution operation on each of the z second local latent vectors respectively to output corresponding z second local convolution vectors; Performing a vector aggregation operation on the z second local convolution vectors and the w-th first local latent vector to output a w-th first local aggregation vector corresponding to the w-th first local latent vector, where the w-th first local latent vector belongs to one of the z first local latent vectors; After obtaining the z first local aggregation vectors corresponding to the z first local latent vectors, determining a corresponding first scheduling instruction aggregation vector according to the z first local aggregation vectors. For each of the z first local latent vectors, concatenating the first local latent vector with the z second local convolution vectors in sequence to form a first local aggregation vector corresponding to the first local latent vector.

[0008] In a preferred option of the present invention, in the above method for detecting anomalies in a power grid scheduling instruction sequence, the step of performing an interference removal operation on the interference scheduling instruction sequence according to the instruction vector to be detected and outputting a corresponding interference removal instruction sequence includes: Performing an embedding operation on the interference scheduling instruction sequence to output a corresponding interference instruction embedding vector, and performing a vector compression operation on the interference instruction embedding vector to output a corresponding interference instruction compression vector; Performing multi-level latent feature mining on the interference instruction compression vector to output corresponding multiple interference instruction latent vectors; Performing an interference removal operation on the c-th interference instruction latent vector among the multiple interference instruction latent vectors according to the scheduling instruction expansion vector and the scheduling instruction latent vector to output a corresponding interference removal instruction sequence.

[0009] In a preferred option of the present invention, in the above method for detecting anomalies in a power grid scheduling instruction sequence, the step of performing multi-level latent feature mining on the scheduling instruction compression vector to output corresponding multiple scheduling instruction latent vectors includes: Performing a vector aggregation operation on the d-th interference instruction latent vector and the scheduling instruction compression vector to output a corresponding second scheduling instruction aggregation vector, where d is less than c; Performing multi-level latent feature mining on the second scheduling instruction aggregation vector to output corresponding multiple scheduling instruction latent vectors.

[0010] In a preferred embodiment of the present invention, in the above-mentioned abnormal detection method for the power grid dispatching instruction sequence, the step of performing interference removal operation on the c-th interference instruction latent vector among the multiple interference instruction latent vectors according to the dispatching instruction expansion vector and the dispatching instruction latent vector, and outputting the corresponding interference removal instruction sequence includes: Performing interference restoration operation on the c-th interference instruction latent vector according to the dispatching instruction expansion vector and the dispatching instruction latent vector, and outputting the corresponding predicted interference information, where the predicted interference information belongs to the predicted data of the applied interference information; Performing interference removal operation on the interference dispatching instruction sequence according to the predicted interference information, and outputting the corresponding interference removal instruction sequence.

[0011] In a preferred embodiment of the present invention, in the above-mentioned abnormal detection method for the power grid dispatching instruction sequence, the step of performing interference restoration operation on the c-th interference instruction latent vector according to the dispatching instruction expansion vector and the dispatching instruction latent vector, and outputting the corresponding predicted interference information includes: When the c-th interference instruction latent vector belongs to the last interference instruction latent vector, semantically associating and aggregating the c-th interference instruction latent vector and the last dispatching instruction latent vector to form the corresponding first first associated aggregation vector; Semantically associating and aggregating the first first associated aggregation vector and the dispatching instruction expansion vector to form the first second associated aggregation vector; Semantically associating and aggregating the c-th interference instruction latent vector and the first second associated aggregation vector to form the corresponding second first associated aggregation vector; Semantically associating and aggregating the second first associated aggregation vector and the dispatching instruction expansion vector to form the second second associated aggregation vector; Determining the last second associated aggregation vector based on the second second associated aggregation vector, and performing interference information prediction operation based on the last second associated aggregation vector, and outputting the corresponding predicted interference information.

[0012] In a preferred embodiment of the present invention, in the above-mentioned abnormal detection method for the power grid dispatching instruction sequence, the abnormal detection method for the power grid dispatching instruction sequence further includes: Determining the sample interference dispatching instruction sequence corresponding to the sample dispatching instruction sequence, where the sample dispatching instruction sequence includes multiple sample power grid dispatching instructions, and the sample interference dispatching instruction sequence is formed by applying interference information to the sample dispatching instruction sequence, and the way of applying interference information includes at least one of adjusting the instruction order, deleting instructions, adding instructions, and replacing instructions of the multiple sample power grid dispatching instructions; Through a candidate anomaly detection model, potential features of the sample scheduling instruction sequence are mined, and a corresponding sample instruction vector is output, where the sample instruction vector is used to reflect potential semantic features of the multiple sample power grid scheduling instructions in the sample scheduling instruction sequence; Through the candidate anomaly detection model, according to the sample instruction vector, an interference removal operation is performed on the sample interference scheduling instruction sequence, and a corresponding sample interference removal instruction sequence is output; According to the sequence matching parameter between the sample scheduling instruction sequence and the sample interference removal instruction sequence, anomaly detection data corresponding to the sample scheduling instruction sequence is output, and based on the error between the anomaly detection data and the anomaly label data corresponding to the sample scheduling instruction sequence, the candidate anomaly detection model is updated to form a target anomaly detection model.

[0013] The present invention also provides a power grid scheduling instruction sequence anomaly detection system, including: A memory for storing a computer program; A processor connected to the memory for executing the computer program stored in the memory to implement the above-mentioned power grid scheduling instruction sequence anomaly detection method.

[0014] A power grid scheduling instruction sequence anomaly detection method and system provided by the present invention, first, determine an interference scheduling instruction sequence corresponding to a scheduling instruction sequence to be detected; second, mine potential features of the scheduling instruction sequence to be detected and output a corresponding instruction vector to be detected; then, according to the instruction vector to be detected, perform an interference removal operation on the interference scheduling instruction sequence and output a corresponding interference removal instruction sequence; finally, according to the sequence matching parameter between the scheduling instruction sequence to be detected and the interference removal instruction sequence, output anomaly detection data corresponding to the scheduling instruction sequence to be detected. Based on the above content, by mining potential features of the scheduling instruction sequence to be detected to obtain the instruction vector to be detected, the instruction vector to be detected guides the interference scheduling instruction sequence to remove interference information, ensuring that the power grid scheduling instructions in the interference removal instruction sequence after removing interference information are consistent with the power grid scheduling instructions in the scheduling instruction sequence to be detected, and then comparing the sequence matching parameter to determine the anomaly situation of the power grid scheduling instructions in the scheduling instruction sequence to be detected, which can improve the reliability of power grid scheduling instruction anomaly detection (fully utilizing the potential semantic features of power grid scheduling instructions). Therefore, it can improve the problem that the reliability of power grid scheduling instruction sequence anomaly detection in the prior art is relatively low. Description of the Drawings

[0015] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and cooperates with the attached drawings for detailed description as follows.

[0016] Figure 1 It is a structural block diagram of an abnormal detection system for power grid dispatching instruction sequences provided by an embodiment of the present invention.

[0017] Figure 2 It is a schematic flowchart of a method for detecting abnormal power grid dispatching instruction sequences provided by an embodiment of the present invention.

[0018] Figure 3 It is a schematic flowchart of an interference removal operation provided by an embodiment of the present invention.

[0019] Figure 4 It is a partial schematic flowchart of an interference removal operation provided by an embodiment of the present invention. Detailed implementation manners

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings below is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0022] As Figure 1 shown, an embodiment of the present invention provides an abnormal detection system for power grid dispatching instruction sequences. Among them, the abnormal detection system for power grid dispatching instruction sequences may include a memory and a processor.

[0023] Specifically, the memory and the processor are electrically connected directly or indirectly to realize data transmission or interaction. For example, the memory and the processor can be electrically connected through one or more communication buses or signal lines. The abnormal detection device 100 for power grid dispatching instruction sequences includes at least one software function module stored in the memory in the form of software or firmware (firmware). The processor is used to execute the executable computer program stored in the memory to implement the method for detecting abnormal power grid dispatching instruction sequences provided by the embodiments of the present invention.

[0024] Optionally, the memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. And, the processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a System on Chip (SoC), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0025] It can be understood that Figure 1 The structure shown is only for illustration, and the power grid dispatching instruction sequence anomaly detection system may also include more or fewer components than those shown Figure 1 in the figure, or have a different configuration from that shown Figure 1 in the figure. For example, it may also include a communication unit for information interaction with other devices.

[0026] In combination with Figure 2 , the embodiment of the present invention also provides a power grid dispatching instruction sequence anomaly detection method applicable to the above power grid dispatching instruction sequence anomaly detection system. Among them, the method steps defined by the processes related to the power grid dispatching instruction sequence anomaly detection method can be implemented by the power grid dispatching instruction sequence anomaly detection system. The following will elaborate on Figure 2 the specific process shown in detail.

[0027] Step S110, determine the interference dispatching instruction sequence corresponding to the dispatching instruction sequence to be detected.

[0028] In an embodiment of the present invention, the power grid dispatching instruction sequence anomaly detection system can determine an interfering dispatching instruction sequence corresponding to the to-be-detected dispatching instruction sequence. Among them, the to-be-detected dispatching instruction sequence includes a plurality of to-be-detected power grid dispatching instructions (such as generator start-stop instructions, substation load adjustment instructions, line switching instructions, etc.), and the interfering dispatching instruction sequence is formed by applying interference information to the to-be-detected dispatching instruction sequence. The ways of applying interference information include at least one of adjusting the instruction order, deleting instructions, adding instructions, and replacing instructions for the plurality of to-be-detected power grid dispatching instructions. The specific content of the to-be-detected power grid dispatching instruction may include: Instruction timestamp, such as: February 17, 2025, 14:30:15; Execution status, such as: Execution success: All relevant devices operate normally according to the instruction, or Execution failure: A certain device fails or cannot operate according to the instruction; Dispatching content, such as: Generator start-stop instruction, February 17, 2025 14:30:15, start "Generator Set No. 3 in the West Area", load is 50MW.

[0029] Step S120, perform potential feature mining on the to-be-detected dispatching instruction sequence, and output a corresponding to-be-detected instruction vector.

[0030] In an embodiment of the present invention, after determining the to-be-detected dispatching instruction sequence, the power grid dispatching instruction sequence anomaly detection system can perform potential feature mining on the to-be-detected dispatching instruction sequence and output a corresponding to-be-detected instruction vector. Among them, the to-be-detected instruction vector is used to reflect the potential semantic features of the plurality of to-be-detected power grid dispatching instructions in the to-be-detected dispatching instruction sequence, that is, to mine the semantic information therein and represent it in the form of a vector.

[0031] Step S130, according to the to-be-detected instruction vector, perform interference removal operation on the interfering dispatching instruction sequence, and output a corresponding interference-removed instruction sequence.

[0032] In an embodiment of the present invention, after outputting the to-be-detected instruction vector, the power grid dispatching instruction sequence anomaly detection system can perform interference removal operation on the interfering dispatching instruction sequence according to the to-be-detected instruction vector, and output a corresponding interference-removed instruction sequence. That is, using the to-be-detected instruction vector as a guide, remove the interference information applied in the interfering dispatching instruction sequence, so as to obtain an interference-removed instruction sequence after removing the interference information.

[0033] Step S140, according to the sequence matching parameter between the to-be-detected dispatching instruction sequence and the interference-removed instruction sequence, output the anomaly detection data corresponding to the to-be-detected dispatching instruction sequence.

[0034] In an embodiment of the present invention, after outputting the interference removal instruction sequence, the power grid dispatching instruction sequence anomaly detection system may output anomaly detection data corresponding to the to-be-detected dispatching instruction sequence according to the sequence matching parameter between the to-be-detected dispatching instruction sequence and the interference removal instruction sequence. Wherein, the anomaly detection data is used to reflect whether there is an abnormal to-be-detected power grid dispatching instruction in the to-be-detected dispatching instruction sequence. Exemplarily, the above steps S120-S130 may be implemented based on a corresponding neural network model (such as the target anomaly detection model described later). In this way, the neural network model can learn the semantic information of the normal instruction sequence during the training process. Thus, during the application process, the interference information imposed in the interference dispatching instruction sequence can be removed to obtain a normal sequence, that is, the interference removal instruction sequence. Then, the interference removal instruction sequence can be matched and analyzed with the to-be-detected dispatching instruction sequence to determine whether there is an anomaly. The specific principle is that if there is an anomaly in the to-be-detected dispatching instruction sequence, the to-be-detected instruction vector carries the semantic information of the abnormal instruction, and it is difficult to effectively guide the interference removal operation of the interference dispatching instruction sequence, making it difficult to effectively remove the interference information in the obtained interference removal instruction sequence. Therefore, it is difficult to match with the to-be-detected dispatching instruction sequence, such as the sequence matching parameter being less than a preset value (which can be configured according to actual needs, such as 0.8, 0.9, 1, etc.). On the contrary, if there is no anomaly in the to-be-detected dispatching instruction sequence, the to-be-detected instruction vector does not carry the semantic information of the abnormal instruction, and it can effectively guide the interference removal operation of the interference dispatching instruction sequence, making the interference information in the obtained interference removal instruction sequence can be effectively removed. Therefore, it can match with the to-be-detected dispatching instruction sequence, such as the sequence matching parameter being greater than or equal to the preset value. In addition, the specific determination method of the sequence matching parameter between the to-be-detected dispatching instruction sequence and the interference removal instruction sequence is not limited. For example, traditional text semantic similarity can be used, or the to-be-detected dispatching instruction sequence and the interference removal instruction sequence can be respectively embedded to obtain corresponding embedding vectors, and then the similarity between the embedding vectors, such as cosine similarity, etc., can be calculated as the corresponding sequence matching parameter.

[0035] Based on the above, by means of mining potential features of the scheduling instruction sequence to be detected to obtain the instruction vector to be detected, the instruction vector to be detected is used to guide the interference scheduling instruction sequence to remove interference information, ensuring that the power grid scheduling instructions in the interference removal instruction sequence after removing the interference information are consistent with the power grid scheduling instructions in the scheduling instruction sequence to be detected. Furthermore, by comparing the sequence matching parameters to determine the abnormal conditions of the power grid scheduling instructions in the scheduling instruction sequence to be detected, the reliability of the abnormal detection of the power grid scheduling instructions can be improved (the potential semantic features of the power grid scheduling instructions can be fully utilized, making the reliability of subsequent processing higher). Therefore, the problem of relatively low reliability in the abnormal detection of the power grid scheduling instruction sequence existing in the prior art can be improved.

[0036] Further, in the above step S120, the specific manner of mining potential features of the scheduling instruction sequence to be detected is not limited. For example, in a schematic implementation manner, in order to improve the reliability of potential feature mining and make the semantic information represented by the mined instruction vector to be detected more abundant, the above step S120 may further include step S121, step S122, step S123, and step S124. The specific step contents are as follows (in combination with Figure 3 shown).

[0037] Step S121: Perform an embedding operation on the scheduling instruction sequence to be detected, output the corresponding scheduling instruction embedding vector, and perform a vector compression operation on the scheduling instruction embedding vector to output the corresponding scheduling instruction compression vector.

[0038] In an embodiment of the present invention, the to-be-detected scheduling instruction sequence can be subjected to an embedding operation to output a corresponding scheduling instruction embedding vector, and the scheduling instruction embedding vector can be subjected to a vector compression operation to output a corresponding scheduling instruction compressed vector. Among them, the embedding operation can be implemented by a word embedding model (such as Word2Vec), etc. The vector compression operation can refer to a pooling operation (which can be implemented by a pooling network), etc., so that the large-sized scheduling instruction embedding vector is compressed into a small-sized scheduling instruction compressed vector to reduce the data volume for subsequent processing. For example, for a part of the to-be-detected scheduling instruction sequence, such as "Enable Generator Set No. 3 in the West Area", after performing a word segmentation and embedding operation, the embedding vectors corresponding to each word can be obtained, such as: Enable: [0.12, -0.43, 0.56, -0.89, 0.33, 0.17, 0.47, -0.11, 0.22, 0.90,...]; West Area: [-0.28, 0.15, 0.38, -0.51, 0.42, -0.77, 0.59, 0.61, -0.16, 0.08,...]; Generate Electricity: [0.76, -0.34, 0.61, 0.13, -0.21, 0.98, -0.53, 0.62, -0.07, -0.44,...]; Generator Set: [-0.01, 0.75, 0.55, 0.26, -0.86, 0.45, 0.20, -0.14, 0.31, -0.17,...]; No. 3: [0.03, -0.82, 0.54, 0.27, -0.46, 0.88, 0.19, -0.65, 0.61, -0.11,...].

[0039] Step S122: Perform multi-level latent feature mining on the scheduling instruction compressed vector to output a corresponding plurality of scheduling instruction latent vectors.

[0040] In an embodiment of the present invention, after obtaining the scheduling instruction compression vector, the scheduling instruction compression vector can be subjected to multi-level latent feature mining to output a corresponding plurality of scheduling instruction latent vectors. Among them, the a-th scheduling instruction latent vector is formed by performing latent feature mining on the b-th scheduling instruction latent vector. The plurality of scheduling instruction latent vectors respectively correspond to different latent feature levels, a = b + 1, and b is greater than or equal to 1. That is to say, the latter scheduling instruction latent vector is formed by performing latent feature mining on the previous scheduling instruction latent vector. In addition, as the latent feature level increases, the size of the corresponding scheduling instruction latent vector can gradually decrease. For example, the size of the first scheduling instruction latent vector can be 128*128, the size of the second scheduling instruction latent vector can be 64*64, the size of the third scheduling instruction latent vector can be 32*32, and the size of the fourth scheduling instruction latent vector can be 16*16. Based on this, various levels of semantic information in the scheduling instruction compression vector can be fully captured, and as the depth increases, some high-level abstract semantic features can be mined out.

[0041] Step S123: Perform a vector expansion operation on at least one scheduling instruction latent vector among the plurality of scheduling instruction latent vectors, and output a corresponding at least one scheduling instruction expansion vector.

[0042] In an embodiment of the present invention, after obtaining the plurality of scheduling instruction latent vectors, at least one scheduling instruction latent vector among the plurality of scheduling instruction latent vectors can be subjected to a vector expansion operation to output a corresponding at least one scheduling instruction expansion vector. Among them, the vector expansion operation and the vector compression operation are two mutually inverse operations. For example, through the vector expansion operation, the size of the scheduling instruction expansion vector can be made equal to the size of the above-mentioned scheduling instruction embedding vector.

[0043] Step S124: Determine a corresponding instruction vector to be detected based on the at least one scheduling instruction expansion vector.

[0044] In an embodiment of the present invention, after obtaining the at least one scheduling instruction expansion vector, a corresponding instruction vector to be detected can be determined based on the at least one scheduling instruction expansion vector. For example, any one scheduling instruction expansion vector can be determined as the corresponding instruction vector to be detected; or, a plurality of scheduling instruction expansion vectors can be added together and then normalized to obtain the corresponding instruction vector to be detected.

[0045] Further, in the above step S123, the specific manner of performing the vector expansion operation on at least one of the plurality of scheduling instruction latent vectors is not limited. For example, in a schematic embodiment, in order to make the semantic information of the obtained scheduling instruction expansion vector richer during the implementation of the vector expansion operation, the above step S123 may include step S123a and step S123b, and the specific step content is as follows.

[0046] Step S123a: Perform a vector aggregation operation on at least two of the plurality of scheduling instruction latent vectors, and output a corresponding first scheduling instruction aggregation vector.

[0047] In the embodiment of the present invention, a vector aggregation operation may be performed on at least two of the plurality of scheduling instruction latent vectors, and a corresponding first scheduling instruction aggregation vector is output. In this way, the first scheduling instruction aggregation vector can represent the semantic information in at least two scheduling instruction latent vectors, that is, represent two different levels of semantic features.

[0048] Step S123b: Perform a vector expansion operation on the first scheduling instruction aggregation vector, and output a corresponding scheduling instruction expansion vector.

[0049] In the embodiment of the present invention, after obtaining the first scheduling instruction aggregation vector, a vector expansion operation may be performed on the first scheduling instruction aggregation vector to output a corresponding scheduling instruction expansion vector. For example, interpolation may be performed on the first scheduling instruction aggregation vector to obtain a scheduling instruction expansion vector with the same size as the above scheduling instruction embedding vector.

[0050] Further, in the above step S123a, the specific manner of performing vector aggregation operation on at least two of the plurality of scheduling instruction latent vectors is not limited. For example, in a schematic implementation manner, in order to improve the accuracy of the vector aggregation operation and make the semantic representation accuracy of the obtained first scheduling instruction aggregation vector higher, and the at least two scheduling instruction latent vectors include the x-th scheduling instruction latent vector and the y-th scheduling instruction latent vector (which can be two scheduling instruction latent vectors adjacent at the latent feature level or two scheduling instruction latent vectors not adjacent at the latent feature level, such as the first scheduling instruction latent vector and the last scheduling instruction latent vector). The x-th scheduling instruction latent vector includes z first local latent vectors (the value of z can be formed during training. In this way, the scheduling instruction latent vector can be equally divided based on z to obtain z first local latent vectors), and the y-th scheduling instruction latent vector includes z second local latent vectors (formed in the same way as the previous one). Based on this, the above step S123a may include the following implementable content: First, convolution operations can be respectively performed on the z second local latent vectors to output corresponding z second local convolution vectors; schematically, it can be implemented through a convolution network, and the obtained z second local convolution vectors have the same size as the first local latent vectors; Second, a vector aggregation operation is performed on the z second local convolution vectors and the w-th first local latent vector to output the w-th first local aggregation vector corresponding to the w-th first local latent vector, where the w-th first local latent vector belongs to one of the z first local latent vectors. In this way, the first local aggregation vector corresponding to each first local latent vector can be obtained; Third, after obtaining the z first local aggregation vectors corresponding to the z first local latent vectors, based on the z first local aggregation vectors, the corresponding first scheduling instruction aggregation vector is determined. For each first local latent vector among the z first local latent vectors, the first local latent vector is sequentially concatenated with the z second local convolution vectors to form the first local aggregation vector corresponding to the first local latent vector. For example, the first local latent vector and the first second local convolution vector are concatenated to obtain the first concatenated vector, and then the first concatenated vector and the second local convolution vector are concatenated to obtain the second concatenated vector. In this way, by processing sequentially, the first scheduling instruction aggregation vector can be obtained.

[0051] Further, in the above step S122, the specific manner of performing multi-level latent feature mining on the scheduling instruction compression vector is not limited. For example, in a schematic implementation manner, during the process of performing multi-level latent feature mining on the scheduling instruction compression vector, semantic information in the interference scheduling instruction sequence can also be fused. The specific manner of fusion is not limited. For example, in an exemplary implementation manner, when performing interference removal operation on the interference scheduling instruction sequence, multi-level latent feature mining is also performed. In this way, on the one hand, based on the semantic vector corresponding to the latent feature mining in the previous level, the scheduling instruction compression vector can be subjected to multi-level latent feature mining; on the other hand, based on the mined scheduling instruction latent vector, interference removal operation can be performed on the semantic vector corresponding to the latent feature mining in the subsequent level.

[0052] Based on this, on the first aspect, the above step S130 can further include step S131, step S132, and step S133. The specific step contents are as follows (in combination with Figure 3 shown).

[0053] Step S131, perform an embedding operation on the interference scheduling instruction sequence, output the corresponding interference instruction embedding vector, and perform a vector compression operation on the interference instruction embedding vector to output the corresponding interference instruction compression vector.

[0054] In the embodiment of the present invention, the interference scheduling instruction sequence can be subjected to an embedding operation to output the corresponding interference instruction embedding vector, and a vector compression operation is performed on the interference instruction embedding vector to output the corresponding interference instruction compression vector. Schematically, the embedding operation can be performed through a corresponding word embedding model. In addition, the vector compression operation can refer to a pooling operation (which can be implemented through a pooling network), etc., so that the large-size interference instruction embedding vector is compressed into a small-size interference instruction compression vector to reduce the data volume for subsequent processing.

[0055] Step S132, perform multi-level latent feature mining on the interference instruction compression vector to output the corresponding multiple interference instruction latent vectors.

[0056] In an embodiment of the present invention, after obtaining the interference instruction compression vector, the interference instruction compression vector can be subjected to multi-level latent feature mining to output a corresponding plurality of interference instruction latent vectors, such as the first interference instruction latent vector, the second interference instruction latent vector, the third interference instruction latent vector, and the fourth interference instruction latent vector, etc. Among them, the a-th interference instruction latent vector is formed by performing latent feature mining on the b-th interference instruction latent vector. The plurality of interference instruction latent vectors respectively correspond to different latent feature levels, a = b + 1, and b is greater than or equal to 1. That is to say, the latter interference instruction latent vector is formed by performing latent feature mining on the previous interference instruction latent vector. In addition, as the latent feature level increases, the size of the corresponding interference instruction latent vector can gradually decrease. For example, the size of the first interference instruction latent vector can be 128*128, the size of the second interference instruction latent vector can be 64*64, the size of the third interference instruction latent vector can be 32*32, and the size of the fourth interference instruction latent vector can be 16*16. Based on this, various levels of semantic information in the interference instruction compression vector can be fully captured, and as the depth increases, some high-level abstract semantic features can be mined. For example, the specific manner of latent feature mining can include self-attention processing, convolutional processing, pooling processing, and activation processing. That is to say, the interference instruction compression vector can be subjected to self-attention processing to obtain a corresponding self-attention vector, so that the important information in the interference instruction compression vector is mined. Then, the self-attention vector is subjected to convolutional processing to obtain a corresponding convolutional vector, so that some high-level and abstract features are mined. Then, the convolutional vector is subjected to pooling processing to obtain a corresponding pooling vector, so that important semantic features are maintained while reducing the vector size. Finally, the pooling vector is subjected to activation processing, and non-linear relationships can be mined. In this way, the reliability of multi-level latent feature mining can be fully improved.

[0057] Step S133, according to the scheduling instruction expansion vector and the scheduling instruction latent vector, perform an interference removal operation on the c-th interference instruction latent vector among the plurality of interference instruction latent vectors, and output a corresponding interference removal instruction sequence.

[0058] In an embodiment of the present invention, after obtaining the plurality of interference instruction latent vectors, according to the scheduling instruction expansion vector and the scheduling instruction latent vector, an interference removal operation can be performed on the c-th interference instruction latent vector among the plurality of interference instruction latent vectors, and a corresponding interference removal instruction sequence is output. That is, according to the semantic information in the scheduling instruction sequence to be detected, the interference information imposed on the interference scheduling instruction sequence is removed, so as to obtain an interference removal instruction sequence.

[0059] Based on this, in the second aspect, in the above step S122, the specific method for multi-level latent feature mining of the scheduling instruction compression vector can be as follows (in combination with Figure 4 ) In the first step, a vector aggregation operation can be performed on the d-th interference instruction latent vector and the scheduling instruction compression vector to output a corresponding second scheduling instruction aggregation vector, where d is less than c; illustratively, considering that the scheduling instruction compression vector has not undergone multi-level latent feature mining, the semantic information it has belongs to shallow semantic information. Thus, to avoid semantic information matching problems in the vector aggregation operation, the d-th interference instruction latent vector can refer to the first interference instruction latent vector, that is, a vector aggregation operation is performed on the first interference instruction latent vector and the scheduling instruction compression vector. For example, the dot product between the first interference instruction latent vector and the transposed vector of the scheduling instruction compression vector can be calculated to obtain a corresponding dot product parameter distribution. In this way, the association relationship between the first interference instruction latent vector and the scheduling instruction compression vector can be characterized by this dot product parameter distribution. Then, a weighted sum calculation can be performed on the scheduling instruction compression vector based on this dot product parameter distribution to obtain the second scheduling instruction aggregation vector. In this way, important semantic information related to the first interference instruction latent vector can be mined from the scheduling instruction compression vector, that is, semantic aggregation between vectors is achieved. In the second step, the second scheduling instruction aggregation vector can be subjected to multi-level latent feature mining to output corresponding multiple scheduling instruction latent vectors. Schematically, at the first level, the second scheduling instruction aggregation vector can be subjected to self-attention processing to obtain a corresponding self-attention vector, so that important information in the second scheduling instruction aggregation vector is mined. Then, the self-attention vector is subjected to convolution processing to obtain a corresponding convolution vector, so that some high-level and abstract features are mined. Then, the convolution vector is subjected to pooling processing to obtain a corresponding pooling vector, so that important semantic features are maintained while reducing the vector size. Finally, the pooling vector is subjected to activation processing, which can mine non-linear relationships, thereby obtaining the first scheduling instruction latent vector. At the second level, the first scheduling instruction latent vector can be subjected to self-attention processing to obtain a corresponding self-attention vector, so that important information in the first scheduling instruction latent vector is mined. Then, the self-attention vector is subjected to convolution processing to obtain a corresponding convolution vector, so that some high-level and abstract features are mined. Then, the convolution vector is subjected to pooling processing to obtain a corresponding pooling vector, so that important semantic features are maintained while reducing the vector size. Finally, the pooling vector is subjected to activation processing, which can mine non-linear relationships, thereby obtaining the second scheduling instruction latent vector. And so on, the third scheduling instruction latent vector, the fourth scheduling instruction latent vector, etc. can be obtained in turn.

[0060] Further, in the above step S133, the specific manner of performing interference removal operation on the c-th interference instruction latent vector among the multiple interference instruction latent vectors is not limited. For example, in a schematic implementation manner, an instruction sequence can be directly generated based on the scheduling instruction expansion vector, the scheduling instruction latent vector, and the c-th interference instruction latent vector, so as to generate a corresponding interference removal instruction sequence. Another example is that, in another schematic implementation manner, considering that the content of the instruction sequence is relatively large, and for the sake of generation accuracy, the above step S133 can further include step S133a and step S133b, and the specific step content is as follows (in combination with Figure 4 ).

[0061] Step S133a: Based on the scheduling instruction expansion vector and the scheduling instruction latent vector, perform interference restoration operation on the c-th interference instruction latent vector to output corresponding predicted interference information.

[0062] In an embodiment of the present invention, the c-th interference instruction latent vector may be subjected to an interference restoration operation according to the scheduling instruction expansion vector (as described above, since there is at least one scheduling instruction expansion vector, when there are multiple ones, any one of the scheduling instruction expansion vectors may be used) and the scheduling instruction latent vector, and corresponding predicted interference information is output. Wherein, the predicted interference information belongs to the predicted data of the applied interference information. Schematically, the c-th interference instruction latent vector may refer to the last interference instruction latent vector (in other embodiments, each interference instruction latent vector may also be superimposed and normalized, and then the interference restoration operation is performed), and the scheduling instruction latent vector may also be the last scheduling instruction latent vector, so that the level of semantic information can be ensured to be consistent.

[0063] Step S133b: According to the predicted interference information, perform an interference removal operation on the interference scheduling instruction sequence, and output a corresponding interference removal instruction sequence.

[0064] In an embodiment of the present invention, after the predicted interference information is predicted and output, the interference scheduling instruction sequence may be subjected to an interference removal operation according to the predicted interference information, and a corresponding interference removal instruction sequence is output. For example, based on the predicted interference information, the adjusted instruction order, the deleted instructions, the added instructions, and the replaced instructions are restored.

[0065] Furthermore, in step S133a above, the specific manner of performing the interference restoration operation on the c-th interference instruction latent vector is not limited. For example, in a schematic embodiment, in order to ensure the reliable progress of the interference restoration operation and make the reliability of the obtained predicted interference information higher, step S133a above may further include the following implementable content: First, when the c-th interference instruction latent vector belongs to the last interference instruction latent vector, the c-th interference instruction latent vector and the last scheduling instruction latent vector may be semantically associated and aggregated to form a corresponding first first association aggregation vector; Schematically, the dot product between the last scheduling instruction latent vector and the transposed vector of the c-th interference instruction latent vector may be calculated to obtain a corresponding dot product parameter distribution, where the dot product parameter distribution may be used to reflect the association relationship between the last scheduling instruction latent vector and the c-th interference instruction latent vector. Then, based on the dot product parameter distribution, a weighted sum calculation may be performed on the c-th interference instruction latent vector to obtain a corresponding association vector. In addition, considering that the semantic association aggregation will have a certain depth, to avoid the problem of semantic distortion, the association vector and the c-th interference instruction latent vector may be added, and then the added vector is normalized to obtain the first first association aggregation vector; Secondly, the first first associated aggregation vector and the scheduling instruction expansion vector can be semantically associated and aggregated to form a first second associated aggregation vector; illustratively, the dot product between the scheduling instruction expansion vector and the transposed vector of the first first associated aggregation vector can be calculated to obtain a corresponding dot product parameter distribution, where the dot product parameter distribution can be used to reflect the association relationship between the scheduling instruction expansion vector and the first first associated aggregation vector. Then, based on the dot product parameter distribution, a weighted sum calculation can be performed on the first first associated aggregation vector to obtain a corresponding associated vector. Then, the associated vector and the first first associated aggregation vector can be added together. Finally, the added vector can be normalized to obtain the first second associated aggregation vector; Then, the c-th interference instruction latent vector and the first second associated aggregation vector can be semantically associated and aggregated to form a corresponding second first associated aggregation vector; After that, the second first associated aggregation vector and the scheduling instruction expansion vector can be semantically associated and aggregated to form a second second associated aggregation vector; Finally, a last second associated aggregation vector can be determined based on the second second associated aggregation vector, and an interference information prediction operation can be performed based on the last second associated aggregation vector to output corresponding predicted interference information. Exemplarily, in a schematic implementation manner, the second second associated aggregation vector can be directly used as the last second associated aggregation vector, or, in other implementation manners, semantic association aggregation can also be sequentially performed in the above manner to obtain a third second associated aggregation vector, a fourth second associated aggregation vector, etc., until the last second associated aggregation vector is obtained. Additionally, the interference information prediction operation can gradually generate each word in the predicted interference information through a decoder. For example, in the first time step, the last second associated aggregation vector can be subjected to a fully connected process to output a corresponding fully connected vector, and then, through an output function (such as a softmax function, etc.) for mapping, a corresponding probability distribution can be obtained. Each parameter in this probability distribution represents the probability of each word in the dictionary, and then, the word with the highest probability is used as the output of the first time step. In the second time step, the output of the first time step can be subjected to a word embedding process to obtain a corresponding embedding vector, and then, the embedding vector and the last second associated aggregation vector can be subjected to a cross-attention process to obtain a corresponding cross-attention vector. Then, the cross-attention vector can be subjected to a fully connected process to output a corresponding fully connected vector, and then, through the output function for mapping, a corresponding probability distribution can be obtained. Each parameter in this probability distribution represents the probability of each word in the dictionary, and then, the word with the highest probability is used as the output of the second time step. Thus, by analogy, the output of the third time step, the output of the fourth time step, etc. can be obtained. Finally, the outputs of each time step can be combined to form corresponding predicted interference information. It can be understood that, in other implementation manners, after obtaining the last second associated aggregation vector, the decoder can also be used to process the last second associated aggregation vector (the generation method of the predicted interference information can be referred to) to generate an interference removal instruction sequence.

[0066] Further, in a schematic implementation manner, to ensure the reliable implementation of the above step S120 and step S130, step S120 and step S130 can be implemented through a neural network formed by training, such as a target anomaly detection model. The training process of the target anomaly detection model can be as follows: In the first step, the sample interference scheduling instruction sequence corresponding to the sample scheduling instruction sequence can be determined. The sample scheduling instruction sequence includes multiple sample power grid scheduling instructions. The sample interference scheduling instruction sequence is formed by applying interference information to the sample scheduling instruction sequence. The ways of applying interference information include at least one of adjusting the instruction order, deleting instructions, adding instructions, and replacing instructions for the multiple sample power grid scheduling instructions, as described previously. In the second step, through the candidate anomaly detection model, potential features of the sample scheduling instruction sequence can be mined, and the corresponding sample instruction vector can be output. The sample instruction vector is used to reflect the potential semantic features of the multiple sample power grid scheduling instructions in the sample scheduling instruction sequence, as described previously. In the third step, through the candidate anomaly detection model, based on the sample instruction vector, interference removal operations can be performed on the sample interference scheduling instruction sequence, and the corresponding sample interference removal instruction sequence can be output, as described previously. In the fourth step, based on the sequence matching parameter between the sample scheduling instruction sequence and the sample interference removal instruction sequence, the anomaly detection data corresponding to the sample scheduling instruction sequence can be output (as described previously), and based on the error (such as cross-entropy error, etc.) between the anomaly detection data and the anomaly label data corresponding to the sample scheduling instruction sequence, the candidate anomaly detection model can be updated (such as updating the model parameters along the direction of reducing the error until the error converges. The error convergence can mean that the error is reduced to a preset value or the amplitude of the error reduction is less than a preset amplitude), and the target anomaly detection model can be formed.

[0067] In summary, for the power grid dispatching instruction sequence anomaly detection method and system provided by the present invention, first, the interfering dispatching instruction sequence corresponding to the to-be-detected dispatching instruction sequence is determined; second, potential feature mining is performed on the to-be-detected dispatching instruction sequence to output the corresponding to-be-detected instruction vector; then, based on the to-be-detected instruction vector, interference removal operation is performed on the interfering dispatching instruction sequence to output the corresponding interference-removed instruction sequence; finally, based on the sequence matching parameter between the to-be-detected dispatching instruction sequence and the interference-removed instruction sequence, the anomaly detection data corresponding to the to-be-detected dispatching instruction sequence is output. Based on the above content, by performing potential feature mining on the to-be-detected dispatching instruction sequence to obtain the to-be-detected instruction vector, the to-be-detected instruction vector is used to guide the interference removal of the interfering dispatching instruction sequence, ensuring that the power grid dispatching instructions in the interference-removed instruction sequence after interference removal are consistent with the power grid dispatching instructions in the to-be-detected dispatching instruction sequence. Furthermore, by comparing the sequence matching parameter, the anomaly situation of the power grid dispatching instructions in the to-be-detected dispatching instruction sequence is determined, which can improve the reliability of power grid dispatching instruction anomaly detection (it can make full use of the potential semantic features of power grid dispatching instructions, making the reliability of subsequent processing higher). Therefore, it can improve the problem of relatively low reliability in power grid dispatching instruction sequence anomaly detection existing in the prior art.

[0068] In several embodiments provided by the embodiments of the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device and method embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0069] In addition, in each embodiment of the present invention, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0070] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes. It should be noted that in this article, the terms "including", "comprising", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0071] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for detecting abnormality in a power grid dispatching instruction sequence, characterized in that: include: Determine an interference scheduling instruction sequence corresponding to the scheduling instruction sequence to be detected, wherein the scheduling instruction sequence to be detected includes multiple power grid scheduling instructions to be detected, and the interference scheduling instruction sequence is formed by applying interference information to the scheduling instruction sequence to be detected, and the manner of applying the interference information includes at least one of adjusting the instruction sequence, deleting instructions, adding instructions, and replacing instructions for the multiple power grid scheduling instructions to be detected; Performing potential feature mining on the to-be-detected dispatch instruction sequence, and outputting a corresponding to-be-detected instruction vector, wherein the to-be-detected instruction vector is used to reflect the potential semantic features of the plurality of to-be-detected power grid dispatch instructions in the to-be-detected dispatch instruction sequence; According to the instruction vector to be detected, the interference scheduling instruction sequence is subjected to interference removal operation, and a corresponding interference removal instruction sequence is output; Based on the sequence matching parameters between the scheduling instruction sequence to be detected and the interference removal instruction sequence, the abnormality detection data corresponding to the scheduling instruction sequence to be detected is output, wherein the abnormality detection data is used to reflect whether there are abnormal power grid scheduling instructions to be detected in the scheduling instruction sequence to be detected.

2. The method for detecting abnormality of a power grid dispatching instruction sequence according to claim 1, characterized in that: The step of mining potential features of the to-be-detected scheduling instruction sequence and outputting a corresponding to-be-detected instruction vector comprises: Performing an embedding operation on the scheduling instruction sequence to be detected, outputting a corresponding scheduling instruction embedding vector, and performing a vector compression operation on the scheduling instruction embedding vector, outputting a corresponding scheduling instruction compression vector; Performing multi-level latent feature mining on the scheduling instruction compression vector, and outputting a plurality of corresponding scheduling instruction latent vectors, wherein the a-th scheduling instruction latent vector is formed based on performing latent feature mining on the b-th scheduling instruction latent vector, and the plurality of scheduling instruction latent vectors respectively correspond to different latent feature levels, a=b+1, and b is greater than or equal to 1; Performing a vector expansion operation on at least one scheduling instruction potential vector among the plurality of scheduling instruction potential vectors, and outputting at least one corresponding scheduling instruction expansion vector, wherein the vector expansion operation and the vector compression operation are two mutually inverse operations; Based on the at least one scheduling instruction extension vector, a corresponding instruction vector to be detected is determined.

3. The method for detecting abnormality of a power grid dispatching instruction sequence according to claim 2, characterized in that: The step of performing a vector expansion operation on at least one of the plurality of scheduling instruction potential vectors and outputting at least one corresponding scheduling instruction expansion vector comprises: Performing a vector aggregation operation on at least two scheduling instruction potential vectors among the plurality of scheduling instruction potential vectors, and outputting a corresponding first scheduling instruction aggregation vector; Perform a vector expansion operation on the first scheduling instruction aggregation vector and output a corresponding scheduling instruction expansion vector.

4. The method for detecting abnormality of a power grid dispatching instruction sequence according to claim 3, characterized in that: The at least two scheduling instruction potential vectors include an x-th scheduling instruction potential vector and a y-th scheduling instruction potential vector, the x-th scheduling instruction potential vector includes z first local potential vectors, and the y-th scheduling instruction potential vector includes z second local potential vectors; The step of performing a vector aggregation operation on at least two scheduling instruction potential vectors among the plurality of scheduling instruction potential vectors and outputting a corresponding first scheduling instruction aggregation vector comprises: Perform convolution operations on the z second local potential vectors respectively, and output corresponding z second local convolution vectors; Performing a vector aggregation operation on the z second local convolution vectors and the w-th first local latent vector, and outputting a w-th first local aggregation vector corresponding to the w-th first local latent vector, wherein the w-th first local latent vector belongs to a first local latent vector among the z first local latent vectors; After obtaining the z first local aggregation vectors corresponding to the z first local latent vectors, a corresponding first scheduling instruction aggregation vector is determined based on the z first local aggregation vectors, wherein, for each of the z first local latent vectors, the first local latent vector and the z second local convolution vectors are sequentially concatenated to form a first local aggregation vector corresponding to the first local latent vector.

5. The method for detecting abnormality of a power grid dispatching instruction sequence according to claim 2, characterized in that: The step of performing interference removal operation on the interference scheduling instruction sequence according to the instruction vector to be detected and outputting a corresponding interference removal instruction sequence comprises: Performing an embedding operation on the interference scheduling instruction sequence to output a corresponding interference instruction embedding vector, and performing a vector compression operation on the interference instruction embedding vector to output a corresponding interference instruction compression vector; Perform multi-level potential feature mining on the interference instruction compression vector, and output a corresponding plurality of interference instruction potential vectors; According to the scheduling instruction expansion vector and the scheduling instruction potential vector, an interference removal operation is performed on the cth interference instruction potential vector among the multiple interference instruction potential vectors, and a corresponding interference removal instruction sequence is output.

6. The method for detecting abnormality in a power grid dispatching instruction sequence according to claim 5, characterized in that: The step of performing multi-level potential feature mining on the scheduling instruction compression vector and outputting a plurality of corresponding scheduling instruction potential vectors comprises: Performing a vector aggregation operation on the dth interference instruction potential vector and the scheduling instruction compression vector, and outputting a corresponding second scheduling instruction aggregation vector, wherein d is less than c; The second scheduling instruction aggregation vector is subjected to multi-level potential feature mining to output a corresponding plurality of scheduling instruction potential vectors.

7. The method for detecting abnormality in a power grid dispatching instruction sequence according to claim 5, characterized in that: The step of performing an interference removal operation on a cth interference instruction potential vector among the multiple interference instruction potential vectors according to the scheduling instruction expansion vector and the scheduling instruction potential vector, and outputting a corresponding interference removal instruction sequence comprises: According to the scheduling instruction expansion vector and the scheduling instruction potential vector, the c-th interference instruction potential vector is subjected to interference restoration operation, and corresponding predicted interference information is output, wherein the predicted interference information belongs to predicted data of the applied interference information; According to the predicted interference information, the interference scheduling instruction sequence is subjected to an interference removal operation, and a corresponding interference removal instruction sequence is output.

8. The method for detecting abnormality in a power grid dispatching instruction sequence according to claim 7, characterized in that: The step of performing an interference restoration operation on the c-th interference instruction potential vector according to the scheduling instruction expansion vector and the scheduling instruction potential vector, and outputting corresponding predicted interference information, comprises: When the c-th interference instruction potential vector belongs to the last interference instruction potential vector, semantically associating and aggregating the c-th interference instruction potential vector and the last scheduling instruction potential vector to form a corresponding first first associative aggregation vector; Performing semantic association aggregation on the first first association aggregation vector and the scheduling instruction expansion vector to form a first second association aggregation vector; Performing semantic association aggregation on the c-th interference instruction potential vector and the first second association aggregation vector to form a corresponding second first association aggregation vector; Performing semantic association aggregation on the second first association aggregation vector and the scheduling instruction expansion vector to form a second second association aggregation vector; A last second association aggregation vector is determined based on the second second association aggregation vector, and an interference information prediction operation is performed based on the last second association aggregation vector to output corresponding predicted interference information.

9. The method for detecting abnormality in a power grid dispatching instruction sequence according to any one of claims 1 to 8, characterized in that: The power grid dispatching instruction sequence abnormality detection method also includes: Determine a sample interference scheduling instruction sequence corresponding to the sample scheduling instruction sequence, wherein the sample scheduling instruction sequence includes a plurality of sample power grid scheduling instructions, and the sample interference scheduling instruction sequence is formed by applying interference information to the sample scheduling instruction sequence, and the manner of applying the interference information includes at least one of adjusting the instruction sequence, deleting instructions, adding instructions, and replacing instructions for the plurality of sample power grid scheduling instructions; Through the candidate anomaly detection model, the sample scheduling instruction sequence is subjected to potential feature mining, and a corresponding sample instruction vector is output, wherein the sample instruction vector is used to reflect the potential semantic features of the plurality of sample power grid scheduling instructions in the sample scheduling instruction sequence; By using the candidate anomaly detection model, according to the sample instruction vector, the sample interference scheduling instruction sequence is subjected to interference removal operation, and a corresponding sample interference removal instruction sequence is output; According to the sequence matching parameters between the sample scheduling instruction sequence and the sample interference removal instruction sequence, the anomaly detection data corresponding to the sample scheduling instruction sequence is output, and based on the error between the anomaly detection data and the anomaly label data corresponding to the sample scheduling instruction sequence, the candidate anomaly detection model is updated to form a target anomaly detection model.

10. A power grid dispatching instruction sequence abnormality detection system, characterized in that: include: Memory for storing computer programs; A processor connected to the memory is used to execute a computer program stored in the memory to implement the power grid dispatching instruction sequence anomaly detection method as described in any one of claims 1-9.

Images