Chip system, chip anti-cracking method and electronic equipment

Abstract

The invention provides a chip system, a chip anti-cracking method and electronic equipment, and relates to the field of chips. The chip system comprises an anti-cracking circuit, and the anti-cracking circuit comprises at least one target signal line. And the interference signal lines are coupled with each target signal line, and each interference signal line is used for adjusting the signal delay of the target signal line and enabling other parts of the chip system after the signal delay meets the verification condition. Thus, the design introduces a dynamic adjustable time sequence confusion mechanism, the difficulty of an attacker for performing reverse analysis and cracking on the chip time sequence constraint condition is increased, and the security of a chip system is effectively improved.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly, to a chip system, a chip anti-cracking method, and an electronic device. Background Art

[0002] A chip netlist is a key data structure in integrated circuit design, which describes in detail the connection relationships between internal circuit elements of a chip in a text or graphical form. Specifically, the netlist contains the electrical connection information between each basic element such as transistors, logic gates, and registers in the circuit, as well as the topological structure of the signal transmission path. Therefore, through the chip netlist, chip designers can clearly understand how each element in the circuit is interconnected, and thus deduce the overall logical structure and functional characteristics of the circuit. Therefore, in practical applications, the netlist is not only used for circuit design and simulation, but also plays an important role in chip verification, synthesis optimization, and other aspects.

[0003] In addition, in the process of integrated circuit design, in addition to the chip netlist, chip constraints are also crucial components. Chip constraints refer to a series of restrictions and specifications on design parameters and conditions during the design process to ensure that the chip can work properly and meet specific performance, power consumption, and area requirements. These constraints mainly include timing constraints and physical constraints, etc. Timing constraints involve clock frequency, setup time, hold time, etc., to ensure that signals arrive at the correct time; physical constraints cover layout and routing rules, power consumption limits, heat dissipation requirements, etc. These constraint conditions together constitute the "design rules" of chip design, providing clear guidance and specifications for the entire design process.

[0004] In the process of chip cracking or reverse engineering, professionals usually can use a variety of technical means to obtain the internal information of the chip. For example, through physical methods such as focused ion beam (FIB) analysis, layer-by-layer photography, and chemical etching, the various layers of the chip are gradually peeled off to obtain the physical layout information of the chip. Then, using image processing technology and pattern recognition algorithms, these physical information are converted into a circuit netlist. Reverse designers gradually analyze the constraint conditions of the chip based on the obtained netlist information, combined with the speculation and understanding of the chip function. For example, the timing requirements are inferred through netlist analysis; the layout and routing rules are speculated based on the physical structure; the electrical constraints are determined through power consumption analysis. Finally, the speculated constraint information is verified and corrected through decompilation and debugging tools, and finally the complete chip design data is obtained.

[0005] Therefore, the existing chip design process lacks an effective protection mechanism, making it easy for key design information such as netlists and constraints to be extracted and reconstructed through reverse engineering technology. How to effectively protect chip design information and prevent key data from being illegally extracted and reconstructed has become an important technical problem that needs to be solved in the current integrated circuit security field. Summary of the invention

[0006] In order to overcome at least one of the deficiencies in the prior art, the present application provides a chip system, a chip anti-cracking method and an electronic device, specifically comprising:

[0007] In a first aspect, the present application provides a chip system, the chip system comprising:

[0008] An anti-cracking circuit, wherein the anti-cracking circuit includes at least one target signal line;

[0009] An interference signal line coupled to each of the target signal lines, wherein each of the interference signal lines is used to adjust the signal delay of the target signal line and enable the rest of the chip system after the signal delay meets a verification condition.

[0010] In a second aspect, the present application provides a chip anti-cracking method, the method being applied to a chip system, the chip system comprising an anti-cracking circuit; the anti-cracking circuit comprising a target signal line and at least one interference signal line coupled to the target signal line; the method comprising:

[0011] Sending a target interference signal to each of the interference signal lines;

[0012] Obtaining a signal delay generated by the target signal line under the action of each of the interference signal lines;

[0013] If the signal delay satisfies the verification condition, the rest of the chip system is enabled.

[0014] In a third aspect, the present application provides an electronic device and the chip system described in the electronic device.

[0015] Compared with the prior art, this application has the following beneficial effects:

[0016] The present application provides a chip system, a chip anti-cracking method, and an electronic device. Among them, the chip system includes an anti-cracking circuit, where the anti-cracking circuit includes at least one target signal line; interference signal lines coupled to each target signal line, where each interference signal line is used to adjust the signal delay of the target signal line, and after the signal delay meets the verification condition, enable the rest of the chip system. In this way, this design introduces a dynamically adjustable timing confusion mechanism, increasing the difficulty for attackers to perform reverse analysis and cracking on the chip timing constraint conditions, thereby effectively improving the security of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0018] Figure 1 One of the schematic structural diagrams of the anti-cracking circuit provided by the embodiment of the present application;

[0019] Figure 2 The equivalent schematic diagram of the anti-cracking circuit provided by the embodiment of the present application;

[0020] Figure 3 Another schematic structural diagram of the anti-cracking circuit provided by the embodiment of the present application;

[0021] Figure 4 The schematic flow diagram of the chip anti-cracking method provided by the embodiment of the present application;

[0022] Figure 5 One of the measured signal curve diagrams of the first target signal line provided by the embodiment of the present application;

[0023] Figure 6 Another measured signal curve diagram of the first target signal line provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Accordingly, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0026] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0027] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance. In addition, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0028] In addition, terms such as "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0029] In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "arranged", "installed", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0030] Based on the above statements, as introduced in the background art, the existing chip design process lacks an effective protection mechanism, making it easy for key design information such as netlists and constraint conditions to be extracted and reconstructed through reverse engineering techniques.

[0031] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions through creative labor to solve or improve the above problems. It should be noted that the defects existing in the above solutions in the prior art are the results obtained by the inventors through practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed in the embodiments of the present application below for the above problems should be the contributions made by the inventors to the present application during the invention and creation process, rather than being understood as the technical content known to those skilled in the art.

[0032] In view of the above technical problems, an embodiment of the present application (hereinafter referred to as this embodiment) provides a chip system. The chip system includes an anti-cracking circuit, wherein the anti-cracking circuit includes at least one target signal line; and interference signal lines coupled to each target signal line, wherein each interference signal line is used to adjust the signal delay of the target signal line and enable the rest of the chip system after the signal delay meets the verification condition. In this way, this design introduces a dynamically adjustable timing confusion mechanism, increasing the difficulty for attackers to perform reverse analysis and cracking on the chip timing constraint conditions, thereby effectively improving the security of the chip system.

[0033] To make the solution provided in this embodiment clearer, the chip system provided in this embodiment will be described in detail below. In this embodiment, the rest of the chip system except the anti-cracking circuit is referred to as the chip functional circuit. It can be understood that the chip functional circuit refers to the specific functional modules inside the chip system, and these functional modules are responsible for performing specific tasks or providing specific services. Therefore, the chip functional circuit provides different functions depending on the device to which the chip system is applied. For example, in a printer, the chip functional circuit may include a timer for controlling the motor operation and IIC and SPI communications for communicating with external devices. In a medical device, the chip functional circuit may include precise timers and IIC communications for monitoring and recording data.

[0034] Therefore, the chip functional circuit is not fixed but is configured and customized according to the specific requirements of the application device. Regardless of the device, the chip functional circuit is a key part for realizing the core functions of the device. Through the anti-cracking circuit, the cracking difficulty of the entire chip system is increased.

[0035] In the related art, multiple data links are set between the internal ports and external ports of the chip. The lengths of the multiple data links are different, and then different resistances are generated, thereby causing different degrees of signal delay. Then, a target link is dynamically selected from the multiple data links to send data, so as to achieve the purpose of timing confusion. However, this design principle is very easy to be cracked by restoring an identical link.

[0036] In this embodiment, the signal delay of the target signal line is adjusted by introducing an interference signal line, thereby increasing the difficulty of chip cracking. Specifically, the anti-cracking circuit consists of a target signal line and an interference signal line coupled thereto. The target signal line is responsible for transmitting the key signal, while the interference signal line affects the target signal line by adjusting the signal delay. It can be understood that the design principle of the anti-cracking circuit is to increase the unpredictability of the signal delay by introducing an interference signal line, so that it is difficult for an attacker to accurately simulate the correct signal delay, and ultimately achieve the purpose of protecting the chip functional circuit.

[0037] In the specific implementation manner, during the chip design stage, the delay can be adjusted by adjusting the line length of the target signal line. Among them, the longer the signal line, the higher its equivalent resistance, which means the longer the delay time. The shorter the signal line, the lower its equivalent resistance, which means the shorter the delay time. In addition, during the chip design stage, each target signal line can be arranged in parallel with the interference signal line; the output end of each target signal line is connected to the output end of the interference signal line. And it is ensured that the distance between the target signal line and each interference signal line is less than a preset distance threshold, so that a parasitic capacitance is generated between the target signal line and the interference signal line. Therefore, the magnitude of the parasitic capacitance is limited by the distance between the target signal line and the interference signal line, the number of interference signal lines, the signal input to the interference signal line, etc. It can be understood that the target signal line can control the magnitude of the parasitic capacitance from both the hardware and software levels. Finally, the resistance generated by the line length and the parasitic capacitance generated between the signal lines together form an RC circuit.

[0038] However, it should be understood that the line length of the target signal line, the number of interference lines, and the distance between them are all physical characteristics of the chip. These characteristics are determined during the chip design stage and are fixed through the production and manufacturing of the chip. That is to say, the physical characteristics of the chip can only be adjusted during the design stage. Once the chip is produced and leaves the factory, these physical characteristics cannot be modified any further.

[0039] Exemplarily, Figure 1 shows 2 interference signal lines, called the first interference signal line 11 and the second interference signal line 12; and a target signal line, called the first target signal line 13. The first interference signal line 11 and the second interference signal line 12 are respectively parallel to the first target signal line 13 and maintain a certain distance, so as to form a parasitic capacitance with the target signal. At the same time, the first interference signal line 11, the second interference signal line, and the first target signal line 13 itself all have a certain resistance. Therefore, Figure 1 The circuit shown can be simplified to the Figure 2 shown RC equivalent circuit. In the equivalent circuit, the resistance and parasitic capacitance of each signal line are abstracted into multiple resistors Ra 1 ~Ra n 、Rb1 ~Rb n 、Rs 1 ~Rs n and a plurality of capacitors Ca 1 ~Ca n 、Cb 1 ~Cb n combination.

[0040] In other alternative embodiments, each interference signal line includes an interference main line and at least one capacitor, and each interference main line forms a coupling with a target signal line through at least one capacitor. In this way, without making the interference main line parallel to the target signal, a coupling can be formed with the target signal line through a physical capacitor.

[0041] Exemplarily, Figure 3 two interference signal lines are shown, referred to as a third interference signal line 21 and a fourth interference signal line 22, and a target signal line, referred to as a second target signal line 23. Taking the third interference signal line 21 as an example, the third interference signal line 21 includes an interference main line and a plurality of capacitors. The interference main line of the third interference signal line 21 forms a coupling with the second target signal line 23 through a plurality of capacitors.

[0042] Based on the above description of the chip system, the chip anti-cracking method applied to the chip system will be described next. Similarly, the chip system includes an anti-cracking circuit; the anti-cracking circuit includes a target signal line and at least one interference signal line coupled to the target signal line. As Figure 4 shown, the method includes:

[0043] S1, sending a target interference signal to each interference signal line;

[0044] S2, obtaining the signal delay generated by the target signal line under the action of each interference signal line;

[0045] S3, if the signal delay meets the verification condition, enabling the remaining parts of the chip system.

[0046] In this way, by introducing an interference signal that can dynamically change and a complex delay verification mechanism, it is difficult for illegal crackers to predict and imitate the correct combination of interference signals. Even if the cracker can guess some interference signals, it is difficult to simultaneously meet all verification conditions, thus greatly improving the anti-cracking ability of the chip.

[0047] In this embodiment, the chip anti-cracking method can be implemented by a processor in the chip system. To make the chip anti-cracking method provided in this embodiment clearer, the following Figure 4Each step of the method shown will be elaborated in detail. However, it should be understood that the operations of the flowchart may not be implemented in sequence, and steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application. Therefore, continue to refer to Figure 4 , the method includes:

[0048] S1, sending a target interference signal to each interference signal line.

[0049] In an alternative implementation, the processor may select a target interference strategy from multiple preset interference strategies of at least one interference signal line; according to the target interference strategy, send a target interference signal to each interference signal line.

[0050] It can be understood that in the system design stage, multiple interference strategies will be preset in advance. These interference strategies may include different types of interference signals, signal intensities, frequencies, and other parameter combinations. Each interference strategy is designed to produce different signal delay effects, thereby increasing the difficulty of cracking. Therefore, during the actual control process, the processor will select a target interference strategy from these preset interference strategies according to the current environment or specific conditions. The selection process may be based on randomness, fixed rotation, or more complex logical algorithms. For example, the processor can determine which interference strategy to select based on the current state of the chip, external input, or internal counter.

[0051] Then, once the target interference strategy is selected, the processor will send the corresponding target interference signal to each interference signal line according to this strategy. The target interference signal of each interference signal line can be a low-level signal, a high-level signal, a signal with the same frequency or multiple frequencies as the target signal line, or a signal with a different phase. The specific form and parameters of the interference signal depend on the selected target interference strategy. Some of these signals are explained below:

[0052] The signal with the same frequency as the target signal line refers to an electrical signal with the same frequency as the target signal line, that is, their periods are the same.

[0053] The multiple-frequency signal of the target signal line refers to an electrical signal with a frequency that is an integer multiple of the frequency of the target signal line. For example, when the frequency of the target signal line is 1 MHz, the multiple-frequency signal may be 2 MHz, 3 MHz, etc.

[0054] The signal with the same frequency but different phase as the target signal line refers to an electrical signal with the same frequency as the target signal line but different phases, that is, their periods are the same but the starting points are different.

[0055] In this way, by introducing diverse interference sources with these signals, it increases the difficulty for crackers to identify and imitate the correct signal combination, thereby enhancing the security of the chip.

[0056] Continue to refer to Figure 4 , the description of the target interference signal in each interference signal line based on the above implementation. Next, continue to describe Figure 4 the step S2 in

[0057] S2, obtain the signal delay generated by the target signal line under the action of each interference signal line.

[0058] In this regard, after the interference signal is sent, the processor can monitor in real time the signal delay generated by the target signal line under the action of these interference signals. The change of the signal delay reflects the influence degree of the interference signal on the target signal line. Among them, the signal delay includes the rising edge duration from low level to high level and the falling edge duration from high level to low level.

[0059] Exemplarily, continue to take the Figure 1 shown anti-cracking circuit as an example. As Figure 5 shown, when a low level is applied to the first interference signal line 11 and the second interference signal line 12 in Figure 1 , and a square wave signal is applied to the first target signal line 13, a first level change curve (purple) is collected on the first target signal line 13. Since both the first interference signal line 11 and the second interference signal line 12 are at low level and the parasitic capacitance is very small, the delay of the first level change curve is only determined by the line length of the first target signal line 13.

[0060] As Figure 6 shown, when a same-frequency pulse signal is applied to the first interference signal line 11 respectively, a second level change curve (light blue) is collected on the first target signal line 13. In addition, a same-frequency 1% delay pulse signal is applied to the first interference signal line 11 respectively, that is, signals with the same frequency but a 1% difference in delay are applied to the first interference signal line 11 and the first target signal line 13, and a third level change curve (dark blue) is collected on the first target signal line. In addition, a same-frequency 50% delay pulse signal is applied to the first interference signal line 11 respectively, that is, signals with the same frequency but a 50% difference in delay are applied to the first interference signal line 11 and the first target signal line 13, and a fourth level change curve (purple) is collected on the first target signal line 13.

[0061] Based on the description of the signal delay in the above embodiments, next, continue to describe Figure 4 the step S3 in

[0062] S3, if the signal delay meets the verification condition, enable the rest of the chip system.

[0063] In this embodiment, the processor can determine whether the signal delay is within the delay interval corresponding to the target interference strategy; if so, it is determined that the signal delay meets the verification condition.

[0064] Among them, the verification condition refers to that the signal delay on the target signal line that needs to be detected during the operation of the chip system must meet the preset standard or range. It can be understood that the signal delay on the target signal line should be within a certain specific time range. If the delay time is too long or too short, it indicates that the chip may be abnormal or cracked.

[0065] Moreover, only when the processor detects that the signal delay on the target signal line meets the preset verification condition, will the functional modules of the rest of the chip system be allowed to work normally. This mechanism can effectively prevent unauthorized access or cracking behavior. Because even if an attacker can copy the hardware structure of the chip, it is very difficult to precisely match the delay condition on the target signal line, thus unable to enable the chip functional circuit.

[0066] Exemplarily, assume that this chip system is applied to a printer. When the printer system starts or is about to execute a certain function (such as communicating with the consumable chip or controlling the motor operation), the chip system will automatically start the verification process.

[0067] Then, the printer will send a specific target interference signal to the interference signal line in the anti-cracking circuit. These interference signals may be one of a low-level signal, a high-level signal, a signal with the same frequency as the target signal line, a frequency-doubled signal, or a signal with the same frequency but different phases. The selection of the target interference signal is based on multiple preset interference strategies. Therefore, by sending the interference signal, the printer will detect the signal delay of the target signal line under the action of these interference signals. The signal delay can be determined by measuring the rising edge duration or the falling edge duration of the signal. Specifically, the chip system will monitor the electrical signal change on the target signal line in real time and calculate the rising edge duration of the signal from low level to high level or the falling edge duration from high level to low level.

[0068] Finally, the printer determines whether the detected signal delay meets the preset verification condition. For example, if the signal delay is between 10 microseconds and 15 microseconds, or the rising edge duration is within a specific range, then it can be considered that the verification condition is met. If the detected signal delay meets the verification condition, the printer will enable the corresponding functional circuit. For example, when the printer system needs to communicate with the consumable chip, only when the delay verification passes can the printer conduct normal data communication with the consumable chip. Similarly, when the printer needs to control the motor operation through a timer or control the scanning operation through an ADC, these operations also need to be executed after the delay verification passes.

[0069] It should be understood that the processor implementing the above chip anti-cracking method may be an integrated circuit chip with signal processing capabilities, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the above processor may include a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), an Application Specific Instruction-set Processor (ASIP), a Graphics Processing Unit (GPU), a Physics Processing Unit (PPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a microcontroller unit, a Reduced Instruction Set Computing (RISC), or a microprocessor, etc., or any combination thereof.

[0070] In addition, it should also be understood that technical improvements can be divided into hardware improvements (such as circuit structures) and software improvements (such as method flows). With the development of technology, many improvements in method flows can be directly regarded as improvements in hardware circuit structures. Designers usually program the improved method flows into hardware circuits, for example, using a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA). The logic function of an FPGA is determined by user programming. Designers can integrate the method flow into an integrated circuit through a Hardware Description Language (HDL), such as VHDL or Verilog, without customizing a dedicated chip. For example, designers can program with a Hardware Description Language (HDL), such as VHDL or Verilog, through a logic compiler software to integrate the method flow into an integrated circuit, thus easily implementing the hardware circuit. Therefore, the implementation logic of the above chip anti-cracking method can also be solidified into a specific logic circuit implementation.

[0071] Of course, in some embodiments, the chip system may further include a memory, which may be an information recording device based on any electronic, magnetic, optical, or other physical principles, for recording execution instructions, data, etc. In some embodiments, the memory may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0072] In some embodiments, the volatile memory may be a Random Access Memory (RAM); in some embodiments, the non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electric Erasable Programmable Read-Only Memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a disk drive, a solid state drive, any type of storage disk (such as an optical disk, a DVD, etc.), or a similar storage medium, or a combination thereof, etc.

[0073] This embodiment also provides an electronic device, which includes the above chip system. Specifically, the electronic device may be, but is not limited to, a printer, printing consumables, smart home appliances, medical devices, automotive electronics, mobile terminals, tablet computers, laptop computers, etc.

[0074] It should be understood that the devices and methods disclosed in the above embodiments may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

[0075] As described above, these are only various embodiments of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized in that: The chip system comprises: An anti-cracking circuit, wherein the anti-cracking circuit includes at least one target signal line; An interference signal line coupled to each of the target signal lines, wherein each of the interference signal lines is used to adjust the signal delay of the target signal line and enable the rest of the chip system after the signal delay meets a verification condition.

2. The chip system according to claim 1, characterized in that: Each of the target signal lines is arranged in parallel with the interference signal line; The output end of each of the target signal lines is connected to the output end of the interference signal line.

3. The chip system according to claim 2, characterized in that: The distance between the target signal line and each of the interference signal lines is less than a preset distance threshold.

4. The chip system according to claim 1, characterized in that: Each of the interference signal lines includes an interference main line and at least one capacitor; Each of the interfering main lines is coupled to the target signal line through the at least one capacitor.

5. A chip anti-cracking method, characterized in that: The method is applied to a chip system, the chip system includes an anti-cracking circuit; the anti-cracking circuit includes a target signal line and at least one interference signal line coupled to the target signal line; the method includes: Sending a target interference signal to each of the interference signal lines; Obtaining a signal delay generated by the target signal line under the action of each of the interference signal lines; If the signal delay satisfies the verification condition, the rest of the chip system is enabled.

6. The chip anti-cracking method according to claim 5, characterized in that: The sending a target interference signal to each interference signal line includes: Selecting a target interference strategy from a plurality of interference strategies preset for the at least one interference signal line; According to the target interference strategy, a target interference signal is sent to each interference signal line.

7. The chip anti-cracking method according to claim 6, characterized in that: The method further comprises: Determining whether the signal delay is within a delay interval corresponding to the target interference strategy; If so, it is determined that the signal delay satisfies the verification condition.

8. The chip anti-cracking method according to any one of claims 5 to 7, characterized in that: The target interference signal is one of a low level signal, a high level signal, a same frequency signal of the target signal line, a double frequency signal of the target signal line, and a same frequency but different phase signal of the target signal line.

9. The chip anti-cracking method according to any one of claims 5 to 7, characterized in that: The signal delay includes the rising edge duration of the signal changing from a low level to a high level and the falling edge duration of the signal changing from a high level to a low level.

10. An electronic device, characterized in that: The electronic device comprises the chip system according to any one of claims 1-5.

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