Scan chain reordering method, computer device and storage medium

Abstract

The present disclosure provides a scan chain reordering method, computer device, and storage medium. The method includes: obtaining a chip design layout; determining a scan chain and multiple components contained in the scan chain based on the chip design layout; grouping the multiple components according to their number to generate at least one component set; reordering the at least one component set to generate at least one subchain corresponding to the at least one component set; and splicing the at least one subchain to complete the scan chain reordering.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip layout planning, and in particular to a scan chain reordering method, a computer device, and a storage medium. Background Art

[0002] Scan chain is a commonly used digital integrated circuit (IC) testing technology, falling under the umbrella of Design for Testability (DFT). Scan chain reordering (‌Scan Reordering‌) refers to the process of reorganizing scan chains during chip design.

[0003] With the development of chip technology, some scan chains are designed to be very long. If these scan chains are to be reordered, according to relevant technical methods, the overall time consumption will be very long, which will seriously affect the overall efficiency.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure proposes a scan chain reordering method, a computer device, and a storage medium to solve or partially solve the above-mentioned problem.

[0006] Based on the above objectives, in a first aspect, the present disclosure provides a scan chain reordering method, comprising:

[0007] Obtain chip design layout;

[0008] Determining a scan chain and a plurality of components included in the scan chain according to the chip design layout;

[0009] Grouping the plurality of components according to the number of components to generate at least one component set;

[0010] reordering the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets;

[0011] The at least one sub-chain is spliced ​​together to complete the reordering of the scan chain.

[0012] In a second aspect, the present disclosure provides a computer device comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0013] In a third aspect, the present disclosure provides a non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method described in the first aspect.

[0014] As can be seen from the above, the present disclosure provides a scan chain reordering method, computer equipment and storage medium. The present disclosure first determines any scan chain through the chip design layout, and then determines the number of elements contained in the scan chain, and groups the elements contained in the scan chain according to the number of elements, and then reorders each group of elements according to the relevant reordering rules to generate multiple sub-chains corresponding to each group of elements, and finally splices these sub-chains to complete the reordering of the scan chain. This is equivalent to dividing the scan chain, reordering each of the divided sub-chains, and then splicing the reordered sub-chains to form a reordered scan chain. In this way, the overly long scan chain segments can be reordered, and the various groups of segments can be reordered in parallel using multi-threading and other methods, which can greatly optimize the running time of the scan chain reordering and improve the overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present disclosure is shown.

[0017] Figure 2 A basic structural diagram of the EDA tool provided by an embodiment of the present disclosure is shown.

[0018] Figure 3 A schematic diagram showing a basic execution flow of a calculation command of an EDA tool provided by an embodiment of the present disclosure is shown.

[0019] Figure 4 A flowchart of an exemplary method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this specification more clear, this specification is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements, objects or method steps appearing before the word include the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Figure 1 The following is a schematic diagram of the structure of a computer device 100 provided by an embodiment of the present disclosure. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are connected to each other within the device via the bus 110.

[0023] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the technology described in this disclosure. In some embodiments, the processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0024] The memory 104 may be configured to store data (eg, instruction sets, computer code, intermediate data, etc.). Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of the present disclosure) and data to be processed. The processor 102 may also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0025] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near-field communication (NFC)), a cellular network, the Internet, or a combination thereof. It will be appreciated that the type of network is not limited to the specific examples above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

[0026] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, and various sensors, as well as output devices such as a display, a speaker, a vibrator, and an indicator light.

[0027] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0028] It should be noted that although the above device only shows the processor 102, memory 104, network interface 106, peripheral interface 108 and bus 110, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above device may only include the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0029] Figure 2 FIG. 2 shows a basic structural diagram of an EDA tool 200 according to an embodiment of the present disclosure.

[0030] like Figure 2As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software that performs placement and routing based on chip designs. The EDA tool 200 can include a Tcl command (or graphical / window interface) module 204, various calculation modules (e.g., a Placement calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. A user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphical / window interface) module 204.

[0031] The Tcl command module 204 mainly performs the function of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific content of the instructions.

[0032] Depending on the calculation task, each calculation module can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization calculation module 210 can be used to optimize the placement position and wire connection method between each component. The calculation process of these calculation modules can be, for example, Figure 1 is performed in the processor 102.

[0033] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information can be stored in, for example, Figure 1 in the memory 104.

[0034] Figure 3 FIG. 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present disclosure. Figure 3As shown, in step 302, user 202 can issue a command (e.g., the do_place command) to the EDA tool 200 via the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses the command and dispatches it to the corresponding computation module (e.g., the Place computation module 206). In step 306, each computation module performs its required calculations. During this process, as shown in step 308, each computation module needs to frequently and repeatedly access data from the database system 212 to perform its calculations. After the calculations are complete, as shown in step 310, each computation module can write the results to the database system 212 and return the results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the results to user 202 via the command interface or graphical user interface (GUI), concluding the processing of the computation command by the EDA tool 200. In step 314, the user can evaluate the results and determine the next steps.

[0035] In some embodiments, scan chains are a design-for-test (DFT) technique that, by embedding shift registers, allows testers to externally control and observe the signal values ​​of internal flip-flops. The basic principle is to connect all flip-flops in the design into a chain, drive them with a unified scan clk, and shift them into the chip bit by bit using a pre-designed scan pattern. Capture is then enabled, and the Q output (output) of each flip-flop is fed into the combinational circuit it drives. The D input (input) of the next-level flip-flop captures the output of this combinational circuit. The resulting vector of results is compared with the tool's pre-calculated expectations to determine if there are any manufacturing errors in the chip. Scan chain reordering refers to the process of reordering the scan chain during chip design. Scan chains are a design technique in Design for Testability (DFT). By replacing ordinary registers with registers with scan functionality and connecting them into a chain through specific input and output ports, these registers can be shifted under external control during testing, enabling testing of the chip's internal logic. The main function of scan chain reordering is to optimize the connection mode of scan chains to ensure that data can flow quickly and safely.

[0036] As chip design becomes more complex, very long scan chains may appear in some scenarios. These scan chains may contain tens of thousands or even hundreds of thousands of components (inst). If such scan chains need to be reordered, if the reordering methods of related technologies are used to directly reorder the entire scan chain, the overall reordering time will be very long, which may reach tens of minutes or even hours. Such long time and low efficiency can no longer meet the current EDA industry's demand for high efficiency.

[0037] In view of this, the present disclosure proposes a scan chain reordering method. The present disclosure first determines any scan chain through the chip design layout, and then determines the number of elements contained in the scan chain, and groups the elements contained in the scan chain according to the number of elements, and then reorders each group of elements according to the relevant reordering rules to generate multiple sub-chains corresponding to each group of elements, and finally splices these sub-chains to complete the reordering of the scan chain. This is equivalent to dividing the scan chain, reordering each of the divided sub-chains, and then splicing the reordered sub-chains to form a reordered scan chain. In this way, the overly long scan chain segments can be reordered, and the various groups of segments can be reordered in parallel using multi-threading and other methods, which can greatly optimize the running time of the scan chain reordering and improve the overall efficiency.

[0038] Figure 4 The flow chart of the exemplary method 400 provided by the embodiment of the present disclosure is shown. The method 400 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 A portion of the functionality of the EDA tool 200. Figure 4 As shown, the method 400 may further include the following steps.

[0039] Step 402: Obtain chip design layout.

[0040] Typically, a chip design layout includes every layer of chip fabrication, including transistor layout, wiring, routing, and inter-layer connection locations for channels and vias. Based on this chip design layout, chip fabrication service providers can directly execute and mass-produce the chips. Furthermore, the chip design layout itself is drawn step by step, accompanied by various optimizations, ultimately completing the entire chip design layout. In the initial stages of a chip design layout, it may only indicate hierarchical functional information, such as which layer is a routing layer or an insulation layer; or it may simply list individual functional components, indicating their location, size, and other information. Subsequently, EDA tools are used for step-by-step design and optimization, ultimately resulting in a complete version of the chip design layout. Here, components (inst) can refer to standard processing units, modules or hard cores, input / output ports, registers, and so on within the chip.

[0041] In this step, since this embodiment involves operations related to the scan chain, it is generally necessary to obtain a chip design layout with the relevant scan chain drawn. This chip design layout can be used to determine the specific form of the current scan chain and related attribute data, such as the scan chain's starting position (which can be represented by coordinates, etc.), the ending position, the connection relationship between each component in the scan chain, the location of these components (which can be represented by coordinates, etc.), etc. In specific application scenarios, initial data information such as scan chain data and component positions can be obtained through DEF (Design Exchange File, physical information of the design library) files and / or LEF (Library Exchange File, physical information of the process library) files of the chip design layout.

[0042] In addition, in this step, the chip design layout can be local (for example, the entire design layout is divided into a large number of sub-areas) or overall.

[0043] Step 404 : Determine a scan chain and a plurality of components included in the scan chain according to the chip design layout.

[0044] In this step, after obtaining the chip design layout, at least one scan chain can be determined based on the records therein. These scan chains are generally set with a starting position and then proceed from the starting position to the end position after passing through multiple components connected in series and / or parallel. It should be noted that in this embodiment, a scan chain generally includes at least two components. If a scan chain only includes one component, then there is no need to reorder the scan chain itself.

[0045] After determining a scan chain, the multiple components included in the scan chain can be further determined based on the chip design layout, and the relevant properties of these components can be determined through the chip design layout, such as the connection relationship, setting position and other property information of each component.

[0046] Step 406 : Grouping the plurality of components according to the quantity to generate at least one component set.

[0047] In this step, after determining the multiple components included in the scan chain, the number of components included in the scan chain can be determined by reading the chip design layout data or by statistical methods. These components can then be grouped according to this number to generate at least one component set.

[0048] In some embodiments, the number of groups to be divided can be preset and used to group the components. For example, if five groups are required, after the number of components is determined, the components can be divided into five groups using random, equal, or proximity clustering (clustering components that are close to each other based on distance), thereby generating five component sets.

[0049] In other embodiments, the components may be grouped by setting a maximum number of components per group. For example, if the number of components is 200 and the maximum number of components per group is 20, the components may be divided into 10 groups, generating 10 component sets.

[0050] Furthermore, to improve processing efficiency, the processing power of the relevant processor can be pre-determined, and a threshold value can be set based on the processing power. If the number of components does not exceed the threshold value, no grouping is required, and the entire scan chain is directly reordered. If the number of components exceeds the threshold value, grouping is required. Specifically, the ratio of the number of components to the threshold value can be rounded up. For example, if there are 100 components and the threshold value is set to 20, the components are divided into 5 sets of components; if the threshold value is 30, the components are divided into 4 sets of components. In this way, the processing power of the processor can be fully utilized, and the scan chain can be grouped and reordered, improving the overall reordering efficiency. That is, in some embodiments, grouping based on the number of the plurality of components includes: determining a threshold value; and determining the number of groups based on the ratio between the number and the threshold value.

[0051] Furthermore, in some specific application scenarios, due to different grouping strategies or methods, such as when grouping components using certain algorithms, the number of components in each component set may vary. Consequently, according to the aforementioned embodiments, the number of components in a component set may exceed a set threshold. In this case, reordering this component set will also impact overall efficiency. Therefore, to prevent this situation and provide more room for error during reordering, a set number of groups can be added to the number of groups previously defined to determine the final number of groups. For example, if the number of groups determined based on the ratio between the number of components and the set threshold is five, one (the set number) group can be added to the five, resulting in a final number of groups of six. That is, in some embodiments, after determining the number of groups based on the ratio between the number of components and the set threshold, the method further includes: updating the number of groups by adding the set number to the determined number of groups.

[0052] In some embodiments, when arranging and connecting components in chip design, there is a more important parameter that needs to be considered, namely, wire length gain. Each time the components are adjusted and / or the connections are adjusted, it is expected that the loss of wire length gain will be minimized. For the scenario of this embodiment, if the loss of wire length gain is minimized, it is necessary to rearrange components with close distances together or group them in the same group as much as possible during the reordering process. In this way, in a specific application scenario, the distance between each component in the scan chain can be determined based on the chip design layout, and then these components can be clustered using a clustering algorithm based on these distances to complete the grouping of these components, so as to finally make the components in each group of components as close as possible, thereby reducing the global optimization loss of wire length gain. For example, assuming that 100 components need to be divided into 5 groups of component sets, a clustering algorithm can be used to first randomly select 5 origins. Then, based on the distance between the components, clustering can be performed with these 5 origins as the center. After the initial clustering is completed, the center origin is re-determined for each cluster set, and clustering is performed again. This iterative process is repeated until a set termination condition is met, and the 5 groups of component sets are completed. That is, in some embodiments, grouping based on the number of the multiple components includes: determining the distance between the multiple components; clustering the multiple components using a clustering algorithm based on the distance; and performing the grouping based on the clustering results.

[0053] Furthermore, in some more specific application scenarios, among the various clustering algorithms, the K-means clustering algorithm can be selected for clustering, taking into account the application scenario of this embodiment and the requirements for convergence speed, scalability, etc. That is, in some embodiments, the clustering algorithm includes the K-means clustering algorithm.

[0054] Furthermore, in specific application scenarios, when clustering components in a scan chain using a clustering algorithm, the clustering convergence process can sometimes take a long time due to factors such as the excessive number of clustering objects (components), the specificity of the clustering objects (components), or the specificity of the connection relationships between the clustering objects (components), which can also affect overall efficiency. Therefore, it is possible to consider accelerating the clustering algorithm, for example, by reducing dimensionality (such as principal component analysis (PCA)), using efficient databases (such as the NumPy library), and locality-sensitive hashing (LSH). Due to its outstanding performance in optimizing data structures and automatic vectorization, the Eigen template library can be used to accelerate the clustering algorithm. The Eigen template library also demonstrates significant advantages in the specific application scenarios of this embodiment, significantly reducing the clustering process for components. The Eigen template library is a C++ template library for linear algebra: for matrices, vectors, numerical solvers, and related algorithms. That is, in some embodiments, clustering the plurality of elements using a clustering algorithm according to the distance includes: accelerating the clustering algorithm using an Eigen template library.

[0055] Step 408: reorder the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets.

[0056] In this step, after the component sets are determined, since these component sets are essentially part of the scan chain, they can be reordered according to the reordering rules originally applied to the scan chain. This can be understood as dividing the scan chain into multiple sub-chains and reordering these sub-chains. The specific reordering rules can be set based on the specific application scenario, but the main purpose is to optimize the component connection relationships. By reordering at least one component set, adjusting the connection relationships of the components in each component set, and optimizing the connection relationships, at least one reordered sub-chain can be generated, where one sub-chain corresponds to one component set.

[0057] In some embodiments, to facilitate subsequent splicing, the sub-chain can be adjusted to a ring-shaped sub-chain. This allows the entire sub-chain to be spliced ​​together, regardless of which element in the sub-chain is used as the starting point for splicing. Furthermore, a single element at the end can be determined to facilitate splicing the next sub-chain. That is, in some embodiments, the at least one sub-chain comprises a ring-shaped chain.

[0058] Step 410: splice the at least one sub-chain to complete the reordering of the scan chain.

[0059] In this step, after reordering each sub-chain, these sub-chains need to be spliced ​​together to restore the entire scan chain. The splicing can be performed according to a pre-set configuration. For example, the order of the sub-chains corresponding to each component set is determined before reordering. This order can be manually set or determined based on other requirements.

[0060] Then, in some embodiments, the order and / or method of splicing can be determined based on certain properties of the sub-chains. In a specific application, the scan chain can be a single long chain or a multi-chain form including multiple sub-chains; then, for a scan chain, it generally has a starting position and an ending position, that is, the starting point and end point of a scan chain. The starting point and end point will have corresponding specific position information in the chip design layout (such as the starting point coordinates and the end point coordinates, etc.). At the same time, each component will also correspond to a specific setting position in the chip design layout (such as the position coordinates of each component, etc.). In this way, the splicing method and / or order can be determined based on the relative position relationship between the position coordinates of the components contained in each sub-chain and the starting point coordinates and the end point coordinates. For example, suppose there are three subchains: A, B, and C. In the first scenario, the distance between the component closest to the starting position in A and the starting position is 3 units, the distance between the component closest to the starting position in B and the starting position is 8 units, and the distance between the component closest to the starting position in C and the starting position is 13 units. Then, the connection order can be determined: A subchain is connected to the starting position first, then B subchain is connected to A subchain, and finally C subchain is connected to B subchain. In the second scenario, the connection order with the first subchain is determined. For a scenario with a similar distance, first connect subchain A to the starting position, then use the element at the end of subchain A as the target element to determine the distance between the elements in subchain B and subchain C and the target element. Assuming that a certain element in subchain C is closest to the target element, connect subchain C to subchain A, and so on. In the third scenario, assuming that it is determined that there are elements in subchain A and subchain B that are 3 units away from the starting position, it can be considered that subchain A and subchain B are connected side by side to the starting position, and the subchains are spliced ​​accordingly. That is, in some embodiments, splicing the at least one subchain includes: determining the starting position of the scan chain and the setting positions of the multiple elements according to the chip design layout; sorting the at least one subchain with the starting position as the origin and the setting positions of the elements contained in the at least one subchain; and completing the splicing of the at least one subchain in order with the starting position as the origin according to the sorting result.

[0061] Furthermore, considering the continuity of the splicing and the loss of wire length gain when splicing sub-chains, when connecting sub-chains, try to find the sub-chain with the element closest to the element at the end of the sub-chain after the sub-chain is sorted or connected as the next sub-chain. Of course, if no sub-chain has been sorted or connected yet, the sub-chain with the element closest to the starting position can be determined as the sub-chain connected to the starting position. For example, suppose there are three subchains: subchain A, subchain B, and subchain C. When sorting begins (generally, all subchains have not yet been sorted), the relative positional relationship between the components contained in each of the three subchains and the starting position can be determined first. Assuming that subchain A contains the component closest to the starting position, subchain A is the first subchain to be sorted, and when connecting, the component closest to the starting position can be connected to the starting position. After that, after expanding according to the connection order of subchain A, the first component at the end of subchain A can be determined. Then, based on the position of the first component, the second component closest to the target component is determined in subchains B and C. Assuming that the second component exists in subchain B, subchain B connects the second component to the first component. After that, after expanding according to the connection order of subchain B, the third component at the end of subchain B can be determined. Then, the connection of subchain C is completed in a similar manner to subchain B. That is, in some embodiments, the sorting of the at least one sub-chain includes: in response to a sub-chain that has not completed sorting, determining, based on the set position, that the sub-chain where the element closest to the starting position is located is the first sub-chain to be sorted; in response to the existence of a sub-chain that has completed sorting, determining that the element at the end of the sub-chain currently being sorted is the last element (which may correspond to the aforementioned first element), and, based on the set position, determining, that the sub-chain where the element closest to the last element (which may correspond to the aforementioned second element) is located is the next sub-chain currently being sorted.

[0062] From the above, it can be seen that the embodiment of the present disclosure provides a scan chain reordering method. The present disclosure first determines any scan chain through the chip design layout, and then determines the number of elements contained in the scan chain, and groups the elements contained in the scan chain according to the number of elements, and then reorders each group of elements according to the relevant reordering rules to generate multiple sub-chains corresponding to each group of elements, and finally splices these sub-chains to complete the reordering of the scan chain. This is equivalent to dividing the scan chain, reordering each of the divided sub-chains, and then splicing the reordered sub-chains to form a reordered scan chain. In this way, the overly long scan chain segments can be reordered, and the various groups of segments can be reordered in parallel using multi-threading and other methods, which can greatly optimize the running time of the scan chain reordering and improve the overall efficiency.

[0063] From the above, it can be seen that the present disclosure uses the K-means clustering algorithm accelerated by the Eigen template library to form sub-chains for scan chains containing a number of elements greater than a set threshold, and then uses a divide-and-conquer strategy to reorder the scan chains. The reordered sub-chains are then spliced ​​together, thereby efficiently and maximally reducing the wire length gain loss, thereby solving the problem of high computational complexity when reordering ultra-long scan chains (containing tens of thousands to hundreds of thousands of instances).

[0064] It should be noted that the methods of the embodiments of the present disclosure can be performed by a single device, such as a computer or server. The methods of the embodiments of the present disclosure can also be applied in a distributed scenario, performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the methods of the embodiments of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0065] It should be noted that the above description is of specific embodiments of the present disclosure. In some cases, the actions or steps described in the above embodiments of the present disclosure can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0066] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing a computer program stores computer instructions, and the computer instructions are used to enable the computer to execute method 400 described in any of the above embodiments.

[0067] The computer-readable storage media of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0068] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0069] Based on the same inventive concept, corresponding to method 400 in any of the above embodiments, this application also provides a computer program product comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform method 400. For the execution entities corresponding to the steps in each embodiment of method 400, the processors executing the corresponding steps may belong to the corresponding execution entities.

[0070] The computer program product of the above embodiment is used to enable a processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0071] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0072] In addition, to simplify the description and discussion, and to avoid obscuring the understanding of the embodiments of the present application, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the understanding of the embodiments of the present application, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (i.e., these details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations therefrom. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0073] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0074] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the above-described embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A scan chain reordering method, characterized in that: include: Obtain chip design layout; Determining a scan chain and a plurality of components included in the scan chain according to the chip design layout; Grouping the plurality of components according to the number of components to generate at least one component set; Reordering the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets; wherein the reordering includes adjusting connection relationships among components within the at least one set of component sets; splicing the at least one sub-chain to complete the reordering of the scan chain; The grouping according to the number of the plurality of elements comprises: determining distances between the plurality of elements; clustering the plurality of elements using a clustering algorithm according to the distance; The grouping is performed according to the clustering result.

2. The method according to claim 1, characterized in that The grouping according to the number of the plurality of elements comprises: Determine the set threshold; The number of groups is determined according to a ratio between the number and the set threshold.

3. The method according to claim 2, characterized in that After determining the number of groups according to the ratio between the number and the set threshold, the method further includes: The set number is increased based on the determined number of groups, thereby updating the number of groups.

4. The method according to claim 1, wherein Clustering the plurality of elements using a clustering algorithm according to the distance includes: The clustering algorithm is accelerated using the Eigen template library.

5. The method according to claim 1, wherein The clustering algorithm includes a K-means clustering algorithm.

6. The method according to claim 1, wherein The at least one sub-chain comprises an endless chain.

7. The method according to claim 1, characterized in that The step of splicing the at least one subchain comprises: Determining a starting position of the scan chain and arrangement positions of the plurality of components according to the chip design layout; Taking the starting position as an origin, sorting the at least one sub-chain according to the arrangement positions of the components included in the at least one sub-chain; According to the sorting result, the at least one subchain is spliced ​​in sequence with the starting position as the origin.

8. The method according to claim 7, characterized in that The sorting of the at least one subchain includes: In response to the sub-chains that have not completed sorting, determining, according to the setting position, the sub-chain where the element closest to the starting position is located as the first sub-chain to be sorted; In response to the existence of a sub-chain that has completed sorting, the element at the end of the sub-chain that is currently sorted is determined as the last element, and according to the set position, the sub-chain where the element closest to the last element is located is determined as the next sub-chain in the current sorting.

9. A computer device, characterized in that: The method comprises one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 8.

10. A non-volatile computer-readable storage medium containing a computer program, characterized in that When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 8.

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