Display device and driving method thereof

Abstract

The application provides a display device and a driving method thereof. A pixel driving circuit in the display device comprises a driving transistor connected between a first voltage line and a light-emitting element, a first reset transistor and a data writing transistor electrically connected to a gate of the driving transistor, a second reset transistor electrically connected to a source of the driving transistor, and a first switch transistor electrically connected between the first voltage line and a drain of the driving transistor. When the first reset transistor and the data writing transistor are sequentially turned on, the driving transistor is turned on, and the first switch transistor is turned on and turned off, respectively. The threshold voltage compensation effect of the driving transistor in the plurality of pixel driving circuits is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a driving method thereof. BACKGROUND

[0002] In the current self-luminous display product, when the pixel driving circuit works in the data writing stage, the driving transistor is in the on state, which causes the electrical conduction between the high-voltage signal line and the source of the driving transistor, and the potential of the source of the driving transistor is continuously charged by the high-voltage signal, resulting in that the gate-source voltage of the driving transistor contains a distortion voltage caused by the lifting of the source potential in the data writing stage in the light-emitting stage. The distortion voltage is related to the threshold voltage of the driving transistor, which weakens the compensation effect of the threshold voltage of the driving transistor in the pixel driving circuit. SUMMARY

[0003] The present application aims to provide a display device and a driving method thereof to improve the problem of weakened compensation effect of the threshold voltage of the pixel driving circuit in the current self-luminous display product.

[0004] Embodiments of the present application provide a display device, comprising a plurality of sub-pixels, each of the sub-pixels comprising a light-emitting element and a pixel driving circuit electrically connected to each other, wherein the pixel driving circuit comprises:

[0005] a driving transistor, one of a source and a drain of the driving transistor being electrically connected to a first voltage line, and the other being electrically connected to the light-emitting element;

[0006] a first reset transistor electrically connected to a gate of the driving transistor, for transmitting a first reset signal to the gate of the driving transistor according to a first control signal;

[0007] a second reset transistor electrically connected to the other of the source and the drain of the driving transistor, for transmitting a second reset signal to the other of the source and the drain of the driving transistor according to a second control signal;

[0008] a first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor, for controlling the formation of a current path between the first voltage line and one of the source and the drain of the driving transistor according to a third control signal;

[0009] a data writing transistor electrically connected to the gate of the driving transistor, for transmitting a data signal to the gate of the driving transistor according to a fourth control signal;

[0010] when the first reset transistor is turned on in response to the first control signal, the driving transistor is turned on, and the first switch transistor is turned on in response to the third control signal;

[0011] The driving transistor is turned on when the data write transistor is turned on in response to the fourth control signal.

[0012] In some embodiments, the second reset transistor is turned on in response to the second control signal before the first reset transistor is turned on in response to the first control signal.

[0013] In some embodiments, a pulse of the first control signal is in a same period as a pulse of the third control signal.

[0014] In some embodiments, the first switch transistor is turned on in response to the third control signal after the data write transistor is turned on in response to the fourth control signal.

[0015] In some embodiments, the pixel driving circuit further comprises:

[0016] A second switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor, for controlling a current path between the first voltage line and the one of the source and the drain of the driving transistor according to a fifth control signal;

[0017] The second switch transistor is turned off in response to the fifth control signal when the first switch transistor is turned off and the data write transistor is turned on.

[0018] The second switch transistor is turned on in response to the fifth control signal after the data write transistor is turned on in response to the fourth control signal.

[0019] In some embodiments, the pixel driving circuit further comprises:

[0020] A third switch transistor electrically connected between the light emitting element and the other one of the source and the drain of the driving transistor, for controlling a current path between the light emitting element and the other one of the source and the drain of the driving transistor according to the fifth control signal;

[0021] The third switch transistor is turned off in response to the fifth control signal when the second reset transistor is turned on in response to the second control signal.

[0022] In some embodiments, one of the anode and the cathode of the light emitting element is electrically connected to a second voltage line, and the other one is electrically connected to the other one of the source and the drain of the driving transistor.

[0023] The pixel driving circuit further comprises:

[0024] A third reset transistor electrically connected to the other one of the anode and the cathode of the light emitting element, for transmitting a third reset signal to the other one of the anode and the cathode of the light emitting element according to the second control signal.

[0025] In some embodiments, the data signal includes a plurality of data voltages corresponding to a plurality of the light emitting elements, and the fourth control signal includes a first gate pulse for controlling the corresponding data write transistor to be turned on;

[0026] The starting time of the first gate pulse is ahead of the starting time of the period in which the corresponding data voltage is located.

[0027] In some embodiments, the third control signal includes a second gate pulse for controlling the corresponding first switch transistor to be turned on;

[0028] The ending time of the second gate pulse is separated from the starting time of the first gate pulse by a time interval greater than or equal to 0.1xH, where H is the driving period of a row of the sub-pixels of the display device in a frame.

[0029] In some embodiments, the pulse width of the first gate pulse is different at different refresh rates.

[0030] Embodiments of the present application provide a driving method of a display device, which is applied to a pixel driving circuit and a light emitting element electrically connected in the display device, and the pixel driving circuit includes:

[0031] A driving transistor, one of the source and the drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light emitting element;

[0032] A first reset transistor electrically connected to the gate of the driving transistor;

[0033] A second reset transistor electrically connected to the other one of the source and the drain of the driving transistor;

[0034] A first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor;

[0035] A data write transistor electrically connected to the gate of the driving transistor;

[0036] The driving method of the display device includes:

[0037] In a first stage, the first reset transistor is turned on to transmit a first reset signal to the gate of the driving transistor in response to a first control signal, so as to turn on the driving transistor, and the first switch transistor is turned on in response to a third control signal;

[0038] In a second stage after the first stage, the data write transistor is turned on in response to the fourth control signal to enable the data signal to the driving transistor.

[0039] The present application provides a display device and a driving method thereof, by setting a first switch transistor electrically connected between the first voltage line and the drain of the driving transistor, and when the first reset transistor and the data write transistor are turned on in turn, the driving transistor is turned on, the first switch transistor is turned on and turned off respectively, so that the potential of the source of the driving transistor is raised to "Vref-Vth", and then the potential is maintained unchanged when the data voltage is written, avoiding the source of the driving transistor being continuously charged by the first voltage signal to raise the potential, so that the potential of the source of the driving transistor can compensate the threshold voltage of the driving transistor when the light emitting element emits light, and the compensation effect of the threshold voltage of the driving transistor in the multiple pixel driving circuits is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 The schematic diagram of the architecture of the display device provided by the embodiment of the present application is shown.

[0041] Figure 2 and Figure 3 The circuit diagram of the sub-pixel and the corresponding timing diagram provided by the comparative example of the present application are shown respectively.

[0042] Figure 4 and Figure 5 The circuit diagram of the sub-pixel and the corresponding timing diagram provided by an embodiment of the present application are shown respectively.

[0043] Figure 6 and Figure 7 The circuit diagram of the sub-pixel and the corresponding timing diagram provided by another embodiment of the present application are shown respectively.

[0044] Figure 8 The flow chart of the driving method of the display device provided by the embodiment of the present application is shown.

[0045] Figure 9 The potential curve diagram of the source of the driving transistor corresponding to multiple sub-pixels provided by the comparative example of the present application is shown. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0047] In the description of the application, it should be understood that the terms "first", "second" and the like are used only for descriptive purposes, and cannot be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited, and "electrically connected" means that the two are conductive, without limiting whether they are directly connected or indirectly connected.

[0048] In addition, it should be noted that the drawings provided are only structures and steps closely related to the application, and some details not closely related to the application are omitted, the purpose is to simplify the drawings and make the application points clear at a glance, and not to indicate that the actual device is exactly the same as the drawings, and is not a limitation on the actual device. Figure 1

[0049] The application provides a display device, which can include but is not limited to the following embodiments and combinations between the following embodiments.

[0050] In some embodiments, in combination with Figure 1 , Figure 4 and Figure 6 As shown in the drawings, the display device 100 includes a plurality of sub-pixels 10, which include an electrically connected light emitting element 101 and a pixel driving circuit 102, the pixel driving circuit 102 includes: a driving transistor T1, one of the source s and the drain d of the driving transistor T1 is electrically connected to a first voltage line (for transmitting a first voltage signal VDD), and the other is electrically connected to the light emitting element 101; a first reset transistor T2 electrically connected to the gate g of the driving transistor T1, for transmitting a first reset signal Vref to the gate g of the driving transistor T1 according to a first control signal REF; a second reset transistor T3 electrically connected to the other of the source s and the drain g of the driving transistor T1, for transmitting a second reset signal Vini to the other of the source s and the drain g of the driving transistor T1 according to a second control signal INI; a first switch transistor T4 electrically connected between the first voltage line and one of the source s and the drain d of the driving transistor T1, for controlling the formation of a current path between the first voltage line and one of the source s and the drain d of the driving transistor T1 according to a third control signal REF'; a data writing transistor T5 electrically connected to the gate g of the driving transistor T1, for transmitting a data signal Vdata to the gate g of the driving transistor T1 according to a fourth control signal Gn; as Figure 5 and Figure 6 ​As shown, when the first reset transistor T2 is turned on in response to the first control signal REF, the driving transistor T1 is turned on, and the first switch transistor T4 is turned on in response to the third control signal REF'; when the data writing transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switch transistor T4 is turned off in response to the third control signal REF'.

[0051] The display device 100 is, but not limited to, an organic self-luminous display device or an inorganic self-luminous direct-view display device. As shown in the following figure, Figure 1 As shown, the display device 100 can also include a plurality of gate lines 30, a plurality of data lines 40, a source driver 50 electrically connected to the plurality of data lines 40, and a gate driver 60 electrically connected to the plurality of gate lines 30. The plurality of gate lines 30 and the plurality of data lines 40, and the plurality of sub-pixels 10 can also be located on the substrate of the display panel 20, and the gate driver 60 can be a gate driving circuit located on the substrate of the display panel 20 or a chip independent of the display panel 20 (only the former is exemplified). Figure 1

[0052] Specifically, each gate line 30 is electrically connected to a plurality of pixel driving circuits 102 in the plurality of sub-pixels 10 in the corresponding row to output at least the corresponding fourth control signal Gn to the plurality of pixel driving circuits 102. In each frame, the fourth control signal Gn includes a first gate pulse p1 for controlling the corresponding plurality of pixel driving circuits 102 to be turned on, and the pixel driving circuits 102 in the plurality of rows of sub-pixels 10 are sequentially turned on under the control of the plurality of first gate pulses p1 in the plurality of fourth control signals Gn. Each data line 40 is connected to a plurality of pixel driving circuits 102 in the plurality of sub-pixels 10 in the corresponding column to output a corresponding data signal Vdata to the plurality of pixel driving circuits 102. The data signal Vdata includes a plurality of data voltages Vd1 corresponding to the corresponding plurality of sub-pixels 10 and an invalid voltage Vd2 located between adjacent two data voltages Vd1. The plurality of data signals Vdata corresponding to the plurality of columns of sub-pixels 10 are configured to transmit the corresponding plurality of data voltages Vd1 to the plurality of sub-pixels 10 in the corresponding row through the plurality of data lines 40 respectively when the plurality of sub-pixels 10 in each row are turned on. The invalid voltage Vd2 is used to separate the plurality of data voltages Vd1 to reduce the risk of incorrect charging of the data voltage Vd1.

[0053] ​Specifically, the gate driver 60 may include a multi-level gate driving module corresponding to multiple rows of sub-pixels 10. Each gate driving module includes multiple gate driving units for generating multiple gate signals. The multiple gate signals may include, but are not limited to, the first control signal REF, the second control signal INI, the third control signal REF', and the fourth control signal Gn mentioned above. That is, multiple sub-pixels 10 in the same row are controlled by multiple gate signals output by the same gate driving module. These multiple gate signals can control the on-time of multiple transistors in the multiple pixel driving circuits 102 of the same row, and together with multiple data signals Vdata output by the source driver 50, realize the light emission of the light-emitting element 101 in that row. In this way, the multiple row pixel driving circuits 102 operate sequentially under the control of the corresponding multiple gate driving modules and are sequentially loaded with multiple data voltages Vd1 corresponding to the multiple data signals Vdata, thereby displaying a frame of image.

[0054] It is important to note that, such as Figure 2 and Figure 3 As shown, the pixel circuits 1-2 in the comparative example provided by the present invention are compared with the above-mentioned... Figure 4 In the embodiment shown, the first switching transistor T4 is not disposed between the first voltage line and either the source s or the drain d of the driving transistor T1; that is, the two are electrically connected by a wire. Each sub-pixel 10 includes at least the following operating stages:

[0055] During the first comparison period t1', the second control signal INI is at the corresponding high potential, the second reset transistor T3 is turned on, and the second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it.

[0056] During the second comparison period t2' (including the first stage mentioned above), the second control signal INI and the first control signal REF are both at their corresponding high potentials. The second reset transistor T3 remains on, and the first reset transistor T2 is on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is on, and the first voltage signal VDD is transmitted through the driving transistor T1 to the source s of the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref-Vth".

[0057] During the third comparison period t3', the fourth control signal Gn is at a high potential, the data writing transistor T5 is turned on, and the data voltage Vd1 corresponding to the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 is still turned on, but because the first voltage line and the driving transistor T1 are electrically connected, the first voltage signal VDD keeps pulling up the potential of the source s of the driving transistor T1, causing the final gate-source voltage Vgs of the driving transistor T1 to be distorted by the ΔV raised by the source s of the driving transistor T1, resulting in Vgs being approximately Vdata-(Vref-Vth+ΔV).

[0058] During the fourth comparison period t4', the fourth control signal Gn is at a corresponding low potential. Data writing transistor T5 is cut off, and driving transistor T1 is turned on, forming a current path between the first and second voltage lines. Driving transistor T1 generates a driving current flowing through the light-emitting element 101, causing it to emit light. The magnitude of the driving current is approximately k×{[Vdata-(Vref-Vth)]-Vth} 2 ≈k×(Vdata-Vref-ΔV) 2 k is a constant.

[0059] Therefore, as Figure 9 As shown, a graph illustrating the potential Vs of the source s of the driving transistor T1 in multiple sub-pixels 10 of the same display panel 20 in a comparative example is presented. The horizontal axis represents the working time of the sub-pixel 10, and the vertical axis represents the potential Vs of the source s of the driving transistor T1.

[0060] Based on the analysis of the working stages of the comparative example above, it can be seen that during the third comparison period t3', since the first switching transistor T4 is not turned off to form a current break between the first voltage line and the source s of the driving transistor T1, that is, during the third comparison period t3' of the comparative example, the first voltage line and the source s of the driving transistor T1 have a current path. This causes the potential Vs of the source s of the driving transistor T1 of each sub-pixel 10 to be charged by the first voltage signal VDD, thus raising its potential. The degree of the rise is related to the threshold voltage Vth of each driving transistor T1. For example, L1 to L5 are five sub-pixels 10. The curve of the potential Vs of the source s of the driving transistor T1 shows that since the threshold voltage Vth of each of the five driving transistors T1 corresponding to L1 to L5 is different from the former, the potential Vs of the source s of the driving transistor T1 of each of L1 to L5 in the third comparison period t3 has differences of ΔV1, ΔV2, ΔV3, and ΔV4 respectively from the former. This results in the potential Vs of the source s of the five driving transistors T1 in the fourth period t4 still being different, ultimately causing the values ​​of the five corresponding driving currents to be different, making it impossible to effectively compensate for the threshold voltage Vth of all driving transistors T1.

[0061] wherein, as shown in FIG. 1, for the convenience of description, it is assumed that the source s of the driving transistor T1 is directly electrically connected to the second reset transistor T3, the drain d of the driving transistor T1 is directly electrically connected to the first switch transistor T4, all the transistors in the pixel driving circuit 102 are N-type transistors, and the first voltage signal VDD, the first reset signal Vref, and the second reset signal Vini are constant voltage signals, and each sub-pixel 10 at least includes the following working stages: Figure 4 to Figure 7

[0062] When the first reset transistor T2 is turned on in response to the first control signal REF, the driving transistor T1 is turned on, and the first switch transistor T4 is turned on in response to the third control signal REF’;

[0063] That is, when the first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset the potential thereof in response to the first reset transistor T2 being turned on in response to the first control signal REF, the gate-source voltage Vgs of the driving transistor T1 is greater than the threshold voltage Vth thereof at this time to turn on the driving transistor T1, and at the same time, the first switch transistor T4 is turned on in response to the potential of the third control signal REF’ at this time, the first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switch transistor T4 and the driving transistor T1 to charge the source s of the driving transistor T1, and the driving transistor T1 is turned off when the gate-source voltage Vgs of the driving transistor T1 is less than or equal to the threshold voltage Vth thereof, so the potential of the source s of the driving transistor T1 is “Vref-Vth”;

[0064] When the data write transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switch transistor T4 is turned off in response to the third control signal REF’;

[0065] That is, when the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1 to write the data voltage Vd1 into the gate g of the driving transistor T1 in response to the data write transistor T5 being turned on in response to the fourth control signal Gn, the gate-source voltage Vgs of the driving transistor T1 is also greater than the threshold voltage Vth thereof at this time to turn on the driving transistor T1, but at this time, the first switch transistor T4 is turned off in response to the potential of the third control signal REF’ at this time, and at this time, the first voltage signal VDD will not be transmitted to the source s of the driving transistor T1 to charge the source s of the driving transistor T1, that is, the potential of the source s of the driving transistor T1 is maintained as “Vref-Vth”, so the gate-source voltage Vgs of the driving transistor T1 is “Vd1-Vref+Vth”.

[0066] ​Understandably, in this embodiment, the second reset transistor T3 responds to the potential corresponding to the second control signal INI and resets the source s of the driving transistor T1 through the second reset signal Vini. When the first reset transistor T2 responds to the potential corresponding to the first control signal REF and resets the gate g of the driving transistor T1 through the first reset signal Vref, and responds to the potential corresponding to the fourth control signal Gn and writes the data voltage Vd1 to the gate g of the driving transistor T1 through the data voltage Vd1, the first switching transistor T4 is controlled to turn on and off sequentially. This allows the potential of the source s of the driving transistor T1 to rise to "Vref-Vth" and remain unchanged, preventing the source s of the driving transistor T1 from continuing to be charged by the first voltage signal VDD and causing its potential to rise. This allows the potential of the source s of the driving transistor T1 to compensate for the threshold voltage Vth of the driving transistor T1 when the light-emitting element 101 emits light, thus improving the compensation effect of the threshold voltage of the driving transistor T1 in the multiple pixel driving circuits 102.

[0067] In some embodiments, such as Figure 4 to Figure 7 As shown, before the first reset transistor T2 is turned on in response to the first control signal REF, the second reset transistor T3 is turned on in response to the second control signal INI. That is, before the first reset signal Vref resets the gate g of the driving transistor T1 through the first reset transistor T2, the second reset transistor T3 can be turned on in response to the second control signal INI, so that the second reset signal Vini resets the source s of the driving transistor T1. Therefore, it can be considered that when the first reset transistor T2 is turned on in response to the first control signal REF, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on.

[0068] Specifically, after multiple light-emitting elements 101 have stabilized and emitted light in the previous frame, the differences in the on-state voltage drop of different colored light-emitting elements 101 cause differences in the potential of the source s of different driving transistors T1. Therefore, it is necessary to reset the potential of the source s of all driving transistors T1 using the same second reset signal Vini. Furthermore, since the potential of the source s of all driving transistors T1 may affect the potential of the anode or cathode of the light-emitting element 101, resetting the potential of the source s of all driving transistors T1 first can ensure that multiple light-emitting elements 101 are turned off, avoiding false emission of light-emitting elements 101 when the gate g of the driving transistors T1 is reset later.

[0069] The pixel driving circuit 102 can further include a storage capacitor Cst electrically connected between the gate g and the source s of the driving transistor T1. The storage capacitor Cst is configured to maintain the voltage difference between the gate g and the source s of the driving transistor T1, thereby achieving the function of storing the threshold voltage Vth of the driving transistor T1, but not limited thereto.

[0070] In some embodiments, as shown in Figure 4 and Figure 5 , the time period in which the pulse of the first control signal REF is located is included in the time period in which the pulse of the third control signal REF' is located, or as shown in Figure 6 and Figure 7 , the time period in which the pulse of the first control signal REF is located is the same as the time period in which the pulse of the third control signal REF' is located. In this case, Figure 4 and Figure 6 , the potential corresponding to the pulse of the first control signal REF can turn on the first reset transistor T2 to reset the gate g of the driving transistor T1, and the potential corresponding to the pulse of the third control signal REF' can turn on the first switch transistor T4 to raise the potential of the source s of the driving transistor T1.

[0071] As discussed above, as shown in Figure 4 and Figure 5 , the embodiment sets the time period in which the pulse of the first control signal REF is located to be included in the time period in which the pulse of the third control signal REF' is located, so that in the period of resetting the gate g of the driving transistor T1, it is included in the stage of raising the potential of the source s of the driving transistor T1, so that the potential of the source s of the driving transistor T1 can be raised to "Vref-Vth".

[0072] Further, Figure 6 and Figure 7 , in order to save the types of signals, by reasonably setting the electrical characteristics of the first reset transistor T2 and the first switch transistor T4, the first control signal REF and the third control signal REF' can be the same signal, that is, the waveforms of the two can be the same, at this time, the time period in which the pulse of the first control signal REF is located and the time period in which the pulse of the third control signal REF' is located can be the same, and the above-mentioned functions can also be achieved.

[0073] It should be noted that, Figure 4 In the corresponding circuit diagram, the time period in which the pulse of the first control signal REF is located and the time period in which the pulse of the third control signal REF' is located can also be set to be the same, at this time, the above-mentioned functions can also be achieved.

[0074] In some embodiments, as shown in Figure 4 andFigure 5 As shown, after the data writing transistor T5 is turned on in response to the fourth control signal Gn, the first switching transistor T4 is turned on in response to the third control signal REF'. It can be understood that when only the first switching transistor T4 is connected in series between the first voltage line and the drain d of the driving transistor T1, after the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the first switching transistor T4 needs to be turned on to form a current path between the first voltage line and the drain d of the driving transistor, in preparation for forming the driving current. Therefore, the first switching transistor T4 can also function as a current path for forming the driving current in the pixel driving circuit 102.

[0075] In some embodiments, such as Figure 6 As shown, the pixel driving circuit 102 further includes: a second switching transistor T6, electrically connected between the first voltage line and one of the source s and drain d of the driving transistor T1, for controlling the formation of a current path between the first voltage line and one of the source s and drain d of the driving transistor according to the fifth control signal EM; as shown Figure 7 As shown, when the first switching transistor T4 (in response to the third control signal REF') is off and the data writing transistor T5 (in response to the fourth control signal Gn) is on, the second switching transistor T6 is off in response to the fifth control signal EM; after the data writing transistor T5 is on in response to the fourth control signal Gn, the second switching transistor T6 is on in response to the fifth control signal EM.

[0076] As discussed above, the first switching transistor T4 sequentially turns on and off when the data voltage Vd1 corresponding to the first reset signal Vref and the data signal Vdata is written to the gate g of the driving transistor T1. Based on this, in this embodiment, the second switching transistor T6 is also electrically connected between the first voltage line and one of the source s or drain d of the driving transistor T1. After the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the second switching transistor T6 turns on to form a current path between the first voltage line and the drain d of the driving transistor, preparing for the generation of the driving current. Therefore, by setting the second switching transistor T6, the function of providing the driving current in the pixel driving circuit 102 can be retained.

[0077] In particular, in order to ensure that a current break is formed between the first voltage line and the drain d of the driving transistor T1 when the above data voltage Vd1 is written, the second switching transistor T6 also needs to be cut off in response to the potential corresponding to the fifth control signal EM.

[0078] Further, as shown in Figure 6 The pixel driving circuit 102 further includes a third switch transistor T7 electrically connected between the light emitting element 101 and the other of the source s and the drain d of the driving transistor T1, for controlling the formation of a current path between the light emitting element 101 and the other of the source s and the drain d of the driving transistor T1 according to the fifth control signal EM. Figure 7 As shown, when the second reset transistor T3 is turned on in response to the second control signal INI, the third switch transistor T7 is turned off in response to the fifth control signal EM.

[0079] As can be known from the above description, the third switch transistor T7 and the second switch transistor T6 are both controlled to be turned on or turned off by the fifth control signal EM, i.e. both are turned off when the data voltage Vd1 is written on the first switch transistor T4, and are both turned on to form the current path of the driving current after the data voltage Vd1 is written. At the same time, since the third switch transistor T7 is electrically connected between the light emitting element 101 and the source s of the driving transistor T1, in order to avoid the second reset signal Vini affecting the potential of the anode or cathode of the light emitting element 101 when the source s of the driving transistor T1 is reset, thus causing the light emitting element 101 to emit light mistakenly, the third switch transistor T7 can be turned off at this time.

[0080] In some embodiments, as shown in Figure 6 One of the anode and the cathode of the light emitting element 101 is electrically connected to a second voltage line (for transmitting a second voltage signal VSS), and the other is electrically connected to the other of the source s and the drain d of the driving transistor T1; the pixel driving circuit 102 further includes a third reset transistor T8 electrically connected to the other of the anode and the cathode of the light emitting element 101, for transmitting a third reset signal Viano to the other of the anode and the cathode of the light emitting element 101 according to the second control signal INI.

[0081] For ease of description, the anode of the light emitting element 101 is electrically connected to the second reset transistor T3 (further electrically connected to the third reset transistor T8 and the third switch transistor T7), and the cathode of the light emitting element 101 is electrically connected to the second voltage line, and the third reset signal Viano and the second voltage signal VSS are also constant voltage signals, as an example for illustration.

[0082] As discussed above, the third reset transistor T8 and the second reset transistor T3 are controlled by the second control signal INI to be turned on or turned off, i.e., both are turned on at the same time before the first reset signal Vref resets the gate g of the driving transistor T1, so that the second reset signal Vini and the third reset signal Viano reset the source s of the driving transistor T1 and the anode of the light emitting element 101, respectively.

[0083] It should be noted that, since the driving transistor T1 needs to be turned on when the first reset signal Vref resets the gate g of the driving transistor T1 and the second reset signal Vini resets the source s of the driving transistor T1, i.e., the gate-source voltage Vgss of the driving transistor T1 needs to be greater than its threshold voltage Vth, the difference between the amplitudes of the second reset signal Vini and the first reset signal Vref is limited by the threshold voltage Vth. At the same time, since the third reset signal Viano needs to ensure that the light emitting element 101 is turned off when resetting the anode of the light emitting element 101, Viano < VSS + Vth oled, and Vth oled is the turn-on voltage of the light emitting element 101.

[0084] Therefore, in the embodiment, the second reset transistor T3, the third reset transistor T8, and the third switch transistor T7 are provided to reset the source s of the driving transistor T1 and the anode of the light emitting element 101, respectively, and when resetting both, the third switch transistor T7 can avoid interference between the potentials of the two, and the second reset transistor T3 and the third reset transistor T8 are both controlled by the second control signal INI, which can effectively reduce the number of signals.

[0085] In some embodiments, as shown in Figure 1 、 Figure 4 to Figure 7 The data signal Vdata includes a plurality of data voltages Vd1 corresponding to a plurality of light emitting elements 101, and the fourth control signal Gn includes a first gate pulse p1 for controlling the corresponding data write transistor T5 to be turned on; wherein the starting time of the first gate pulse p1 is ahead of the starting time of the period in which the corresponding data voltage Vd1 is located.

[0086] As shown in Figure 5 and Figure 7As shown, the pulse plotted by solid line in the fourth control signal Gn can be understood as the first comparative gate pulse p1' in the comparative example, and the pulse plotted by dashed line can be understood as the first gate pulse p1 in the embodiment. It can be observed that the starting time of the first comparative gate pulse p1' in the comparative example lags behind the starting time of the period in which the corresponding data voltage Vd1 is located, while in the embodiment, since the first switch transistor T4 and the second switch transistor T6 are both off during the period in which the first gate pulse p1 is located, the turn-on of the driving transistor T1 does not cause the potential of the source s of the driving transistor T1 to be charged by the first voltage signal VDD and thus the potential of the source s of the driving transistor T1 is not lifted.

[0087] Therefore, compared with the comparative example, the embodiment advances the starting time of the first gate pulse p1 to be ahead of the starting time of the period in which the corresponding data voltage Vd1 is located, which not only avoids the potential of the source s of the driving transistor T1 being charged by the first voltage signal VDD and thus the potential of the source s of the driving transistor T1 being lifted, but also increases the overlap length of the first gate pulse p1 and the period in which the corresponding data voltage Vd1 is located, so that the corresponding sub-pixel 10 has a larger charging time, which is conducive to the charging rate of the sub-pixel 10 under high refresh rate, especially under heavy load, and can support a higher refresh rate under the same resolution, or support a higher resolution under the same refresh rate.

[0088] Further, as shown in Figure 1 、 Figure 4 to Figure 7 , the third control signal REF' includes a second gate pulse p2 for controlling the turn-on of the corresponding first switch transistor T4; wherein the interval between the ending time of the second gate pulse p2 and the starting time of the first gate pulse p1 is greater than or equal to 0.1xH, and the H is the driving period of one row of sub-pixels 10 of the display device 100 in one frame.

[0089] , the driving period of one row of sub-pixels 10 of the display device 100 in one frame can be understood as the time length required for one row of pixel driving circuits 102 to be turned on to write at least the corresponding data voltage Vd in one frame, which can be calculated as follows: 1H = 1 / (refresh rate x vertical line number), and the vertical line number can include the sum of the number of rows of sub-pixels 10 in the display area of the display panel 20 and the number of virtual rows in the non-display area, for example, the display device 100 with a resolution of 1080p working at a refresh rate of 60Hz has a corresponding 1H time length of about 15.6 microseconds.

[0090] Of course, considering that a time is generally required between the data voltages Vd1 of two adjacent frames for the system to perform operations such as caching, it can be considered that 1H is slightly less than 1 / (refresh rate x vertical line number).

[0091] It can be understood that, based on the fact that the starting time of the first gate pulse p1 is ahead of the starting time of the corresponding data voltage Vd1, the interval between the starting time of the first gate pulse p1 and the ending time of the second gate pulse p2 is set to be greater than or equal to 0.1xH, so as to avoid the case that the first gate pulse p1 overlaps with the corresponding second gate pulse p2, and the data voltage Vd1 is written to the gate g of the driving transistor T1 before the potential of the source s of the driving transistor T1 reaches “Vref-Vth”, which causes the threshold voltage Vth to be not compensated in place.

[0092] Based on the above explanation of 1H, Figure 5 and Figure 7 The pulse width of the pulses of the signals and the interval of different pulses are also shown by H, but the above markings do not limit the waveforms of the signals of the present application.

[0093] Further, in combination with Figure 1 , Figure 4 and to Figure 7 It can be seen that the pulse width of the first gate pulse p1 is different under different refresh rates. As can be known from the above discussion, for the same display device 100, the time length reserved for the driving circuit 102 of a row of pixels to be turned on to write at least the corresponding data voltage Vd is different under different refresh rates. For high refresh rate, it can be considered that Figure 4 and Figure 6 The pulse width of the pulses of different signals is reduced compared with low refresh rate, and the time length for scanning a row of sub-pixels 10 is shorter, which is prone to the problem of insufficient charging.

[0094] It can be understood that, since the starting time of the first gate pulse p1 is ahead of the starting time of the corresponding data voltage Vd1, and as shown in Figure 5 and Figure 7 To avoid the problem of incorrect charging of the data voltage Vd1, the ending time of the first gate pulse p1 needs to be earlier than the ending time of the corresponding data voltage Vd1 by a certain time length, so it can be considered that the interval of the ending time of the corresponding data voltage Vd1 of different first gate pulses p1 is the same, so the starting time of the first gate pulse p1 can be set differently under different refresh rates, that is, the pulse width of the first gate pulse p1 can be set differently. For example, for high refresh rate, the pulse width of the first gate pulse p1 can be set to be larger, so that in the case that the pulse width of the first gate pulse p1 and the time length of the corresponding data voltage Vd1 are both small, the overlap time length of the two is set to be larger, so that the overlap time length of the first gate pulse p1 and the corresponding data voltage Vd1 under different refresh rates can be consistent, thereby improving the uniformity of the display device 100 under different refresh rates.

[0095] The present application provides a driving method of a display device, which is applied to a pixel driving circuit and a light emitting element electrically connected in the display device, the pixel driving circuit comprising: a driving transistor, one of a source and a drain of the driving transistor being electrically connected to a first voltage line, and the other being electrically connected to the light emitting element; a first reset transistor electrically connected to a gate of the driving transistor; a second reset transistor electrically connected to the other of the source and the drain of the driving transistor; a first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor; and a data writing transistor electrically connected to the gate of the driving transistor. The specific circuit of the pixel driving circuit and the connection mode thereof with the light emitting element can refer to the above Figure 1 、 Figure 4 to Figure 7 related discussions.

[0096] As shown in Figure 8 , the driving method of the display device comprises but is not limited to the following steps and the combination between the following steps.

[0097] S1, in a first stage, the first reset transistor is turned on in response to a first control signal to make a first reset signal transmitted to the gate of the driving transistor to make the driving transistor turned on, and the first switch transistor is turned on in response to a third control signal;

[0098] As can be known from the above discussion, in the first stage, the potential of the first control signal REF controls the first reset transistor T2 to be turned on, the first reset signal Vref is transmitted to the gate g of the driving transistor T1, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to make it turned on, at the same time, the potential of the third control signal REF' controls the first switch transistor T4 to be turned on, the first voltage signal VDD is transmitted to the source s of the driving transistor T1 until the driving transistor T1 is turned off, at this time, the potential of the source s of the driving transistor T1 is "Vref-Vth";

[0099] S2, in a second stage after the first stage, the data writing transistor is turned on in response to a fourth control signal to make a data signal transmitted to the gate of the driving transistor to make the driving transistor turned on, and the first switch transistor is turned off in response to the third control signal;

[0100] As discussed above, in the second stage, the potential control of the fourth control signal Gn turns on the data writing transistor T5, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. The gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on. However, at this time, the potential control of the third control signal REF' turns off the first switching transistor T4. At this time, the first voltage signal VDD will not be transmitted to the source s of the driving transistor T1, that is, the potential of the source s of the driving transistor T1 is maintained at "Vref-Vth". Therefore, the gate-source voltage Vgs of the driving transistor T1 is "Vd1-Vref+Vth".

[0101] To better illustrate the display device and its driving method provided by the present invention, in conjunction with... Figure 7 The timing diagram shown is for Figure 6 The working period of sub-pixel 10 shown is explained as follows:

[0102] During the first time period t1, the second control signal INI is at a corresponding high potential, and both the second reset transistor T3 and the third reset transistor T8 are turned on. The second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it, and the third reset signal Viano is transmitted to the anode of the light-emitting element 101 to reset it.

[0103] In the second time period t2 (including the first stage mentioned above), the second control signal INI, the first control signal REF, and the third control signal REF' are all at their corresponding high potentials. The second reset transistor T3 and the third reset transistor T8 remain on, and the first reset transistor T2 and the first switching transistor T4 are both on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is on, and the first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switching transistor T4 and the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref-Vth".

[0104] In the third time period t3 (including the second stage mentioned above), the fourth control signal Gn is at a high potential, the data writing transistor T5 is turned on, and the data voltage Vd1 corresponding to the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 is still turned on, but the first switching transistor T4 and the second switching transistor T6 are both turned off. The potential of the source s of the driving transistor T1 is maintained at "Vref-Vth", so the gate-source voltage Vgs of the driving transistor T1 is "Vd1-Vref+Vth".

[0105] In the fourth period t4, the fifth control signal EM is at a corresponding high level, the second switch transistor T6, the third switch transistor T7 and the drive transistor T1 are all turned on to form a current path between the first voltage line and the second voltage line, the drive transistor T1 generates a drive current flowing through the light emitting element 101, and the light emitting element 101 emits light, the size of the drive current is approximately k x {[Vdata-(Vref-Vth)]-Vth} 2 ≈k x (Vdata-Vref) 2 , k is a constant.

[0106] Referring to the above description of the first period t1 to the fourth period t4 shown in Figure 6 and Figure 7 , as shown in Figure 4 and Figure 5 , the following working stages can also be included:

[0107] In the first period t1, the second control signal INI and the third control signal REF' are both at a corresponding high level, and on the basis of resetting the source s of the drive transistor T1, the first voltage signal VDD is transmitted to the drain d of the drive transistor T1 to reset it;

[0108] In the second period t2 (including the first stage described above), the second control signal INI, the first control signal REF and the third control signal REF' are all at a corresponding high level, the second reset transistor T3 and the first switch transistor T4 are maintained in conduction, and the first reset transistor T2 is turned on, the first reset signal Vref is transmitted to the gate g of the drive transistor T1 to reset it, the drive transistor T1 is turned on, and the first voltage signal VDD is further transmitted to the source s of the drive transistor T1 through the drive transistor T1 to raise the potential of the source s of the drive transistor T1 until the drive transistor T1 is turned off, and the potential of the source s of the drive transistor T1 is "Vref-Vth";

[0109] In the third period t3 (including the second stage described above), the fourth control signal Gn is at a corresponding high level, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the drive transistor T1. Similarly, in the third period t3 described above Figure 7 , the gate-source voltage Vgs of the drive transistor T1 is finally "Vd1-Vref+Vth";

[0110] In the fourth period t4, the fourth control signal Gn and the third control signal REF' are both at the corresponding high level, the data writing transistor T5 is cut off, the driving transistor T1 and the first switch transistor T4 are both turned on to form a current path between the first voltage line and the second voltage line, the driving transistor T1 generates a driving current flowing through the light emitting element 101, the light emitting element 101 emits light, and the size of the driving current is approximately k x {[Vdata-(Vref-Vth)]-Vth} 2 ≈k x (Vdata-Vref) 2 , k is a constant.

[0111] It should be noted that, according to the above description, since Figure 4 the first switch transistor T4 is only connected in series between the first voltage line and the drain d of the driving transistor T1 in the fourth period t4 of the third period t3, Figure 5 the third control signal REF' needs to be set at the corresponding high level to form a current path between the first voltage line and the second voltage line.

[0112] The structure of the display device and the driving method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized by comprising: The pixel driving circuit comprises a plurality of sub-pixels, each of the sub-pixels comprising a light emitting element and a pixel driving circuit electrically connected to the light emitting element, the pixel driving circuit comprising: a driving transistor, one of a source and a drain of the driving transistor being electrically connected to a first voltage line, and the other being electrically connected to the light emitting element; a first reset transistor electrically connected to a gate of the driving transistor, for transmitting a first reset signal to the gate of the driving transistor according to a first control signal; a second reset transistor electrically connected to the other of the source and the drain of the driving transistor, for transmitting a second reset signal to the other of the source and the drain of the driving transistor according to a second control signal; a first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor, for controlling a current path between the first voltage line and one of the source and the drain of the driving transistor according to a third control signal; a data writing transistor electrically connected to the gate of the driving transistor, for transmitting a data signal to the gate of the driving transistor according to a fourth control signal; when the first reset transistor is turned on in response to the first control signal, the driving transistor is turned on, and the first switch transistor is turned on in response to the third control signal; when the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switch transistor is turned off in response to the third control signal; wherein a time period in which a pulse of the first control signal is located is included in a time period in which a pulse of the third control signal is located; or, the time period in which the pulse of the first control signal is located is the same as the time period in which the pulse of the third control signal is located; before the first reset transistor is turned on in response to the first control signal, the second reset transistor is turned on in response to the second control signal; the data signal comprises a plurality of data voltages corresponding to a plurality of the light emitting elements, and the fourth control signal comprises a first gate pulse for controlling a corresponding data writing transistor to be turned on; a starting time of the first gate pulse is ahead of a starting time of a time period in which a corresponding data voltage is located; the third control signal comprises a second gate pulse for controlling a corresponding first switch transistor to be turned on; an interval between an ending time of the second gate pulse and the starting time of the first gate pulse is greater than or equal to 0.1×H, and the H is a driving period of a row of the sub-pixels of the display device in one frame.

2. The display device of claim 1, wherein after the data writing transistor is turned on in response to the fourth control signal, the first switch transistor is turned on in response to the third control signal.

3. The display device of claim 1, wherein The pixel driving circuit further comprises: a second switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor, for controlling a current path between the first voltage line and one of the source and the drain of the driving transistor according to a fifth control signal; when the first switch transistor is turned off and the data writing transistor is turned on, the second switch transistor is turned off in response to the fifth control signal; The second switch transistor is turned on in response to the fifth control signal after the data writing transistor is turned on in response to the fourth control signal.

4. The display device of claim 3, wherein, The pixel driving circuit further comprises: a third switch transistor electrically connected between the light emitting element and the other one of the source and the drain of the driving transistor, for controlling a current path between the light emitting element and the other one of the source and the drain of the driving transistor according to the fifth control signal; The third switch transistor is turned off in response to the fifth control signal when the second reset transistor is turned on in response to the second control signal.

5. The display device of claim 4, wherein, One of the anode and the cathode of the light emitting element is electrically connected to a second voltage line, and the other one is electrically connected to the other one of the source and the drain of the driving transistor; The pixel driving circuit further comprises: a third reset transistor electrically connected to the other one of the anode and the cathode of the light emitting element, for transmitting a third reset signal to the other one of the anode and the cathode of the light emitting element according to the second control signal.

6. The display device of claim 1, wherein The pulse width of the first gate pulse is different at different refresh rates.

7. A driving method of a display device, comprising the steps of: The pixel driving circuit and the light emitting element are applied to the display device. a driving transistor, one of the source and the drain of the driving transistor is electrically connected to a first voltage line, and the other one is electrically connected to the light emitting element; a first reset transistor electrically connected to the gate of the driving transistor; a second reset transistor electrically connected to the other one of the source and the drain of the driving transistor; a first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor; a data writing transistor electrically connected to the gate of the driving transistor; The driving method of the display device comprises: In a first stage, the first reset transistor is turned on in response to a first control signal to transmit a first reset signal to the gate of the driving transistor to turn on the driving transistor, and the first switch transistor is turned on in response to a third control signal; In a second stage after the first stage, the data writing transistor is turned on in response to a fourth control signal to transmit a data signal to the gate of the driving transistor to turn on the driving transistor, and the first switch transistor is turned off in response to the third control signal; The pulse of the first control signal is located in the time period corresponding to the pulse of the third control signal. Alternatively, the pulse of the first control signal is located in the same time period as the pulse of the third control signal. The second reset transistor is turned on in response to a second control signal before the first reset transistor is turned on in response to the first control signal. The data signal comprises a plurality of data voltages corresponding to a plurality of light emitting elements, and the fourth control signal comprises a first gate pulse for controlling the corresponding data writing transistor to be turned on; The starting time of the first gate pulse is ahead of the starting time of the time period in which the corresponding data voltage is located. The third control signal comprises a second gate pulse for controlling the corresponding first switch transistor to be turned on; An interval between an ending moment of the second gate pulse and a starting moment of the first gate pulse is greater than or equal to 0.1xH, where H is a driving period of a row of sub-pixels of the display device in a frame.

Images