Display control method, display driving chip and electronic device

Abstract

This application discloses a display control method, a display driver chip, and an electronic device, relating to the field of image display, for implementing DDIC adaptive adjustment of the display screen's frame rate. The display control method includes: step S1, receiving image data; step S2, scanning the display screen according to the image data within a first scan interval in a first refresh period, where the first scan interval refers to the minimum time required to complete the scan of one frame of image; the period following the first scan interval in the first refresh period is a first hold interval; step S3, sending multiple tearing effect TE signals within the first hold interval, where the TE signals indicate that the image data has been refreshed; step S4, if new image data is received within the first hold interval, execution restarts from step S2.

Description

Technical Field

[0001] This application relates to the field of image display, and more particularly to a display control method, a display driver chip, and an electronic device. Background Technology

[0002] With the increasing popularity of organic light-emitting diode (OLED) displays such as low-temperature polycrystalline oxide (LTPO) displays and low-temperature poly-silicon (LTPS) displays, many electronic devices now support switching between different frame rates.

[0003] Traditionally, the upper layer determines the display's frame rate based on the application scenario of the electronic device and then sends commands to the display driver IC (DDIC) to set the display's frame rate. However, due to the large variety of applications (APPs) in the application layer, it is difficult to accurately identify the application scenario, thus making it impossible to accurately determine the display's frame rate. Alternatively, excessive latency in identifying the application scenario can lead to untimely frame rate switching, resulting in display stuttering and negatively impacting the user experience. Summary of the Invention

[0004] This application provides a display control method, a display driver chip, and an electronic device for implementing DDIC adaptive adjustment of the display screen's frame rate.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a display control method is provided, comprising: step S1, receiving image data; step S2, scanning the display screen according to the image data within a first scan interval in a first refresh period; the period following the first scan interval in the first refresh period is a first hold interval, the first scan interval referring to the minimum time required to complete the scanning of one frame of image; step S3, sending multiple tearing effect TE signals within the first hold interval, the TE signals being used to indicate that the image data has been refreshed; step S4, if new image data is received within the first hold interval, then execution restarts from step S2.

[0007] The display control method provided in this application sends multiple TE signals to the processor during the hold interval of the refresh period, instead of waiting until the end of the refresh period to send TE signals. The reciprocal of the time from the start of the scan interval of the refresh period to the completion of sending any TE signal equals a frame rate (the frame rate is essentially a frequency). When the processor needs the display screen to refresh at a certain frame rate, it does not need to directly instruct the DDIC to set the frame rate of the display screen; it only needs to send image data to the DDIC in fixed response to the TE signal corresponding to that frame rate. In other words, during the hold interval of the refresh period, the DDIC provides multiple TE signals for the processor to choose from with finer granularity. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate desired by the processor) determines the frame rate at which the DDIC refreshes the display screen, thereby realizing the DDIC's adaptive adjustment of the display screen's frame rate.

[0008] In one possible implementation, the method further includes: if no new image data is received within the first holding interval, then the image displayed on the screen is held for the first holding interval. Since the DDIC sends multiple TE signals within the first holding interval, it is possible to receive new image data within the first holding interval. If no new image data is received, the current frame is held, eliminating the need for frequent refreshes and thus reducing power consumption.

[0009] In one possible implementation, the method further includes sending a TE signal just before the first scan interval ends. At the end of the first scan interval, the DDIC can prepare to receive new image data. When new image data is received, it can return to the first scan interval for refreshing, thereby achieving the highest base frame rate (the reciprocal of the duration of the first scan interval).

[0010] In one possible implementation, if no new image data is received within the first hold interval, the method further includes: scanning the display screen based on the most recently received image data within a second scan interval of a second refresh period following the first refresh period; the period following the second scan interval of the second refresh period is the second hold interval; multiple TE signals are sent within the second hold interval; if new image data is received within the second hold interval, execution restarts from step S2. More frame rate options can be used for self-refresh.

[0011] In one possible implementation, the method further includes: if no new image data is received within the second holding interval, then the image displayed on the screen is held for the second holding interval. Since the DDIC sends multiple TE signals within the second holding interval, it is possible to receive new image data within the second holding interval. If no new image data is received, the current frame is held, eliminating the need for frequent refreshes and thus reducing power consumption.

[0012] In one possible implementation, the method further includes sending a TE signal just before the second scanning interval ends. At the end of the first scanning interval, the DDIC can be ready to receive new image data. When new image data is received, it can return to the first scanning interval for refreshing, thus shortening the DDIC response time.

[0013] In one possible implementation, the difference between the duration of the second hold interval and the duration of the first hold interval is m times the period of the TE signal, where m is a positive integer. The duration of the hold interval between different refresh periods is incremented by the period of the TE signal, so that the hold interval exactly accommodates an integer number of TE signal periods, thereby improving the utilization rate of the hold interval.

[0014] In one possible implementation, the period of the TE signal is k times the period of the emission (EM) signal, where k is a positive integer. The EM signal is used to control the illumination of pixels on the display screen. That is, the frequency of the EM signal is k times the frequency of the TE signal.

[0015] Secondly, a display control method is provided, comprising: step S1, the processor sending image data to the display driver chip DDIC; step S2, the DDIC scanning the display screen according to the image data within a first scan interval in a first refresh period; the period after the first scan interval in the first refresh period is a first hold interval; the first scan interval refers to the minimum time required to complete the scanning of one frame of image; step S3, within the first hold interval, the DDIC sending multiple tearing effect TE signals to the processor, the TE signals indicating that the image data has been refreshed; step S4, the processor responding to any TE signal within the first hold interval, sending new image data to the DDIC within the first hold interval; if the DDIC receives new image data within the first hold interval, execution restarts from step S2.

[0016] In one possible implementation, the method further includes: if the DDIC does not receive new image data within the first holding interval, then holding the image displayed on the screen within the first holding interval.

[0017] In one possible implementation, the DDIC also sends a TE signal to the processor just before the first scan interval is about to end.

[0018] In one possible implementation, if the DDIC does not receive new image data within the first holding interval, the method further includes: during the second scan interval of the second refresh period following the first refresh period, the DDIC scans the display screen based on the most recently received image data; the period following the second scan interval in the second refresh period is the second holding interval; during the second holding interval, the DDIC sends multiple TE signals to the processor; in response to any TE signal within the second holding interval, the processor sends new image data to the DDIC within the first holding interval; if the DDIC receives new image data within the second holding interval, execution restarts from step S2.

[0019] In one possible implementation, the method further includes: if the DDIC does not receive new image data during the second holding interval, then holding the image displayed on the screen during the second holding interval.

[0020] In one possible implementation, the DDIC sends a TE signal to the processor just before the second scan interval is about to end.

[0021] In one possible implementation, the difference between the duration of the second hold interval and the duration of the first hold interval is m times the period of the TE signal, where m is a positive integer.

[0022] In one possible implementation, the period of the TE signal is k times the period of the EM signal, where k is a positive integer, and the EM signal is used to control the illumination of the pixels on the display screen.

[0023] Thirdly, a display driver chip is provided, which is used to perform the methods described in the first aspect and any embodiment thereof.

[0024] Fourthly, an electronic device is provided, including a processor, a display screen, and a DDIC as described in the third aspect and any embodiment thereof. The processor is configured to send image data to the DDIC; the DDIC is configured to scan the display screen according to the image data within a first scan interval during a first refresh period; the period following the first scan interval during the first refresh period is a first hold interval; the first scan interval refers to the minimum time required to complete the scanning of one frame of image; the DDIC is further configured to send a plurality of tearing effect TE signals to the processor during the first hold interval, the TE signals indicating that the image data has been refreshed; the processor is further configured to send new image data to the DDIC during the first hold interval in response to any TE signal; the DDIC is further configured to return to the first scan interval during the first refresh period and scan the display screen according to the new image data if new image data is received during the first hold interval.

[0025] Fifthly, a computer-readable storage medium is provided, including instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in the first aspect and any embodiment thereof, or to perform the method as described in the second aspect and any embodiment thereof.

[0026] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on the aforementioned electronic device, cause the electronic device to perform the method as described in the first aspect and any embodiment thereof, or to perform the method as described in the second aspect and any embodiment thereof.

[0027] The technical effects of the second to sixth aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the structure of a display control circuit provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram illustrating the relationship between a tearing effect (TE) signal and the frame rate of a display screen, provided for an embodiment of this application;

[0031] Figure 4 A schematic diagram illustrating a display screen refreshing line by line, provided as an embodiment of this application;

[0032] Figure 5 This is a schematic diagram illustrating how DDIC sequentially refreshes itself according to different frame rates, as provided in an embodiment of this application.

[0033] Figure 6 A schematic diagram of a software architecture provided for an embodiment of this application;

[0034] Figure 7 A schematic diagram illustrating a method for switching the frame rate of a display screen, provided as an embodiment of this application;

[0035] Figure 8 A schematic diagram of a display control method provided in an embodiment of this application;

[0036] Figure 9 A schematic diagram illustrating a TE signal transmission frequency provided in an embodiment of this application;

[0037] Figure 10 A schematic diagram illustrating another TE signal transmission frequency provided in an embodiment of this application;

[0038] Figure 11 A schematic diagram of another software architecture provided for an embodiment of this application;

[0039] Figure 12 This is a schematic diagram of another display control method provided in an embodiment of this application. Detailed Implementation

[0040] First, some concepts involved in this application will be described.

[0041] The terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0042] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0043] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0044] This application provides an electronic device with a display screen. The electronic device can be mobile or fixed. It can be deployed on land (e.g., indoors or outdoors, handheld or vehicle-mounted), on water (e.g., on ships), or in the air (e.g., airplanes, balloons, and satellites). This electronic device can be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device. For example, it can be a mobile phone, tablet computer, laptop computer, smart bracelet, smart screen, smartwatch, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical care, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. This application does not limit the specific type and structure of the electronic device. The following describes one possible structure of the electronic device.

[0045] Taking mobile phones as an example, Figure 1 A possible structure of an electronic device 101 is shown. This electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, antenna 1, antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, it may also include an audio digital signal processor (ADSP) 243.

[0046] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 101. In other embodiments of this application, the electronic device 101 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0047] Processor 210 may include one or more processing units, such as: a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a baseband processor, and a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, processor 210 may be an application processor (AP). Alternatively, processor 210 may be integrated into a system-on-chip (SoC). Or, processor 210 may be integrated into an integrated circuit (IC) chip. The processor 210 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0048] The processor 210 executes the display control method provided in this application embodiment by executing the program and computer instructions stored in the internal memory 221.

[0049] The processor 210 may also include a memory for storing computer instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. This memory can store computer instructions or data that the processor 210 has just used or that are being used repeatedly. If the processor 210 needs to use the same computer instructions or data again, it can retrieve them directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 210, and thus improves system efficiency.

[0050] In some embodiments, the processor 210 may include one or more interfaces. These interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0051] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can process audio signals and sensor data. Even when the processor is in sleep mode, the ADSP 243 can remain operational, thereby reducing the power consumption of the electronic device.

[0052] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 101. In other embodiments of this application, the electronic device 101 may also adopt different interface connection methods or a combination of multiple interface connection methods as described in the above embodiments.

[0053] The wireless communication function of electronic device 101 can be realized through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, modem processor and baseband processor.

[0054] Antennas 1 and 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 101 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0055] Mobile communication module 250 can provide wireless communication solutions including 2G / 3G / 4G / 5G for use on electronic device 101. Wireless communication module 260 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) for use on electronic device 101. In some embodiments, antenna 1 of electronic device 101 is coupled to mobile communication module 250, and antenna 2 is coupled to wireless communication module 260, enabling electronic device 101 to communicate with networks and other devices via wireless communication technology.

[0056] The external storage interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 101. The external memory card communicates with the processor 210 through the external storage interface 220 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0057] Internal memory 221 can be used to store computer executable program code, which includes computer instructions. Processor 210 executes various functional applications and data processing of electronic device 101 by running the computer instructions stored in internal memory 221. In addition, internal memory 221 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0058] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0059] Electronic device 101 can implement audio functions such as music playback and recording through audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone jack 270D, and application processor.

[0060] Audio module 270 is used to convert digital audio information into analog audio signal output, and also to convert analog audio input into digital audio signal. In some embodiments, audio module 270 may be located in processor 210, or some functional modules of audio module 270 may be located in processor 210. Speaker 270A, also called a "loudspeaker," is used to convert audio electrical signals into sound signals. Receiver 270B, also called a "handpiece," is used to convert audio electrical signals into sound signals. Microphone 270C, also called a "microphone" or "microphone," is used to convert sound signals into electrical signals. Electronic device 101 may be equipped with at least one microphone 270C. Headphone jack 270D is used to connect wired headphones. Headphone jack 270D may be a USB interface 230, or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, or a Cellular Telecommunications Industry Association of the USA (CTIA) standard interface.

[0061] Buttons 290 include a power button, volume buttons, etc. Buttons 290 can be mechanical buttons or touch buttons. Electronic device 101 can receive button input and generate key signal inputs related to user settings and function control of electronic device 101. Motor 291 can generate vibration alerts. Motor 291 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 292 can be an indicator light, used to indicate charging status, battery level changes, messages, missed calls, notifications, etc. SIM card interface 295 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with electronic device 101. Electronic device 101 can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. In some embodiments, electronic device 101 employs an embedded SIM (eSIM) card, which can be embedded in electronic device 101 and cannot be separated from electronic device 101.

[0062] Electronic device 101 can implement shooting functions through an ISP, camera 293, video codec, GPU, display 294, and application processor. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be set in the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, electronic device 101 may include one or N cameras 293, where N is a positive integer greater than 1.

[0063] Electronic device 101 can implement display functions through a GPU, display screen 294, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 210 may include one or more GPUs, which execute computer instructions to generate or modify display information.

[0064] The sensor module 280 may include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, an angle sensor, etc. When the display screen 294 is a foldable screen, the angle sensor can detect the folding angle of the display screen 294, which ranges from 0 to 180 degrees.

[0065] Battery 241 may include one or more batteries to power a load.

[0066] The power management module 240 is used to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock, or other electronic device 101 with reverse wireless charging capability. The power management module 240 can receive wireless charging input via the wireless charging coil 242 of the electronic device. The charger can also be a wired charger; for example, the power management module 240 can receive charging input from a wired charger via a USB interface 230. The power management module 240 is also referred to as a charging chip.

[0067] The power management module 240 charges the battery 241 while simultaneously supplying power to the electronic devices. It receives input from the battery 241 and powers the processor 210, internal memory 221, external memory interface 220, display screen 294, camera 293, and wireless communication module 260. The power management module 240 can also monitor parameters such as the battery 241's capacity, voltage, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 240 may also be integrated into the processor 210.

[0068] Display screen 294 is used to display images, videos, etc. Display screen 294 includes a display panel. In some embodiments, electronic device 101 may include one or more display screens 294. The display screen involved in the embodiments of this application may be a variable frame rate OLED display screen. With the popularization of OLED displays such as LTPO displays and LTPS displays, many OLED displays can support switching between different frame rates. In particular, LTPO displays support lower frame rates, such as 120Hz, 90Hz, 30Hz, 10Hz, and even 1Hz flicker-free frame rate. The reason is that OLED displays include thin film transistors (TFTs) for driving pixels to emit light. However, TFTs in LTPS displays are prone to leakage, while TFTs in LTPO displays use indium gallium zinc oxide (IGZO) technology, which makes the leakage current generated through the TFT after the capacitor coupled to the TFT gate is fully charged very small. This ensures that the voltage applied to the TFT gate can be kept constant for a long time, and the pixels driven by the TFT can continue to emit light for a long time, thereby achieving a very low frame rate.

[0069] like Figure 2 As shown, the display screen 294 can be connected to the display driver IC (DDIC) 31 via a flexible circuit board. The processor 210 sends image data to the DDIC 31 through the display serial interface (DSI), and the DDIC 31 refreshes the image displayed on the display screen 294 based on the image data. Figure 2 and Figure 3 As shown, after refreshing one frame of image data, DDIC 31 sends a frame synchronization signal—a tearing effect (TE) signal—to processor 210. The TE signal indicates that one frame of image data has been refreshed. After completing the rendering and composition of the next frame of image data, processor 210 will not send the next frame of image data to DDIC 31 until it receives the TE signal corresponding to the previous frame of image data. Therefore, the frequency of the TE signal changes with the frame rate of display screen 294.

[0070] The TE signal enables frame synchronization between the processor 210 and the DDIC 31, preventing image data sent by the processor 210 to the DDIC 31 from being out of sync with the image data refreshed by the DDIC 31 to the display screen 294, thus preventing display tearing on the display screen 294 (where part of the display screen 294 displays the previous frame while the rest displays the next frame). Figure 4As shown, since the display screen 294 refreshes one frame of image line by line, the DDIC 31 cannot send the TE signal too early. Otherwise, if it receives new image data before completing the refresh of the previous frame, the aforementioned display tearing problem will occur. Ideally, the DDIC 31 should receive the image data of the next frame immediately after completing the refresh of the previous frame, thus starting the refresh of the next frame. Therefore, the DDIC 31 can send the TE signal as early as when refreshing the last few rows of pixels on the display screen 294, so that the DDIC 31 can receive new image data earlier.

[0071] DDIC 31 may include graphics random access memory (GRAM) or may not include GRAM. This application uses DDIC 31 with GRAM as an example for illustration, but it is not intended to be limited thereto.

[0072] When DDIC 31 does not include GRAM, the display screen 294 is called a video display screen. DDIC 31 cannot store image data and cannot achieve self-refresh of display screen 294. Only after processor 210 sends image data to DDIC 31 can DDIC 31 refresh the image displayed on the display screen according to the image data.

[0073] When DDIC 31 includes GRAM, the GRAM can be used to store image data, enabling self-refreshing of display screen 294. In this case, display screen 294 is called a command display screen. After the processor 210 completes the drawing and synthesis of a frame of image data, it sends a command to DDIC 31 only after receiving the TE signal, indicating that image data to be written to the GRAM in DDIC 31 is to be written, along with the position coordinates of the image data to be written. Then, the processor 210 writes the image data to the GRAM in DDIC 31, and DDIC 31 reads the image data from the GRAM to refresh the image displayed on display screen 294. If the processor 210 does not send new image data to DDIC 31, DDIC 31 can automatically read the image data of the previous frame from the GRAM and continuously refresh display screen 294 to display the previous frame, thus achieving self-refreshing of display screen 294.

[0074] like Figure 5As shown, in the prior art, when the processor 210 does not send new image data to the DDIC 31, the DDIC 31 continuously refreshes the previous frame image according to the frame rate corresponding to different sequences (essentially different refresh periods). Typically, the frame rates corresponding to different sequences can be set differently; for example, the frame rates for each sequence can gradually decrease, thereby reducing power consumption while maintaining image smoothness. Furthermore, a repetition count can be set for each sequence, indicating the number of times the self-refresh is repeated according to the frame rate corresponding to that sequence. That is, the DDIC 31 can continuously perform multiple self-refreshes at the same frame rate. After each self-refresh is completed, the DDIC 31 sends a TE signal to the processor 210.

[0075] For example, different sequences can include sequences 1 to 8, etc., and the specific sequence is not limited. Taking sequences 1 to 5 as an example, the frame rate of sequence 1 can be set to 120 Hz and the number of repetitions is 0 (i.e., perform 1 self-refresh at this frame rate); the frame rate of sequence 2 is 60 Hz and the number of repetitions is 2 (i.e., perform 3 self-refreshes at this frame rate); the frame rate of sequence 3 is 30 Hz and the number of repetitions is 2 (i.e., perform 3 self-refreshes at this frame rate); the frame rate of sequence 4 is 10 Hz and the number of repetitions is 2 (i.e., perform 3 self-refreshes at this frame rate); the frame rate of sequence 5 is 1 Hz and the number of repetitions is 2 (i.e., perform 3 self-refreshes at this frame rate). In fact, the frame rates at which DDIC 31 refreshes itself from sequence 1 to sequence 5 are as follows: 120hz->60hz->60hz->60hz->30hz->30hz->30hz->10hz->10hz->10hz->5hz->5hz->5hz->1hz->1hz->1hz.

[0076] The time required to complete one refresh is called a refresh period, therefore a sequence may include one or more refresh periods. Each refresh period includes at least a scan interval, and optionally a hold interval. During the scan interval, DDIC 31 scans the display screen line by line based on the most recently received image data, i.e., controls the TFTs of the driving pixels to turn on line by line. The scan interval is the minimum time required to complete the scan of one frame of image; the reciprocal of the scan interval is called the base frame rate (or base frequency). This means that regardless of how the display screen's frame rate switches, the display screen's frame rate will not exceed the base frame rate; otherwise, there would not be enough time to complete the scan of one frame of image. During the hold interval, DDIC 31 holds the image displayed on the display screen, i.e., controls the TFTs of the driving pixels to remain in the on state after the scan, so that the display screen continuously displays the most recent frame of image.

[0077] If DDIC 31 does not receive new image data from processor 210 after performing a self-refresh of the last refresh period of the last sequence (e.g., the third refresh period of sequence 5), DDIC 31 will maintain the refresh rate of that sequence (e.g., 1 Hz) to achieve self-refresh with minimal power consumption. If new image data is received from processor 210 during the self-refresh process of DDIC 31, it will jump back to the first sequence and repeat the above process.

[0078] Besides DDIC 31 controlling the display's self-refresh at a certain frame rate, processor 210 can also control DDIC 31 to switch the display's frame rate. For example, when a user performs a swipe operation on the display, a frame rate of 120Hz or 90Hz is desired to avoid display stuttering. When displaying video, a frame rate of 60Hz or 30Hz is desired to reduce power consumption while ensuring smooth image display. When displaying still images, the frame rate is further reduced. For example, when the video includes on-screen display (OSD) elements such as bullet comments and user experience (UX) interactions, a frame rate of 60Hz is desired; when the video lacks bullet comments or UX elements, a frame rate of 30Hz is desired, and so on. The frame rate switching control logic is relatively complex and requires the display's frame rate to switch rapidly.

[0079] The following section explains, from the perspective of the processor 210's software architecture, how the processor 210 executes the frame rate switching control logic in the prior art.

[0080] From a software architecture perspective, the programs run by the processor 210 can be based on an operating system, such as... Etc. For example Figure 6 As shown, the program running on processor 210 is based on For example, the programs running on the processor 210 are layered according to their functions, which may include the kernel layer, the hardware abstraction layer (HAL), and the application layer.

[0081] The kernel layer includes the operating system (OS) kernel and hardware drivers that drive hardware resources, such as display drivers. The OS kernel manages system processes, memory, drivers, file systems, and network systems. The display driver facilitates communication between the processor 210 and the DDIC 31. HAL provides a set of device function interface specifications to implement a virtual hardware platform that abstracts the hardware, hiding hardware interface details, making the code hardware-independent and portable across multiple platforms. For example, HAL includes a rendering service (SurfaceFlinger), which periodically renders and draws image data. The application layer can include apps that need to display images, such as photo album apps and video apps.

[0082] like Figure 6 and Figure 7 As shown, in the prior art, the control logic for switching the display frame rate in the processor 210 is as follows: The application layer APP in the processor 210 performs drawing and rendering to obtain image data, and sends it to the rendering service (SurfaceFlinger). The rendering service (SurfaceFlinger) identifies the application scenario of the electronic device (e.g., the user performing a swipe operation on the display screen, or displaying video, or displaying a static image, as mentioned above), determines the frame rate of the display screen based on the identified application scenario, and sends a frame rate setting command and image data to the DDIC 31 through the display driver. The frame rate setting command instructs the DDIC 31 to set the display frame rate. The DDIC 31 sets the display frame rate according to the frame rate setting command. After refreshing one frame of image based on the image data, it sends a TE signal to the processor 210. The frequency of the TE signal is equal to the frame rate of the display screen. The display driver sends a vertical synchronization (VSYNC) signal to the APP through the rendering service (SurfaceFlinger). The frequency of the VSYNC signal is equal to the frequency of the TE signal, which is also equal to the frame rate of the display screen. After receiving the VSYNC signal, the APP draws and renders a frame of image to obtain new image data, and sends it to the rendering service (SurfaceFlinger) to refresh the next frame of image, thereby realizing frame synchronization between the processor 210 and DDIC 31.

[0083] However, due to the large variety of applications (APPs) in the application layer, the rendering service (SurfaceFlinger) has difficulty accurately identifying the application scenario, thus failing to accurately determine the display's frame rate. Alternatively, the latency in identifying the application scenario may be too high, causing the display's frame rate to switch untimely, resulting in stuttering on the display and affecting the user experience.

[0084] This application provides a display control method in which the DDIC sends multiple TE signals to the processor during the hold interval of the self-refreshing sequence 1, instead of waiting until the self-refresh of the sequence is completed before sending TE signals. The reciprocal of the time from the start of the scan interval of sequence 1 to the completion of sending any TE signal equals a frame rate (the frame rate is essentially a frequency). When the processor needs the display to refresh at a certain frame rate, it does not need to instruct the DDIC to set the display's frame rate; it only needs to send image data to the DDIC in fixed response to the TE signal corresponding to that frame rate. In this way, the DDIC receives image data according to that frame rate (i.e., frequency) and, after each reception of image data, jumps back to the scan interval of sequence 1 to scan the display based on the new image data. That is, during the hold interval of sequence 1, the DDIC provides multiple TE signals for the processor to choose from with finer granularity. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display in response to the received new image data. In other words, the frequency at which the processor sends image data (i.e., the frame rate desired by the processor) determines the frame rate at which the DDIC refreshes the display, thereby achieving adaptive adjustment of the display's frame rate by the DDIC. like Figure 8 As shown, the display control method includes:

[0085] S1. The processor sends image data to the DDIC.

[0086] Accordingly, DDIC receives image data from the processor.

[0087] S2. In the first scan interval of the first refresh period, the DDIC scans the display screen line by line based on the most recently received image data.

[0088] The first refresh period is sequence 1 as mentioned above. For example... Figure 9 and Figure 10As shown, the first refresh period includes a first scan interval and a first hold interval following the first scan interval. During the first scan interval, the DDIC scans the display screen line by line based on the most recently received image data to complete the scan of one frame. If no new image data is received during the first refresh period, the DDIC holds the image displayed on the screen during the first hold interval, that is, it controls the TFTs driving the pixels to maintain their on-state after scanning, and the display screen continues to display the most recent frame.

[0089] The duration of the first refresh period is equal to the reciprocal of the lowest frame rate in sequence 1. For example, as... Figure 9 and Figure 10 As shown, assuming a minimum frame rate of 30Hz in the most common application scenario, the duration of the first refresh interval is equal to 33.33ms. The duration of the first scan interval is equal to the reciprocal of the base frame rate. For example, as... Figure 9 and Figure 10 As shown, assuming a base frame rate of 120Hz, the duration of the first scan interval is 8.33ms. The base frame rate is described above and will not be repeated here.

[0090] S3. During the first refresh period, DDIC sends multiple TE signals to the processor.

[0091] like Figure 9 As shown, DDIC can send multiple TE signals to the processor during the entire first refresh period, which can be referred to as high-frequency TE signals (e.g., 360Hz). Or, as... Figure 10 As shown, the DDIC can send a TE signal A (e.g., 120 Hz) to the processor just before the end of the first scan interval, and send multiple high-frequency TE signals (e.g., 360 Hz) to the processor during the first hold interval, thereby forming a hybrid TE signal including different frequencies (e.g., 120 Hz and 360 Hz). The frequency of the TE signal refers to the reciprocal of the time between sending two adjacent TE signals.

[0092] Multiple TE signals can be transmitted at equal intervals, thus exhibiting periodic transmission. Figure 9 (as shown); or, multiple TE signals do not exhibit periodic transmission or exhibit partially periodic transmission (as shown). Figure 10 (as shown), etc. This application uses the periodic or partial periodic transmission of multiple TE signals as an example, but is not intended to be limited thereto. The period of the TE signal is k times the period of the transmission (EM) signal, where k is a positive integer. For example, Figure 9 In this example, the period of the TE signal is one time the period of the ordinary EM signal and six times the period of the high-frequency EM signal. The duration of the first hold interval is n times the period of the TE signal, where n is a positive integer. For example, Figure 9 and Figure 10 In this case, the duration of the first hold interval is 9 times the period of the TE signal.

[0093] The EM signal is used to control the on and off states of the TFTs in the OLED driving circuit, thereby controlling whether the pixels emit light. Since TFTs are typically P-channel metal-oxide-semiconductor (PMOS) structures, when the EM signal is high, the TFT is off, preventing the TFT-driven OLED pixels from emitting light; when the EM signal is low, the TFT is on, allowing the TFT-driven OLED pixels to emit light.

[0094] When using direct current (DC) dimming, the EM signal is low, and the OLED brightness is adjusted by regulating the power of the OLED driver circuit. When using pulse width modulation (PWM) dimming, the EM signal can be a PWM signal with a variable duty cycle, and the OLED brightness is adjusted by regulating the duty cycle of the EM signal. For PWM dimming, since the scanning actions such as refreshing, resetting, compensating, and charging each row of OLED pixels are performed when the OLED pixels are not emitting light (i.e., the EM signal is high), the frequency of the TE signal is a multiple of the frequency of the EM signal. That is, the frequency of the EM signal is k times the frequency of the TE signal, or the period of the TE signal is k times the period of the EM signal, where k is a positive integer.

[0095] For example, assuming the base frame rate (the reciprocal of the scanning interval duration) mentioned above is 120 Hz, and high-frequency PWM dimming requires 18 EM signal pulses to complete the scanning of one frame of image, then the frequency of the EM signal is 2160 Hz (120 * 18 = 2160 Hz), the frequency of the TE signal can be 360 ​​Hz, and the duration of the TE signal is 1 / 360 = 2.778 ms. The duration of each TE signal corresponds to the duration of 6 EM signals.

[0096] It should be noted that this application is not limited to the above example with a base frame rate of 120Hz and a TE signal frequency of 360Hz. The base frame rate and the TE signal frequency can be flexibly set according to actual product requirements. For example, the base frame rate can also be 90Hz, 144Hz, etc., and the TE signal frequency can also be 120Hz, 240Hz, 360Hz, 480Hz, etc.

[0097] in addition, Figure 10 The scheme shown is relative to Figure 9 The advantages of the proposed solution are: Figure 9This scheme enables the DDIC to receive new image data during the hold interval (e.g., the first hold interval) but not during the scan interval (e.g., the first scan interval). The reason is that even if the DDIC sends a TE signal during the scan interval, causing it to receive new image data, the DDIC cannot respond and refresh the image data; otherwise, it would interrupt the current scanning process, leading to image tearing or other display anomalies. Instead, it waits until entering the hold interval to process the image data. This effectively avoids the risk of abnormal interruption of the DDIC during scanning within the scan interval.

[0098] S4. In response to any TE signal during the first refresh period, the processor sends new image data to the DDIC during the first refresh period. If the DDIC receives new image data during the first refresh period, it restarts execution from step S2 after a first preset time.

[0099] like Figure 11 As shown, after DDIC 31 sends a high-frequency TE signal or a mixed TE signal to processor 210, the display driver of processor 210 responds to any TE signal among multiple TE signals (e.g., the most recently received TE signal) by sending a vertical synchronization (VSYNC) signal to the application through the rendering service (SurfaceFlinger). The frequency of the VSYNC signal is equal to the frame rate that the processor expects the display to refresh, such as 120Hz, 90Hz, or 60Hz. After receiving the VSYNC signal, the application draws and renders a frame of image to obtain new image data, and after receiving the TE signal corresponding to the required frame rate, sends the new image data to the rendering service (SurfaceFlinger), which in turn sends it to the display driver. The display driver then sends the new image data to DDIC 31. DDIC can then refresh the display according to the frequency of image data transmission. Figure 6 The traditional solution shown offers a more timely response and better performance.

[0100] The first preset time refers to the latest of the following two times: the time when the image data was most recently received, and the time when the first hold interval begins.

[0101] In other words, if the DDIC receives new image data within the first scanning interval, it waits for the first scanning interval to end to complete the scanning of the previous frame before restarting from step S2 to re-enter the first scanning interval and scan the next frame. If the DDIC receives new image data within the first holding interval, it can directly stop holding the previous frame and restart from step S2, i.e., re-enter the first scanning interval to scan the next frame.

[0102] The following is combined with Figure 9 or Figure 10 The example illustrates the above display control method.

[0103] After receiving image data from the processor, the DDIC begins refreshing the display screen according to sequence 1 (corresponding to the first refresh period). First, the DDIC completes the scan of the display screen within the first scan interval, and sends a TE signal A (with a frequency of 120 Hz) to the processor just before the first scan interval ends. When the processor responds to this TE signal A by sending image data to the DDIC, the processor also sends image data at a frequency of 120 Hz. After the TE signal A, the DDIC receives new image data from the processor, re-enters the first scan interval, and completes the scan of a new frame of image. At this point, the display screen's frame rate adaptively becomes 120 Hz.

[0104] If the TE signal A of the DDIC is not responded to by the processor, a TE signal is periodically sent to the processor within the first hold interval. When the processor responds to the TE signal B (which has a frequency of 90 Hz) within the first hold interval and sends new image data to the DDIC, the processor is actually sending image data at a frequency of 90 Hz. After receiving the new image data from the processor following the TE signal B, the DDIC re-enters the first scan interval and completes the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 90 Hz.

[0105] Similarly, when the processor responds to the TE signal C (which has a frequency of 60 Hz) within the first holding interval and sends new image data to the DDIC, the processor is actually sending image data at a frequency of 60 Hz. After receiving the new image data from the processor following the TE signal C, the DDIC re-enters the first scanning interval and completes the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 60 Hz.

[0106] When the processor responds to the TE signal D (with a frequency of 30 Hz) within the first holding interval and sends new image data to the DDIC, the processor actually sends the image data at a frequency of 30 Hz. After receiving the new image data from the processor following the TE signal D, the DDIC re-enters the first scanning interval and completes the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 30 Hz.

[0107] In practical use, the DDIC may continuously send TE signals at one or two frequencies, such as 360Hz, 120Hz, 90Hz, 60Hz, 120Hz & 360Hz (a mix of 120Hz and 360Hz). The frequency of the TE signal determines the highest frequency at which the AP sends image data and the highest frame rate of the display refresh—that is, the base frame rate. The above display control method can theoretically achieve adaptive frame rate adjustment from the base frame rate to the range of 1 / [(1 / base frame rate) + n*(1 / TE signal frequency)], where n refers to the duration of the first hold interval mentioned above being n times the period of the TE signal. For example, Figure 9 In the example shown, n is 9, and the DDIC sends a TE signal at 120Hz. Therefore, the frequency range of the AP sending image data and the frame rate range of the display screen are both 120Hz to 1 / [(1 / 120)+n*(1 / 360)]Hz, which are frequencies or frame rates divisible by 120Hz, such as 120Hz-60Hz-40Hz-30Hz. Similarly, if the DDIC sends a TE signal at 60Hz, the frequency range of the AP sending image data and the frame rate range of the display screen are both frequencies or frame rates divisible by 60Hz, such as 60Hz-30Hz-20Hz-10Hz.

[0108] Optional, such as Figure 12 As shown, if DDIC does not receive new image data during the first refresh period (including the first hold interval) corresponding to sequence 1, then a self-refresh for subsequent sequences is executed. Specifically, the above display control method also includes:

[0109] S5. In the second scan interval of the second refresh period following the first refresh period, the DDIC scans the display screen based on the most recently received image data.

[0110] The second refresh period can refer to self-refreshed sequences other than sequence 1 (e.g., sequences 2 through 8). Similar to the first refresh period, such as... Figure 9 and Figure 10As shown, the second refresh period includes a second scan interval and a second hold interval following the second scan interval. During the second scan interval, the DDIC scans the display screen line by line based on the most recently received image data to complete the scan of one frame. If no new image data is received during the second refresh period, the DDIC holds the image displayed on the screen during the second hold interval, that is, it controls the TFTs driving the pixels to maintain their on-state after scanning, and the display screen continues to display the most recent frame.

[0111] The duration of each second refresh interval is equal to the reciprocal of the lowest frame rate of the corresponding sequence. The lowest frame rates of the sequences can be the same or different; specifically, the lowest frame rates of the sequences can decrease sequentially, thus increasing the duration of the refresh intervals for each sequence sequentially. For example, the lowest frame rate of sequence 1 is 30 Hz, sequence 2 is 24 Hz, sequence 3 is 20 Hz, sequence 4 is 15 Hz, sequence 5 is 10 Hz, sequence 6 is 5 Hz, and sequence 7 is 1 Hz. In this case, the difference between the duration of the second hold interval and the duration of the first hold interval is m times the period of the TE signal, where m is a positive integer.

[0112] S6. During the second refresh period, DDIC sends multiple TE signals.

[0113] Similar to step S3, such as Figure 9 As shown, DDIC can send multiple TE signals to the processor throughout the entire second refresh period; these can be referred to as high-frequency TE signals (e.g., 360Hz). Alternatively, as... Figure 10 As shown, DDIC can send a TE signal (e.g., at a frequency of 120 Hz) to the processor just before the end of the second scan interval, and send multiple high-frequency TE signals (e.g., at a frequency of 360 Hz) to the processor during the second hold interval, thereby forming a hybrid TE signal that includes different frequencies (e.g., 120 Hz and 360 Hz).

[0114] The other contents of step S6 are described in step S3 and will not be repeated here.

[0115] S7. In response to any TE signal during the second refresh period, the processor sends new image data to the DDIC during the second refresh period. If the DDIC receives new image data during the second refresh period, it restarts execution from step S2 after a second preset time. If the DDIC does not receive new image data during the second refresh period, it restarts execution from step S5.

[0116] Regarding the processor 210 sending new image data to DDIC 31 in response to the TE signal, refer to... Figure 11 The relevant descriptions will not be repeated here. The second preset time refers to the latest of the following two times: the time when the most recently received image data was received, and the time when the second hold interval begins.

[0117] In other words, if the DDIC receives new image data within the second scanning interval, it waits for the second scanning interval to end to complete the scanning of the previous frame before restarting from step S2 to re-enter the first scanning interval and scan the next frame. If the DDIC receives new image data within the second holding interval, it can directly stop holding the previous frame and restart from step S2, i.e., re-enter the first scanning interval to scan the next frame. If the DDIC does not receive new image data within the second refresh period, it enters the next second refresh period and restarts self-refreshing.

[0118] The repetition count for each sequence can be set according to actual needs. For example, sequence 1 can be repeated once, and sequences 2 through 7 can each be repeated three times. Therefore, the next second refresh period can refer to the next sequence, such as moving from sequence 2 to sequence 3, or it can refer to the same sequence, such as repeatedly entering sequence 2 according to the repetition count. For example, when the DDIC does not receive new image data from the processor, it can self-refresh from sequence 1 to sequence 7, with the refresh frame rates sequentially as follows: 120Hz->30Hz->24Hz->24Hz->24Hz->20Hz->20Hz->20Hz->15Hz->15Hz->15Hz->10Hz->10Hz->10Hz->5Hz->5Hz->5Hz->1Hz. The DDIC then maintains the refresh rate of the last sequence (e.g., 1Hz), thus achieving self-refresh with minimal power consumption. This allows for adaptive frame rate adjustment from dynamic image refresh to static, refreshless image refresh.

[0119] In addition, since DDIC sends high-frequency TE signals during the hold intervals of each refresh period (i.e., sequence), it does not have to wait until the end of the entire refresh period to send TE signals. Therefore, after any TE signal, DDIC can respond to new image data from the processor and re-enter the first scan interval to refresh new image data at a faster speed.

[0120] The display control method provided in this application sends multiple TE signals to the processor during the hold interval of the refresh period, instead of waiting until the end of the refresh period to send TE signals. The reciprocal of the time from the start of the scan interval of the refresh period to the completion of sending any TE signal equals a frame rate (the frame rate is essentially a frequency). When the processor needs the display screen to refresh at a certain frame rate, it does not need to directly instruct the DDIC to set the frame rate of the display screen; it only needs to send image data to the DDIC in fixed response to the TE signal corresponding to that frame rate. In other words, during the hold interval of the refresh period, the DDIC provides multiple TE signals for the processor to choose from with finer granularity. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate desired by the processor) determines the frame rate at which the DDIC refreshes the display screen, thereby realizing the DDIC's adaptive adjustment of the display screen's frame rate.

[0121] This application also provides a computer-readable storage medium including instructions that, when executed on the electronic device, cause the electronic device to perform the steps described in the method embodiments, such as executing... Figure 8 and Figure 12 The method shown.

[0122] This application also provides a computer program product including instructions, which, when executed on the aforementioned electronic device, cause the electronic device to perform the various steps in the method embodiments described above, such as executing... Figure 8 and Figure 12 The method shown.

[0123] The technical effects of computer-readable storage media and computer program products are described in the preceding method embodiments.

[0124] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0125] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0128] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0130] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display control method characterized by comprising: Comprising: Step S1, receiving image data; Step S2, in a first scanning interval in a first refresh period, scanning a display screen according to the image data; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time for completing the scanning of one frame of image data; Step S3, in the first holding interval, sending a plurality of tearing effect (TE) signals, the TE signals being used to indicate that the image data has completed refreshing; the length of the first holding interval is n times the period of the TE signals, n being a positive integer; Step S4, if new image data is received in the first holding interval, starting to execute from step S2 again; if no new image data is received in the first holding interval, in a second scanning interval in a second refresh period after the first refresh period, scanning the display screen according to the most recently received image data; The period after the second scanning interval in the second refresh period is a second holding interval; In the second holding interval, the TE signals are sent; if new image data is received in the second holding interval, jumping to the first refresh period corresponding to the new image data; The minimum frame rate of the first refresh period is greater than the minimum frame rate of the second refresh period.

2. The method of claim 1, wherein, Further comprising: If no new image data is received in the first holding interval, holding the image displayed on the display screen in the first holding interval.

3. The method according to claim 1 or 2, characterized in that, Further comprising: Before the first scanning interval is about to end, a TE signal is sent.

4. The method of claim 1, wherein, Further comprising: If no new image data is received in the second holding interval, holding the image displayed on the display screen in the second holding interval.

5. The method of claim 1, wherein, Further comprising: Before the second scanning interval is about to end, a TE signal is sent.

6. The method of claim 1, wherein, The difference between the length of the second holding interval and the length of the first holding interval is m times the period of the TE signals, m being a positive integer.

7. The method according to claim 1 or 2, characterized in that, The period of the TE signals is k times the period of an emission (EM) signal, k being a positive integer, the EM signal being used to control the light emission of a pixel point of the display screen.

8. A display control method characterized by comprising: Comprising: Step S1, a processor sends image data to a display driver integrated circuit (DDIC); Step S2, the DDIC scans a display screen according to the image data in a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time for completing the scanning of one frame of image data; Step S3, in the first holding interval, the DDIC sends a plurality of tearing effect (TE) signals to the processor, the TE signals being used to indicate that the image data has completed refreshing; the length of the first holding interval is n times the period of the TE signals, n being a positive integer; Step S4, the processor sends new image data to the DDIC in the first holding interval in response to any TE signal in the first holding interval; if the DDIC receives new image data in the first holding interval, the execution restarts from step S2; if the DDIC does not receive new image data in the first holding interval, the DDIC scans the display screen according to the latest received image data in a second scanning interval in a second refresh period after the first refresh period; The period after the second scanning interval in the second refresh period is a second holding interval; In the second holding interval, the DDIC sends a plurality of TE signals to the processor; the processor sends new image data to the DDIC in the first holding interval in response to any TE signal in the second holding interval; if the DDIC receives new image data in the second holding interval, jump to the first refresh period corresponding to the new image data; The minimum frame rate of the first refresh period is greater than the minimum frame rate of the second refresh period.

9. The method of claim 8, wherein, Further comprising: If the DDIC does not receive new image data in the first holding interval, the image displayed on the display screen is maintained in the first holding interval.

10. The method according to claim 8 or 9, characterized in that, Further comprising: The DDIC sends a TE signal to the processor before the first scanning interval ends.

11. The method of claim 8, wherein, Further comprising: If the DDIC does not receive new image data in the second holding interval, the image displayed on the display screen is maintained in the second holding interval.

12. The method of claim 8, wherein, Further comprising: The DDIC sends a TE signal to the processor before the second scanning interval ends.

13. The method of claim 8, wherein, The difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, m being a positive integer.

14. The method of claim 8 or 9, wherein, The period of the TE signal is k times the period of the emitted EM signal, k being a positive integer, and the EM signal is used to control the pixel points of the display screen to emit light.

15. A display driving chip, characterized in that, The display driving chip is used to execute the method of any one of claims 1-7.

16. An electronic device, comprising: A display driving chip (DDIC) is provided, comprising a processor, a display screen, and the display driving chip (DDIC) of claim 15. The processor is configured to send image data to the DDIC; The DDIC is configured to scan the display screen according to the image data in a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time to complete the scanning of one frame of image; The DDIC is further configured to send a plurality of tearing effect (TE) signals to the processor in the first holding interval, the TE signal being used to indicate that the image data has completed refreshing; the duration of the first holding interval is n times the period of the TE signal, n being a positive integer; The processor is further configured to send new image data to the DDIC in the first holding interval in response to any TE signal in the first holding interval; The DDIC is further configured to return to the first scanning interval in the first refresh period to scan the display panel according to new image data if the new image data is received in the first holding interval; and to scan the display panel according to the most recently received image data in a second scanning interval in a second refresh period after the first refresh period if the new image data is not received in the first holding interval. A period after the second scanning interval in the second refresh period is a second holding interval; the DDIC is further configured to send a plurality of TE signals to the processor in the second holding interval; the processor is further configured to send new image data to the DDIC in the first holding interval in response to any TE signal in the second holding interval; and the DDIC is further configured to jump to a first refresh period corresponding to the new image data if the new image data is received in the second holding interval. The lowest frame rate of the first refresh period is greater than the lowest frame rate of the second refresh period.

17. A computer readable storage medium characterized by: The instructions, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1-7, or the method of any one of claims 8-14.

Images