Pixel circuit and display device including same

Abstract

A pixel circuit includes: a light emitting element having an anode; a driving transistor having a first electrode connected to the high-potential driving voltage line and a second electrode connected to the light emitting element, and controlling a magnitude of a driving current supplied to the light emitting element in response to a voltage applied to the gate; a first switching transistor connected between the data line and the gate electrode of the driving transistor, and receiving a first scan signal through the gate electrode; a light emitting transistor connected between the driving transistor and the light emitting element, and receiving a light emitting signal through a gate; and an initialization transistor connected between an initialization voltage line and an anode and receiving an inverted light emission signal through a gate, a phase of the inverted light emission signal being opposite to a phase of the light emission signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0170642, filed on November 30, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a pixel and a display device including the pixel. Background art

[0004] With the development of the information society, various demands for display devices for displaying images are continuously increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light - emitting diode (OLED) display devices are used.

[0005] The image displayed on the display device may be a still image or a moving image, and the moving image may include various types such as sports images, game images, and movies. The display device is driven at a driving frequency in a variable refresh rate (VRR) mode that varies according to the type of the image, thereby reducing power consumption and extending the lifespan of the display device.

[0006] When the variable refresh rate mode is applied to drive pixels at different refresh rates, due to the different refresh rates, a brightness difference occurs between the pixels, resulting in a degradation of the image quality, such as image distortion or flicker. Summary of the invention

[0007] Embodiments of the present disclosure are directed to providing a pixel and a display device including the pixel, the pixel including a transistor formed to have a gate that receives an inverted light - emitting signal, thereby minimizing or at least reducing the charging / discharging of a light - emitting element.

[0008] Embodiments of the present disclosure are also directed to providing a pixel and a display device including the pixel, the pixel reducing the on - bias stress of a driving transistor by forming a capacitor between an inverted light - emitting signal line and a node of the pixel.

[0009] Embodiments of the present disclosure are also directed to providing a pixel capable of adjusting a charging / discharging delay time by separating a reference voltage and an initialization voltage.

[0010] A pixel circuit according to one or more embodiments of the present disclosure may include: a light-emitting element having an anode; a driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to the light-emitting element, and a gate, the driving transistor being configured to control the magnitude of the driving current supplied to the light-emitting element in response to a voltage applied to the gate of the driving transistor; a first switching transistor having a gate, the first switching transistor being connected between a data line and the gate of the driving transistor, and the first switching transistor being configured to receive a first scan signal through the gate of the first switching transistor; a light-emitting transistor having a gate, the light-emitting transistor being connected between the driving transistor and the light-emitting element, and the light-emitting transistor being configured to receive a light-emitting signal through the gate of the light-emitting transistor; and an initialization transistor having a gate, the initialization transistor being connected between an initialization voltage line and the anode of the light-emitting element, and the initialization transistor being configured to receive an inverted light-emitting signal through the gate of the initialization transistor, the phase of the inverted light-emitting signal being opposite to the phase of the light-emitting signal.

[0011] In the variable refresh rate mode, the timing controller may drive the pixel circuit at a low frequency. Here, one frame includes an anode initialization period and a light-emitting period. During the anode initialization period, a light-emitting signal at a cut-off level may be applied. During the light-emitting period, a light-emitting signal at a conductive level is applied, and the initialization transistor may apply an initialization voltage to the anode of the light-emitting element in response to the inverted light-emitting signal during the anode initialization period.

[0012] The pixel circuit may further include a coupling capacitor connected between an inverted light-emitting signal line to which the inverted light-emitting signal is applied and the gate of the driving transistor.

[0013] The coupling capacitor may transfer a coupling voltage corresponding to the inverted light-emitting signal to the gate of the driving transistor during the anode initialization period.

[0014] The pixel circuit may further include a storage capacitor connected to the first switching transistor through a first node and to the gate of the driving transistor through a second node.

[0015] The pixel circuit may further include a coupling capacitor connected between an inverted light-emitting signal line to which the inverted light-emitting signal is applied and the first node.

[0016] The pixel circuit may further include: a second switching transistor connected between the gate of the driving transistor and the second electrode of the driving transistor and receiving a second scan signal through the gate; a third switching transistor connected between the reference voltage line and the first node and receiving a light emission signal through the gate; and a fourth switching transistor connected between the initialization voltage line and the anode of the light emitting element and receiving a second scan signal through the gate.

[0017] The second switching transistor may be formed of a plurality of sub-transistors connected in series and receiving a second scan signal through the gate.

[0018] A display device according to one or more embodiments of the present disclosure may include: a display panel including a display area and a non-display area adjacent to the display area, the display area having a plurality of pixel circuits; at least one gate driver configured to apply a first scan signal, a light emission signal, and an inverted light emission signal to the plurality of pixel circuits, the phase of the inverted light emission signal being opposite to the phase of the light emission signal; a data driver configured to apply a data voltage to the plurality of pixel circuits; a power supply unit configured to apply a voltage for driving the plurality of pixel circuits; and a timing controller configured to control a driving timing of the display panel.

[0019] Each pixel circuit among the plurality of pixel circuits may include: a light emitting element having an anode; a driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to the light emitting element, and a gate, and the driving transistor being configured to control a magnitude of a driving current supplied to the light emitting element in response to a voltage applied to the gate of the driving transistor; a first switching transistor configured to transmit a data voltage to the gate of the driving transistor in response to the first scan signal; a light emitting transistor configured to form a current path between the driving transistor and the light emitting element in response to the light emission signal; and an initialization transistor configured to transmit an initialization voltage to the anode of the light emitting element in response to the inverted light emission signal.

[0020] At least one gate driver may include gate drivers respectively provided on the left and right sides of the display area in the non-display area and symmetrically configured.

[0021] Each gate driver may include: a first shift register configured to output a first scan signal; a second shift register configured to output a second scan signal; a third shift register configured to output a light emission signal; and a fourth shift register configured to output an inverted light emission signal.

[0022] The fourth shift register may be provided closer to the display area than the third shift register and configured to receive the light emission signal output from the third shift register to the pixel circuit to invert the phase and invert the phase of the received light emission signal.

[0023] The timing controller can drive the pixel circuit at a low frequency in a variable refresh rate mode, where one frame includes an anode initialization period and a light emission period. The gate driver can apply a light emission signal with a cut-off level to the pixel circuit during the anode initialization period, and apply a light emission signal with a conductive level to the pixel circuit during the light emission period. And the initialization transistor can apply an initialization voltage to the anode of the light emitting element in response to an inverted light emission signal during the anode initialization period.

[0024] The pixel circuit may further include a coupling capacitor connected between the inverted light emission signal line to which the inverted light emission signal is applied and the gate of the driving transistor.

[0025] The coupling capacitor can transfer a coupling voltage corresponding to the inverted light emission signal to the gate of the driving transistor during the anode initialization period.

[0026] The pixel circuit may further include a storage capacitor, which is connected to the first switching transistor through a first node and to the gate of the driving transistor through a second node.

[0027] The pixel circuit may further include a coupling capacitor connected between the inverted light emission signal line to which the inverted light emission signal is applied and the first node.

[0028] The pixel circuit may further include: a second switching transistor, connected between the gate of the driving transistor and the second electrode of the driving transistor, and receiving a second scan signal through the gate; a third switching transistor, connected between the reference voltage line and the first node, and receiving a light emission signal through the gate; and a fourth switching transistor, connected between the initialization voltage line and the anode of the light emitting element, and receiving a second scan signal through the gate.

[0029] The second switching transistor may be formed by a plurality of sub-transistors connected in series and receiving a second scan signal through the gate. Description of the Drawings

[0030] Figure 1 is a block diagram showing the configuration of a display device according to one or more embodiments of the present disclosure.

[0031] Figure 2 is a diagram showing a driving method of a display device according to an embodiment of the present disclosure.

[0032] Figure 3 is a diagram showing a driving method of a display device according to another embodiment of the present disclosure.

[0033] Figure 4 is a block diagram showing the configuration of a gate driver according to one or more embodiments of the present disclosure.

[0034] Figure 5 is a circuit diagram of a pixel according to a first embodiment of the present disclosure.

[0035] Figure 6 is a diagram showing Figure 5 a driving method of the pixel according to the first embodiment of the present disclosure shown above.

[0036] Figure 7 is a circuit diagram of a pixel according to a second embodiment of the present disclosure.

[0037] Figure 8 is a circuit diagram of a pixel according to a third embodiment of the present disclosure.

[0038] Figure 9 is a diagram showing Figure 8 a driving method of the pixel according to the third embodiment of the present disclosure shown above.

[0039] Figure 10 is a cross-sectional view showing a stacked form of a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the present disclosure, when a first component (or region, layer, part, etc.) is described as being "on", "connected" or "coupled to" a second component, this means that the first component can be directly connected / coupled to the second component, or a third component can be disposed between the first component and the second component.

[0041] Identical reference numerals denote identical components. Additionally, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description of the technical content. The term "and / or" includes all combinations of more than one defined by the relevant configuration.

[0042] For example, terms such as first and second can be used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the embodiment, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Unless the context clearly dictates otherwise, singular expressions include plural expressions.

[0043] For example, terms such as "below", "underneath", "above", "on top" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described with respect to the directions marked in the drawings.

[0044] It should be understood that terms such as "comprising", "including", or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the present disclosure, without precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0045] Figure 1 is a block diagram showing the configuration of a display device according to one or more embodiments of the present disclosure.

[0046] Referring to Figure 1 , the display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0047] The timing controller 10 can receive an image signal RGB and a control signal CS from an external host system 2 or the like. The image signal RGB can include a plurality of grayscale data. The control signal CS can include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0048] The timing controller 10 can process the image signal RGB and the control signal CS according to the operating conditions of the display panel 60, and generate and output image data DATA, a gate drive control signal CONT1, a light emission drive control signal CONT2, a data drive control signal CONT3, and a power control signal CONT4.

[0049] The gate driver 20 can include a scan driver 20A for generating a scan signal based on the gate drive control signal CONT1 output from the timing controller 10. The scan driver 20A can supply the generated scan signal to the pixel circuit PX through a plurality of gate lines GL1. In one or more embodiments, one pixel circuit PX can be configured to receive a plurality of scan signals having different waveforms. In one or more embodiments, the scan driver 20A can supply a plurality of scan signals to the pixel circuit PX through corresponding gate lines GL1 and GL2.

[0050] The gate driver 20 can further include a light emission driver 20B for generating a light emission control signal based on the light emission drive control signal CONT2 output from the timing controller 10. The light emission driver 20B can supply the generated light emission control signal to the pixel circuit PX through a light emission line EL.

[0051] The gate driver 20 can be configured in the form of an in-panel gate mounted on the display panel 50. The gate driver 20 can be provided on one side of the display panel 50 or as Figure 1It is arranged on both sides (e.g., the left side and the right side) of the display panel 50 as shown. Depending on the driving method, panel design method, etc., the gate driver 20 can be arranged on both sides (e.g., the left side and the right side) of the display panel 50 as shown or connected to more than two of the four sides of the display panel 50.

[0052] The data driver 30 can generate data signals based on the image data DATA output from the timing controller 10 and the data driving control signal CONT3. The data driver 30 can supply the generated data signals to the pixel circuits PX through a plurality of data lines DL.

[0053] The power supply unit (e.g., power supply circuit) 40 can generate a high-potential driving voltage VDD and a low-potential driving voltage VSS to be supplied to the display panel 50 based on the power supply control signal CONT4. The power supply unit 40 can supply the generated driving voltages VDD and VSS to the pixel circuits PX through corresponding voltage lines PL1 and PL2. Additionally, the power supply unit 40 can also generate a reference voltage Vref and / or an initialization voltage Vini required to drive the pixel circuits PX, and supply the reference voltage Vref and / or the initialization voltage Vini to the pixel circuits PX through corresponding voltage lines VrefL and ViniL.

[0054] A plurality of pixel circuits PX (or referred to as "sub-pixel circuits") are arranged on the display panel 50. For example, the pixel circuits PX can be arranged in a matrix form on the display panel 50. The pixel circuits PX arranged in one pixel row are connected to the same gate lines GL1 and GL2 and the emission line EL, and the pixel circuits PX arranged in one pixel column are connected to the same data line DL. The pixel circuits PX can emit light having a brightness corresponding to the gate signals and data signals supplied through the gate lines GL1 and GL2 and the data line DL in response to the emission control signal applied through the emission line EL.

[0055] In one or more embodiments, each pixel circuit PX can display any one of red, green, and blue. In one or more embodiments, each pixel circuit PX can display any one of cyan, magenta, and yellow. In various embodiments, each pixel circuit PX can display any one of red, green, blue, and white.

[0056] In one or more embodiments, one or more optical regions OA1 and OA2 can be provided in the display panel 50. One or more optical regions OA1 and OA2 can be provided to overlap with one or more optoelectronic devices such as a photographing device (e.g., a camera (image sensor)) or a detection sensor (e.g., a proximity sensor and an illuminance sensor).

[0057] For the operation of an optoelectronic device, one or more optical regions OA1 and OA2 may include a light-transmissive structure and have a light transmittance above a predetermined level. The light-transmissive structure may be formed by patterning a cathode in a portion where no pixel circuit PX is provided. The cathode may be patterned by removing the cathode using a laser or by selectively forming the cathode through a cathode deposition prevention layer.

[0058] Alternatively, the light-transmissive structure may be formed by separating a light-emitting element from the pixel circuit PX. In one or more embodiments, the light-emitting element of the pixel circuit PX may be located in the optical regions OA1, OA2, a plurality of transistors constituting the pixel circuit PX may be provided near the optical regions OA1, OA2, and the light-emitting element and the pixel may be electrically connected through a transparent metal layer.

[0059] The number of pixel circuits PX per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixel circuits PX per unit area in the remaining regions other than the optical regions OA1 and OA2. In other words, the resolution of one or more optical regions OA1 and OA2 may be lower than that of the remaining regions. The timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 may all be configured as separate integrated circuits (ICs) or ICs integrating at least a part thereof.

[0060] In one or more embodiments, the display device 1 may be driven in a variable refresh rate mode in which the drive frequency is variable. For example, the display device 1 may be driven at a refresh rate higher or lower than a predetermined reference refresh rate. When the display device 1 is driven at a rate lower than the reference refresh rate, it may be referred to as "low-frequency driving", and when the display device 1 is driven at a rate higher than the reference refresh rate, it may be referred to as "high-frequency driving". The refresh rate may be determined according to the type of image to be displayed and the like, but is not limited thereto.

[0061] The timing controller 10 may generate control signals CONT1 to CONT4 such that the pixel circuit PX can be driven at various refresh rates. For example, the timing controller 10 may change the refresh rate by changing the frequency of the clock signals included in the control signals CONT1 to CONT4, adjusting the timing of the horizontal synchronization signal or the vertical synchronization signal, or driving the gate driver 20 in a masked manner.

[0062] Figure 2 It is a diagram showing a driving method of a display device according to an embodiment of the present disclosure.

[0063] In the variable refresh rate mode, one frame may be composed of a combination of at least one refresh period RP and at least one skip period SP. During the refresh period RP, each pixel circuit PX may be supplied with a new data voltage (see Figure 1)Programming is performed, and the light-emitting element of the pixel circuit PX can emit light in response to the programmed data voltage. The refresh period RP can be subdivided into an initialization period, a sampling period, a holding period, etc. to perform data voltage programming. The refresh period RP can also be referred to as a "refresh frame".

[0064] The process of applying a new data voltage to the pixel circuit PX during the skip period SP is omitted. During the skip period SP, the light-emitting element of each pixel circuit PX can emit light in response to the data voltage programmed in the previous refresh period RP. The skip period SP can be referred to as a "holding period", a "skip frame", a "holding frame", etc.

[0065] In one or more embodiments, to change the refresh rate, the length of a frame can be changed by adjusting the number or length of the skip periods SP. Therefore, the length of the refresh period RP can be fully ensured so that the data voltage can be programmed stably.

[0066] In one or more embodiments, the generation period of the refresh period RP can be changed according to the variable refresh rate. As the refresh rate decreases, the generation period of the refresh period RP increases, and as the refresh rate decreases, the number of skip periods SP between the refresh periods RP increases.

[0067] For example, the generation period of the refresh period RP at 120 Hz can be 120 / 1 seconds, the generation period of the refresh period RP at 60 Hz can be 60 / 1 seconds, the generation period of the refresh period RP at 24 Hz can be 24 / 1 seconds, and the generation period of the refresh period RP at 1 Hz can be 1 / 1 seconds. The number of skip periods SP between two adjacent refresh periods RP at 120 Hz can be 0, the number of skip periods SP between two adjacent refresh periods RP at 60 Hz can be 1, the number of skip periods SP between two adjacent refresh periods RP at 24 Hz can be 4, and the number of skip periods SP between two adjacent refresh periods RP at 1 Hz can be 9, and Figure 2 An example of 24 Hz is shown. However, this embodiment is not limited thereto.

[0068] The refresh period RP includes a programming period PP and a light-emitting period EP. During the programming period PP, a new data voltage is programmed into the pixel circuit PX, and during the light-emitting period EP, the pixel circuit PX emits light in response to the programmed data voltage.

[0069] The skip period SP only includes the light-emitting period EP in which the light-emitting signal EM (see Figure 1 ) has a conductive level. During the light-emitting period EP, the pixel circuit PX maintains the light-emitting brightness of the previous refresh period RP.

[0070] In one or more embodiments, the length of the emission period EP of the skip period SP may be greater than the length of the emission period EP of the refresh period RP. Therefore, comparing the luminance integration amount for a constant time, the lower the refresh rate (i.e., the greater the number of skip periods SP), the relatively greater the luminance integration amount. For example, the luminance integration amount for a constant time at 60 Hz is greater than that at 120 Hz, the luminance integration amount for a constant time at 24 Hz is greater than that at 60 Hz, and the luminance integration amount for a constant time at 1 Hz is greater than that at 24 Hz.

[0071] Since there are differences in the luminance integration amount according to the refresh rate, flickering may be seen when the refresh rate changes.

[0072] Figure 3 FIG. is a diagram showing a driving method of a display device according to another embodiment of the present disclosure.

[0073] In one or more embodiments, during the skip period SP, the anode of the light-emitting element included in the pixel circuit PX (see Figure 1 ) may be reset to a predetermined reset voltage (e.g., an initialization voltage). In one or more embodiments, the skip period SP may be referred to as an "anode initialization period" or an "anode initialization frame".

[0074] The refresh period RP includes a programming period PP and an emission period EP. During the programming period PP, a new data voltage is programmed into the pixel circuit PX, and during the emission period EP, the pixel circuit PX emits light in response to the programmed data voltage.

[0075] The skip period SP includes an anode initialization period ARP during which the emission signal EM (see Figure 1 ) has a cut-off level and an emission period EP during which the emission signal EM has a conductive level. During the anode initialization period ARP, a predetermined reset voltage (e.g., an initialization voltage) is applied to the anode of the light-emitting element included in the pixel circuit PX. During this period, the light-emitting element may not emit light due to this reset voltage. During the emission period EP, the pixel circuit PX emits light with the emission luminance of the previous refresh period RP.

[0076] The length of the anode initialization period ARP may be equal to the length of the programming period PP, so that the luminance integration amounts of the skip period SP and the refresh period RP are equal to each other. As described above, in the embodiment including the anode initialization period ARP, there is no deviation in the luminance integration amount according to the refresh rate, and flickering caused by the difference in the luminance integration amount can be suppressed.

[0077] Figure 4It is a block diagram showing the configuration of a gate driver according to one or more embodiments of the present disclosure.

[0078] Referring to Figure 4 , the display panel 50 may include a display area AA for displaying an image and a non-display area NAA for not displaying an image near the display area AA.

[0079] A pixel circuit PX array is provided in the display area AA. At least part of the driver may be mounted or connected to the non-display area NAA. For example, the gate driver 20 may be provided on one or both sides (e.g., the left and right sides) of the display area AA in the non-display area NAA, as shown in the figure. The gate drivers 20 provided on both sides of the display area AA may be symmetrically configured (in a mirror image form). The configuration will be described below based on the gate driver 20 being provided on the left side of the display area AA.

[0080] The gate driver 20 may include a first shift register 21, a second shift register 22, a third shift register 23, and a fourth shift register 24.

[0081] The first shift register 21 and the second shift register 22 are configured to output scan signals. For example, the first shift register 21 may sequentially output a first scan signal S1 through a first gate line GL1, and the second shift register 22 may sequentially output a second scan signal S2 through a second gate line GL2.

[0082] Each of the first shift register 21 and the second shift register 22 may be composed of independently connected stage circuits. Each stage circuit may be connected to the corresponding gate lines GL1 and GL2 to output the scan signals S1 and S2 to the gate lines GL1 and GL2.

[0083] The first scan signal S1 and the second scan signal S2 may be used to drive at least one transistor provided in the pixel circuit PX. For example, the first scan signal S1 and the second scan signal S2 may be used to program image data DATA (see Figure 1 ) into the pixel circuit PX, initialize the voltage stored in the pixel circuit PX, or compensate for the characteristics of circuit elements.

[0084] The third shift register 23 and the fourth shift register 24 are configured to output a light emission signal and an inverted light emission signal. For example, the third shift register 23 may output a light emission signal EM through a light emission line EL, and the fourth shift register 24 may output an inverted light emission signal having a phase opposite to that of the light emission signal EM through an inverted light emission line IEL. In one or more embodiments, the fourth shift register 24 may be configured to receive the light emission signal EM output from the third shift register 23, and generate and output an inverted signal of the light emission signal EM through at least one circuit element for inverting the phase of the input light emission signal EM.

[0085] The light emission signal EM and the inverted light emission signal IEM may be used to drive at least one transistor provided in the pixel circuit PX. For example, the light emission signal EM may be used to change or control the light emission time of the pixel circuit PX.

[0086] In Figure 4 the illustrated embodiment, the first shift register 21 and the second shift register 22 may be disposed adjacent to the display area AA, and the third shift register 23 and the fourth shift register 24 may be disposed at a position relatively far from the display area AA. In addition, the fourth shift register 24 that outputs the inverted light emission signal IEM may be disposed at a position closer to the display area AA than the third shift register 23, and receive the light emission signal EM output from the third shift register 23 to the pixel circuit PX.

[0087] However, the arrangement manners of the shift registers 21, 22, 23, and 24 are not limited to Figure 4 the illustrated arrangement manners. According to the specifications of the display panel 50, various changes may be made to the arrangement manners of the shift registers 21, 22, 23, and 24 within a possible range to reduce the size of the non-display area NAA and reduce the length and number of lines.

[0088] Figure 5 is a circuit diagram of a pixel according to a first embodiment of the present disclosure. In Figure 5 it, for ease of explanation, a pixel connected to the nth pixel row (n is an integer greater than 0) is shown as an example.

[0089] Referring to Figure 5 , a pixel circuit PX according to one or more embodiments may include a driving transistor DT, a light emitting element LD connected to the driving transistor DT, and a control circuit for controlling the magnitude of a driving current applied to the light emitting element LD through the driving transistor DT. For example, the control circuit may include a first transistor T1 to a sixth transistor T6 and a first capacitor C1 and a second capacitor C2.

[0090] The first electrode of the driving transistor DT is formed to receive a high potential driving voltage VDD (connected to the high potential driving voltage line PL1), and the second electrode of the driving transistor DT is connected to the third node N3. The gate of the driving transistor DT is connected to the second node N2. The driving transistor DT can be turned on according to the voltage applied to the second node N2 to control the magnitude of the driving current flowing to the light emitting element LD.

[0091] The first electrode of the first transistor T1 is connected to the data line DL, and the second electrode of the first transistor T1 is connected to the first node N1. The gate of the first transistor T1 can be connected to the first gate line GL1 to receive the first scan signal S1. The first transistor T1 can be turned on according to the first scan signal S1 applied to the first gate line GL1 to transfer the data voltage Vdata applied to the data line DL to the first node N1. The first transistor T1 can be referred to as the "first switching transistor".

[0092] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 can store a voltage corresponding to the difference between the data voltage Vdata applied to the data line DL and the voltage at the second node N2, and hold the stored voltage for one frame period, thereby stabilizing the voltage of the gate of the driving transistor DT (i.e., the second node N2). The first transistor C1 can be referred to as the "storage capacitor".

[0093] The second transistor T2 is connected between the second node N2 and the third node N3. The gate of the second transistor T2 can be connected to the second gate line GL2 to receive the second scan signal S2. The second transistor T2 can be turned on according to the second scan signal S2 applied to the second gate line GL2 to electrically connect the gate of the driving transistor DT (the second node N2) and the second electrode T2 (the third node N3). The second transistor T2 can be referred to as the "second switching transistor".

[0094] The first electrode of the third transistor T3 is formed to receive a reference voltage Vref (connected to the reference voltage line Vref1), and the second electrode of the third transistor T3 is connected to the first node N1. The gate of the third transistor T3 can be connected to the emission line EL to receive the emission signal EM. The third transistor T3 can be turned on according to the emission signal EM applied to the emission line EL to transfer the reference voltage Vref to the first node N1. The third transistor T3 can be referred to as the "third switching transistor".

[0095] The fourth transistor T4 is connected between the third node N3 and the fourth node N4. The gate of the fourth transistor T4 may be connected to the emission line EL to receive the emission signal EM. The fourth transistor T4 may be turned on according to the emission signal EM applied to the emission line EL to electrically connect the driving transistor DT (third node N3) and the light-emitting element LD (fourth node N4). The fourth transistor T4 may be referred to as an "emission transistor".

[0096] The first electrode of the fifth transistor T5 is formed to receive the initialization voltage Vini (connected to the initialization voltage line ViniL), and the second electrode of the fifth transistor T5 is connected to the fourth node N4. The gate of the fifth transistor T5 may be connected to the second gate line GL2 to receive the second scan signal S2. The fifth transistor T5 may be turned on according to the second scan signal S2 applied to the second gate line GL2 to apply the initialization voltage Vini to the anode (fourth node N4) of the light-emitting element LD. The fifth transistor may be referred to as a "fourth switching transistor".

[0097] The first electrode of the sixth transistor T6 is formed to receive the initialization voltage Vini, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. The gate of the sixth transistor T6 may be connected to the inverted emission line IEL to receive the inverted emission signal IEM. The sixth transistor T6 may be turned on according to the inverted emission signal IEM applied to the inverted emission line IEL to apply the initialization voltage Vini to the anode (fourth node N4) of the light-emitting element LD. The sixth transistor T6 may be referred to as an "initialization transistor".

[0098] The second capacitor C2 is connected between the inverted emission line IEL and the second node N2. When the inverted emission signal IEM is applied to the inverted emission line IEL, the second capacitor C2 may be formed to transfer the coupling voltage to the second node N2. The second capacitor C2 may be referred to as a "coupling capacitor".

[0099] The anode of the light-emitting element LD may be connected to the fourth node N4, and the cathode of the light-emitting element LD may be connected to the low-potential driving voltage VSS. When the driving transistor DT and the fourth transistor T4 are turned on, a current path may be formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS so that the driving current can flow to the light-emitting element LD. The light-emitting element LD may emit light with a brightness corresponding to the magnitude of the applied driving current.

[0100] In Figure 5 the illustrated embodiment, the pixel circuit PX includes low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0101] The LTPS thin film transistor includes a gate, a source, and a drain. The LTPS thin film transistor has an active layer made of polysilicon. The LTPS thin film transistor can be formed as a p-type thin film transistor or an n-type thin film transistor. The LTPS thin film transistor has a high electron mobility and thus has the characteristic of fast driving.

[0102] However, this embodiment is not limited thereto. In another embodiment, at least one of the transistors DT, T1 to T6 can be formed as an oxide semiconductor thin film transistor.

[0103] The oxide semiconductor thin film transistor includes a gate, a source, and a drain. The oxide semiconductor thin film transistor has an active layer formed of an oxide semiconductor. Here, the oxide semiconductor can be set as an amorphous oxide semiconductor or a crystalline oxide semiconductor. The oxide semiconductor thin film transistor can be formed as an n-type transistor. The oxide semiconductor thin film transistor can be processed at a low temperature and has a lower charge mobility than the LTPS thin film transistor. The oxide semiconductor thin film transistor has excellent off-current characteristics.

[0104] Figure 6 is a diagram showing Figure 5 a driving method of a pixel according to a first embodiment of the present disclosure as shown.

[0105] Referring to Figure 5 and Figure 6 , in the variable refresh rate mode, one frame can be configured as a combination of at least one refresh period RP and at least one skip period SP.

[0106] The refresh period RP can include an initialization period t1, a sampling period t2, a holding period t3, and a light emission period t4.

[0107] During the initialization period t1, a second scan signal S2 with a conductive level is applied to turn on the second transistor T2 and the fifth transistor T5. In addition, during the initialization period t1, a light emission signal EM with a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. Therefore, during the initialization period t1, the reference voltage Vref is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4 and the third node N3.

[0108] When the second transistor T2 is turned on, the voltage at the third node N3 can be transferred to the second node N2. Thus, the initial voltage at the second node N2 can correspond to the initialization voltage Vini. During the initialization period t1, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini. Additionally, during the initialization period t1, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini in response to the charging voltage of the first capacitor C1.

[0109] Meanwhile, during the initialization period t1, the anode of the light-emitting element LD can be initialized to the initialization voltage Vini in response to the voltage at the fourth node N4.

[0110] During the sampling period t2, a first scan signal S1 at a conductive level is further applied to turn on the first transistor T1. Additionally, during the sampling period t2, the light-emitting signal EM can be switched to a cutoff level to turn off the third transistor T3 and the fourth transistor T4. Conversely, during the sampling period t2, the inverted light-emitting signal IEM is switched to a conductive level. Thus, the sixth transistor T6 can be turned on in response to the conductive-level inverted light-emitting signal IEM. Therefore, during the sampling period t2, the data voltage Vdata applied to the data line DL is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4.

[0111] During the sampling period t2, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the data voltage Vdata and the initialization voltage Vini. Additionally, during the sampling period t2, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the data voltage Vdata and the initialization voltage Vini in response to the charging voltage of the first capacitor C1.

[0112] When the charging voltage of the first capacitor C1 is transferred to the gate of the driving transistor DT, the source-gate voltage of the driving transistor DT is higher than the threshold voltage Vth, so the driving transistor DT can be turned on. In this case, the source-drain current of the driving transistor DT can be determined based on the data voltage Vdata, the reference voltage Vref, the initialization voltage Vini, and the threshold voltage of the driving transistor DT.

[0113] When the source - gate voltage reaches the threshold voltage of the driving transistor DT, the driving transistor DT can supply a source - drain current to the third node N3. Additionally, the second transistor T2 can supply the voltage at the third node N3 to the second node N2. In this way, when the driving transistor DT is turned on, the voltage at the second node N2 and the source - drain current of the driving transistor DT change, and finally the voltage at the second node N2 converges to a voltage corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0114] Meanwhile, during the sampling period t2, since the initialization voltage Vini is applied to the fourth node N4 through the sixth transistor T6, the anode of the light - emitting element LD can hold the initialization voltage Vini in response to the voltage at the fourth node N4.

[0115] During the holding time t3, the first scan signal S1 and the second scan signal S2 are switched to the cut - off level, turning off the first transistor T1, the second transistor T2, and the fifth transistor T5. During the holding period t3, the voltage at the second node N2 can be stably held by the first capacitor C1.

[0116] During the light - emitting period t4, the light - emitting signal EM at the conductive level is applied, turning on the third transistor T3 and the fourth transistor T4. During the light - emitting period t4, a current path is formed from the high - potential driving voltage VDD through the driving transistor DT to the light - emitting element LD. Therefore, a driving current having a magnitude corresponding to the voltage applied to the driving transistor DT can flow along the current path to cause the light - emitting element LD to emit light with a corresponding brightness.

[0117] The skip period SP can include an anode initialization period t5 and a light - emitting period t6.

[0118] During the anode initialization period t5, the light - emitting signal EM can be switched to the cut - off level to turn off the third transistor T3 and the fourth transistor T4. Conversely, during the anode initialization period t5, the inverted light - emitting signal IEM is switched to the conductive level. Therefore, the sixth transistor T6 can be turned on in response to the conductive - level inverted light - emitting signal IEM. Thus, during the anode initialization period t5, the initialization voltage Vini is applied to the fourth node N4.

[0119] During the anode initialization period t5, due to the initialization voltage Vini applied to the anode of the light - emitting element LD, the light - emitting element LD does not emit light. Instead, the gate voltage of the driving transistor DT can be held at the voltage programmed during the previous refresh period RP by the first capacitor C1.

[0120] During the anode initialization period t5, when an inverted emission signal IEM is applied to the inverted emission line IEL, a parasitic capacitance (coupled voltage) can be generated in the second capacitor C2, so the voltage at the second node N2 can decrease (recoil) at a predetermined level Δ. When the source voltage of the driving transistor DT remains unchanged, the decrease in the voltage at the second node N2 increases the source-gate voltage of the driving transistor DT. Therefore, the driving transistor DT can remain in the on state during the anode initialization period t5, and the hysteresis of the driving transistor DT can be reduced.

[0121] Meanwhile, during the anode initialization period t5, since the initialization voltage Vini is directly applied to the anode of the light-emitting element LD, the voltage of the anode can be charged at a relatively fast speed, thereby minimizing or at least reducing the charging delay of the light-emitting element LD. Through anode initialization, there is no deviation in the luminance integration amount according to the refresh rate, and flicker caused by differences in the luminance integration amount can be suppressed.

[0122] During the emission period t6, an emission signal EM at a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. During the emission period t4, the light-emitting element LD can emit light with a luminance corresponding to the voltage programmed during the previous refresh period RP.

[0123] Meanwhile, during the anode initialization period t5 before the emission period t6, the anode of the light-emitting element LD is charged to the initialization voltage Vini. Therefore, during the emission period t6, the luminance of the light-emitting element LD can reach the target luminance faster, thereby minimizing or at least reducing the charging delay of the light-emitting element LD. Specifically, since the initialization voltage Vini can be separated from the reference voltage Vref and supplied to the anode of the light-emitting element LD, the voltage level of the initialization voltage Vini can be adjusted independently, and the charge and discharge delay time of the light-emitting element LD can be effectively controlled.

[0124] Figure 7 is a circuit diagram of a pixel according to a second embodiment of the present disclosure. In Figure 7 for ease of description, a pixel connected to the nth pixel row (n is an integer greater than 0) is shown as an example.

[0125] Compared with Figure 5 the first embodiment of, in the second embodiment, the second transistor T2 can be composed of a plurality of second sub-transistors T21 and T22 connected in series. The gates of the second sub-transistors T21 and T22 can be connected to the second gate line GL2 to receive the second scan signal S2. The second transistor T2 can be turned on according to the second scan signal S2 applied to the second gate line GL2 to electrically connect the gate (second node N2) of the driving transistor DT to the second electrode (third node N3).

[0126] In Figure 7 the illustrated embodiment, the second transistor T2 is formed of two sub-transistors T21 and T22, but the embodiment is not limited thereto. In another embodiment, the second transistor T2 may be formed of a greater number of sub-transistors.

[0127] Figure 8 is a circuit diagram of a pixel according to a third embodiment of the present disclosure. In Figure 8 order to facilitate description, a pixel connected to the n-th pixel row (n is an integer greater than 0) is shown as an example.

[0128] Referring to Figure 8 , a pixel circuit PX according to one or more embodiments may include a driving transistor DT, a light-emitting element LD connected to the driving transistor DT, and a control circuit for controlling the magnitude of a driving current applied to the light-emitting element LD through the driving transistor DT. For example, the control circuit may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2'.

[0129] A first electrode of the driving transistor DT is connected to a high-potential driving voltage VDD, and a second electrode of the driving transistor DT is connected to a third node N3. A gate of the driving transistor DT is connected to a second node N2. The driving transistor DT may be turned on according to a voltage applied to the second node N2 to control the magnitude of a driving current flowing to the light-emitting element LD.

[0130] A first electrode of the first transistor T1 is connected to a data line DL, and a second electrode of the first transistor T1 is connected to a first node N1. A gate of the first transistor T1 may be connected to a first gate line GL1 to receive a first scan signal S1. The first transistor T1 may be turned on according to the first scan signal S1 applied to the first gate line GL1 to transmit a data voltage Vdata applied to the data line DL to the first node N1. The first transistor T1 may be referred to as a "first switching transistor".

[0131] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 may store a voltage corresponding to a voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 may store a voltage corresponding to a difference between the data voltage Vdata applied to the data line DL and the voltage at the second node N2, and hold the stored voltage for one frame period, thereby stabilizing the voltage of the gate (i.e., the second node N2) of the driving transistor DT. The first transistor C1 may be referred to as a "storage capacitor".

[0132] The second transistor T2 is connected between the second node N2 and the third node N3. The gate of the second transistor T2 may be connected to the second gate line GL2 to receive the second scan signal S2. The second transistor T2 may be turned on according to the second scan signal S2 applied to the second gate line GL2 to electrically connect the gate (the second node N2) of the driving transistor DT and the second electrode (the third node N3). The second transistor T2 may be referred to as the "second switching transistor".

[0133] The first electrode of the third transistor T3 is formed to receive the reference voltage Vref, and the second electrode of the third transistor T3 is connected to the first node N1. The gate of the third transistor T3 may be connected to the emission line EL to receive the emission signal EM. The third transistor T3 may be turned on according to the emission signal EM applied to the emission line EL to transmit the reference voltage Vref to the first node N1. The third transistor T3 may be referred to as the "third switching transistor".

[0134] The fourth transistor T4 is connected between the third node N3 and the fourth node N4. The gate of the fourth transistor T4 may be connected to the emission line EL to receive the emission signal EM. The fourth transistor T4 may be turned on according to the emission signal EM applied to the emission line EL to electrically connect the driving transistor DT (the third node N3) and the light-emitting element LD (the fourth node N4). The fourth transistor T4 may be referred to as the "light-emitting transistor".

[0135] The first electrode of the fifth transistor T5 is formed to receive the initialization voltage Vini (connected to the initialization voltage line ViniL), and the second electrode of the fifth transistor T5 is connected to the fourth node N4. The gate of the fifth transistor T5 may be connected to the second gate line GL2 to receive the second scan signal S2. The fifth transistor T5 may be turned on according to the second scan signal S2 applied to the second gate line GL2 to apply the initialization voltage Vini to the anode (the fourth node N4) of the light-emitting element LD. The fifth transistor may be referred to as the "fourth switching transistor".

[0136] The first electrode of the sixth transistor T6 is formed to receive the initialization voltage Vini, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. The gate of the sixth transistor T6 may be connected to the inverted emission line IEL to receive the inverted emission signal IEM. The sixth transistor T6 may be turned on according to the inverted emission signal IEM applied to the inverted emission line IEL to apply the initialization voltage Vini to the anode (the fourth node N4) of the light-emitting element LD. The sixth transistor T6 may be referred to as the "anode initialization transistor".

[0137] The second capacitor C2' is connected between the inverted emission line IEL and the first node N1. When the inverted emission signal IEM is applied to the inverted emission line IEL, the second capacitor C2' can be formed to transfer a coupling voltage to the first node N1. The second capacitor C2' can be referred to as a "coupling capacitor".

[0138] The anode of the light-emitting element LD can be connected to the fourth node N4, and the cathode of the light-emitting element LD can be connected to the low-potential drive voltage VSS. When the drive transistor DT and the fourth transistor T4 are turned on, a current path can be formed between the high-potential drive voltage VDD and the low-potential drive voltage VSS so that a drive current can flow to the light-emitting element LD. The light-emitting element LD can emit light with a brightness corresponding to the magnitude of the applied drive current.

[0139] Figure 9 is a diagram showing the driving Figure 8 method of the pixel according to the third embodiment of the present disclosure shown in the figure.

[0140] See Figure 9 , in the variable refresh rate mode, one frame can be configured as a combination of at least one refresh period RP and at least one skip period SP.

[0141] The refresh period RP can include an initialization period t1, a sampling period t2, a holding period t3, and a light-emitting period t4.

[0142] During the initialization period t1, a second scan signal S2 with a conductive level is applied to turn on the second transistor T2 and the fifth transistor T5. In addition, during the initialization period t1, a light-emitting signal EM with a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. Therefore, during the initialization period t1, the reference voltage Vref is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4 and the third node N3.

[0143] When the second transistor T2 is turned on, the voltage at the third node N3 can be transferred to the second node N2. Therefore, the initial voltage at the second node N2 can correspond to the initialization voltage Vini. During the initialization period t1, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini. In addition, during the initialization period t1, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini in response to the charging voltage of the first capacitor C1.

[0144] Meanwhile, during the initialization period t1, the anode of the light-emitting element LD can be initialized to the initialization voltage Vini in response to the voltage at the fourth node N4.

[0145] During the sampling period t2, a first scan signal S1 at a conductive level is further applied to turn on the first transistor T1. In addition, during the sampling period t2, the light emission signal EM can be switched to a cut-off level to turn off the third transistor T3 and the fourth transistor T4. Conversely, during the sampling period t2, the inverted light emission signal IEM is switched to a conductive level. Therefore, the sixth transistor T6 can be turned on in response to the conductive-level inverted light emission signal IEM. Thus, during the sampling period t2, the data voltage Vdata applied to the data line DL is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4.

[0146] During the sampling period t2, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the data voltage Vdata and the initialization voltage Vini. In addition, during the sampling period t2, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the data voltage Vdata and the initialization voltage Vini in response to the charging voltage of the first capacitor C1.

[0147] When the charging voltage of the first capacitor C1 is transmitted to the gate of the driving transistor DT, the source-gate voltage of the driving transistor DT is higher than the threshold voltage Vth, so the driving transistor DT can be turned on. In this case, the source-drain current of the driving transistor DT can be determined based on the data voltage Vdata, the reference voltage Vref, the initialization voltage Vini, and the threshold voltage of the driving transistor DT.

[0148] When the source-gate voltage reaches the threshold voltage of the driving transistor DT, the driving transistor DT can supply the source-drain current to the third node N3. In addition, the second transistor T2 can supply the voltage at the third node N3 to the second node N2. In this way, when the driving transistor DT is turned on, the voltage at the second node N2 and the source-drain current of the driving transistor DT change, and finally the voltage at the second node N2 converges to a voltage corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0149] Meanwhile, during the sampling period t2, since the initialization voltage Vini is applied to the fourth node N4 through the sixth transistor T6, the anode of the light-emitting element LD can hold the initialization voltage Vini in response to the voltage at the fourth node N4.

[0150] During the holding time t3, the first scan signal S1 and the second scan signal S2 are switched to a cut-off level to turn off the first transistor T1, the second transistor T2, and the fifth transistor T5. During the holding period t3, the voltage at the second node N2 can be stably held through the first capacitor C1.

[0151] During the light emission period t4, a light emission signal EM at a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. During the light emission period t4, a current path is formed from the high-potential drive voltage VDD through the drive transistor DT to the light emitting element LD. Therefore, a drive current having a magnitude corresponding to the voltage programmed into the drive transistor DT can flow along the current path to cause the light emitting element LD to emit light with a corresponding brightness.

[0152] The skip period SP may include an anode initialization period t5 and a light emission period t6.

[0153] During the anode initialization period t5, the light emission signal EM may be switched to a cut-off level to turn off the third transistor T3 and the fourth transistor T4. On the contrary, during the anode initialization period t5, the inverted light emission signal IEM is switched to a conductive level. Therefore, the sixth transistor T6 can be turned on in response to the conductive-level inverted light emission signal IEM. Therefore, during the anode initialization period t5, the initialization voltage Vini is applied to the fourth node N4.

[0154] During the anode initialization period t5, due to the initialization voltage Vini applied to the anode of the light emitting element LD, the light emitting element LD does not emit light. On the contrary, the gate voltage of the drive transistor DT can be maintained at the voltage programmed during the previous refresh period RP through the first capacitor C1.

[0155] During the anode initialization period t5, when the inverted light emission signal IEM is applied to the inverted light emission line IEL, a parasitic capacitance (coupling voltage) can be generated in the second capacitor C2, so the voltage at the second node N2 can be reduced (recoil) at a predetermined level Δ. When the source voltage of the drive transistor DT remains unchanged, the reduction in the voltage at the first node N1 increases the source-gate voltage of the drive transistor DT. Therefore, the drive transistor DT can remain in the on state during the anode initialization period t5, and the hysteresis of the drive transistor DT can be reduced.

[0156] Meanwhile, during the anode initialization period t5, since the initialization voltage Vini is directly applied to the anode of the light emitting element LD, the voltage of the anode can be charged at a faster speed, thereby minimizing or at least reducing the charging delay of the light emitting element LD. Through anode initialization, there is no deviation in the brightness integration amount according to the refresh rate, and it is possible to suppress flicker caused by differences in the brightness integration amount.

[0157] During the light emission period t6, a light emission signal EM at a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. During the light emission period t4, the light emitting element LD can emit light with a brightness corresponding to the voltage programmed during the previous refresh period RP.

[0158] Meanwhile, during the anode initialization period t5 before the light emission period t6, the anode of the light emitting element LD is charged to the initialization voltage Vini. Therefore, during the light emission period t6, the brightness of the light emitting element LD can reach the target brightness more quickly, thereby minimizing or at least reducing the charging delay of the light emitting element LD. Specifically, since the initialization voltage Vini can be separated from the reference voltage Vref and supplied to the anode of the light emitting element LD, the voltage level of the initialization voltage Vini can be adjusted independently, and the charge and discharge delay time of the light emitting element LD can be effectively controlled.

[0159] Figure 10 is a cross-sectional view showing a stacked form of a display device according to one or more embodiments.

[0160] Referring to Figure 10 , a thin film transistor TFT for driving the light emitting element LD may be provided on the substrate 101 in the display area AA. In Figure 10 , for ease of description, only the driving transistor DT among the various thin film transistors that may be included in the display device 1 is shown (see Figure 5 ), but the thin film transistor TFT is not limited thereto. Hereinafter, although an example in which the thin film transistor TFT has a coplanar structure will be described, the thin film transistor TFT may be implemented as any one of various other structures, such as a staggered structure.

[0161] The driving transistor DT can control the current supplied from the high potential driving voltage VDD to the light emitting element LD in response to the data signal supplied to the gate 125. Therefore, the driving transistor DT can control the light emitting intensity of the light emitting element LD. In this case, a constant current may be supplied to the light emitting element LD until the voltage charged in the storage capacitor (e.g., Figure 5 the first capacitor C1 in Figure 1 ) supplies the data signal of the next frame, so that the light emitting state of the light emitting element LD can be maintained. The high potential driving voltage line PL1 for supplying the high potential driving voltage VDD (see Figure 1 ) may be formed parallel to the data line DL (see

[0162] The thin film transistor TFT may include a semiconductor layer 115 provided on the first insulating layer 110, a gate 125 overlapping the semiconductor layer 115 (the second insulating layer 120 is interposed between the semiconductor layer 115 and the gate 125), and a source and a drain 140 formed on the third insulating layer 135 and in contact with the semiconductor layer 115.

[0163] The semiconductor layer 115 can be a region where a channel is formed when the thin-film transistor TFT is driven. The semiconductor layer 115 can be formed of an oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or various organic semiconductors (e.g., pentacene), but is not limited thereto.

[0164] The semiconductor layer 115 can be formed on the first insulating layer 110. The semiconductor layer 115 can include a channel region, a source region, and a drain region. The channel region can overlap with the gate 125 (the first insulating layer 110 is interposed between the channel region and the gate 125) to form a channel region between the source and the drain 140. The source region is electrically connected to the source 140 through a contact hole penetrating the second insulating layer 120 and the third insulating layer 135. The drain region is electrically connected to the drain 140 through a contact hole penetrating the second insulating layer 120 and the third insulating layer 135.

[0165] The buffer layer 105 and the first insulating layer 110 can be provided between the semiconductor layer 115 and the substrate 101. The buffer layer 105 can delay the diffusion of moisture and / or oxygen that has penetrated into the substrate 101. The first insulating layer 110 can protect the semiconductor layer 115 and block various types of impurities introduced from the substrate 101.

[0166] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 can be made of a material having different etching characteristics from the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 can be made of any one of silicon nitride (SiN x ) and silicon oxide (SiO x ). The remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 can be made of the other of silicon nitride (SiN x ) and silicon oxide (SiO x ). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 can be made of silicon nitride (SiN x ), while the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 can be made of silicon oxide (SiO x ), but is not limited thereto.

[0167] The gate 125 may be formed on the second insulating layer 120 and may overlap with the channel region of the semiconductor layer 115 (the second insulating layer 120 is interposed between the gate 125 and the semiconductor layer 115). The gate 125 may be made of a first conductive material, and the first conductive material is a single layer or multiple layers made of one or more of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but is not limited thereto.

[0168] The source electrode 140 may be connected to the source region of the semiconductor layer 115 exposed through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may face the source electrode 140 and may be connected to the drain region of the semiconductor layer 115 through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The source and drain electrodes 140 may be made of a second conductive material, and the second conductive material is a single layer or multiple layers made of an alloy of any one or two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but is not limited thereto.

[0169] The connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be exposed through a connection electrode contact hole 156 passing through the protective film 145 and the first intermediate layer 150 and connected to the drain electrode 140. The connection electrode 155 may be made of the same or similar low-resistivity material as the drain electrode 140, but is not limited thereto.

[0170] The light-emitting element LD including the light-emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light-emitting element LD may include an anode 171, at least one light-emitting layer 172 formed on the anode 171, and a cathode 173 formed on the light-emitting layer 172.

[0171] The anode 171 may be disposed on the first intermediate layer 150 through a contact hole passing through the second intermediate layer 160 and electrically connected to the connection electrode 155 exposed upward from the second intermediate layer 160.

[0172] The anode 171 of each pixel is formed to be exposed through the bank layer 165. The bank layer 165 may be made of an opaque material (e.g., black) to prevent interference of light between adjacent pixels. In this case, the bank layer 165 may contain a light-shielding material made of at least any one of a colored pigment, organic black, and carbon, but is not limited thereto.

[0173] At least one light-emitting layer 172 may be formed on the anode 171 in the light-emitting region defined by the bank layer 165. The at least one light-emitting layer 172 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer located on the anode 171, and the respective layers may be sequentially stacked or stacked in the reverse order in the light-emitting direction. Additionally, the light-emitting layer 172 may include a first light-emitting laminate and a second light-emitting laminate that face each other and have a charge generation layer interposed therebetween. In this case, since the light-emitting layer 172 of either the first light-emitting laminate or the second light-emitting laminate may generate blue light, and the light-emitting layer 172 of the other of the first light-emitting laminate and the second light-emitting laminate may generate yellow-green light, white light may be generated by the first light-emitting laminate and the second light-emitting laminate. The white light emitted from the light-emitting laminate is incident on a color filter located above or below the light-emitting layer 172, enabling a color image to be realized. As another example, a color image may be realized by emitting color light corresponding to each pixel from each light-emitting layer 172 without a separate color filter. For example, the light-emitting layer 172 of a red pixel may emit red light, the light-emitting layer 172 of a green pixel may emit green light, and the light-emitting layer 172 of a blue pixel may emit blue light.

[0174] The cathode 173 may be formed to face the anode 171 (the light-emitting layer 172 is interposed between the cathode 173 and the anode 171), and the cathode 173 may receive a high-potential driving voltage VDD.

[0175] The encapsulation layer 180 may prevent external moisture or oxygen from entering the light-emitting element LD that is vulnerable to external moisture or oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. Hereinafter, the structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked will be described as an example.

[0176] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third encapsulation layer 183 may be formed on the substrate 101 on which the second encapsulation layer 182 is formed, and together with the first encapsulation layer 181, is formed to surround the upper surface, lower surface, and side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 can minimize or at least reduce or prevent external moisture or oxygen from flowing into the light-emitting element LD. The first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO N ), or aluminum oxide (A1 2 O 3)。Since the first encapsulation layer 181 and the third encapsulation layer 183 are deposited in a low-temperature atmosphere, the light-emitting element LD, which is vulnerable to a high-temperature atmosphere during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183, can be prevented from being damaged.

[0177] The second encapsulation layer 182 can act as a buffer to relieve the interlayer stress caused by the bending of the display device 1 and flatten the step difference between layers. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed using a non-photosensitive organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxycarbide (SiOC)), or a photosensitive organic insulating material (e.g., photoacrylic), but the material is not limited thereto. When the second encapsulation layer 182 is formed by an inkjet method, a dam DAM can be provided to prevent the liquid second encapsulation layer 182 from spreading to the edge of the substrate 101. The dam DAM can be provided closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM can prevent the second encapsulation layer 182 from spreading to the pad region where the conductive pad provided on the outermost side of the substrate 101 is located.

[0178] The dam DAM can be designed to prevent the spread of the second encapsulation layer 182. However, when the second encapsulation layer 182 is formed to exceed the height of the dam DAM during the process, the second encapsulation layer 182, which is an organic layer, may be exposed to the outside, and thus moisture and the like may easily flow into the light-emitting element. Therefore, to prevent this, at least two dams DAM can be formed.

[0179] The dam DAM can be provided on the protective film 145 in the non-display area NAA. In addition, the dam DAM can be formed simultaneously with the first intermediate layer 150 and the second intermediate layer 160. When the first intermediate layer 150 is formed, the lower layer of the dam DAM can be formed together, and when the second intermediate layer 160 is formed, the upper layer of the dam DAM can be formed together. Therefore, the dam DAM can be formed by laminating into a double-layer structure. Therefore, the dam DAM can be made of the same material as the first intermediate layer 150 and the second intermediate layer 160, but it is not limited thereto.

[0180] The dam DAM can be formed to overlap with the low-potential driving voltage line PL2. For example, the low-potential driving voltage line PL2 can be formed on the lower layer of the area where the dam DAM is located in the non-display area NAA.

[0181] The low-potential driving voltage line PL2 formed in the form of GIP and the gate driver 20 can be formed in a form surrounding the outer side of the display panel, and the low-potential driving voltage line PL2 can be located outside the gate driver 20. Additionally, the low-potential driving voltage line PL2 can be connected to the anode 171 to apply a common voltage. The gate driver 20 is briefly shown in the plan view and cross-sectional view, but can be configured using thin film transistors TFT having the same structure as the thin film transistors TFT in the display area AA.

[0182] The low-potential driving voltage line PL2 is provided outside the gate driver 20. The low-potential driving voltage line PL2 is provided outside the gate driver 20 and surrounds the display area AA. The low-potential driving voltage line PL2 can be made of the same material as the source and drain 140 of the thin film transistor TFT, but is not limited thereto. For example, the low-potential driving voltage line PL2 can be made of the same material as the gate 125.

[0183] Additionally, the low-potential driving voltage line PL2 can be electrically connected to the anode 171. The low-potential driving voltage line PL2 can supply the low-potential driving voltage VSS to a plurality of pixels in the display area AA.

[0184] The touch layer 190 can be provided on the encapsulation layer 180. In the touch layer 190, the touch buffer film 191 can be located between the touch sensor metal including the touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 and the cathode 173 of the light-emitting element LD.

[0185] The touch buffer film 191 can block the inflow of chemical solutions (developer, etchant, etc.) or external moisture used in the manufacturing process of the touch sensor metal provided on the touch buffer film 191 into the light-emitting layer 172 containing organic materials. Therefore, the touch buffer film 191 can prevent damage to the light-emitting layer 172 that is vulnerable to chemical solutions or moisture.

[0186] The touch buffer layer 191 can be formed at a predetermined temperature (for example, a low temperature below 100 °C) to prevent damage to the light-emitting layer 172 made of an organic insulating material having a low dielectric constant of 1 to 3 and containing organic materials vulnerable to high temperatures. For example, the touch buffer film 191 can be made of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film 191 made of an organic insulating material and having a planarization property can prevent damage to the encapsulation layer 180 due to the bending of the organic light-emitting diode display device and the rupture of the touch sensor metal formed on the touch buffer film 191.

[0187] According to the mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 can be provided on the touch buffer film 191, and the touch electrodes 195 and 196 can be provided to cross each other.

[0188] The touch electrode connection lines 192 and 194 can be electrically connected to the touch electrodes 195 and 196. The touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 can be located on different layers (the touch insulating film 193 is inserted therebetween).

[0189] The touch electrode connection lines 192 and 194 can be arranged to overlap with the bank layer 165, thereby preventing a reduction in the aperture ratio.

[0190] Meanwhile, a part of the touch electrode connection line 192 can be electrically connected to a touch driving circuit (not shown) through a touch pad 198 after passing through the upper and side portions of the encapsulation layer 180 and the upper and side portions of the dam DAM.

[0191] After receiving a touch driving signal from the touch driving circuit, a part of the touch electrode connection line 192 can transmit the touch driving signal to the touch electrodes 195 and 196 and transmit a touch sensing signal from the touch electrodes 195 and 196 to the touch driving circuit.

[0192] A touch protection film 197 can be provided on the touch electrodes 195 and 196. In the drawings, the touch protection film 197 is shown as being provided only on the touch electrodes 195 and 196, but is not limited thereto, and the touch protection film 197 can extend to an area before or after the dam DAM and can be provided on the touch electrode connection line 192.

[0193] In addition, a color filter (not shown) can be provided on the encapsulation layer 180, and the color filter can be located on the touch layer or between the encapsulation layer 180 and the touch layer 190.

[0194] The pixel according to an embodiment of the present disclosure and a display device including the pixel can prevent a charging delay of a light-emitting element during low-frequency driving in a variable refresh rate mode and can adjust characteristics of a driving transistor and a turn-on bias stress.

[0195] The pixel according to an embodiment of the present disclosure and a display device including the pixel can minimize or at least reduce a flicker phenomenon in a variable refresh rate mode and can uniformly control overall brightness.

[0196] The pixel according to an embodiment of the present disclosure and a display device including the pixel have a hybrid form capable of minimizing or at least reducing leakage current by using an oxide semiconductor thin film transistor.

[0197] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, those skilled in the art to which the present disclosure pertains will be able to understand that the above technical configurations of the present disclosure can be implemented in other specific forms without changing the technical concept or basic features of the present disclosure. Therefore, it should be understood that the above embodiments are exemplary rather than restrictive in all aspects. In addition, the scope of the present disclosure is described by the following appended claims rather than the specific embodiments. Furthermore, the meaning and scope of the claims and all changes or modifications derived from equivalent concepts should be construed as being included within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: A light-emitting element having an anode; a driving transistor having a first electrode connected to a high potential driving voltage line, a second electrode connected to the light emitting element, and a gate, and the driving transistor is configured to control the magnitude of a driving current supplied to the light emitting element in response to a voltage applied to the gate of the driving transistor; a first switch transistor, the first switch transistor having a gate, the first switch transistor being connected between the data line and the gate of the driving transistor, and the first switch transistor being configured to receive a first scan signal through the gate of the first switch transistor; a light emitting transistor having a gate, the light emitting transistor being connected between the driving transistor and the light emitting element, and the light emitting transistor being configured to receive a light emitting signal through the gate of the light emitting transistor; as well as An initialization transistor having a gate, the initialization transistor is connected between an initialization voltage line and the anode of the light-emitting element, and the initialization transistor is configured to receive an inverted light-emitting signal through the gate of the initialization transistor, the phase of the inverted light-emitting signal being opposite to the phase of the light-emitting signal.

2. The pixel circuit according to claim 1, wherein: In the variable refresh rate mode, the pixel circuit is driven at a frequency of one frame including an anode initialization period and a light emitting period, wherein, during the anode initialization period, the light emitting signal of the cut-off level is applied, wherein, during the light emitting period, the light emitting signal of the on level is applied, and During the anode initialization period, the initialization transistor applies an initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal. 3 . The pixel circuit according to claim 2 , further comprising a coupling capacitor connected between an inverted light emitting signal line to which the inverted light emitting signal is applied and the gate of the driving transistor.

4. The pixel circuit according to claim 3, wherein: During the anode initialization period, the coupling capacitor transmits a coupling voltage corresponding to the inverted light emitting signal to the gate of the driving transistor. 5 . The pixel circuit of claim 2 , further comprising a storage capacitor having a first node and a second node, the storage capacitor being connected to the first switching transistor through the first node and to the gate of the driving transistor through the second node. 6 . The pixel circuit according to claim 5 , further comprising a coupling capacitor connected between an inverted light emitting signal line to which the inverted light emitting signal is applied and the first node.

7. The pixel circuit according to claim 5, further comprising: a second switch transistor having a gate, the second switch transistor being connected between the gate of the drive transistor and the second electrode of the drive transistor, and the second switch transistor being configured to receive a second scan signal through the gate of the second switch transistor; a third switch transistor, the third switch transistor having a gate, the third switch transistor being connected between a reference voltage line and the first node, and the third switch transistor receiving the light emitting signal through the gate of the third switch transistor; as well as A fourth switch transistor has a gate, is connected between the initialization voltage line and the anode of the light emitting element, and is configured to receive the second scan signal through the gate of the fourth switch transistor.

8. The pixel circuit according to claim 7, wherein: The second switching transistor includes a plurality of sub-transistors connected in series, the plurality of sub-transistors include a plurality of gates, and the plurality of sub-transistors receive the second scan signal through the plurality of gates.

9. A display device, comprising: The display panel comprises a display area and a non-display area adjacent to the display area, wherein the display area has a plurality of pixel circuits; at least one gate driver configured to apply a first scanning signal, a light emitting signal, and an inverted light emitting signal to the plurality of pixel circuits, wherein a phase of the inverted light emitting signal is opposite to a phase of the light emitting signal; a data driver configured to apply data voltages to the plurality of pixel circuits; a power supply unit configured to apply a voltage for driving the plurality of pixel circuits; as well as a timing controller configured to control the driving timing of the display panel, Wherein, each pixel circuit of the plurality of pixel circuits comprises: A light-emitting element having an anode; a driving transistor having a first electrode connected to a high potential driving voltage line, a second electrode connected to the light emitting element, and a gate, and the driving transistor is configured to control the magnitude of a driving current supplied to the light emitting element in response to a voltage applied to the gate of the driving transistor; a first switching transistor configured to transmit the data voltage to the gate of the driving transistor in response to the first scan signal; a light emitting transistor configured to form a current path between the driving transistor and the light emitting element in response to the light emitting signal; and The initialization transistor is configured to transmit an initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal.

10. The display device according to claim 9, wherein: The at least one gate driver includes a plurality of gate drivers symmetrically disposed on a first side of the non-display area and a second side of the non-display area, respectively.

11. The display device according to claim 10, wherein: Each gate driver of the plurality of gate drivers comprises: a first shift register configured to output the first scanning signal; a second shift register configured to output a second scanning signal; a third shift register configured to output the light emitting signal; and The fourth shift register is configured to output the inverted light emitting signal.

12. The display device according to claim 11, wherein: The fourth shift register is closer to the display area than the third shift register, and the fourth shift register is configured as follows: receiving the light emission signal output from the third shift register to the plurality of pixel circuits; and The phase of the received light emitting signal is inverted to generate the inverted light emitting signal.

13. The display device according to claim 9, wherein: In the variable refresh rate mode, the timing controller drives the plurality of pixel circuits at a frequency of one frame including an anode initialization period and a light emitting period, wherein, during the anode initialization period, the at least one gate driver applies the light emission signal of the cut-off level to the plurality of pixel circuits, wherein, during the light emitting period, the at least one gate driver applies a light emitting signal of a conduction level to the plurality of pixel circuits, and During the anode initialization period, the initialization transistor applies the initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal.

14. The display device according to claim 13, wherein: The pixel circuit further includes a coupling capacitor connected between an inverted phase light emitting signal line to which the inverted phase light emitting signal is applied and the gate of the driving transistor.

15. The display device according to claim 14, wherein: During the anode initialization period, the coupling capacitor transmits a coupling voltage corresponding to the inverted light emitting signal to the gate of the driving transistor.

16. The display device according to claim 13, wherein: The pixel circuit further includes a storage capacitor having a first node and a second node, the storage capacitor being connected to the first switching transistor through the first node and to the gate of the driving transistor through the second node.

17. The display device according to claim 16, wherein: The pixel circuit further includes a coupling capacitor connected between an inverted phase light emitting signal line to which the inverted phase light emitting signal is applied and the first node.

18. The display device according to claim 16, wherein: The pixel circuit further comprises: a second switch transistor having a gate, the second switch transistor being connected between the gate of the drive transistor and the second electrode of the drive transistor, and the second switch transistor being configured to receive a second scan signal through the gate of the second switch transistor; a third switch transistor, the third switch transistor having a gate, the third switch transistor being connected between a reference voltage line and the first node, and the third switch transistor being configured to receive the light emission signal through the gate of the third switch transistor; and A fourth switch transistor has a gate, is connected between the initialization voltage line and the anode of the light emitting element, and is configured to receive the second scan signal through the gate of the fourth switch transistor. 19 . The display device according to claim 18 , the second switching transistor comprises a plurality of sub-transistors connected in series, and the plurality of sub-transistors comprise a plurality of gates, and the plurality of sub-transistors receive the second scan signal through the plurality of gates.

20. A pixel circuit comprising: A light-emitting element having an anode; a driving transistor having a first electrode connected to the high potential driving voltage line, a second electrode connected to the light emitting element, and a gate connected to the data line; a light emitting transistor having a first electrode connected to the driving transistor, a second electrode connected to the light emitting element, and a gate connected to a light emitting signal line; as well as an initialization transistor having a first electrode connected to an initialization voltage line, a second electrode connected to the anode of the light emitting element, and a gate connected to an inverted light emitting signal line; as well as A coupling capacitor connected between the inverted light emitting signal line and the data line, The light emission signal is supplied through the light emission signal line, and the inverted light emission signal is supplied through the inverted light emission signal line, and the phase of the inverted light emission signal is opposite to the phase of the light emission signal.

21. A method for driving the pixel circuit of claim 20, wherein: driving the pixel circuit in a variable refresh rate mode, each of a plurality of frames including at least one refresh period and at least one skip period, wherein each of the at least one skip period comprises an initialization period and a light emitting period, and During the initialization period, an inverted light emitting signal having a conduction level is applied to the gate of the initialization transistor, and an initialization voltage is applied to the anode of the light emitting element.

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