An 8K LCD screen TCON board and a high-speed differential signal output method

Abstract

This invention provides an 8K LCD screen TCON board and its high-speed differential signal output method. The TCON board scales the vertical resolution of the input image to 1 / N of the LCD screen's vertical resolution, ensuring that the number of effective image data lines output within one image frame is 1 / N of the LCD screen's vertical resolution, where N ranges from 2 to 4. This invention reduces the data transmission rate of the TCON board's high-speed differential signal, avoiding the need for a high-speed transceiver to output high-speed differential signals, thereby significantly reducing the cost of the 8K LCD screen TCON board's main control chip.

Description

Technical Field

[0001] This invention relates to the field of TCON board technology, and in particular to an 8K LCD screen TCON board, its high-speed differential signal output method, and the TCON board itself. Background Technology

[0002] With the development of technology, the resolution of LCD screens is getting higher and higher. The data bandwidth required for TCON boards to drive high-resolution LCD screens is very high. Taking a common 8K LCD screen with a resolution of 7680*4320, a refresh rate of 60Hz, and 24 source driver chips as an example, the image data transmission bandwidth between the TCON board and the LCD screen is as high as about 65Gbps. Each source driver chip on the LCD screen usually transmits image data through a pair of high-speed differential signals. The data transmission rate of each pair of high-speed differential signals is as high as 65Gbps / 24=2.7Gbps. Therefore, the TCON main control chip must integrate as many as 24 high-speed data transmitters to drive the 8K LCD screen normally.

[0003] FPGA (Field Programmable Gate Array) is a programmable integrated circuit pre-designed and implemented on a silicon chip. The advantage of using an FPGA chip as the TCON main control chip is its fast development speed and highly flexible function customization and modification. However, as mentioned above, the FPGA chip must integrate 24 high-speed transceivers to meet the basic data transmission bandwidth requirements of an 8K LCD screen. FPGA chips supporting 24 high-speed transceivers are very expensive, making such a high cost difficult for the market to accept. If the data transmission speed of the high-speed differential signal between the TCON board and the LCD screen can be reduced to below 1.5Gbps, then the ordinary differential ports of the FPGA can meet the data transmission bandwidth requirements, thereby significantly reducing the cost of the TCON board main control chip. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides an 8K LCD screen TCON board and its high-speed differential signal output method, which reduces the data transmission rate of the high-speed differential signal of the TCON board and avoids the use of a high-speed transceiver to output high-speed differential signals, thereby significantly reducing the cost of the main control chip.

[0005] The technical solution adopted by the present invention to solve its technical problem is: a high-speed differential signal output method for an 8K LCD screen TCON board, characterized in that the TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the LCD screen, and the number of effective image data rows output within one image frame is 1 / N of the vertical resolution of the LCD screen, where N ranges from 2 to 4.

[0006] As a further preferred embodiment, after the Kth row of image data of the high-speed differential signal is output, the LCD screen begins to scan the pixels of rows [(K-1)*N+1] to K*N in sequence, where the value of K ranges from 1 to 4320 / N; the pixels of rows [(K-1)*N+1] to K*N of the LCD screen together display the Kth row of valid image data output by the TCON board.

[0007] This invention also provides a TCON board for implementing the above-described high-speed differential signal output method. The TCON board includes a main control chip, a GOA driver chip, a power supply circuit, an input interface, and an output interface. The main control chip and the output interface are connected via 24 or 48 pairs of high-speed differential signals, with each pair of high-speed differential signals having a data transmission rate of:

[0008]

[0009] As a further preferred embodiment, the main control chip is an FPGA or a chip with integrated FPGA functionality.

[0010] As a further preferred embodiment, the main control chip consists of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module;

[0011] The signal decoding module is used to receive LVDS or V-by-One signals from the input interface, and after decoding the LVDS or V-by-One signals, obtains the line and field synchronization signals and parallel image data;

[0012] The GOA timing control module is used to receive horizontal and vertical synchronization signals and generate GOA control signals.

[0013] The resolution conversion and encoding module is used to receive parallel image data. The image data after resolution conversion and encoding is transmitted to the output interface through a high-speed differential signal.

[0014] As a further preferred embodiment, the horizontal resolution of the LCD screen is 7680 and the vertical resolution is 4320.

[0015] As a further preferred embodiment, the data transmission efficiency is 0.6 to 0.9.

[0016] As a further preferred embodiment, the color depth is 24 bits or 30 bits; the refresh rate is 60Hz or 120Hz.

[0017] The present invention also provides an electronic device, characterized in that it includes: an FPGA or a chip with integrated FPGA functions; and a memory for storing a configuration program for the FPGA or the chip with integrated FPGA functions; wherein the FPGA or the chip with integrated FPGA functions is configured by the configuration program to execute the high-speed differential signal output method of the 8K LCD screen TCON board.

[0018] The positive effects of this invention:

[0019] 1. Significantly reduces the data transmission rate of high-speed differential signals.

[0020] The high-speed differential signal output method provided by this invention adopts a group scanning mechanism. When the TCON board drives the LCD screen to scan the pixels of rows [(K-1)*N+1] to K*N, the source driver chip of the LCD screen outputs the pixel voltage corresponding to the effective image data of row K under the drive of the high-speed differential signal of the TCON board. The pixels of rows [(K-1)*N+1] to K*N of the LCD screen jointly display the effective image data of row K output by the TCON, thereby reducing the number of effective image data rows output by the TCON board in one image frame to 1 / N of the vertical resolution of the LCD screen. The data transmission rate of the high-speed differential signal of the TCON board is also reduced to 1 / N of the existing transmission rate.

[0021] 2. Significantly reduce the cost of the main control chip

[0022] This invention can reduce the data transmission speed of high-speed differential signals between the TCON board and the LCD screen to below 1.5Gbps. Therefore, this invention can use an FPGA or a chip with integrated FPGA functions as the main control chip of the TCON board, and can use the ordinary differential port of the FPGA to output high-speed differential signals, avoiding the use of a high-speed transceiver to output high-speed differential signals, thereby significantly reducing the cost of the main control chip.

[0023] 3. Improve system compatibility and stability

[0024] Low-speed signals reduce electromagnetic interference and signal attenuation, enhancing system reliability; meanwhile, conventional differential port designs simplify PCB routing and reduce production complexity.

[0025] 4. Flexible adaptation to different resolution requirements

[0026] By adjusting the N value (2-4), the transmission rate and display effect can be dynamically balanced to adapt to high refresh rate (e.g., 120Hz) or higher color depth (e.g., 30-bit) scenarios.

[0027] 5. Maintain display quality

[0028] The group scanning mechanism ensures that each line of image data synchronously drives N lines of pixels, avoiding screen tearing or delay and maintaining the 8K resolution display effect.

[0029] 6. Expand application scenarios

[0030] Low-cost solutions are suitable for consumer-grade 8K display devices (such as TVs and monitors), facilitating the adoption of high-resolution technology. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall frame structure of the TCON board described in this invention;

[0032] Figure 2 This is a functional structure diagram of the main control chip described in this invention;

[0033] Figure 3 This is a schematic diagram of the output of the high-speed differential signal described in this invention. Detailed Implementation

[0034] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0035] Reference Figure 3 The preferred embodiment of the present invention first provides a high-speed differential signal transmission method for an 8K LCD screen TCON board, wherein the TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the LCD screen, and the number of effective image data lines output within one image frame is 1 / N of the vertical resolution of the LCD screen, wherein the value of N ranges from 2 to 4.

[0036] Specifically, taking an 8K LCD screen with a resolution of 7680*4320 as an example, the TCON board scales the vertical resolution of the input image to 1 / N (i.e., 4320 / N) of the LCD screen's vertical resolution. After the TCON board finishes outputting the first line of high-speed differential signal image data, the LCD screen begins to scan the first to N lines of pixels sequentially. After the high-speed differential signal finishes outputting the second line of image data, the LCD screen begins to scan the (N+1) to 2N lines of pixels sequentially. After the high-speed differential signal finishes outputting the third line of image data, the LCD screen begins to scan the (2N+1) to 3N lines of pixels sequentially, and so on. After the high-speed differential signal finishes outputting the 4320 / N lines of image data, the LCD screen begins to scan the (4320-N+1) to 4320 lines of pixels sequentially. That is, after the high-speed differential signal finishes outputting the K line of image data, the LCD screen begins to scan the [(K-1)*N+1] to K*N lines of pixels sequentially, where the value of K ranges from 1 to 4320 / N. Using this invention, when the LCD screen scans the pixels of rows [(K-1)*N+1] to K*N, the source driver chip of the LCD screen outputs the pixel voltage corresponding to the effective image data of row K under the drive of the high-speed differential signal of the TCON board. The pixels of rows [(K-1)*N+1] to K*N of the LCD screen jointly display the effective image data of row K output by the TCON, thereby reducing the number of effective image data rows output by the TCON board in one image frame to 4320 / N, and the data transmission rate of the high-speed differential signal of the TCON board is also reduced to 1 / N of the existing transmission rate.

[0037] in, Figure 3 This is a schematic diagram of the high-speed differential signal output of the TCON board of the present invention. Within one frame, the high-speed differential signal sequentially outputs the first line of image data, the second line of image data, the third line of image data, and so on, up to the "4320 / N"th line of image data. There is a line idle interval between adjacent lines of image data, and a frame idle interval between adjacent frames. During the line idle and frame idle periods, the high-speed differential signal outputs clock training data, configuration data, etc., required by the encoding protocol. The frame time is determined by the refresh rate, which is 1 / 60 second or 1 / 120 second.

[0038] That is, the present invention employs a group scanning mechanism (such as...). Figure 3 As shown, the vertical resolution (4320 lines) of the LCD screen is divided into 4320 / N groups (N = 2~4), with each group containing N lines of pixels; for each line of valid image data output by the TCON board, the LCD screen synchronously scans N lines of pixels. Through this mechanism, the number of valid data lines output by the TCON board per frame is reduced to 4320 / N, and the data transmission rate is correspondingly reduced to 1 / N of the original rate.

[0039] like Figure 1 and Figure 2As shown, a preferred embodiment of the present invention also provides a TCON board for implementing the above-described high-speed differential signal output method. The TCON board includes a main control chip, a GOA driver chip, a power supply circuit, an input interface, and an output interface. The main control chip and the output interface are connected via 24 or 48 pairs of high-speed differential signals, with each pair of high-speed differential signals having a data transmission rate of:

[0040]

[0041] The input interface of the TCON board is used to input LVDS or V-by-One signals and power supply to the TCON board.

[0042] The GOA driver chip is driven by the GOA control signal generated by the main control chip of the TCON board, which generates the LCD screen GOA drive signal. The LCD screen GOA drive signal is connected to the output interface of the TCON board.

[0043] The main control chip consists of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module.

[0044] The signal decoding module is used to receive LVDS or V-by-One signals from the input interface, and after decoding the LVDS or V-by-One signals, obtains the line and field synchronization signals and parallel image data;

[0045] The GOA timing control module is used to receive horizontal and vertical synchronization signals and generate GOA control signals.

[0046] The resolution conversion and encoding module receives parallel image data. The image data, after resolution conversion and encoding, is transmitted to the output interface via high-speed differential signals. The TCON board main control chip uses the FPGA's ordinary differential port to output high-speed differential signals. The TCON board main control chip and the TCON board output interface are connected via 24 or 48 pairs of high-speed differential signals. The data transmission rate of each pair of high-speed differential signals is (taking an 8K LCD screen with a resolution of 7680*4320 as an example):

[0047]

[0048] The power supply circuit is used to generate the operating voltage of the TCON board's main control chip and the operating voltage of the LCD screen. The main control chip's operating voltage is connected to the main control chip to provide power to it, and the LCD screen's operating voltage is connected to the TCON board's output interface to provide power to the LCD screen.

[0049] The TCON board output interface outputs the LCD screen GOA drive signal, high-speed differential signal, and LCD screen operating voltage to the externally connected LCD screen.

[0050] The main control chip is an FPGA or a chip with integrated FPGA functions. It uses the FPGA's ordinary differential port to output high-speed differential signals, avoiding the use of a high-speed transceiver to output high-speed differential signals, thereby significantly reducing the cost of the main control chip.

[0051] Furthermore, the data transmission efficiency is defined as the total number of valid image data bits transmitted by the TCON board in one frame via high-speed differential signal / the total number of transmitted data bits. The total number of transmitted data bits includes not only valid image data but also clock training data, configuration data, etc. The data transmission efficiency ranges from 0.6 to 0.9.

[0052] In addition, the color depth is 24 bits or 30 bits; the refresh rate is 60Hz or 120Hz.

[0053] Taking a common resolution of 7680*4320, N=2, refresh rate of 60Hz, color depth of 24 bits, data transmission efficiency of 0.8, and high-speed differential signal pairs of 24 pairs as an example:

[0054] The data transmission rate of each pair of high-speed differential signals is 2.7 / 2 = 1.35Gbps, which is lower than 1.5Gbps. This rate can meet the performance requirements of ordinary FPGA differential ports. In other words, the present invention can meet the bandwidth requirements of data transmission using ordinary FPGA differential ports, thereby significantly reducing the cost of the TCON board main control chip.

[0055] Furthermore, a preferred embodiment of the present invention also provides an electronic device, characterized in that it includes: an FPGA or a chip with integrated FPGA functions; and a memory for storing a configuration program for the FPGA or the chip with integrated FPGA functions; wherein the FPGA or the chip with integrated FPGA functions is configured by the configuration program to execute the high-speed differential signal output method of the 8K LCD screen TCON board.

[0056] The above description is only a preferred embodiment of the present invention. It should be understood that the above description of the embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention, and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, etc. made within the idea and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A TCON board, characterized in that: It includes a main control chip, a GOA driver chip, a power supply circuit, an input interface, and an output interface. The main control chip and the output interface are connected via 24 or 48 pairs of high-speed differential signals, and the data transmission rate of each pair of high-speed differential signals is: The TCON board is used to implement the following method for high-speed differential signal output of the 8K LCD screen TCON board: The TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the LCD screen, and the number of effective image data rows output within one image frame is 1 / N of the vertical resolution of the LCD screen, with N ranging from 2 to 4. After the high-speed differential signal outputs the Kth row of image data, the LCD screen begins to scan the pixels of rows [(K-1)*N+1] to K*N sequentially, where K ranges from 1 to 4320 / N. The pixels of rows [(K-1)*N+1] to K*N on the LCD screen together display the Kth row of valid image data output by the TCON board.

2. A TCON board according to claim 1, characterized in that: The main control chip is an FPGA or a chip with integrated FPGA functionality.

3. A TCON board according to claim 2, characterized in that: The main control chip consists of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module. The signal decoding module is used to receive LVDS or V-by-One signals from the input interface, and after decoding the LVDS or V-by-One signals, obtains the line and field synchronization signals and parallel image data; The GOA timing control module is used to receive horizontal and vertical synchronization signals and generate GOA control signals. The resolution conversion and encoding module is used to receive parallel image data. The image data after resolution conversion and encoding is transmitted to the output interface through a high-speed differential signal.

4. A TCON board according to claim 1, characterized in that: The LCD screen has a horizontal resolution of 7680 and a vertical resolution of 4320.

5. A TCON board according to claim 1, characterized in that: The data transmission efficiency is 0.6 to 0.

9.

6. A TCON board according to claim 1, characterized in that: The color depth is 24 bits or 30 bits.

7. A TCON board according to claim 1, characterized in that: The refresh rate is 60Hz or 120Hz.

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