Method of operating memory controller, method of controlling memory device, and memory controller

Abstract

A method of operating a memory controller, a method of controlling a memory device, and a memory controller are provided. A method of operating a memory controller includes receiving first information of an MRS of a memory device, the first information of the MRS including a control parameter indicating that the memory device supports a DFE amount operation of a DQ pin of the memory device; transmitting a CAS command synchronized with the clock signal to the memory device; sending the write command to the memory device; transmitting a write clock signal synchronized with the clock signal to the memory device after a predetermined time elapses from the CAS command; transmitting the write data to the memory device through the data line; and transmitting the second information to the MRS of the memory device. The data lines are pre-driven for a predetermined pre-drive time at a logical low based on the control parameter. The second information of the MRS includes a global operating parameter and a per-pin operating parameter of the DFE amount operation, the global operating parameter being associated with the DQ pin, and the per-pin operating parameter being associated with a respective DQ pin.

Description

[0001] This application is a divisional application of the invention patent application with the application date of October 22, 2021, the application number of "202111231244.7", and the invention name of "Device, Memory Device, and Method for Storing Multiple Parameter Codes of Operation Parameters". Technical Field

[0002] The present disclosure relates to a device, a memory device, and a method of operating the same for storing multiple parameter codes of an operation parameter. Background Art

[0003] To support a high-speed interface with a memory device, a controller (or a central processing unit (CPU)) may provide a clock signal to the memory device. The memory device may process a signal received from the controller in response to the clock signal received from the controller, and synchronize a signal transmitted to the controller with the clock signal. According to the operating frequency of the clock signal, the memory device may support various data rates (e.g., 1600 Mbps, 2400 Mbps, 6400 Mbps, etc.). Due to the demand for high data rates, it is important to accurately capture a signal transmitted between the controller and the memory device at a high clock frequency.

[0004] Generally, a memory device includes a mode register that provides various operation parameters and control parameters for setting operation conditions of the memory device. Examples of the operation parameters and the control parameters include parameters associated with a burst length, a read latency / write latency, a preamble length / postamble length, an on-die termination (ODT) calibration, an impedance adjustment (ZQ) calibration, a reference voltage setting, etc.

[0005] The memory device transmits data to and receives data from the controller through data lines. Since physical characteristics of the data lines are different from each other, characteristics of signals carried through the corresponding data lines may be different. When operating at a high clock frequency, data transmitted to the memory device has a data eye diagram state. The data eye diagram is shown as a superposition of multiple data transitions representing jitter caused by noise. Depending on the environment of the corresponding data line, the data may exhibit a data eye diagram of different distorted waveforms.

[0006] When promoting reception of data according to signal characteristics of the corresponding data line when transmitting data to the memory device, a state in which an eye opening region of the data eye diagram of the corresponding data line is symmetric and maximized may be found, thereby promoting improvement of signal integrity (SI) characteristics of the data. Summary of the Invention

[0007] Example embodiments provide a device, a memory device, and a method of operating the same for storing multiple codes of an operation parameter.

[0008] According to an aspect of an example embodiment, there is provided a device including: a plurality of signal pins connected to a plurality of signal lines, wherein each of the plurality of signal pins is connected to a signal line among the plurality of signal lines, and each signal line carries a signal; and a mode register configuration configured to store a first parameter code and a second parameter code of an operation parameter of the device in a first register and a second register, respectively, wherein the first parameter code includes a global operation parameter code associated with an operation condition of a signal pin associated with the operation parameter, the second parameter code includes a per-pin operation parameter code associated with an operation condition of a corresponding signal pin associated with the operation parameter, and the per-pin operation parameter code is represented as an offset value from the global operation parameter code.

[0009] According to an aspect of an example embodiment, there is provided a memory device configured to be set to a current operation condition, the memory device including: a mode register configured to store a first parameter code and a second parameter code for setting a first operation condition and a second operation condition of an operation parameter of the memory device; and a control logic circuit configured to: set the first operation condition to the current operation condition by using the first parameter code of the operation parameter based on a first control code stored in the mode register, and set the second operation condition to the current operation condition by using the first parameter code and the second parameter code of the operation parameter based on a second control code stored in the mode register, wherein the second parameter code is represented as an offset value from the first parameter code.

[0010] According to an aspect of an example embodiment, there is provided a method of setting a current operation condition of a memory device, the method including: storing a first parameter code for setting a first operation condition of an operation parameter in a first register of a mode register; storing a second parameter code for setting a second operation condition of the operation parameter in a second register of the mode register, wherein the second parameter code is represented as an offset value from the first parameter code; setting the first operation condition to the current operation condition by using the first parameter code of the operation parameter; and setting the second operation condition to the current operation condition by using the first parameter code and the second parameter code of the operation parameter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and / or other aspects will be more clearly understood from the following detailed description of example embodiments with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing a memory system including a memory device according to an example embodiment.

[0013] Figure 2 is a block diagram of a memory device according to an exemplary embodiment.

[0014] Figure 3 is a flowchart showing Figure 1 the operation of the memory system.

[0015] Figure 4 is a conceptual diagram for describing a data operation circuit system according to an exemplary embodiment.

[0016] Figure 5A , Figure 5B and Figure 5C are diagrams for describing Figure 4 the reference voltage of the data line.

[0017] Figure 6 is a diagram showing a part of a mode register set (MRS) according to an exemplary embodiment.

[0018] Figure 7 is a diagram showing a part of the MRS according to an exemplary embodiment.

[0019] Figure 8 is a diagram showing the effect of a decision feedback equalizer (DFE) of a data line according to an exemplary embodiment.

[0020] Figure 9 is a diagram for describing Figure 8 the DFE.

[0021] Figure 10 is a diagram showing a part of the MRS according to an exemplary embodiment.

[0022] Figures 11 to 13 is a diagram for describing an example of the operation of a memory device according to an exemplary embodiment.

[0023] Figure 14 is a diagram for describing the swing width calibration of a data line according to an exemplary embodiment.

[0024] Figure 15 is a diagram for describing the pre - emphasis operation of a data row according to an exemplary embodiment. DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram of a memory system including a memory device according to an exemplary embodiment.

[0026] Referring to Figure 1, the memory system 10 may include a memory controller 100 and a memory device 120. The memory system 10 may represent an integrated circuit, an electronic device or system, a smart phone, a tablet PC, a computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a computing device (such as other suitable computers), a virtual machine or its virtual computing device. Optionally, the memory system 10 may be one of the components included in a computing system (e.g., a graphics card). According to an example embodiment, the memory system 10 may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a low-loaded DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small DIMM (SODIMM), etc.

[0027] The memory controller 100 may be connected to and communicate with the memory device 120 via a memory bus 110. The memory controller 100 may include a register control word (RCW) 102, a training circuit system 104, and a memory physical layer (PHY) 106.

[0028] The RCW 102 may be provided to control the memory device 120 according to initialization and / or operation characteristics. The RCW 102 may include various algorithms for configuring the memory controller 100 such that the memory controller 100 can interact with the memory device 120 properly. For example, codes indicating the frequency, timing, driving, and detailed operation parameters of the memory device 120 may be set to the RCW 102. Memory training of the memory device 120 may be performed according to the codes set to the RCW 102.

[0029] The training circuit system 104 may perform memory core parameter training associated with the memory core of the memory device 120 and / or perform peripheral circuit parameter training of peripheral circuits other than the memory core under the control of the memory controller 100. The training circuit system 104 may determine optimal parameters of the memory core parameters and / or peripheral circuit parameters of the memory device 120. The training circuit system 104 may perform memory training of the memory device 120 via the memory controller 100. In the present example embodiment, although the training circuit system 104 is described as being included in the memory controller 100, the training circuit system 104 may be included in the memory device 120 such that the memory device 120 may be the memory device performing memory training.

[0030] The memory PHY 106 provides a physical layer or electrical layer and logical layer for signals, frequencies, timings, drive signals, detailed operation parameters, and functionality required for efficient communication between the memory controller 100 and the memory device 120. The memory PHY 106 may support features of the Double Data Rate (DDR) protocol and / or the Low Power Double Data Rate (LPDDR) protocol of the Joint Electron Device Engineering Council (JEDEC) standard.

[0031] The memory PHY 106 may connect the memory controller 100 to the memory device 120 via the memory bus 110. To simplify the drawing, the clock signal CLK, command / address signal CA, and data DQ are shown to be provided between the memory controller 100 and the memory device 120 via a single signal line, but in reality, the clock signal CLK, command / address signal CA, and data DQ may be provided via multiple signal lines. The signal lines between the memory controller 100 and the memory device 120 may be connected through a connector. The connector may be implemented as pins, balls, signal lines, or other hardware components.

[0032] The clock signal CLK may be sent from the memory controller 100 to the memory device 120 via the clock signal line of the memory bus 110. The command / address signal CA may be sent from the memory controller 100 to the memory device 120 via the command / address bus of the memory bus 110. The chip select signal CS may be sent from the memory controller 100 to the memory device 120 via the chip select line of the memory bus 110. As Figure 11 shown, the chip select signal CS activated as a logic high may indicate that the command / address signal CA sent via the command / address bus is a command. The data DQ may be sent from the memory controller 100 to the memory device 120 or from the memory device 120 to the memory controller 100 via the data bus of the memory bus 110 including bidirectional signal lines.

[0033] The memory device 120 may write or read the data DQ under the control of the memory controller 100. The memory device 120 may include a memory cell array 200, a Mode Register Set (MRS) 210, and control logic circuitry 220.

[0034] The memory cell array 200 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at the intersection points of the word lines and the bit lines. The memory cells of the memory cell array 200 may include volatile memory cells (e.g., dynamic random access memory (DRAM) cells, static RAM (SRAM) cells, etc.), non-volatile memory cells (e.g., flash memory cells, resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, magnetic RAM (MRAM) cells, etc.), or some other type of memory cells.

[0035] The MRS 210 may be programmed to set a plurality of operation parameters, options, various functions, features, and modes of the memory device 120. When an MRS command is issued by the memory controller 100, the MRS 210 may store a parameter code including appropriate bit values to be provided to the command / address bus of the memory bus 110.

[0036] For example, the MRS 210 may be used to control burst length, read latency / write latency, preamble length / postamble length, write equalization enable / write equalization disable, decision feedback equalization (DFE) amount, pull-down / on die termination (ODT), pull-up / output high voltage (Voh) calibration, pre-emphasis, reference voltage setting, etc.

[0037] The burst length may be provided to set the maximum number of column positions that can be accessed for a read command and / or a write command. The read latency / write latency may be provided to define the clock cycle latency between a read command and / or a write command and the first bit of valid output data and / or input data. Write equalization may be provided to enable or disable skew compensation between a clock signal and a data strobe signal during a write operation.

[0038] The DFE amount may be provided to subtract the remainder of the bits of the previously read data DQ to determine the current data bit. The pull-down / ODT calibration and the pull-up / Voh calibration may be provided to improve signal integrity (SI) by adjusting the swing width and / or drive strength of the signals received through the command / address bus and / or the data bus.

[0039] The pre-emphasis function may be provided to improve SI by increasing the data eye opening area of the signals transmitted through the data bus. The reference voltage setting may be provided to compare with the logical value of the received signal to determine the logical value. The voltage used for comparison with the received signal may be referred to as the decision level. For example, in some embodiments, Figure 9At the input of sampler 920, a first value of the received signal observed as being higher than the decision level will cause the sampler to output a high voltage (“1”) as value SDQ0. The level of the input can be changed using the VREF operating parameter. In contrast, at Figure 9 At the input of sampler 920, a first value of the received signal observed as being lower than the decision level will cause the sampler to output a low voltage (“0”) as value SDQ0. See Figure 9 .

[0040] In addition, MRS 210 can be used to control DRAM-related delay locked loop (DLL) reset, DLL enable / disable, output drive strength, additional delay, termination data strobe (TDQS) enable / disable, input / output buffer enable / disable, CAS (Column Address Strobe) write delay, dynamic termination, write cyclic redundancy check (CRC), multi-purpose register (MPR) location function, MPR operation function, gear down mode, MPR read format, power-down mode, Vref monitoring, read preamble training mode, read preamble function, write preamble function, command and address (CA) parity check function, CRC error status, CA parity check error status, ODT function, data mask function, write data bus inversion (DBI) function, read DBI function, error detection code (EDC) hold mode, etc.

[0041] The control logic circuit 220 can receive the clock signal CLK through the clock signal line of the memory bus 110 and control the operation timing of the memory device 120. In addition to the clock signal CLK, the operation timing of the memory device 120 can also be provided based on signals (e.g., strobe signals) provided to the memory device 120. The control logic circuit 220 can receive commands received through the command / address bus and generate control signals for performing various memory operations in the memory device 120 in response to the commands.

[0042] Figure 2 is a block diagram of a memory device according to an exemplary embodiment.

[0043] Referring to Figure 1 and Figure 2 , the memory device 120 can include a memory cell array (MCA) 200, a row decoder 202, a word line driver 204, a column decoder 206, an input / output gating circuit 208, an MRS 210, a control logic circuit 220, an address buffer 230, an ODT circuit 240, a reference voltage generation circuit 250, a data input buffer 260, and a data output buffer 270.

[0044] The memory cell array 200 includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array 200 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The word lines WL can be connected to the memory cells in a row, and the plurality of bit lines BL can be connected to the memory cells in a column.

[0045] The row decoder 202 can select any one of the word lines WL connected to the memory cell array 200. The row decoder 202 can decode the row address ROW_ADDR received from the address buffer 230, select any one of the word lines corresponding to the row address ROW_ADDR, and connect the selected word line to the word line driver 204 that activates the selected word line. The column decoder 206 can select a predetermined number of bit lines among the bit lines BL of the memory cell array 200. The column decoder 206 can generate a column selection signal CSL by decoding the column address COL_ADDR received from the address buffer 230, and connect the bit lines selected by the column selection signal CSL to the input / output gating circuit 208. The input / output gating circuit 208 can include a read data latch for storing the read data of the bit lines selected by the column selection signal CSL and a write driver for writing the write data into the memory cell array 200. The read data stored in the read data latch of the input / output gating circuit 208 can be provided to the data bus through the data output buffer 270. The write data can be applied to the memory cell array 200 through the data input buffer 260 connected to the data bus and through the write driver of the input / output gating circuit 208.

[0046] The control logic circuit 220 can receive a clock signal CLK and a command CMD, and generate control signals CTRLS for controlling the operation timing and / or memory operations of the memory device 120. The control logic circuit 220 can use the control signals CTRLS to read data from the memory cell array 200 and write data into the memory cell array 200.

[0047] The MRS 210 can store information used by the control logic circuit 220 to configure the operation of the memory device 120 to set the operation conditions of the memory device 120. The MRS 210 can include registers for storing parameter codes of various operation parameters and control parameters for setting the operation conditions of the memory device 120. The parameter codes can be received by the memory device 120 through the command / address bus. The control logic circuit 220 provides the control signals CTRLS to the circuits of the memory device 120 to operate as set by the operation parameters and control parameters stored in the MRS 210. Generally, the term "parameter" represents a variable, and the term "parameter code" represents a pattern of bits on the command / address bus for executing a command related to the variable.

[0048] To minimize the transmission time of signals sent to / from the memory device 120, the swing width of the signals is reduced. As the swing width of the signals is reduced, the impact of external noise on the memory device 120 increases, and signal reflections caused by impedance mismatches at the interface become severe. To solve the impedance mismatch, the memory device 120 controls impedance matching by performing a ZQ calibration operation.

[0049] Pull-down / ODT calibration may be provided to turn on / off the termination resistance of the target memory device and / or fix the termination resistance of non-target memory devices. Pull-up / Voh calibration may be provided to meet the VOH specification SPEC by adjusting the pull-up strength in read operations. Pull-down / ODT calibration and pull-up / Voh calibration may be referred to as impedance adjustment operations, ZQ calibration, or offset removal operations for continuously adjusting the output and / or termination resistance of the memory device 120.

[0050] The ODT circuit 240 may provide a termination resistance for the command / address bus and / or data bus when enabled. The termination resistance may improve the SI of signals received through the bus. The enabling of the ODT circuit 240 and the magnitude of the termination resistance provided to the bus may be set by storing appropriate parameter codes into the MRS 210.

[0051] The reference voltage generation circuit 250 may provide a reference voltage VREF used by the circuits of the memory device 120. For example, the reference voltage VREF may be used by the control logic circuit 220 to compare with the voltage of signals received from the command bus to determine the logical values of the signals. The reference voltage VREF and / or the range of the reference voltage VREF may be set by storing reference voltage operation parameter codes in the MRS 210.

[0052] Figure 3 is a flowchart showing Figure 1 the operation of the memory system.

[0053] Referring to Figure 1 , Figure 2 and Figure 3 , in operation S310, the memory system 10 may perform initialization. When the memory system 10 is powered on, the memory controller 100 and the memory device 120 may perform initial setup operations according to a preset method. Default operation parameters may be set during the initialization of the memory device 120.

[0054] In operation S320, the memory system 10 may perform a command address training operation. The memory controller 100 and the memory device 120 may perform a command address training operation to improve the timing margins of the command CMD and the address ADDR.

[0055] In operation S330, the memory system 10 may perform a read training operation. The memory controller 100 may adjust the operation parameter code of the memory device 120 to have an optimal SI and data eye diagram for data read from the memory device 120.

[0056] In operation S340, the memory system 10 may perform a write training operation. The memory controller 100 may send data to the memory device 120 and adjust the operation parameter code of the memory device 120 such that the sent data has an optimal SI and data eye diagram.

[0057] In operation S350, after performing the initialization operation and the training operation in operations S310 to S340, the memory system 10 may perform a normal operation.

[0058] Figure 4 is a conceptual diagram for describing a data operation circuit system according to an exemplary embodiment. In the following exemplary embodiments, for ease of explanation, the terms data DQ and DQ may be used interchangeably.

[0059] Referring to Figure 2 and Figure 4 , multiple DQ lines may transmit and receive internal data DIO (hereinafter, referred to as "DIO data") through multiple DQ operation circuit systems 400 to 407, 408, 409 to 415. The DQ operation circuit systems 400 to 408 and 408 to 415 may each be an ODT circuit 240, a reference voltage generation circuit 250, a data input buffer 260, a data output buffer 270, or a DFE.

[0060] Generally, signal pins connected to the DQ lines may be referred to as DQ pins. A set of these signal pins may be referred to as multiple DQ pins.

[0061] The DQ0 line may transmit and receive DIO0 data through the DQ0 operation circuit system 400. The DQ1 line to the DQ7 line may transmit and receive DIO1 data to DIO7 data through the DQ1 operation circuit system 401 to the DQ7 operation circuit system 407. Similarly, the DQ8 line to the DQ15 line may transmit and receive DIO8 data to DIO15 data through the DQ8 operation circuit system 408 to the DQ15 operation circuit system 415. DQ0 to DQ7 may be referred to as a low DQ byte DQ[7:0], and DQ8 to DQ15 may be referred to as a high DQ byte DQ[15:8].

[0062] Figures 5A to 5C is a diagram for describing Figure 4 the reference voltage VREF of the data lines of

[0063] Figure 5AShows the SI of the DQ0 line when the reference voltage VREF of the DQ0 line is set to VREF1, VREF2, and VREF3. SI represents the size, vertical height, or width of the data eye diagram of the signal received through the DQ line. The larger the SI, the more accurately the DQ can be recognized. When the reference voltage VREF of the DQ0 line is set to VREF1, the DQ0 line can have SI1 signal integrity. When the reference voltage VREF of the DQ0 line is set to VREF2 or VREF3, the DQ0 line can have SI2 signal integrity or SI3 signal integrity. It can be seen that the SI2 signal integrity or SI3 signal integrity is less than the SI1 signal integrity. In other words, when the reference voltage VREF of the DQ0 line is set to VREF1, the DQ0 line can have optimal SI.

[0064] Referring to Figure 5B , when the reference voltages VREF of the DQ0 line, DQ1 line, and DQ2 line are set to VREF1, the DQ0 line, DQ1 line, and DQ2 line can have SI1 signal integrity, SI2 signal integrity, and SI3 signal integrity respectively. This is because the physical characteristics of the DQ0 line, DQ1 line, and DQ2 line are different from each other. In other words, when the reference voltage VREF is the same, different SIs can be obtained due to the different positions or physical characteristics of the DQ lines. In other words, when the reference voltage VREF is set to VREF1, the DQ0 line can have optimal SI, but the DQ1 line and DQ2 line may not have optimal SI.

[0065] Referring to Figure 5C , the reference voltage VREF of the DQ0 line can be set to VREF1, the reference voltage VREF of the DQ1 line can be set to VREF2, and the reference voltage VREF of the DQ2 line can be set to VREF3. In this case, the DQ0 line, DQ1 line, and DQ2 line can each have optimal SI. In other words, by setting different reference voltages VREF for the DQ0 line, DQ1 line, and DQ2 line respectively, each DQ line can have optimal SI.

[0066] It can be determined through Figure 3 the read training operation in operation S330 or the write training operation in operation S340 of the optimal reference voltage VREF of each of the above DQ lines, and the information about the optimal reference voltage VREF can be stored as a reference voltage parameter code in the MRS 210.

[0067] The eye diagram as Figures 5A to 5C shown indicates changing the reference level to sample the voltage passing through the eye at different levels as the reference level moves up or down. That is to say, Figures 5A to 5C the depiction in Figure 9The error that occurs in sampler 920 is minimized. For example, based on the added offset, Figure 8 the DFE output 810 is adjusted to occur at an optimal level at the input of Figure 9 sampler 920.

[0068] Figure 6 FIG. is a diagram showing a part of MRS 210 according to an exemplary embodiment.

[0069] Referring to Figure 2 and Figure 6 , MRS 210 may include a first mode register 610, a second mode register 620, and a third mode register 630. The first mode register 610, the second mode register 620, and the third mode register 630 each represent a register bank associated with each mode register that can be identified by each mode register address. The first mode register 610 can be identified by the first mode register address MR_A1, the second mode register 620 can be identified by the second mode register address MR_A2, and the third mode register 630 can be identified by the third mode register address MR_A3.

[0070] The first mode register 610, the second mode register 620, and the third mode register 630 can store operation parameter codes regarding the reference voltage VREF of the DQ lines. The first mode register 610 has three parameter codes stored by a plurality of registers OP[7:0] for the reference voltage VREF. The OP[2:0] registers can store the parameter VREFL for setting the reference voltage VREF of the DQ lines of the low DQ byte DQ[7:0]. The reference voltage parameter VREFL of the low DQ byte DQ[7:0] stored in the OP[2:0] registers can be represented by a 3-bit parameter code and can have, for example, 8 setting points or step coefficients. The OP[3] register can be reserved for future use (RFU), and the OP[6:4] registers can store the parameter VREFU for setting the reference voltage VREF of the DQ lines of the high DQ byte DQ[15:8]. The reference voltage parameter VREFU of the high DQ byte DQ[15:8] stored in the OP[6:4] registers can be represented by a 3-bit parameter code and can have, for example, 8 setting points or step coefficients. The reference voltage parameter VREFL of the low DQ byte DQ[7:0] and the reference voltage parameter VREFU of the high DQ byte DQ[15:8] can be referred to as global reference voltage parameters. The OP[7] register can store the control parameter VREFS, and the control parameter VREFS indicates whether the global reference voltage operation parameters VREFL and VREFU are supported for the DQ lines of the low DQ byte DQ[7:0] and the high DQ byte DQ[15:8]. The control parameter VREFS can be a 1-bit parameter code.

[0071] According to an exemplary embodiment, the global reference voltage operation parameters VREFL and VREFU for the low DQ byte DQ[7:0] and the high DQ byte DQ[15:8] can be represented by less than 3 bits or more than 3 bits. The control parameter VREFS indicating whether the global reference voltage operation parameters VREFL and VREFU for the reference voltage VREF with respect to the DQ lines are supported can include more than 1 bit.

[0072] The second mode register 620 has a parameter code for the reference voltage VREF of the DQ0 line stored in the OP[1:0] register. The OP[1:0] register can store a reference voltage sub-parameter VREFDQ0 that sets the reference voltage VREF of the DQ0 line. The reference voltage sub-parameter VREFDQ0 for the DQ0 line stored in the OP[1:0] register can be represented by a 2-bit parameter code and can have, for example, 4 set points or step coefficients.

[0073] By Figure 3 the read training operation in operation S330 or the write training operation in operation S340, the DQ0 line can have a reference voltage VREF (e.g., VREF1) with optimal SI (e.g., SI1). The reference voltage VREF set by the reference voltage parameter VREFL of the low DQ byte DQ[7:0] stored in the OP[2:0] register of the first mode register 610 will be applied to the DQ0 line. In the DQ0 line, a voltage difference (i.e., offset) can occur between the reference voltage VREF set by the reference voltage parameter VREFL for the low DQ byte DQ[7:0] and the reference voltage VREF with optimal SI obtained through the training operation. The reference voltage sub-parameter VREFDQ0 of the DQ0 line can represent such an offset. In other words, the DQ0 line can set the reference voltage VREF by applying (subtracting or adding) the reference voltage sub-parameter VREFDQ0 to the reference voltage VREF set by the reference voltage parameter VREFL of the low DQ byte DQ[7:0]. Thus, the DQ0 line can have a reference voltage VREF with optimal SI. The reference voltage sub-parameter VREFDQ0 with respect to the reference voltage VREF of the DQ0 line can be referred to as a per-pin reference voltage operation parameter.

[0074] The third mode register 630 has a parameter code for the reference voltage VREF of the DQ line stored in the OP[0] register. The OP[0] register can store a control parameter Per-pin VREFS that indicates whether the per-pin reference voltage parameter VREFDQ0 is supported for the reference voltage VREF of the DQ0 line. The control parameter Per-pin VREFS can be a 1-bit parameter code.

[0075] According to an example embodiment, a reference voltage sub-parameter VREFDQ0 of a reference voltage VREF with respect to a DQ0 line may be represented by less than 2 bits or more than 2 bits. A control parameter Per-pinVREFS indicating whether the reference voltage sub-parameter VREFDQ0 is supported may include more than 1 bit. Although Figure 6 it is described that the control parameter VREFS may be stored in the first mode register 610 together with global reference voltage operation parameters VREFL and VREFU of the reference voltage VREF with respect to the DQ lines, the example embodiment is not limited thereto. For example, the control parameter VREFS may be stored in a fourth mode register different from the first mode register 610, the second mode register 620, and the third mode register 610.

[0076] Figure 7 is a diagram showing a part of the MRS 210 according to an example embodiment. Figure 7 shows setting the Figure 6 example of the per-pin reference voltage parameter VREFDQ0 of the reference voltage VREF applied to the DQ0 line and other DQ lines.

[0077] Referring to Figure 6 and Figure 7 , a plurality of mode registers have parameter codes stored for the reference voltages of the DQ[15:0] lines and the lines of signals related to DQ[15:0] (e.g., data mask / invert signal DMI, data strobe signal DQS, etc.).

[0078] In the mode register identified by the MR_A21 mode register address, the OP[1:0] register may store the reference voltage sub-parameter VREFDQ0 applied to set the reference voltage VREF of the DQ0 line. The reference voltage sub-parameter VREFDQ1 applied to set the reference voltage VREF of the DQ1 line may be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ2 applied to set the reference voltage VREF of the DQ2 line may be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ3 applied to set the reference voltage VREF of the DQ3 line may be stored in the OP[7:6] register.

[0079] In the mode register identified by the MR_A22 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ4 of the reference voltage VREF that is applied to set the DQ4 line. The reference voltage sub-parameter VREFDQ5 of the reference voltage VREF that is applied to set the DQ5 line can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ6 of the reference voltage VREF that is applied to set the DQ6 line can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ7 of the reference voltage VREF that is applied to set the DQ7 line can be stored in the OP[7:6] register.

[0080] Based on the reference voltage parameter VREFL for the low DQ byte DQ[7:0] stored in the OP[2:0] register of the first mode register 610, the reference voltage sub-parameters VREFDQ[7:0] stored in the mode registers corresponding to the MR_A21 mode register address and the MR_A22 mode register address can be selectively used. When the control parameter Per-pinVREFS indicating whether the per-pin reference voltage operation parameter is supported in the OP[0] register of the third mode register 630 is enabled, the DQ[7:0] lines can each apply the reference voltage sub-parameters VREFDQ[7:0] to the reference voltage VREF set by the reference voltage parameter VREFL for the low DQ byte DQ[7:0], thereby setting the optimal reference voltage VREF. Figure 6

[0081] In the mode register identified by the MR_A23 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ8 of the reference voltage VREF that is applied to set the DQ8 line. The reference voltage sub-parameter VREFDQ9 of the reference voltage VREF that is applied to set the DQ9 line can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ10 of the reference voltage VREF that is applied to set the DQ10 line can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ11 of the reference voltage VREF that is applied to set the DQ11 line can be stored in the OP[7:6] register.

[0082] ​In the mode register identified by the MR_A24 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ12 of the reference voltage VREF that is applied to set the DQ12 line. The reference voltage sub-parameter VREFDQ13 of the reference voltage VREF that is applied to set the DQ13 line can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ14 of the reference voltage VREF that is applied to set the DQ14 line can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ15 of the reference voltage VREF that is applied to set the DQ15 line can be stored in the OP[7:6] register.

[0083] Based on the reference voltage parameter VREFU of the high DQ byte DQ[15:8] stored in the OP[6:4] register of the first mode register 610 Figure 6 the reference voltage sub-parameters VREFDQ[15:8] stored in the mode registers corresponding to the MR_A23 mode register address and the MR_A24 mode register address can be selectively used. When the control parameter Per-pinVREFS indicating whether the per-pin reference voltage operation parameter is supported by the OP[0] register of the third mode register 630 is enabled, the DQ[15:8] lines can each apply the reference voltage sub-parameter VREFDQ[15:8] to the reference voltage VREF set by the reference voltage parameter VREFU of the high DQ byte DQ[15:8], thereby setting the optimal reference voltage VREF.

[0084] In the mode register identified by the MR_A25 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDMI0 of the reference voltage VREF that is applied to set the first data mask / invert signal DMI0 line (the line for the first data mask / invert signal DMI0), and the OP[3:2] register can store the reference voltage sub-parameter VREFDMI1 of the reference voltage VREF that is applied to set the second data mask / invert signal DMI1 line. The OP[5:4] register can store the reference voltage sub-parameter VREFDQS0 of the reference voltage VREF that is applied to set the first data strobe signal DQS0 line, and the OP[7:6] register can store the reference voltage sub-parameter VREFDQS1 of the reference voltage VREF that is applied to set the second data strobe signal DQS1 line.

[0085] The first data mask / invert signal DMI0 and the first data strobe signal DQS0 can be used as the clock signal and the control signal for the low DQ byte DQ[7:0]. When the low DQ byte DQ[7:0] passes through the memory bus 110 ( Figure 1When the DQ bus of ( ) is transmitted / received, the first data mask / inversion signal DMI0 line and the first data strobe signal DQS0 line can apply reference voltage sub-parameters VREFDMI0 and VREFDQS0 to the reference voltage VREF set by the reference voltage parameter VREFL for the low DQ byte DQ[7:0], so as to set the optimal reference voltage VREF of the first data mask / inversion signal DMI0 line and the first data strobe signal DQS0 line respectively.

[0086] The second data mask / inversion signal DMI1 and the second data strobe signal DQS1 can be used as the clock signal and control signal for the high DQ byte DQ[15:8]. When the high DQ byte DQ[15:8] is transmitted / received through the DQ bus of the memory bus 110, the second data mask / inversion signal DMI1 line and the second data strobe signal DQS1 line can apply reference voltage sub-parameters VREFDMI1 and VREFDQS1 to the reference voltage VREF set by the reference voltage parameter VREFU for the high DQ byte DQ[15:8], so as to set the optimal reference voltage VREF of the second data mask / inversion signal DMI1 line and the second data strobe signal DQS1 line respectively.

[0087] Figure 8 is a diagram showing the effect of the DFE of the DQ line according to an exemplary embodiment.

[0088] Referring to Figure 8 , the DQ line 804 can experience loss and signal reflection. In the DQ line 804, inter-symbol interference (ISI) can cause one bit of data to interfere with subsequent bits and become distorted (i.e., smear out and spill over). One bit of the data signal 802 transmitted through the DQ line 804 can be received as a distorted signal 806 with the residue of the previous bit. ISI can become more significant as the data rate increases, and the pulse width representing the data bit becomes correspondingly narrower. The value of the distorted signal 806 received at the corresponding sampling point can be referred to as the tap value (e.g., the main tap value C0, the first tap value C1, the second tap value C2, etc.) corresponding to the data signal 802 transmitted through the DQ line 804.

[0089] The DFE 808 can calibrate the distorted signal 806 received at the corresponding sampling point by subtracting the residue of the previous bit to determine the current bit and generate a calibrated signal 810. Although Figure 8 shows an example where only the first tap value C1 is calibrated by the DFE 808, this is only for ease of explanation, and the embodiments are not limited thereto.

[0090] Figure 9 is for describing Figure 8Diagram of DFE 808.

[0091] Referring to Figure 9 , DFE 808 may include a filtering unit 910 for calibrating received DQ0 data and a sampler 920 for sampling the filtered data. The filtering unit 910 may include a plurality of coefficient multipliers (also referred to as DFE taps) 911_1 to 911_n that respectively generate tap values C1 to Cn based on time-delayed samples. The time-delayed samples may be provided by a plurality of time-delay units 912_1, 912_2, 912_3 to 912_(n - 1), which delay the sampled signal SDQ0 received from the sampler 920. For example, the amount of time delay may be τ. The adder 913 may add the tap values C1 to Cn to the DQ0 data or subtract the tap values C1 to Cn from the DQ0 data before forwarding the signal calibrated by the filtering unit 910 to the sampler 920. The sampler 920 may sample the calibrated signal in a specific sampling period set by the write clock signal WCK. The DFE taps 911_1 to 911_n may each receive a DFE amount DFEQ optimized for the DQ0 data and multiply the time-delayed samples by DFEQ to determine the tap values C1 to Cn. The DFE amount DFEQ may be provided from the MRS 210 ( Figure 2 ). According to an example embodiment, DFE 808 may be included in Figure 2 the data input buffer 260.

[0092] It can be determined through Figure 3 the read training operation in operation S330 or the write training operation in operation S340 the optimal DFE amount for each DQ[15:0] line including the DQ0 line, and the information about the optimal DFE amount may be stored as a parameter code in the MRS 210.

[0093] Figure 10 is a diagram showing a part of the MRS 210 according to an example embodiment.

[0094] Referring to Figure 2 , Figure 9 and Figure 10 , the MRS 210 may include a first mode register 1010, a second mode register 1020, and a third mode register 1030. The first mode register 1010, the second mode register 1020, and the third mode register 1030 represent a register group associated with the DFE amount DFEQ and may store the operation parameter codes for the DFE amount DFEQ of the DQ[15:0] lines. In this example embodiment, the DFE amount DFEQ corresponding to the first tap value C1 is shown.

[0095] In a first mode register 1010 identified by an MR_B1 mode register address, the OP[2:0] register may store a parameter DFEQL of a DFE amount DFEQ for setting DQ lines of a low DQ byte DQ[7:0]. The DFE amount parameter DFEQL of the low DQ byte DQ[7:0] stored in the OP[2:0] register may be represented by a 3-bit parameter code and may have, for example, 8 setting points or step coefficients. The OP[3] register may be reserved for future use (RFU), and the OP[6:4] register may store a parameter DFEQU of a DFE amount DFEQ for setting DQ lines of a high DQ byte DQ[15:8]. The DFE amount parameter DFEQU of the high DQ byte DQ[15:8] stored in the OP[6:4] register may be represented by a 3-bit parameter code and may have, for example, 8 setting points or step coefficients. The parameter DFEQL of the DFE amount for setting DQ lines of the low DQ byte DQ[7:0] and the parameter DFEQU of the DFE amount for setting DQ lines of the high DQ byte DQ[15:8] may be referred to as global DFE amount parameters. The OP[7] register may store a one-bit control parameter DFES, and the control parameter DFES indicates whether the parameters DFEQL and DFEQU regarding the DFE amount are supported for the DQ lines of the low DQ byte DQ[7:0] and the high DQ byte DQ[15:8].

[0096] According to an exemplary embodiment, the global DFE amount parameters DFEQL and DFEQU of the low DQ byte DQ[7:0] and the high DQ byte DQ[15:8] may be represented by less than 3 bits or more than 3 bits. The control parameter DFES indicating whether the global DFE amount parameters DFEQL and DFEQU of the DQ lines are supported may include more than 1 bit.

[0097] The second mode register 1020 has a parameter code of the DFE amount DFEQ for setting the DQ[15:0] lines and the lines of signals related to DQ[15:0] (e.g., data mask / inversion signal DMI, data strobe signal DQS, etc.). In the mode register identified by the MR_B21 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDQ0 of the DFE amount DFEQ applied to set the DQ0 line. The DFE quantum parameter DFEDQ1 of the DFE amount DFEQ applied to set the DQ1 line can be stored in the OP[3:2] register, the DFE quantum parameter DFEDQ2 of the DFE amount DFEQ applied to set the DQ2 line can be stored in the OP[5:4] register, and the DFE quantum parameter DFEDQ3 of the DFE amount DFEQ applied to set the DQ3 line can be stored in the OP[7:6] register. In the mode register identified by the MR_B22 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDQ4 of the DFE amount DFEQ applied to set the DQ4 line. The DFE quantum parameter DFEDQ5 of the DFE amount DFEQ applied to set the DQ5 line can be stored in the OP[3:2] register, the DFE quantum parameter DFEDQ6 of the DFE amount DFEQ applied to set the DQ6 line can be stored in the OP[5:4] register, and the DFE quantum parameter DFEDQ7 of the DFE amount DFEQ applied to set the DQ7 line can be stored in the OP[7:6] register.

[0098] In the mode register identified by the MR_B23 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDQ8 of the DFE amount DFEQ applied to set the DQ8 line. The DFE quantum parameter DFEDQ9 of the DFE amount DFEQ applied to set the DQ9 line can be stored in the OP[3:2] register, the DFE quantum parameter DFEDQ10 of the DFE amount DFEQ applied to set the DQ10 line can be stored in the OP[5:4] register, and the DFE quantum parameter DFEDQ11 of the DFE amount DFEQ applied to set the DQ11 line can be stored in the OP[7:6] register. In the mode register identified by the MR_B24 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDQ12 of the DFE amount DFEQ applied to set the DQ12 line. The DFE quantum parameter DFEDQ13 of the DFE amount DFEQ applied to set the DQ13 line can be stored in the OP[3:2] register, the DFE quantum parameter DFEDQ14 of the DFE amount DFEQ applied to set the DQ14 line can be stored in the OP[5:4] register, and the DFE quantum parameter DFEDQ15 of the DFE amount DFEQ applied to set the DQ15 line can be stored in the OP[7:6] register.

[0099] In the mode register identified by the MR_B25 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDMI0 of the DFE amount DFEQ applied to set the first data mask / inversion signal DMI0 line, and the OP[3:2] register can store the DFE quantum parameter DFEDMI1 of the DFE amount DFEQ applied to set the second data mask / inversion signal DMI1 line. The OP[5:4] register can store the DFE quantum parameter DFEDQS0 of the DFE amount DFEQ applied to set the first data strobe signal DQS0 line, and the OP[7:6] register can store the DFE quantum parameter DFEDQS1 of the DFE amount DFEQ applied to set the second data strobe signal DQS1 line.

[0100] The third mode register 1030 can store a 1-bit control parameter Per-pin DFES in the OP[0] register. The control parameter Per-pin DFES indicates whether the DFE amount DFEQ of the DFE quantum parameter DFEDQ[15:0] for the DQ[15:0] line is supported. The DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] for the DQ[15:0] line, the data mask / inversion signal DMI0 line and the data mask / inversion signal DMI1 line, and the data strobe signal DQS0 line and the data strobe signal DQS1 line can be referred to as per-pin DFE amount parameters.

[0101] According to an exemplary embodiment, the DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] for the DQ[15:0] line, the data mask / inversion signal DMI0 line and the data mask / inversion signal DMI1 line, and the data strobe signal DQS0 line and the data strobe signal DQS1 line can each be represented by bits less than 2 bits or greater than 2 bits. The control parameter Per-pin DFES indicating whether the DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] are supported can include more than 1 bit. Although Figure 10 it is described that the control parameter DFES can be stored in the first mode register 1010 together with the global DFE amount parameters DFEQL and DFEQU of the DQ line, the exemplary embodiment is not limited thereto. For example, the control parameter DFES can be stored in a fourth mode register different from the first mode register 1010, the second mode register 1020, and the third mode register 1010.

[0102] When the per-pin DFES control parameter indicating whether the per-pin DFE amount operation parameter is supported through the OP[0] register of the third mode register 1030 is enabled, the DQ[7:0] lines, the first data mask / inversion signal DMI0 line, and the first data strobe signal DQS0 line can apply the DFE quantum parameters DFEDQ[7:0], DFEDMI0, and DFEDQS0 to the DFE amount DFEQ set by the DFE amount parameter DFEQL for the low DQ byte DQ[7:0], the DFE amount DFEQ of the first data mask / inversion signal DMI0 line, and the DFE amount DFEQ of the first data strobe signal DQS0 line, respectively, so as to set the optimal DFE amount DFEQ of the corresponding data lines. In addition, the DQ[15:8] lines, the second data mask / inversion signal DMI1 line, and the second data strobe signal DQS1 line can apply the DFE quantum parameters DFEDQ[15:8], DFEDMI1, and DFEDQS1 to the DFE amount DFEQ set by the DFE amount parameter DFEQU for the high DQ byte DQ[15:8], the DFE amount DFEQ of the second data mask / inversion signal DMI1 line, and the DFE amount DFEQ of the second data strobe signal DQS1 line, respectively, so as to set the optimal DFE amount DFEQ of the corresponding data lines.

[0103] Figures 11 to 13 is a diagram for describing an example of the operation of the memory device 120 according to an exemplary embodiment. Figure 11 is for describing the write training operation (operation S340, Figure 3 ) of the memory device 120. Figure 12 is a diagram for describing the operation of storing the operation parameter code in the MRS 210. In the Figure 11 and Figure 12 timing diagrams shown, the horizontal axis and the vertical axis represent time and voltage level, respectively, and are not necessarily drawn to scale.

[0104] Refer to Figure 2 、 Figure 10 and Figure 11, for the write training operation (operation S340) of the memory device 120, a CAS command CAS (WS_WR = 1) can be received synchronously with the clock signal CLK at time T0. After a predetermined time tWCKENL_WR has elapsed from the CAS command CAS (WS_WR = 1), the write clock signal WCK can be synchronized with the clock signal CLK. In one embodiment, the clock signals CLK_t and CLK_c, and the write clock signals WCK_t and WCK_c are differential clock inputs respectively. At time point T1, a write command WRITE can be received after the CAS command CAS (WS_WR = 1). A deselect (DESELECT) command DES can be received after the write command WRITE. At time point T2, write data DQ corresponding to the burst length (e.g., BL16) can be received from the write command WRITE. At this time, a data mask / invert signal DMI can be received together with the write data DQ.

[0105] When a control parameter DFES indicating whether the DQ[15:0] lines support the global DFE amount parameters DFEQL and DFEQU is disabled, time point T2 can be set to a predetermined time TWCK2DQI after the write latency WL of the write command WRITE. In this case, the global DFE amount parameters DFEQL and DFEQU can be set to default operation parameters during the operation S310 ( Figure 3 ) for initializing the memory device 120.

[0106] When the control parameter DFES is enabled, it can be required that the write data DQ lines and the data mask / invert signal DMI lines be pre-driven to logic low for a predetermined pre-drive time tDPRE before time point T2. For example, the pre-drive time tDPRE can be set to about 2 unit intervals (UI). UI represents the unit time period during which 1-bit data is held. In other words, since the DFE needs to process the previous data and feed back the previous data to the current data, the pre-drive time tDPRE will be required considering the time for feeding back the previous data.

[0107] Referring to Figure 12 , the write training operation (operation S340) of the memory device 120 can be performed in parallel for the DQ[15:0] lines, the data mask / invert signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines. The optimal DFE amount DFEQ for each of the DQ[15:0] lines, the data mask / invert signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines can be determined through the write training operation (operation S340).

[0108] The optimal DFE amount DFEQ for the DQ[15:0] lines, the data mask / inversion signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines can be stored in the mode register of the MRS 210 respectively (operation TS1). In this case, the elapsed time tTS1 can pass. Since the mode register write time tM passes for each of the 20 signals DQ[15:0], DMI1[1:0], and DQS[1:0], the time tTS1 is approximately 20 × tM. In addition, the DFE amount DFEQ for each of the data mask / inversion signal DMI1[1:0] lines and the data strobe signal DQS[1:0] lines can represent 8 step coefficients by using a 4-bit parameter code. In this case, when 4 bits are allocated to the parameter for the DFE amount DFEQ for each of the 20 signals DQ[15:0], DMI1[1:0], and DQS[1:0], an 80-bit mode register is required.

[0109] In contrast, the per-pin DFE amount parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] representing the offset values of the global DFE amount parameters DFEQL and DFEQU described in Figure 10 can be stored in the mode register of the MRS 210 respectively (operation TS2). In this case, the elapsed time tTS2 can pass, where the time tTS2 is approximately equal to the write times of five mode registers MR_B21, MR_B22, MR_B23, MR_B24, and MR_B25 (i.e., approximately 5 × tM). It can be seen that the time tTS2 is significantly shorter than the time tTS1. In addition, when the per-pin DFE amount parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] are stored in the five mode registers MR_B21, MR_B22, MR_B23, MR_B24, and MR_B25, as shown in Figure 10 a 40-bit mode register is required, so the mode register resources can be saved.

[0110] Refer to Figure 13, assume that through the write training operation (operation S340) of the memory device 120, the optimal DFE amount DFEQ of the DQ0 line has DFE

[001] among the 8 step coefficients of the DFE, and the optimal DFE amount DFEQ of the DQ7 line has DFE

[111] . When the DFE amount parameter DFEQL of the low DQ byte DQ[7:0] is determined to be DFEQL

[100] among the 8 step coefficients of the DFE, the OP[1:0] register of the MR_B21 mode register corresponding to the DFE quantum parameter of the DQ0 line can be set to DFEDQ0

[11] , and the OP[7:6] register of the MR_B22 mode register corresponding to the DFE quantum parameter of the DQ7 line can be set to DFEDQ7

[11] . When the per-pin DFE operation is enabled, the DQ0 line obtains the optimal DFE amount DFE

[001] by subtracting DFEDQ0

[11] from DFEQL

[100] , and the DQ7 line obtains the optimal DFE amount DFE

[111] by adding DFEDQ7

[11] to DFEQL

[100] .

[0111] Figure 14 is a diagram for describing the swing width calibration of the DQ line according to the exemplary embodiment.

[0112] Refer to Figure 2 and Figure 14 , the VOH specification SPEC of the data DQ output from the data output buffer 270 of the memory device 120 defines that the swing width of the data DQ has a constant value. The memory device 120 can calibrate the swing width of the data DQ through the read training operation (operation S330, Figure 3 ). The memory device 120 can compare the voltage level of the data DQ output from the data output buffer 270 with the voltage level of the reference voltage VREF, and calibrate the magnitudes of the swing widths A_SWING, B_SWING, and C_SWING of the data DQ according to the comparison result. The reference voltage VREF has a voltage value that determines the magnitude of the DQ swing width, and is set to the average value of the maximum voltage and the minimum voltage of the DQ swing width.

[0113] When the level of the reference voltage VREF changes, DQ swing width parameters for determining appropriate DQ swing widths A_SWING, B_SWING, and C_SWING through the read training operation (operation S330) are required. Similar to Figure 10 , the DQ swing width parameters can include a global DQ swing width parameter and a per-pin DQ swing width parameter represented as an offset value of the global DQ swing width parameter, and can be stored in the MRS 210. According to the exemplary embodiment, the DQ swing width parameters can be related to Figure 6 and Figure 7The parameter code combinations of the reference voltage VREF described in

[0114] Figure 15 is a diagram for describing the pre - emphasis operation of the DQ line according to an exemplary embodiment.

[0115] Referring to Figure 2 and Figure 15 , a pre - emphasis operation can be provided to improve the SI of the DQ line and the data mask / inversion signal DMI line. After the signal transmitted through the data bus is attenuated by a transmission line (such as a wire or a cable) on a printed circuit board (PCB), fluctuations in the received signal voltage amplitude and the received signal timing at the receiving end of the transmission line are expected. It is necessary to expand the so - called data eye opening area indicating the normal reception area at the receiving end.

[0116] The memory device 120 may include a data output buffer 270 that performs a pre - emphasis operation on the DQ line through a read training operation (operation S330, Figure 3 ). For example, when the current bit signal of the DQ line and the data mask / inversion signal DMI line changes from logic low to logic high, a first high output voltage Voh1 can be output, so that the logic high waveform can be emphasized (emphasis operation). When the current bit signal remains logic high, a second high output voltage Voh2 lower than the first high output voltage Voh1 can be output to prepare for the next signal change (de - emphasis operation). In addition, when the current bit signal changes from logic high to logic low, a first low output voltage Vol1 can be output, so that the logic low waveform can be emphasized (emphasis operation). When the current bit signal remains logic low, a second low output voltage Vol2 higher than the first low output voltage Vol1 can be output to prepare for the next signal change (de - emphasis operation). For example, the first high output voltage Voh1, the second high output voltage Voh2, the first low output voltage Vol1, and the second low output voltage Vol2 can be respectively between the power supply voltage VDD and the ground voltage VSS.

[0117] The pre - emphasis operation can enable signals to be transmitted at a higher data rate over a longer distance and suppress signal reflection at the transmitting end. Therefore, DQ pre - emphasis parameters for determining appropriate DQ pre - emphasis through a read training operation (operation S330) are required. Similar to Figure 10 , the DQ pre - emphasis parameters can include global DQ pre - emphasis parameters and per - pin DQ pre - emphasis parameters represented as offset values of the global DQ pre - emphasis parameters, and can be stored in the MRS 210.

[0118] As described above, the MRS 210 can set the operation parameters regarding the reference voltage VREF, DFE amount, swing width calibration, and / or pre-emphasis operation to global operation parameters and per-pin operation parameters represented as offset values relative to the global operation parameters by using a set of registers associated with the corresponding operation parameters (i.e., the first mode register, the second mode register, and the third mode register).

[0119] For example, in some embodiments, the combination of the global operation parameter code and the first offset value of the first pin (e.g., any one of the pins associated with Figure 1 DQ in Figure 6 , Figure 7 and Figure 10 ) is configured to determine the first decision level of the first sampler (e.g., sampler 920) by adjusting the VREF value, where the first sampler is configured to operate on the first signal line (e.g., Figure 9 808 of Figure 8 ) connected to the first pin. After the operation of the DFE 808 or DFE taps 911_1,..., 911_n in Figure 8 , the signal considered as a single pulse on the first signal line may have a valid representation as shown by item 810 in Figure 8 .

[0120] In another example, in some embodiments, the combination of the global operation parameter code and the first offset value of the first pin is configured to determine the first DFE tap value (e.g., Figure 9 tap 911_1 of

[0121] ) of the first decision feedback equalizer (DFE) (e.g., DFE 808) used with the first sampler (e.g., sampler 920), where the first DFE and the first sampler are configured to operate on the first signal line connected to the first pin. Except for the description of the DFE tap value, the global operation parameter code, the first offset value, the first pin, and the first sampler may be as described in the description of the decision level immediately above.

[0122] Various operation parameters associated with the MRS 210 may include DQ-ODT values, CA-ODT values, VREF-CA values, VREF-CA ranges, and VREF-DQ ranges. These operation parameters may also be set as global operation parameters and per-pin operation parameters represented as offset values relative to the global operation parameters by using a set of registers associated with the corresponding operation parameters (i.e., a first mode register, a second mode register, and a third mode register). Global operation parameters associated with the CA-ODT value, VREF-CA value, and VREF-CA range may be provided as operation parameter codes for the entire CA signal.

[0123] The memory device may apply common operation conditions to signal pins associated with the operation parameters by using the global operation parameter code, and additionally apply specific offset operation conditions to the corresponding signal pins associated with the operation parameters by using the per-pin operation parameter code, thereby controlling the signal pins with operation conditions optimized for the characteristics of the corresponding signal pins. Further, by setting the offset represented as the difference from the global operation parameter as the per-pin operation parameter code, the number of registers of the mode register required to store the operation parameter code and the update time of the mode register may be reduced.

[0124] Although example embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a memory controller, the method comprises: receiving first information of a mode register configuration (MRS) of a memory device, the first information of the MRS including control parameters, the control parameters indicating that the memory device supports decision feedback equalizer (DFE) amount operations on data (DQ) pins of the memory device; sending a CAS command synchronized with a clock signal to the memory device; sending a write command to the memory device; sending a write clock signal synchronized with the clock signal to the memory device after a predetermined time has elapsed since the CAS command; sending write data to the memory device via a data line; and sending second information to the MRS of the memory device, wherein the data line is pre-driven to a logic low for a predetermined pre-drive time based on the control parameters, and wherein the second information of the MRS includes global operation parameters and per-pin operation parameters of the DFE amount operation, the global operation parameters are associated with the DQ pins, and the per-pin operation parameters are associated with corresponding DQ pins.

2. The method according to claim 1, wherein, the per-pin operation parameters are represented as offset values from the global operation parameters.

3. The method according to claim 1, wherein, the global operation parameters include low-byte DFE amount parameters for low DQ byte pins among the DQ pins and high-byte DFE amount parameters for high DQ byte pins among the DQ pins.

4. The method according to claim 1, wherein, the second information of the MRS includes at least one parameter among the operation parameters of the memory device, and the operation parameters include drive strength parameters, pre-emphasis parameters, on-die termination (ODT) parameters, and reference voltage parameters associated with the DQ pins.

5. The method according to claim 4, wherein, the at least one parameter includes global parameters associated with the DQ pins and second per-pin operation parameters associated with corresponding data DQ pins.

6. The method according to claim 1, further comprises: not sending a command between the CAS command and the write command.

7. The method according to claim 1, further comprises: sending a data mask / inversion signal associated with the write data to the memory device via a signal line, wherein the signal line is pre-driven to a logic low for a predetermined pre-drive time.

8. The method according to claim 1, wherein, the predetermined pre-drive time is set before the time point when the write data is sent.

9. The method according to claim 8, wherein, the predetermined pre-drive time is set to be about two unit intervals (UI).

10. The method according to claim 9, wherein, UI represents the unit time period during which 1-bit data is held.

11. The method according to claim 1, wherein, during the predetermined pre-drive time, the memory device processes previous data and feeds back the previous data to the current data (DQ).

12. The method according to claim 1, wherein, a first number of bits in the per-pin operation parameters associated with one of the corresponding DQ pins is less than a second number of bits in the global operation parameters associated with the DQ pins.

13. A method of controlling a memory device, the method Comprising: Storing a first parameter code of a first operating condition for setting an operating parameter in a first register of a mode register of a memory device; Storing a second parameter code of a second operating condition for setting the operating parameter in a second register of the mode register, wherein the second parameter code is represented as an offset value from the first parameter code; Storing a first control code for selecting the first parameter code in a third register of the mode register; Storing a second control code for selecting the second parameter code in a fourth register of the mode register; Setting the first operating condition as the current operating condition of the memory device by using the first parameter code of the operating parameter; and Setting the second operating condition as the current operating condition by using the first parameter code and the second parameter code of the operating parameter.

14. The method according to claim 13, wherein, the first parameter code includes a global operating parameter code associated with the first operating condition, and the second parameter code includes a per-pin operating parameter code associated with the second operating condition.

15. The method according to claim 14, wherein, the first parameter code includes a first global operating parameter code and a second global operating parameter code, the first global operating parameter code is a low-byte operating parameter code of a low data (DQ) byte pin among the data (DQ) pins of the memory device, and the second global operating parameter code is a high-byte operating parameter code of a high DQ byte pin among the DQ pins of the memory device.

16. The method according to claim 13, further comprising: Performing a training operation to determine the first parameter code and the second parameter code of the operating parameter.

17. The method according to claim 16, wherein, the step of performing the training operation includes: when training the decision feedback equalizer (DFE) amount for setting the first operating condition and the second operating condition, pre-driving the DQ pins of the memory device to logic low before performing the training.

18. The method according to claim 17, further comprising: Pre-driving a data mask / invert signal pin associated with the DQ pins to logic low before performing the training.

19. The method according to claim 13, further comprising: Setting the current operating condition as a default operating parameter.

20. A memory controller, comprising: A register control word (RCW) configured to include information of a mode register configuration (MRS) of a memory device, the information of the MRS including control parameters, the control parameters indicating that the memory device supports a decision feedback equalizer (DFE) amount operation of data (DQ) pins of the memory device; and A training circuit configured to perform training of the DFE amount operation and determine a global operating parameter and a per-pin operating parameter of the DFE amount operation, the global operating parameter being associated with the DQ pins, and the per-pin operating parameter being associated with corresponding DQ pins, wherein the memory controller pre-drives the DQ pins to logic low before performing the training.

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