NOR memory and programming and erasing method thereof

Abstract

The invention provides an NOR memory and a programming and erasing method thereof. The NOR memory comprises N minimum data storage modules which are sequentially arranged along the row direction of a memory unit and share a word line row driving circuit; each data storage module comprises an independent storage unit array, a switch selection unit, a common source electrode, a well and a corresponding switching unit, and the switch selection unit and the switching unit are arranged on the periphery of the storage unit array; grids of storage units in the same row in the storage unit array are connected with the same word line, and drains of storage units in the same column are connected with the same bit line; the switch selection unit is used for connecting every M bit lines in the storage unit array to a corresponding main bit line; the switching unit is connected with the common source electrode and the well of the storage unit array and provides required driving voltage for the common source electrode and the well. When a certain selected sector or block of the NOR memory is programmed and erased, electrical crosstalk to other non-selected sectors or blocks is avoided, and area increase can be well controlled.

Description

Technical Field

[0001] The present invention relates to the field of memory array layout design, and particularly to a NOR memory and its programming and erasing methods. Background Art

[0002] A memory, also known as a memory unit or internal memory, is a hardware component in a computer system used to store data and programs. The function of the memory is to temporarily or permanently store data and instructions so that a processor (CPU) or other hardware components can access and execute them.

[0003] Memories can be divided into two main categories: volatile memories and non-volatile memories. Among them, volatile memories such as random access memories (RAMs) lose data when power is cut off, including dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memories such as hard disk drives (HDDs), solid state drives (SSDs), flash memories, etc. retain data when power is cut off. NOR Flash is a non-volatile memory composed of a series of orderly arranged memory cells, each memory cell having a unique address, and data can be read or written by directly accessing the address; NOR Flash is widely used in multiple fields due to its fast random access capability.

[0004] A general NOR-type memory (NOR Flash) array is generally divided into the following parts: The memory array is the most core part of the NOR-type memory and is used to store data "0" or "1". The memory array is composed of a large number of memory cells connected in parallel in a horizontal and vertical cross manner of word line rows (WL: Wordline) and bit line columns (BL: Bitline) according to the NOR-type layout method. It is the main part of the entire memory array. Its area, cost, performance, and reliability are not only closely related to the manufacturing process but also inseparable from the layout design of the entire array. The word line row driver (WL DRV) is located on the left or right side of the memory array. When performing read, write, erase, etc. operations on the memory cells inside the memory array, it is used to accurately address the gates of the memory cells to be operated and provide the required correct voltage. Since the above operations all involve relatively high voltages, such as -10V to +10V, the devices required for these drive circuits are often high-voltage-resistant devices, and different word lines need to output different voltages according to different operating states, and the situation is complex. Therefore, the area occupied by this part of the circuit in the entire NOR-type memory array is not small. The word line row is located inside the memory array. The two ends of each row are respectively connected to the corresponding word line driver and the gates of the memory cells. When performing read, write, erase, etc. operations on the memory cells inside the memory array, the word line driver accurately addresses the gates of the memory cells to be operated through the word line and provides the required correct voltage. The same word line continuously connects the gates of multiple memory cells on the same row, and the number of its multiple memory cells is equal to the number of bit lines. The bit line column is located inside the memory array. When performing read, write, erase, etc. operations on the memory cells inside the memory array, it accurately addresses the drains of the memory cells to be operated through the bit line and provides the required correct voltage or outputs the current of the memory cells. The same bit line continuously connects the drains of multiple memory cells on the same column, and the number of its multiple memory cells is equal to the number of word lines. The main bit line (MBL: MainBitline): The main bit line is the upper-level bit line of the bit line. Generally, one main bit line is connected to multiple bit lines through multiple switch selection tubes, and usually the main bit line is longer than the bit line and spans a larger area. The switch selection tube module (SG: Select Gate) is located on the upper and lower sides of the memory array and is used to connect the main bit line and the corresponding multiple bit lines. Its number is the same as the number of bit lines. When performing read, write, erase, etc. operations on the memory cells inside the memory array, the chip controls the on and off of the switch selection tubes through the decoding circuit of the operation address, and then determines whether to transmit the operation voltage into the bit line (write operation) or output the current of the memory cells through the bit line to the sense amplifier connected to the main bit line (read operation).The Block Switch, located around the memory matrix, is used to address the source line (SL) and memory well (Mwell) of the sector memory matrix and provide the required voltage drive when performing read, write, erase, etc. operations on the memory cells inside the memory matrix.

[0005] As Figure 1 and Figure 2 shown, taking Block 1 of a 4Mb = 4096Kb capacity NOR-type memory array as an example, this 4Mb Block includes 8 memory sub-matrices 110 - 117 from bottom to top (constituting memory matrix 11), and the capacity of each memory sub-matrix is 512Kb. On the left side of memory matrix 11 are 8 word line row driver units 120 - 127 corresponding to each memory sub-matrix (SEC<0> - SEC<7> constitute word line row drive 12), with a total of 256 word line drive circuits; on the right side is the shared Block Switch 14 (including source line and memory well drive circuits). On both the upper and lower sides of memory matrix 11 are bit line switch selection tube modules 131 and 132 (in this example, four switch control signals SG_0 - SG_3 are set, and each switch control signal controls the gating of 4096 bit lines), and each main bit line MBL is correspondingly connected to 4 lower-level bit lines BL (it can also be 8, 16, 32, etc.), there are 4096 main bit lines MBL, and 16384 bit lines BL. It should be noted that here the entire Block shares a set of switch selection tube modules 13 on both the upper and lower sides, and the sources and memory wells of all 8 sectors are connected together. Each 512Kb sector contains 32 word lines and 16K (= 16 × 1024 = 16384) bit lines, satisfying the sector capacity = the number of word lines per sector × the number of bit lines; on the left side are 32 word line row driver units for each sector, and on the right side is the shared Block Switch 14; there are no independent switch selection tubes on both the upper and lower sides; as Figure 3 and Figure 4 shown, it is one of the sectors with the lowest bit.

[0006] As can be seen from the above, such a 4Mb memory array (Block) can save the area of the memory array to the greatest extent because the switching selection transistor modules, common sources, and wells of each memory sub-matrix are all shared as a group, which is the most compact array layout method. However, according to the erase and write operation conditions of this array, for any selected target memory cell A inside the Block (taking the cell corresponding to SEC<0> at WL<0> and BL<0> as an example) and the unselected memory cell B on the same bit line but belonging to different sectors (taking the cell corresponding to SEC<7> at WL<255> and BL<0> as an example), since they share the switching selection transistor SGa, when performing a write (programming) operation, the 4V programming voltage on the main bit line MBL<0> turns on the switching selection transistor SGa through the control of SG<0>, and then is transmitted to all 256 memory cells connected to the bit line BL<0>, which includes both the selected target cell A and all other unselected cells, such as cell B; similarly, since all sectors share the same well, when performing an erase operation, the well potentials of the selected target cell A and the unselected cell B are also the same. Refer to Figure 2 and Table 1 below.

[0007]

[0008] Table 1

[0009] This results in that for the target operating memory cell A selected and the non-selected memory cell B on the same bit line BL, whether it is erased or written, the only difference in the voltage conditions at each end is the difference between the word lines WL<0> and WL<255>. The other bit lines, source lines, and well potentials are the same. This is caused by the 4Mb memory array Block layout design method. The direct consequence is that during a write operation, the non-selected memory cell on the same bit line has to withstand a 4V bit line crosstalk. The longest total time of this crosstalk can be roughly estimated as: 10us (write time per row) × 32 (number of word lines per sector) × 100,000 (number of repeated erase and write times per sector) × 7 (number of sectors) = 224 seconds. If the non-selected memory cell B is exactly in the data "0" state, it means that there are a lot of negatively charged electrons stored in its floating gate. At this time, the bit line is at a positive 4V. In this way, a long-term forward electric field from the bit line to the floating gate is formed. For the negatively charged electrons in the floating gate, it is very easy to fall out of the floating gate due to the weak FN tunneling effect caused by this long-term forward electric field, thus forming so-called charge loss, which will greatly affect the stability of data "0", reduce the correct window of data "0", and even cause data errors; especially in the case of high temperature where the non-selected cell has also experienced repeated erase and write operations, the situation is even worse. Similarly, during an erase operation, the non-selected memory cell B in different sectors has to withstand a 9V well-to-word line crosstalk. The longest total time of this crosstalk can be roughly estimated as: 50ms (erase time per sector) × 100,000 (number of repeated erase and write times per sector) × 7 (number of sectors) = 35,000 seconds. Similarly, for the data "0" state, this well crosstalk will also form a super-long-term forward electric field weak FN tunneling effect from the well to the floating gate, causing the negatively charged electrons in the floating gate to fall out of the floating gate, forming charge loss, and finally data errors will also occur probabilistically. The above two types of data errors are unacceptable for NOR flash mainly used for storing code.

[0010] Currently, the common solutions to the above problems generally have the problem of large occupied area. Therefore, how to balance cost while improving the reliability of NOR memories has become one of the problems that need to be urgently solved by those skilled in the art.

[0011] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0012] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a NOR memory and its programming and erasing methods, which are used to solve the problem that the reliability and cost of the NOR memory in the prior art cannot be taken into account at the same time.

[0013] To achieve the above object and other related objects, the present invention provides a NOR memory, which at least includes:

[0014] A word line row driving circuit and N data storage modules; the N data storage modules are arranged in sequence along the row direction of the storage cells and share the word line row driving circuit, and the same row of the N data storage modules receives the same word line driving signal;

[0015] Each data storage module includes an independent storage cell array, a switch selection unit, a common source, a well and a switching unit, and the switch selection unit and the switching unit are arranged outside the storage cell array; the gates of the storage cells in the same row of the storage cell array are connected to the same word line, the drains of the storage cells in the same column are connected to the same bit line, each storage cell has a common source and the well potential is the same; the switch selection unit connects every M bit lines in the storage cell array to a corresponding main bit line; the switching unit is connected to the common source and the well of the storage cell array and provides the required driving voltage for the common source and the well of each storage cell in the storage cell array.

[0016] Wherein, the data storage module is the smallest erasable array unit, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2.

[0017] Optionally, the data storage module is a sector or a block.

[0018] Optionally, the word line row driving circuit is arranged outside the storage area formed by each data storage module and is arranged in sequence with each data storage module along the row direction of the storage cells.

[0019] Optionally, the switching unit is arranged at one end of the word line in the corresponding storage cell array.

[0020] More optionally, the structures of two adjacent data storage modules are mirror-distributed.

[0021] Optionally, the switch selection unit is arranged at at least one end of the bit line in the corresponding storage cell array.

[0022] Optionally, the storage cell is an N-type storage cell, a P-type storage cell, a floating gate type storage cell or a charge trap type storage cell.

[0023] To achieve the above and other related objectives, the present invention also provides a programming method for a NOR memory, implemented using the above NOR memory. The programming method of the NOR memory at least includes:

[0024] Configuring a common source voltage and a well voltage for corresponding data storage modules based on each switching unit;

[0025] Selecting the row where the memory cell to be programmed is located based on the word line row driving circuit;

[0026] Based on the switch selection unit in the data storage module where the memory cell to be programmed is located, selecting and enabling the bit line of the column where the memory cell to be programmed is located, and writing data.

[0027] Optionally, the common source voltages of each data storage module are equal, and the well voltages of each data storage module are equal.

[0028] More optionally, when the memory cells in the data storage module are N-type floating gate memory cells, the common source voltage and the well voltage of each data storage module are both configured to 0V.

[0029] To achieve the above and other related objectives, the present invention also provides an erasing method for a NOR memory, implemented using the above NOR memory. The erasing method of the NOR memory at least includes:

[0030] Configuring the same word line voltage and bit line voltage for each memory cell based on the word line row driving circuit and each switch selection unit;

[0031] Based on the corresponding switching unit in the data storage module that does not need to be erased, floating the common source of the data storage module that does not need to be erased, and configuring the well voltage to be equal to the word line voltage;

[0032] Based on the switching unit in the data storage module to be erased, setting the common source voltage and the well voltage of the data storage module to be erased to a set voltage to achieve data erasure.

[0033] Optionally, when the memory cells in the data storage module are N-type floating gate memory cells, the set voltage is 7V to 10V.

[0034] Optionally, when the memory cells in the data storage module are N-type floating gate memory cells, the word lines of each memory cell are configured with a negative high voltage, and the bit lines are floating.

[0035] More optionally, the negative high voltage is -8V to -10V.

[0036] As described above, the NOR memory and its programming and erasing methods of the present invention have the following beneficial effects:

[0037] The NOR memory of the present invention and its programming and erasing methods isolate the bit lines, sources, and wells of each sector or block. When programming and erasing a selected sector or block, electrical crosstalk to other non-selected sectors or blocks is avoided. At the same time, different sectors or blocks in the same row share the same set of word line row driving circuits, thus greatly reducing the occupied area of the NOR memory and taking both reliability and cost into account. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It shows a schematic structural diagram of a 4Mb Block array composed of 8 sectors stacked vertically.

[0039] Figure 2 It shows a schematic structural diagram of a 4Mb Block array composed of memory cells.

[0040] Figure 3 It shows Figure 1 a schematic diagram of a 512Kb sector array in

[0041] Figure 4 It shows Figure 1 a schematic diagram of a 512kb sector array composed of memory cells in

[0042] Figure 5 It shows a schematic structural diagram of a 4Mb Block array composed of 8 sectors arranged horizontally.

[0043] Figure 6 It shows Figure 5 a schematic structural diagram of adjacent two sectors with mirror distribution in

[0044] Figure 7 It shows Figure 5 a schematic diagram of a 512kb sector array composed of memory cells in

[0045] Figure 8 It shows a block diagram of the NOR memory of the present invention.

[0046] Figure 9 It shows a block diagram of a sector of the present invention.

[0047] Figure 10 It shows a schematic structural diagram of a 512kb sector array composed of memory cells of the present invention.

[0048] Figure 11 It shows a block diagram of a 4Mb Block array composed of 8 sectors arranged horizontally of the present invention.

[0049] Figure 12 It shows a schematic structural diagram of adjacent two sectors with mirror distribution of the present invention.

[0050] Description of Component Labels

[0051] 1 NOR-Type Memory Array

[0052] 110, 111, 116, 117 Storage Sub-Matrices

[0053] 11 Storage Matrix

[0054] 120, 121, 126, 127 Word Line Row Driver Units

[0055] 12 Word Line Row Drive

[0056] 131, 132 Switch Selection Transistor Modules

[0057] 14 Block Switching Circuit

[0058] 2 NOR-Type Memory Arrays

[0059] 20, 21, 26, 27 Sectors

[0060] 201, 211 Storage Sub-Matrices

[0061] 202, 212 Word Line Row Driver Units

[0062] 203a, 203b, 213a, 213b, Switch Selection Transistor Modules

[0063] 204, 214 Sector Switching Circuits

[0064] 3 NOR Memory

[0065] 31 Word Line Row Driver Circuit

[0066] 320, 321, 326, 327, 32(N - 2), 32(N - 1) Data Storage Modules

[0067] 32 Storage Area

[0068] 3a Storage Cell Array

[0069] 3b1, 3b2 Switch Selection Units

[0070] 3c Switching Unit Detailed Implementation Modes

[0071] The following describes the implementation modes of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] Please refer to Figures 5 to 12 . It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0073] As Figure 5 shown, a storage array layout is proposed in which each different sector has its own independent switch selection tube module and well. Taking a 4Mb = 4096Kb capacity NOR type memory array (Block) 2 as an example. This 4Mb Block is composed of 8 sectors 20 - 27 from left to right (SECTOR<0> - SECTOR<7> form a Block), and the capacity of each sector is 512Kb. Each sector inside the Block has its own independent 256 word line row driver units, as well as its own independent source and well drive circuits. As Figure 6 shown, sector 20 includes a storage sub-matrix 201, a word line row driver unit 202, switch selection tube modules 203a, 203b, and a sector switching circuit 204; sector 21 includes a storage sub-matrix 211, a word line row driver unit 212, switch selection tube modules 213a, 213b, and a sector switching circuit 214; the compositions of other sectors are the same and will not be elaborated here one by one. On the upper and lower sides of each sector are the switch selection tubes of the bit lines, and each main bit line MBL is correspondingly connected to 4 lower-level bit lines BL (it can also be 8, 16, 32, etc.). The total number of main bit lines MBL in the entire Block is still 4096, and the number of bit lines BL is 16384. For the convenience of layout and wiring, the Mth sector and the (M + 1)th sector (M = 1, 2, 3) inside the 4Mb Block array are in a mirror image relationship in terms of structural layout. As Figure 7 shown (taking the lowest-level sector as an example), each 512Kb sector contains 256 word lines and 2 × 1024 = 2048 = 2K bit lines, satisfying the sector capacity = the number of word lines in each sector × the number of bit lines; on the left side are the 256 word line row driver units of each sector, and on the right side is the independent sector switching circuit (common source and well drive) of each sector; on the upper and lower sides are the independent switch selection tubes of each sector.

[0074] As can be seen from the above, for this type of 4Mb storage array Block, since the sectors are arranged horizontally, and each sector contains its own independent switch selection tube module and well, and also has its own independent 256-word line row driver unit. In terms of the area of the storage array Block, it is the most wasteful, but this is the safest array layout method. According to the erase and write operation conditions of this array, for any selected target storage unit A (taking the unit at the position of WL<0> and BL<0> corresponding to Sec<0> as an example) and the unselected storage unit B (taking the unit at the position of WL<255> and BL<0> corresponding to Sec<0> as an example) on the same bit line in the same sector (since each sector has an independent switch selection tube module, the storage units on the same bit line can only be located inside the same sector) inside the Block, when writing, the 4V programming voltage on the main bit line MBL<0> turns on the switch SGa through SG<0> and is passed to all 256 storage units connected to the bit line BL<0>, which includes both the selected target unit A and all other unselected units, such as unit B; similarly, since all sectors have their own independent word line drivers and wells, when performing the erase operation, the word line and well potentials of the selected target unit A in Sec<0> and the unselected storage unit C (taking the unit at the position of WL<255> and BL<4095> corresponding to Sec<1> as an example) can be different, as Figure 6 and shown in Table II below.

[0075]

[0076]

[0077] Table II

[0078] During the write operation, since the target cell A and the non-selected cell B are in the same sector, there is no need to consider an additional 100,000 erase / write cycles. Only the worst-case scenario of writing the sector from word line WL<0> to word line WL<254> needs to be considered. During this process, although the non-selected memory cell B on the same bit line has to withstand a 4V bit line crosstalk, the total time of this crosstalk can be roughly estimated as: 10us (write time per row) × 255 (number of word lines in each sector - 1) = 2.55 milliseconds, which is significantly reduced compared to the previous 224 seconds, and the impact of its bit line crosstalk can be almost ignored. For the target cell A and the non-selected cell C in different sectors, as can be seen from the operating voltages in Table II, at this time, both BL<4095> and WL<255> of cell C are equal to 0V, without any voltage difference, so there is naturally no bit line crosstalk. During the erase operation, since the target cell A and cell B are in the same sector, and the minimum erase unit of NOR Flash is the sector, these two cells are definitely erased simultaneously, without the so-called well-to-word line crosstalk. For the target cell A and the non-selected cell C in different sectors, since each sector has its own independent well, common source, and word line drive, as can be seen from the operating voltages in Table II, at this time, both WL<255> and the well of cell C are equal to 0V, without any voltage difference, so there is naturally no well-to-word line crosstalk.

[0079] As can be seen from the above, using this storage array Block layout design scheme with completely independent word line drives, switch selection tube modules, wells, and common sources in each sector can solve and avoid the aforementioned bit line crosstalk and well crosstalk. The price is that the array area will become relatively large, and the difference can be more than 20% - 50% according to different array Block capacities.

[0080] To balance the reliability and occupied area of NOR memories, the present invention proposes a NOR memory 3, as Figure 8 shown, the NOR memory 3 includes:

[0081] A word line row drive circuit 31 and N data storage modules (320, 321,..., 32(N - 2), 32(N - 1)), the N data storage modules are arranged in sequence along the row direction of the memory cells, and share the word line row drive circuit 31. The same row of the N data storage modules receives the same word line drive signal.

[0082] As Figure 9 and Figure 10As shown, each data storage module (320, 321, ……, 32(N - 2), 32(N - 1)) includes an independent memory cell array 3a, a switch selection unit (3b1 and 3b2), a common source, well, and switching unit 3c. The switch selection unit (3b1 and 3b2) and the switching unit 3c are arranged outside the memory cell array 3a. Among them, the memory cell array 3a (as an example, is set to an array structure of 256 rows and 2048 columns, Figure 9 and Figure 10 in which i is an integer, satisfying: i = 0, 1, …… N - 1), the gates of the memory cells in the same row are connected to the same word line WL, the drains of the memory cells in the same column are connected to the same bit line BL, and each memory cell has a common source and the same well potential. The switch selection unit (3b1 and 3b2) connects every M bit lines BL in the memory cell array 3a to a corresponding main bit line MBL (as an example, M is set to 4); the lower-level bit lines BL corresponding to the same main bit line MLB are isolated by corresponding switch selection transistors. The switching unit 3c is connected to the common source and well of the memory cell array 3a, and provides the required driving voltage for the common source and well of each memory cell in the memory cell array 3a; the wells of different memory cell arrays 3a are isolated by wells of opposite types. Among them, the data storage module 3a is the smallest erasable array unit, including but not limited to a sector or a block, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2.

[0083] Specifically, as Figure 8 shown, the word line row driving circuit 31 is arranged outside the storage area 32 formed by each data storage module (320, 321, ……, 32(N - 2), 32(N - 1)), and is arranged in sequence with each data storage module (320, 321, ……, 32(N - 2), 32(N - 1)) along the row direction of the memory cells. That is, the word line row driving circuit 31 is arranged at one end of the storage area 32, provides word line driving signals corresponding to the number of rows of memory cells in the data storage module (320, 321, ……, 32(N - 2), 32(N - 1)), and each word line driving signal can simultaneously control one row in N data storage modules (320, 321, ……, 32(N - 2), 32(N - 1)) (that is, the memory cells in different data storage modules in the same row share the same set of word lines).

[0084] Specifically, as Figure 9 and Figure 10As shown, in this embodiment, in each data storage module (320, 321, ……, 32(N - 2), 32(N - 1)), the switching unit 3c is provided at one end (left or right) of the word line in the corresponding memory cell array 3a; that is, the memory cell array 3a and the switching unit 3c are arranged in the row direction of the memory cells. The switch selection units (3b1 and 3b2) are provided at at least one end of the bit line in the corresponding memory cell array 3a; as an example, the switch selection unit is divided into two parts 3b1 and 3b2, and the two parts are respectively provided at both ends (upper and lower sides) of the bit line of the memory cell array 3a.

[0085] It should be noted that, in this example, for the convenience of wiring, the switching unit 3c is arranged in the row direction of the memory cell array 3a, and the switch selection units (3b1 and 3b2) are arranged in the column direction of the memory cell array 3a. In actual use, the positions of the switching unit and the switch selection unit can be swapped, or they can also be arranged on the same side, which is not limited to this embodiment.

[0086] For the convenience of wiring, further, two adjacent data storage modules are set to be mirror - distributed (symmetric). Of course, in actual use, they may not be mirror - set.

[0087] Specifically, the memory cells are set as N - type memory cells, P - type memory cells, floating - gate memory cells or charge - trap memory cells. Any structure that can be used as the memory cell of a NOR memory is applicable to the present invention, and will not be elaborated one by one here.

[0088] The following takes a NOR memory (NOR Flash) with a capacity of 4Mb = 4096Kb as an example to illustrate the present invention. Among them, the data storage module 3a is a sector; of course, the data storage module 3a can also be set as a block. At this time, the block is the smallest erasable unit in the memory, and will not be elaborated one by one here.

[0089] As Figure 11 shown, as an example, this 4Mb block is composed of 8 sectors 320 - 327 (SECTOR<0> - SECTOR<7>) arranged in sequence from left to right, and the capacity of each sector is 512Kb; it can also be set to other configurations according to needs, including but not limited to 16 sectors, and the capacity of each sector is 256Kb; as long as it satisfies Block capacity = capacity of each sector × number of sectors, which is not limited to this embodiment. Each sector has its own independent switching unit 3c (providing the driving voltage of the common source and the well), but there is no independent word - line row driving. Instead, the entire block shares a group of word - line row driving circuits 31. The purpose of doing this is to greatly reduce the area, because if each sector repeats a group of word - line row driving circuits, then 7 more groups are needed in this example. As Figure 9 andFigure 10 As shown, the switching selection transistors for bit lines are located on both the upper and lower sides of the sector, and each main bit line MBL is correspondingly connected to 4 lower-level bit lines BL. Therefore, there are 4096 main bit lines MBL and 16384 bit lines BL in the entire Block. The number of lower-level bit lines corresponding to each main bit line MBL can be set according to actual needs, including but not limited to 8, 16, 32, which will not be elaborated here one by one. Each 512Kb sector contains 256 word lines and 2 × 1024 = 2048 = 2K bit lines, satisfying the sector capacity = the number of word lines per sector × the number of bit lines; on the inner side of each sector, there is no longer an independent 256-word line row driver for each sector, but only metal wiring to the shared word line row driver circuit 31 on the outermost side of the Block; on the right side, there is still an independent switching unit 3c for each sector; on both the upper and lower sides, there are independent switching selection transistor switching selection units (3b1 and 3b2) for each sector.

[0090] Furthermore, as Figure 12 shown, the data storage modules 320 and 321 are arranged adjacent to each other and are mirror-distributed (symmetrical to each other); any two adjacent data storage modules are set in a mirror relationship, which will not be elaborated here one by one.

[0091] As can be seen from the above, since the sectors in the 4Mb storage array Block of the present invention are arranged horizontally, and each sector contains its own independent switching selection unit and well, but there is no independent 256-word line driver for each sector, but the entire Block shares a group of word line row driver circuits. This can not only avoid bit line crosstalk and well crosstalk, but also greatly reduce the area, which is a win-win storage array layout scheme.

[0092] The programming method of the NOR memory 3 of the present invention is as follows:

[0093] 11) Configure the common source voltage and well voltage for the corresponding data storage module based on each switching unit.

[0094] Specifically, the common source voltages SL of each data storage module are equal, and the well voltages Mwell of each data storage module are equal; in this embodiment, the common source voltage and well voltage of each data storage module are both configured to 0V. It should be noted that the common source voltage and well voltage of each data storage module are provided by the corresponding internal switching unit 3c.

[0095] 12) Select the row where the storage unit to be programmed is located based on the word line row driver circuit 31.

[0096] Specifically, the word line row driver circuit 31 provides the word line driving voltages corresponding to each row. Among them, the corresponding rows of each data storage module respectively receive the same word line driving voltage, and the gates of all storage units in the selected row are turned on, and the corresponding driving voltage value can be configured according to actual needs.

[0097] 13) Based on the switch selection unit in the data storage module where the storage unit to be programmed is located, select the bit line of the column where the storage unit to be programmed is located and write data.

[0098] The erasing method of the NOR memory 3 of the present invention is as follows:

[0099] 21) Based on the word line row driving circuit and each switch selection unit, configure the same word line voltage and bit line voltage for each storage unit.

[0100] Specifically, in this embodiment, the word lines of each storage unit are configured as negative high voltages, and the bit lines are floating; among them, the negative high voltage is set to -8V to -10V, including but not limited to -8.5V, -9V, -9.5V, which will not be elaborated here one by one.

[0101] 22) Based on the corresponding switching unit in the data storage module that does not need to be erased, float the common source of the data storage module that does not need to be erased, and configure the well voltage to be equal to the word line voltage.

[0102] Specifically, in this embodiment, the well voltage and the word line voltage of each storage unit in the data storage module that does not need to be erased are both negative high voltages.

[0103] 23) Based on the switching unit in the data storage module to be erased, set the common source voltage and the well voltage of the data storage module to be erased to a set voltage to achieve data erasure.

[0104] Specifically, in this embodiment, the set voltage is 7V to 10V, including but not limited to 8V, 8.5V, 9V, 9.5V, which will not be elaborated here one by one. As an example, the common source voltage and the well voltage of the data storage module to be erased are the same.

[0105] It should be noted that in this embodiment, the programming method and the erasing method of the NOR memory 3 take the N-type floating gate storage unit as an example to set voltage values for each node; in actual use, for storage units of different types and different processes, corresponding voltage values can be configured according to actual needs, not limited to this embodiment.

[0106] Such as Figure 12As shown, for any selected target storage cell A inside the Block (taking the WL<0> and BL<0> cells in the data storage module 320 as an example) and the unselected storage cell B on the same bit line in the same sector (taking the WL<255> and BL<0> cells in the data storage module 320 as an example), during the write operation, the 4V programming voltage on the main bit line MBL<0> is passed to all 256 storage cells connected to the bit line BL<0> through the corresponding switch selection transistors. Here, it includes both the selected target cell A and all other unselected cells, such as cell B. See Table III below. Similarly, since all sectors have their own independent wells, when performing the erase operation, the well potentials of the target cell A and the unselected storage cell C (taking the WL<255> and BL<4095> cells in the data storage module 321 as an example) can be different. See Table III below.

[0107]

[0108] Table III

[0109] During the write operation, since the target cell A and the unselected cell B are in the same sector, there is no need to consider an additional 100,000 erase / write cycles. Just consider the worst-case scenario of programming the sector from WL<0> to WL<254>. During this process, although the unselected storage cell B on the same bit line has to withstand a 4V bit line crosstalk, the total time of this crosstalk can be roughly estimated as: 10us (write time per row) × 255 (number of word lines per sector - 1) = 2.55 milliseconds, which is much smaller than the 224 seconds of the Figure 1 scheme. The impact of its bit line crosstalk can be almost ignored. For the target cell A and the unselected cell C in different sectors, as can be seen from the operating voltages in Table III, at this time, both BL<4095> and WL<255> of the unselected cell C are equal to 0V, without any voltage difference, so there is naturally no BL crosstalk. During the erase operation, also consider two cases: Since the target cell A and the unselected cell B are in the same sector, and the minimum erase unit of NOR Flash is the sector, these two cells will definitely be erased simultaneously, without well-to-word line crosstalk. The target cell A and the unselected cell C are in different sectors. Since different sectors have their own independent Mwell and SL, as can be seen from the operating voltages in Table III, at this time, both WL<255> and the well of the unselected cell C are equal to -9.5V, without any voltage difference, so there is naturally no well-to-word line crosstalk.

[0110] As shown in Table IV below, the present invention can not only solve the crosstalk problem but also effectively control the waste of array area, taking both into account.

[0111]

[0112] Table IV

[0113] In summary, the present invention provides a NOR memory and its programming and erasing methods, including: a word line row driving circuit and N data storage modules; the N data storage modules are arranged in sequence along the row direction of the storage units and share the word line row driving circuit, and the same row of the N data storage modules receives the same word line driving signal; each data storage module includes an independent storage cell array, a switch selection unit, a common source, a well and a switching unit, and the switch selection unit and the switching unit are arranged outside the storage cell array; the gates of the storage cells in the same row of the storage cell array are connected to the same word line, the drains of the storage cells in the same column are connected to the same bit line, each storage cell has a common source and the well potential is the same; the switch selection unit connects every M bit lines in the storage cell array to a corresponding main bit line; the switching unit is connected to the common source and the well of the storage cell array and provides the required driving voltage for the common source and the well of each storage cell in the storage cell array; wherein, the data storage module is the smallest erasable array unit, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2. When programming and erasing a selected sector or block of the NOR memory according to the present invention, electrical crosstalk to other non-selected sectors or blocks is avoided, and the increase in area can also be better controlled. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0114] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A NOR memory, characterized in that: The NOR memory at least comprises: A word line row driving circuit and N data storage modules; the N data storage modules are arranged in sequence along the row direction of the storage unit and share the word line row driving circuit, and the same row of the N data storage modules receives the same word line driving signal; Each data storage module includes an independent memory cell array, a switch selection unit, a common source, a well and a switching unit, wherein the switch selection unit and the switching unit are arranged at the periphery of the memory cell array; the gates of the memory cells in the same row in the memory cell array are connected to the same word line, the drains of the memory cells in the same column are connected to the same bit line, and the memory cells have a common source and the well potential is the same; the switch selection unit connects each M bit lines in the memory cell array to a corresponding main bit line; the switching unit connects the common source and well of the memory cell array, and provides the required driving voltage to the common source and well of each memory cell in the memory cell array; The data storage module is the smallest erase array unit, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2.

2. The NOR memory according to claim 1, wherein: The data storage module is a sector or a block.

3. The NOR memory according to claim 1, wherein: The word line row driving circuit is arranged at the periphery of the storage area formed by each data storage module, and is arranged in sequence with each data storage module along the row direction of the storage unit.

4. The NOR memory according to claim 1, wherein: The switching unit is arranged at one end of a word line in a corresponding memory cell array.

5. The NOR memory according to claim 1 or 4, characterized in that: The structures of two adjacent minimum data storage modules are distributed in a mirrored manner.

6. The NOR memory according to claim 1, wherein: The switch selection unit is arranged at at least one end of a bit line in a corresponding memory cell array.

7. The NOR memory according to claim 1, wherein: The memory cell is an N-type memory cell, a P-type memory cell, a floating gate memory cell or a charge trap memory cell.

8. A method for programming a NOR memory, implemented by using the NOR memory according to any one of claims 1 to 7, characterized in that: The programming method of the NOR memory at least comprises: configuring a common source voltage and a well voltage for a corresponding data storage module based on each switching unit; Selecting a row where the memory cell to be programmed is located based on a word line row driving circuit; Based on the switch selection unit in the data storage module where the memory cell to be programmed is located, the bit line of the column where the memory cell to be programmed is located is selected, and data is written.

9. The method for programming a NOR memory according to claim 8, wherein: The common source voltages of the data storage modules are equal, and the well voltages of the data storage modules are equal.

10. The method for programming a NOR memory according to claim 9, wherein: When the storage cells in the data storage module are N-type floating gate storage cells, the common source voltage and the well voltage of each data storage module are configured to be 0V.

11. A method for erasing a NOR memory, implemented by using the NOR memory according to any one of claims 1 to 7, characterized in that: The erasing method of the NOR memory at least comprises: Based on the word line row driving circuit and each switch selection unit, the same word line voltage and bit line voltage are configured for each memory cell; Based on the corresponding switching unit in the data storage module that does not need to be erased, the common source of the data storage module that does not need to be erased is floated, and the well voltage is configured to be equal to the word line voltage; Based on the switching unit in the data storage module to be erased, the common source voltage and the well voltage of the data storage module to be erased are set to a set voltage to achieve data erasure.

12. The method for erasing a NOR memory according to claim 11, characterized in that: When the storage unit in the data storage module is an N-type floating gate storage unit, the set voltage is 7V to 10V.

13. The method for erasing a NOR memory according to claim 11, characterized in that: When the storage cells in the data storage module are N-type floating gate storage cells, the word lines of each storage cell are configured as negative high voltage, and the bit lines are floating.

14. The method for erasing a NOR memory according to claim 13, wherein: The negative high voltage is -8V to -10V.

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