Memory device, memory controller, and memory device including the same

Abstract

A memory device, a memory controller, and a memory apparatus including the memory device and the memory controller are provided, the memory device including: a memory cell array including a first memory region storing first data; a page buffer including a first latch configured to store data dumped from the memory cell array; and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data, the first parity data including a parity bit generated based on the first user data, and the control logic circuit dumps the first parity data whose size is adjusted based on the parity adjustment information to the first latch.

Description

Technical Field

[0001] The present invention relates to a storage device, and more particularly, to a memory device that variably controls parity data, a memory controller, and a storage device including the memory device and the memory controller. Background Art

[0002] The performance of a storage device based on a non-volatile memory device can be significantly affected by the input / output (I / O) occupation time of internal operations of the non-volatile memory device. The internal operations of the non-volatile memory device may refer to operations that are not visible to a user. Examples of the internal operations of the non-volatile memory device may include operations for correcting error bits to improve data I / O reliability of the storage device.

[0003] The storage device may perform a correction operation on error bits based on parity data. Here, the storage device may perform a correction operation on user data by maintaining a specified format and order of the parity data. However, the fact that the storage device must perform the correction operation according to the specified format and order of the parity data may lead to an increase in the I / O occupation time of the non-volatile memory device, which may deteriorate the overall performance of the storage device. Summary of the Invention

[0004] The inventive concept provides a storage device in which the I / O occupation rate for a non-volatile memory device is reduced by variably adjusting parity data when correcting error bits, thereby having improved performance.

[0005] The technical problems of the inventive concept are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0006] According to an aspect of the inventive concept, there is provided a memory device including: a memory cell array including a first memory area storing first data; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data, the first parity data includes parity bits generated based on the first user data, and the control logic circuit adjusts a size of the first parity data based on the parity adjustment information and dumps the adjusted first parity data to the first latch.

[0007] According to another aspect of the inventive concept, there is provided a memory controller including: an error correction code (ECC) engine configured to generate parity data corresponding to user data received from a host; and a parity controller including reliability information including information indicating reliability of a plurality of memory regions included in a memory device. The parity controller adjusts a size of the parity data based on the reliability information corresponding to a memory region among the plurality of memory regions in which the user data is to be stored, and the memory controller writes the adjusted parity data and the user data into the memory device.

[0008] According to another aspect of the inventive concept, there is provided a storage device including: a memory device configured to adjust a size of first parity data based on parity adjustment information and output the first parity data having the adjusted size; and a memory controller configured to control an operation of the memory device. The memory device includes: a memory cell array including a plurality of memory regions; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; and control logic circuitry configured to receive the parity adjustment information from the memory controller and control an operation of the memory cell array. The memory controller includes a parity controller including reliability information including information indicating reliability of the plurality of memory regions included in the memory device. The parity controller is configured to: determine a format and a size of the first parity data based on the reliability information of a memory region in which user data corresponding to the first parity data is to be stored, and provide the parity adjustment information indicating the determined format and size of the first parity data to the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment;

[0011] Figure 2 is a block diagram illustrating a memory controller according to an embodiment;

[0012] Figure 3 is a block diagram illustrating a memory device according to an embodiment;

[0013] Figure 4 is a block diagram showing a read operation of a memory device according to an embodiment;

[0014] Figure 5 is a block diagram showing a write operation on a memory device according to an embodiment;

[0015] Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D is a block diagram showing a read operation of a memory device according to an embodiment;

[0016] Figure 7 is a block diagram showing a write operation on a memory device according to an embodiment;

[0017] Figure 8 is a diagram showing a system to which a storage device according to an embodiment is applied; and

[0018] Figure 9 is a block diagram showing an example in which a memory controller according to an embodiment is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and redundant description thereof is omitted.

[0020] Figure 1 is a block diagram showing a storage device 10 according to an embodiment.

[0021] The storage device 10 may include a storage medium for storing data according to a request from a host. For example, the storage device 10 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. If the storage device 10 is an SSD, the storage device 10 may be a device compliant with the nonvolatile memory express (NVMe) standard.

[0022] If the storage device 10 is an embedded memory or an external memory, the storage device 10 may be a device compliant with the universal flash storage (UFS) or embedded multimedia card (eMMC) standard. The host and the storage device 10 may each generate and transmit data packets according to the standard protocol adopted. In an embodiment, the storage device 10 may be an embedded memory built into the storage device. For example, the storage device 10 may be an eMMC memory device or an embedded UFS memory device. In an embodiment, the storage device 10 may be an external memory removable from another system. For example, the storage device 10 may include a UFS memory card, a compact flash (CF), a secure digital (SD), a micro SD, a mini SD, an extreme digital (xD), or a memory stick.

[0023] Reference Figure 1 , the storage device 10 may include a memory controller 100 and a memory device 200.

[0024] The memory controller 100 may include an error correction code (ECC) engine 150 and a parity controller 160. The memory controller 100 may control read operations, write operations, and erase operations for the memory device 200 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 200. In an embodiment, in response to a read / write request from the host HOST, the memory controller 100 may read data stored in the memory device 200 or control the memory device 200 to write data to the memory device 200. In an embodiment, the storage device 10 may perform operations such as wear leveling management, bad block management, and garbage collection, and for these operations, the memory controller 100 may provide the address ADDR, the command CMD, the control signal CTRL, and the data DATA to the memory device 200.

[0025] The data DATA may be transmitted and received between the memory controller 100 and the memory device 200. In an embodiment, the data DATA may include user data and parity data. The parity data may be data used by the ECC engine 150 to perform error correction operations. The parity data may be generated by the ECC engine 150. The parity data may be data generated based on the user data.

[0026] The ECC engine 150 can be configured to use ECC to detect and correct errors in data read from the memory device 200. In addition, the ECC engine 150 can generate parity data related to user data to be written to the memory device 200 and write the user data and the parity data to the memory device 200. In an embodiment, the ECC engine 150 can include a circuit, system, or device for error correction.

[0027] The parity controller 160 can provide parity adjustment information PAI to the memory device 200 during a read operation of the first memory region 230_1 to the Nth memory region 230_N (N is a natural number greater than or equal to 2) based on reliability information about the first memory region 230_1 to the Nth memory region 230_N. In addition, the parity controller 160 can adjust the size of the parity data of the data to be written during a write operation of the first memory region 230_1 to the Nth memory region 230_N based on the reliability information about the first memory region 230_1 to the Nth memory region 230_N.

[0028] The memory cell array of the memory device 200 can be divided into a plurality of memory regions. The memory regions can include the first memory region 230_1 to the Nth memory region 230_N. In the present disclosure, a memory region can refer to a region including a plurality of memory cells in the memory cell array.

[0029] The reliability of each of the memory regions 230_1 to 230_N included in the memory device 200 may deteriorate for various reasons. For example, the criteria for determining the reliability of a memory region can include at least one of read count information, program count information, elapsed time information after erasure, and cell temperature information related to each memory region.

[0030] In an embodiment, the reliability of each memory region can be different, and thus, the parity adjustment information PAI provided by the memory controller 100 to the memory device 200 will also be different. For example, the reliability of the first memory region 230_1 can be different from the reliability of the second memory region 230_2. Therefore, the parity adjustment information PAI provided by the memory controller 100 to the memory device 200 can vary depending on whether the data to be read is read from the first memory region 230_1 or the second memory region 230_2.

[0031] In an embodiment, when the memory controller 100 reads data from the memory device 200, the memory controller 100 may provide parity adjustment information PAI to the memory device 200. The memory device 200 may adjust the format and size of parity data related to the data to be read based on the parity adjustment information PAI. The memory device 200 may provide the data DATA having the adjusted format and size of the parity data to the memory controller 100. A detailed description thereof will be provided below with reference to Figures 6A to 6D Provide its detailed description.

[0032] In an embodiment, when the memory controller 100 writes the data received from the host to the memory device 200, the format and size of the parity data related to the data to be written may be adjusted based on the reliability of the memory area in which the data to be written is stored. The memory controller 100 may provide the data DATA having the adjusted format and size of the parity data to the memory device 200. A detailed description thereof will be given below with reference to Figure 7 Give its detailed description.

[0033] When reading data stored in the memory device 200, the storage device 10 according to an embodiment may perform an error correction operation based on the parity data. The memory device 200 may variably adjust the parity data based on the parity adjustment information PAI provided from the memory controller 100. In addition, when writing data to the memory device 200, the storage device 10 may variably adjust the format and size of the parity data generated in response to the user data, and write the user data and the adjusted parity data to the memory device 200. By adjusting the parity data in this way, the speed of the data input / output (I / O) operation from the memory device 200 can be increased, and the performance of the storage device 10 can be improved.

[0034] Figure 2 Is a block diagram showing the memory controller 100 according to an embodiment. It can be described with reference to Figure 1 To describe Figure 2 And redundant descriptions may be omitted.

[0035] Referring to Figure 2 Memory controller 100 may include a processor 110, a flash translation layer (FTL) 120, a memory 130, a host interface (IF) circuit 140, an ECC engine 150, and a memory IF circuit 170, and these components may communicate with each other through a bus 180.

[0036] The processor 110 may include a central processing unit (CPU) or a microprocessor and may control the overall operation of the memory controller 100. The processor 110 may include one or more processor cores that are capable of running an instruction set of program code configured to perform specific operations. For example, the processor 110 may run command codes of firmware stored in the memory 130.

[0037] The FTL 120 may perform various functions such as address mapping, wear leveling, and garbage collection.

[0038] The memory 130 may be used as an operating memory, a buffer memory, a cache memory, etc. For example, the memory 130 may be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change random access memory (PRAM), or a flash memory.

[0039] The host IF circuit 140 may provide an interface between the host HOST and the memory controller 100. For example, the host IF circuit 140 may provide an interface according to the following: universal serial bus (USB), MMC, peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), and integrated drive electronics (IDE). The host IF circuit 140 may receive requests and data from the host HOST and output data to the host HOST.

[0040] The ECC engine 150 may perform error detection and correction functions on data read from the memory device 200. Specifically, the ECC engine 150 may generate parity bits for write data to be provided to the memory device 200, and the generated parity bits may be stored in the memory device 200 together with the write data. When reading data from the memory device 200, the ECC engine 150 may use the parity bits read from the memory device 200 and the read data to correct errors in the read data and output the error-corrected read data.

[0041] The parity controller 160 may include reliability information 161. Specifically, the parity controller 160 may include reliability information 161 about the first memory region 230_1 to the Nth memory region 230_N generated based on a reliability judgment criterion for the memory region. For example, the reliability information 161 may include information indicating the reliability of the first memory region 230_1. In some embodiments, the reliability information 161 may be stored in the memory 130.

[0042] The parity controller 160 may generate parity adjustment information PAI based on the reliability information 161. When performing an operation of reading data from the memory device 200, the parity controller 160 may generate parity adjustment information PAI based on the reliability information 161. The parity adjustment information PAI may include parity data format information and parity data size information. The parity data format information determines the format of the parity data related to the data read from the memory device 200, and the parity data size information determines the size of the parity data.

[0043] In an embodiment, when the reliability information regarding the first memory region 230_1 is a first reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a first format. In the present disclosure, the first reference value indicating the reliability information of the memory region may refer to a reference value used to explain a situation where a high error correction capability is required when performing an error correction operation of the memory controller 100. Here, the situation where a high error correction capability is required may refer to a situation where the reliability of the memory region from which data is read is low. One of the reasons for the low reliability of the memory region may be that the memory cells included in the memory region deteriorate due to frequent read, write, and erase operations performed on the memory region. Reading data from or writing data to deteriorated memory cells may involve a higher probability of error occurrence than in non-deteriorated memory cells. Therefore, the memory controller 100 may select a method of screening out parity data with the highest error correction capability by indicating the parity data format information of the first format. This is merely an example for helping understanding and is not intended to limit the inventive concept. The following reference Figure 6A provides its detailed description.

[0044] In an embodiment, when the reliability information regarding the first memory region 230_1 is a second reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a second format. In the present disclosure, the second reference value indicating the reliability information of the memory region may refer to a reference value used to explain the following situation: when performing an error correction operation of the memory controller 100, a faster I / O speed is required for data to be input to or output from the memory device 200. Here, the situation where a faster I / O speed is required may refer to a situation where the reliability of the memory region from which data is read is high. Different from the situation where the reliability of the memory region is low, the situation where the reliability of the memory region is high may refer to a situation where the degree of deterioration of the memory cells included in the memory region is not high when many read, write, and erase operations are not performed on the memory region. In this way, reading data from a memory region with a low degree of deterioration and writing data to such a memory region may have a relatively lower probability of error occurrence than deteriorated memory cells. Therefore, the memory controller 100 may optimize the I / O performance by selecting and transmitting the most efficient parity according to the reliability of the memory region. This is merely an example for helping understanding and is not intended to limit the inventive concept. The following reference Figure 6B provides its detailed description.

[0045] In an embodiment, when the reliability information regarding the first memory region 230_1 is a third reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a third format. In the present disclosure, the reliability information as the third reference value may refer to performing an error correction operation based on new parity data different from the existing parity data when the memory controller 100 performs an error correction operation. Here, new parity data may be generated based on user data.

[0046] During the error correction operation of the memory controller 100, if the error correction capability achievable by the parity data configured in the first format or the second format is different from the range of the error correction capability considered by the memory controller 100, the third format may be selected as the format of the parity data.

[0047] For example, assume that in the initial state after data is written to the memory region, the reliability of the memory region is very high. In this case, parity data having a size smaller than the size of the parity data with the lowest error correction capability previously considered in the prior art may be sufficient. That is, when a read operation is performed by selecting the first format or the second format as the format of the parity data, it is necessary to transmit parity data in a form having a higher error correction capability than required (i.e., parity data having an unnecessarily large size), and thus, the operation of the memory device 200 may be inefficient in terms of I / O speed. Here, if the memory controller 100 selects the third format as the parity data and performs a read operation, a new parity data having a format different from the parity data of the first format and the second format and a size smaller than the size of the parity data of the first format and the second format may be used to perform the read operation, thereby achieving an improved I / O speed. This is merely an example for helping understanding and is not intended to limit the inventive concept. A detailed description thereof will be provided below with reference to Figure 6C provide its detailed description.

[0048] Moreover, for example, assume that the error correction capability required by the memory controller 100 depending on the reliability of the memory region falls between the case of selecting the first format and performing a read operation and the case of selecting the second format. In such a situation, if the memory controller 100 selects the first format, the parity data may have an error correction capability higher than the required error correction capability (i.e., parity data having an unnecessarily large size), which may be inappropriate, while if the memory controller 100 selects the second format, there is a relatively high probability that error correction may fail, which may also be inappropriate. Here, if the memory controller 100 selects the third format as the parity data and performs a read operation, the memory controller 100 may perform the read operation based on all or part of the newly generated parity data and the existing parity data received together from the memory device 200, and thus, the target error correction reliability can be achieved. This is merely an example for helping understanding and is not intended to limit the inventive concept. The following refers to Figure 6D Provide its detailed description.

[0049] In an embodiment, the first to third reference values may be values previously input to the memory controller 100. Alternatively, the first to third reference values may be values determined by the FTL 120 to achieve a specific level or higher level of error correction capability related to the error correction operation during the process of reading data from the memory device 200.

[0050] When performing a data write operation in the memory device 200, the parity controller 160 may determine the format and size of the parity data of the data to be written based on the reliability information 161.

[0051] In an embodiment, when the reliability information about the first memory region 230_1 is the first write reference value, the memory controller 100 may determine the format of the parity data of the data to be written as the first write format. In some embodiments, the first write reference value may be different from the first reference value in the above read operation. In the present disclosure, the first write reference value indicating the reliability information of the memory region may be a reference value for explaining the following situation: in this case, when the reliability of the memory region to which data is written is low, the memory controller 100 generates parity data corresponding to the user data. The first write format may be a parity data format having an error correction capability superior to that of the second write format. The following refers to Figure 7 Provide its detailed description.

[0052] In an embodiment, when the reliability information regarding the first memory region 230_1 is the second write reference value, the memory controller 100 may determine the format of the parity data of the data to be written as the second write format. In some embodiments, the second write reference value may be different from the second reference value in the above-described read operation. In the present disclosure, the second write reference value indicating the reliability information of the memory region may be a reference value for explaining the following situation: in this situation, when the reliability of the memory region to which data is written is high, the memory controller 100 generates parity data corresponding to the user data. In terms of the I / O performance of the memory device 200, the second write format may be a parity data format that is more efficient than the first write format. The following will refer to Figure 7 Provide a detailed description thereof.

[0053] In an embodiment, the first write reference value and the second write reference value may be values previously input to the memory controller 100. Alternatively, the first write reference value and the second write reference value may be values determined by the FTL 120 to achieve an error correction ability above a specific level in consideration of the reliability of the memory region when writing data during the process of writing data to the memory device 200.

[0054] The parity controller 160 may be implemented in hardware, software, or firmware. When the parity controller 160 is implemented in software or firmware, the parity controller 160 may be loaded into the memory 130 and operate under the control of the processor 110. In some embodiments, the parity controller 160 may be included in the FTL 120, but is not limited thereto.

[0055] The memory IF circuit 170 may provide an interface between the memory controller 100 and the memory device 200. For example, data, commands, and addresses may be transmitted and received between the memory controller 100 and the memory device 200 through the memory IF circuit 170.

[0056] The bus 180 may operate based on one of various bus protocols. The various bus protocols may include at least one of an advanced microcontroller bus architecture (AMBA) protocol, a USB protocol, an MMC protocol, a PCI protocol, a PCI-E protocol, an ATA protocol, a serial ATA protocol, a parallel ATA protocol, an SCSI protocol, an ESDI protocol, an integrated drive electronics (ESDI) protocol, a Mobile Industry Processor Interface (MIPI) protocol, and a UFS protocol.

[0057] Figure 3is a block diagram showing a memory device 200 according to an embodiment. Reference may be made to Figure 1 and Figure 2 to describe Figure 3 , and redundant descriptions may be omitted.

[0058] Referring to Figure 3 , the memory device 200 includes a voltage generator 210, an address decoder 220, a memory cell array 230, a control logic circuit 240, a page buffer 250, and an I / O circuit 260.

[0059] The voltage generator 210 may generate various types of voltages for performing a programming operation, a read operation, and an erase operation on the memory cell array 230 based on a voltage control signal CTRL_vol. Specifically, the voltage generator 210 may generate a word line voltage VWL, such as a programming voltage, a read voltage, a pass voltage, an erase verification voltage, or a programming verification voltage. In addition, the voltage generator 210 may generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol. Further, the voltage generator 210 may generate an erase voltage to be provided to the memory cell array 230.

[0060] The address decoder 220 may select one of a plurality of memory blocks BLK1 to BLKz (z is a natural number greater than 1) of the memory cell array 230, select one word line among the word lines WL of the selected memory block, and select one string selection line among a plurality of string selection lines SSL.

[0061] The memory cell array 230 may be connected to the word line WL, the string selection line SSL, the ground selection line GSL, and the bit line BL. The memory cell array 230 may be connected to the address decoder 220 through the word line WL, the string selection line SSL, and the ground selection line GSL, and may be connected to the page buffer 250 through the bit line BL. The memory cell array 230 may include memory blocks BLK1 to BLKz.

[0062] Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells and a plurality of select transistors. The memory cells may be connected to the word line WL, and the select transistors may be connected to the string selection line SSL or the ground selection line GSL. Each of the memory blocks BLK1 to BLKz may correspond to an erase unit. Each of the memory blocks BLK1 to BLKz may include a plurality of pages, and each page may correspond to a programming or read unit of data in one memory block. In an embodiment, each of the memory blocks BLK1 to BLKz may correspond to Figure 1 the first memory region 230_1 to the Nth memory region 230_N.

[0063] The control logic circuit 240 can output various control signals based on the command CMD, the address ADDR, and the control signal CTRL to perform programming operations, read operations, and erase operations on the memory cell array 230. The control logic circuit 240 can provide the row address X-ADDR to the address decoder 220, the column address Y-ADDR to the page buffer 250, and the voltage control signal CTRL_vol to the voltage generator 210.

[0064] The control logic circuit 240 can include a parity generator 241. The control logic circuit 240 can generate new parity data based on the parity adjustment information PAI received from the memory controller 100. The parity data newly generated by the parity generator 241 can be referred to as the generated parity data GPD. The parity generator 241 can provide the generated parity data GPD to the second latch 252 of the page buffer 250.

[0065] In an embodiment, when the parity adjustment information PAI includes parity data format information indicating that the format of the parity data is the third format, the parity generator 241 can generate parity data GPD different from the parity data corresponding to the read data.

[0066] The page buffer 250 can include a first latch 251 and a second latch 252. During a read operation of the memory device 200, the page buffer 250 can sense the bit lines BL of the selected memory cells under the control of the control logic circuit 240. The sensed data can be dumped into the first latch 251 and the second latch 252 provided inside the page buffer 250. The page buffer 250 can provide the data latched in the first latch 251 and the second latch 252 to the I / O circuit 260 under the control of the control logic circuit 240. During a write operation of the memory device 200, the write data provided from the memory controller 100 can be dumped into the first latch 251 provided inside the page buffer 250. The page buffer 250 can provide the data latched in the latch to the memory cell array 230 under the control of the control logic circuit 240.

[0067] In an embodiment, when the memory device 200 performs a read operation, the parity data can be dumped into the first latch 251 or the second latch 252 according to the parity data format information included in the parity adjustment information PAI. The following is a detailed description with reference to Figures 6A to 6D is given.

[0068] The I / O circuit 260 can temporarily store a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from the outside of the memory device 200. The I / O circuit 260 can temporarily store read data of the memory device 200 and output the data DATA to the outside at a specified time. In addition, the I / O circuit 260 can temporarily store write data provided from the outside and provide the data DATA to the page buffer 250 at a specified time.

[0069] Figure 4 is a block diagram showing a read operation of the memory device 200 according to an embodiment. Specifically, Figure 4 is a diagram showing the memory controller 100 reading second data D2 from the memory device 200. Reference can be made to Figures 1 to 3 to describe Figure 4 and redundant descriptions can be omitted.

[0070] Referring to Figure 4 , the memory device 200 may include a memory cell array 230 and a page buffer 250. The memory cell array 230 may include a first memory area 230_1 to a fourth memory area 230_4. In Figure 4 , the memory cell array 230 is shown as including four memory areas, but this is an example, and the memory cell array 230 may include fewer or more memory areas.

[0071] First data D1 may be stored in the first memory area 230_1. The first data D1 may include first user data UD1 and first parity data PD1. Second data D2 may be stored in the second memory area 230_2. The second data D2 may include second user data UD2 and second parity data PD2. Third data D3 may be stored in the third memory area 230_3. The third data D3 may include third user data UD3 and third parity data PD3. Fourth data D4 may be stored in the fourth memory area 230_4. The fourth data D4 may include fourth user data UD4 and fourth parity data PD4.

[0072] In an embodiment, the formats and sizes of the first parity data PD1 to the fourth parity data PD4 may be different from each other. The formats and sizes of the first parity data PD1 to the fourth parity data PD4 may be determined based on reliability information corresponding to the memory area in which each parity data is stored.

[0073] In an embodiment, the memory device 200 may provide read data to the page buffer 250 during a read operation. For example, when the memory controller 100 reads the second data D2, the memory device 200 may provide the second data D2 to the page buffer 250. The read data RD stored in the page buffer 250 may include second user data UD2 and adjusted parity data PD2a. The adjusted parity data PD2a may have a different format and size from the second parity data PD2. The memory device 200 may provide the read data RD stored in the page buffer 250 to the memory controller 100. In an embodiment, the adjusted parity data PD2a may be generated based on parity adjustment information PAI.

[0074] In an embodiment, the memory controller 100 may perform an error correction operation on the read data RD. Specifically, the memory controller 100 may perform an error correction operation on the second user data UD2 based on the adjusted parity data PD2a.

[0075] Figure 5 is a block diagram showing a write operation of the memory device 200 according to an embodiment. Specifically, Figure 5 is a diagram showing writing the third data D3 into the third memory area 230_3. Reference may be made to Figure 4 to describe Figure 5 , and redundant descriptions may be omitted.

[0076] Reference Figure 5 , the memory device 200 may include a memory cell array 230 and a page buffer 250. The memory cell array 230 may include a first memory area 230_1 to a fourth memory area 230_4. In Figure 5 the memory cell array 230 is shown as including four memory areas, but this is an example, and the memory cell array 230 may include fewer or more memory areas.

[0077] The first data D1 may be stored in the first memory area 230_1. The first data D1 may include first user data UD1 and first parity data PD1. The second data D2 may be stored in the second memory area 230_2. The second data D2 may include second user data UD2 and second parity data PD2. The third memory area 230_1 may be a memory area into which the write data WD provided from the memory controller 100 is written. The fourth memory area 230_4 may be in a state where no data is stored.

[0078] In an embodiment, the memory controller 100 may provide write data WD to the memory device 200 during a write operation. The write data WD may include third user data UD3 and third parity data PD3. Here, the third parity data PD3 may be data generated by the memory controller 100 based on the third user data UD3. The memory device 200 may store the write data D3 in the third memory area 230_3. The data stored in the third memory area 230_3 may be referred to as third data D3.

[0079] In an embodiment, the formats and sizes of the first to third parity data PD1 to PD3 may be different from each other. The formats and sizes of the first to third parity data PD1 to PD3 may be determined based on reliability information corresponding to a memory region storing each parity data.

[0080] Figure 6A , Figure 6B , Figure 6C and Figure 6D 2 is a block diagram showing a read operation of a memory device 200 according to an embodiment. Figures 1 to 4 To describe Figure 6A , Figure 6B , Figure 6C and Figure 6D , and redundant descriptions can be omitted.

[0081] In an embodiment, the first data D1 may include first user data UD1 and first parity data PD1. The first parity data PD1 may be divided into a first parity area P1, a second parity area P2, and a third parity area P3. The memory controller 100 may perform error correction using data corresponding to each parity area, and each parity area may have different error correction capabilities. As an example, it is assumed that the error correction capability of the second parity area P2 is higher than the error correction capability of the first parity area P1, and the error correction capability of the third parity area P3 is the highest among the first parity area P1 to the third parity area P3. Dividing the parity data PD1 into three areas may be an example, and the first parity data PD1 may also be divided into fewer or more parity areas. Here, each parity area may be generated by a different ECC algorithm. For example, the ECC algorithm used to generate the first parity area P1 may be different from the ECC algorithm used to generate the second parity area P2.

[0082] Figure 6A 2 is a diagram showing the reading of the first data D1 stored in the first memory area 230_1a. Figure 6AIn this case, it is assumed that the reliability information corresponding to the first memory region 230_1a is a first reference value, and the parity adjustment information PAI received from the memory controller 100 includes parity data format information indicating that the format of the parity data to be read is a first format.

[0083] The memory device 200 may dump a part of the first data D1 into the first latch 251 of the page buffer 250. Since the format of the parity data indicated by the parity adjustment information PAI is the first format, the memory device 200 may select only the third parity region P3 having the best error correction ability from the first parity data PD1 and dump the selected third parity region P3 into the first latch 251. Accordingly, the first latch 251 may store the latched data LDa including the first user data UD1 and the second parity data PD2a, and here, the second parity data PD2a may include the third parity region P3. In an embodiment, the second parity data PD2a may additionally include the second parity region P2 and / or the first parity region P1. The second parity data PD2a may be referred to as the adjusted first parity data PD1.

[0084] The memory device 200 may provide the latched data LDa as the read data RDa to the I / O circuit 260, and the I / O circuit 260 may provide the read data RDa to the memory controller 100. The memory controller 100 may perform an error correction operation on the first user data UD1 based on the second parity data PD2a.

[0085] Figure 6B FIG. is a diagram illustrating reading of the first data D1 stored in the first memory region 230_1b. Refer to Figure 6B In this case, it is assumed that the reliability information corresponding to the first memory region 230_1b is a second reference value, and the parity adjustment information PAI received from the memory controller 100 includes parity data format information indicating that the format of the parity data to be read is a second format.

[0086] In an embodiment, the memory device 200 may dump a part of the first data D1 into the first latch 251. Since the format of the parity data indicated by the parity adjustment information PAI is the second format, the reliability of the memory region is high, and thus, even if using parity data having a lower error correction ability compared to the parity data having the first format, the memory controller 100 may correct an error. For example, as Figure 6BAs shown, the memory device 200 may select a second parity region P2 from the first parity data PD1 and dump the selected parity region P2 into the first latch 251. The first latch 251 may store latch data LDb including first user data UD1 and second parity data PD2b, and in this case, the second parity data PD2b may include the second parity region P2. In an embodiment, the second parity data PD2b may additionally include the first parity region P1 and / or the third parity region P3. The second parity data PD2b may be referred to as the adjusted first parity data PD1.

[0087] In Figure 6B it, the second parity region P2 as the second parity data PD2b is shown to be dumped into the first latch 251, but this is an example, and the first parity region P1 may be dumped into the first latch 251 as the second parity data PD2b. For example, if it is possible to correct errors only by using the first parity region P1 when the memory controller 100 performs an error correction operation, the first parity region P1 may be dumped into the first latch 251. In this case, the reliability of the first memory region 230_1b may be higher when the first parity region P1 is dumped into the first latch 251 than when the second parity data P2 is dumped into the first latch 251. In this way, it may be determined whether to dump the first parity region P1 or the second parity region P2 into the first latch 251 depending on the reliability of the first memory region 230_1b.

[0088] The memory device 200 may provide the latch data LDb as read data RDb to the I / O circuit 260, and the I / O circuit 260 may provide the read data RDb to the memory controller 100. The memory controller 100 may perform an error correction operation on the first user data UD1 based on the second parity data PD2b.

[0089] Figure 6C is a diagram showing reading of the first data D1 stored in the first memory region 230_1c. In Figure 6C it, it is assumed that the reliability information corresponding to the first memory region 230_1c is a third reference value, and the parity adjustment information PAI received from the memory controller 100 includes parity data format information indicating that the format of the parity data to be read is a third format. In addition, in Figure 6C it, it is assumed that the reliability of the first memory region 230_1c is very high, so the error correction capability required by the memory controller 100 is lower than the error correction capability achieved when performing an error correction operation based on the first parity region P1.

[0090] In an embodiment, since the format of the parity-adjusted information PAI for parity-checking data is the third format, the memory device 200 may dump the first user data UD1 of the first data D1 to the first latch 251. The memory device 200 may not dump the first parity-check data PD1 of the first data D1 to the first latch 251. Here, the control logic circuit 240 may generate parity-check data GPD based on the reliability information of the first memory region 230_1c and the first user data UD1, and provide the generated parity-check data GPD as second parity-check data PD2c to the second latch 252. The second parity-check data PD2c may be generated based on the first user data UD1. The data dumped in the first latch 251 may be referred to as first latched data LD1c, and the data dumped in the second latch 252 may be referred to as second latched data LD2c. Additionally, the second parity-check data PD2c may be referred to as a fourth parity-check region P4a to distinguish the second parity-check data PD2c from the first parity-check region P1 to the third parity-check region P3. The fourth parity-check region P4a may have a size different from the sizes of the first parity-check region P1 to the third parity-check region P3. For example, the size of the fourth parity-check region P4a may be smaller than the size of the first parity-check region P1.

[0091] The memory device 200 may provide the first latched data LD1c and the second latched data LD2c to the I / O circuit 260 as read data RDc, and the I / O circuit 260 may provide the read data RDc to the memory controller 100. The memory controller 100 may perform an error correction operation on the first user data UD1 based on the second parity-check data PD2c.

[0092] Figure 6D FIG. is a diagram illustrating reading of the first data D1 stored in the first memory region 230_1d. In Figure 6D it, it is assumed that the reliability information corresponding to the first memory region 230_1d is a third reference value, and the parity-adjustment information PAI received from the memory controller 100 includes parity-check data format information indicating that the format of the parity-check data to be read is the third format. Additionally, in Figure 6D it, it is assumed that the error correction capability considered by the memory controller 100 lies between the error correction capability achieved when performing an error correction operation based on the first parity-check region P1 and the error correction capability achieved when performing an error correction operation based on the second parity-check region P2.

[0093] In an embodiment, since the format of the parity check adjustment information PAI for parity check data is the third format, the memory device 200 may dump the first user data UD1 of the first data D1 to the first latch 251. The memory device 200 may dump a part of the first parity check data PD1 of the first data D1 as a part of the second parity check data PD2d to the first latch 251. Here, the control logic circuit 240 may generate parity check data GPD based on the reliability information of the first memory area 230_1d and the first user data UD1, and may provide the generated parity check data GPD as a part of the second parity check data PD2d to the second latch 252. The data dumped to the first latch 251 may be referred to as the first latched data LD1d, and the data dumped to the second latch 252 may be referred to as the second latched data LD2d. In addition, the second parity check data PD2d may include a first parity check area P1 and a fourth parity check area P4b. The fourth parity check area P4b of the second parity check data PD2d may be data generated based on the first user data UD1. The fourth parity check area P4b may have a size different from the sizes of the first parity check area P1 to the third parity check area P3. For example, the size of the fourth parity check area P4b may be larger than the size of the first parity check area P1 and smaller than the size of the second parity check area P2.

[0094] The memory device 200 may provide the data latched in the first latch 251 and the second latch 252 to the I / O circuit 260 as read data RDd, and the I / O circuit 260 may provide the read data RDd to the memory controller 100. The memory controller 100 may perform an error correction operation on the first user data UD1 based on the second parity check data PD2d. In an embodiment, the memory controller 100 may first perform an error correction operation based on the first parity check area P1 included in the second parity check data PD2d. Here, if the error correction operation based on the first parity check area P1 fails, the memory controller 100 may perform an error correction operation based on the fourth parity check area P4b included in the second parity check data PD2d.

[0095] Although not shown in Figures 6A to 6D , in an embodiment, the memory device 200 may dump the parity check areas P1 to P3 to the first latch 251.

[0096] Figure 7 is a block diagram showing a write operation of the memory device 200 according to an embodiment. Reference may be made to Figures 1 to 3 and Figure 5 to describe Figure 7 , and redundant descriptions may be omitted.

[0097] Figure 7 This is a diagram for explaining how the memory controller 100 writes data to the memory device 200.

[0098] The memory controller 100 may receive write data from a host. The write data may be divided into user data and parity data. The memory controller 100 may determine the format and size of the parity data according to the reliability information of the memory area in which the write data is to be stored through the parity controller 160.

[0099] In an embodiment, it is assumed that the memory controller 100 stores the first write data WD1 in the first memory area 230_1. When the reliability information about the first memory area 230_1 is the first write reference value, the parity controller 160 may determine that the format of the first parity data PWD1, which is the parity data of the first write data WD1, is the first write format. When the format of the first parity data PWD1 is the first write format, the first parity data PWD1 may be divided into a first parity area P1, a second parity area P2, and a third parity area P3. Dividing the first parity data PWD1 into three areas may be an example, and the first parity data PWD1 may also be divided into fewer or more parity areas. However, when the format of the parity data is the first write format, the parity data PWD1 may be divided into more parity areas than when the format of the parity data is the second write format.

[0100] In an embodiment, it is assumed that the memory controller 100 stores the second write data WD2 in the first memory area 230_1. When the reliability information about the first memory area 230_1 is the second write reference value, the parity controller 160 may determine that the format of the second parity data PWD2, which is the parity data of the second write data WD2, is the second write format. When the format of the second parity data PWD2 is the second write format, the second parity data PWD2 may be divided into a first parity area P1 and a second parity area P2. Specifically, when the format of the parity data is the second write format, the parity data may be divided into fewer parity areas than when the format of the parity data is the first write format. Dividing the parity area of the second parity data PWD2 into the first parity area P1 and the second parity area P2 may be an example, and the parity area of the second parity data PWD2 may be divided into the first parity area P1 and a third parity area P3, or may be divided into the second parity area P2 and the third parity area P3. Alternatively, the second parity data PWD2 may include only one of the parity areas among the first parity area P1 to the third parity area P3.

[0101] In an embodiment, when compared with the first parity data PWD1, the blank area in the second parity data PWD2 may not be filled with separate dummy data and may remain blank. The size of the second parity data PWD2 may be smaller than the size of the first parity data PWD1. Accordingly, the I / O occupancy rate of writing the second write data WD2 based on the second parity data PWD2 into the memory device 200 of the memory device 200 may be lower than the I / O occupancy rate of writing the first write data WD1 based on the first parity data PWD1 into the memory device 200 of the memory device 200, and thus the performance of the storage device 10 may be improved.

[0102] Figure 8 FIG. is a diagram illustrating a system 2000 to which a storage device according to an embodiment is applied.

[0103] Reference Figure 8 , Figure 8 , the system 2000 may basically be a mobile system, such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 8 , the system 2000 is not limited to a mobile system and may also include a personal computer, a laptop computer, a server, a media player, or an automotive device (such as a navigation device).

[0104] Reference Figure 8 The system 2000 may include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b, and may additionally include an image capture device 2410, a user input device 2420, sensors 2430, a communication device 2440, a display 2450, speakers 2460, a power supply device 2470, and a connection interface 2480.

[0105] The main processor 2100 may control the overall operation of the system 2000, and in detail, the main processor 2100 may control the operations of the other components forming the system 2000. The main processor 2100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0106] The main processor 2100 may include one or more CPU cores 2110, and may also include a controller 2120 for controlling the memories 2200a and 2200b and / or the storage devices 2300a and 2300b. According to an embodiment, the main processor 2100 may also include an accelerator 2130, which is a dedicated circuit for high-speed data calculation such as artificial intelligence (AI) data calculation. Such an accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may also be implemented as a separate chip physically independent of the other parts of the main processor 2100.

[0107] The memories 2200a and 2200b may be used as the main memory devices of the system 2000, and may include volatile memories such as SRAM and / or DRAM, but may also include non-volatile memories such as flash memory, PRAM, and / or RRAM. The memories 2200a and 2200b may also be implemented in the same package as the package of the main processor 2100.

[0108] The storage devices 2300a and 2300b can function as non-volatile storage devices that store data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memories 2200a and 2200b. The storage devices 2300a and 2300b can include storage controllers 2310a and 2310b and non-volatile memories (NVMs) 2320a and 2320b that store data under the control of the storage controllers 2310a and 2310b. The NVMs 2320a and 2320b can include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but can also include other types of non-volatile memories such as PRAM and / or RRAM.

[0109] The storage devices 2300a and 2300b can be included in the system 2000 while being physically separated from the main processor 2100, or can be implemented in the same package as the package of the main processor 2100. In addition, the storage devices 2300a and 2300b can have the form of, for example, a solid state device (SSD) or a memory card, and can be removably coupled to other components of the system 2000 through an interface such as the connection interface 2480 described below. The storage devices 2300a and 2300b can be devices that apply standard protocols such as UFS, eMMC, or NVMe, but are not limited thereto. In an embodiment, each of the storage devices 2300a and 2300b can be implemented using Figure 1 the storage device 10. In an embodiment, each of the storage controllers 2310a and 2310b can be implemented using Figure 1 the memory controller 100. In an embodiment, each of the NVMs 2320a and 2320b and each of the memories 2200a and 2200b can be implemented using Figure 1 、 Figures 3 to 5 and Figures 6A to 6D one of the memory devices 200 in

[0110] The image capture device 2410 can capture still images or moving images, and can be a camera, a video camera, and / or a webcam.

[0111] The user input device 2420 can receive various types of data inputs from a user of the system 2000, and can include a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0112] The sensor 2430 can detect various types of physical quantities that can be obtained from outside the system 2000 and convert the detected physical quantities into electrical signals. The sensor 2430 can include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0113] The communication device 2440 can send signals to other devices outside the system 2000 and receive signals from other devices outside the system 2000 according to various communication protocols. The communication device 2440 can be implemented to include an antenna, a transceiver, and / or a modem.

[0114] The display 2450 and the speaker 2460 can function as output devices that respectively output visual information and auditory information to the user of the system 2000.

[0115] The power supply device 2470 can appropriately convert the power supplied from a battery (not shown) built in the system 2000 and / or an external power supply and supply power to each component of the system 2000.

[0116] The connection interface 2480 can provide a connection between the system 2000 and an external device connected to the system 2000 and can exchange data with the system 2000. The connection interface 2480 can be implemented in various interface methods, such as ATA, SATA, external SATA (e-SATA), SCSI, SAS, PCI and PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, embedded universal flash storage (UFS), CompactFlash (CF) card, etc.

[0117] Figure 9 is a block diagram showing an example of applying a memory controller according to an embodiment to the SSD system 2000.

[0118] Reference Figure 9 , the SSD system 3000 can include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector and can receive power through a power connector. The SSD 3200 can include an SSD controller 3210, an auxiliary power supply 3220, and memory devices (e.g., flash memories) 3230, 3240, and 3250. Here, the SSD 3200 can be implemented using Figure 1 of the storage device 10. In an embodiment, the SSD controller 3210 can be implemented using Figure 1 of the memory controller 100. In an embodiment, each of the memory devices 3230, 3240, and 3250 can be implemented usingFigure 1 , Figures 3 to 5 and Figures 6A to 6D implemented by one of the memory devices 200.

[0119] Although the inventive concept has been specifically shown and described with reference to embodiments of the present invention, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A memory device, comprising: a memory cell array, the memory cell array comprising a first memory area storing first data; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; as well as a control logic circuit configured to receive parity adjustment information from an external device and control the operation of the memory cell array, wherein the first data includes first user data and first parity data including parity bits generated based on the first user data, and The control logic circuit is configured to adjust the size of the first parity data based on the parity adjustment information, and dump the adjusted first parity data to the first latch.

2. The memory device according to claim 1, wherein: The memory cell array further includes a second memory area storing second data, The second data includes second user data and second parity data including a parity bit generated based on the second user data, and A size of the first parity data is different from a size of the second parity data.

3. The memory device according to claim 1, wherein: The first parity data includes a first parity area, a second parity area, and a third parity area, the first parity area, the second parity area, and the third parity area have sizes different from each other, and The size of the first parity data dumped to the first latch varies depending on the format of the first parity data indicated by the parity adjustment information.

4. The memory device according to claim 3, wherein: When the format of the first parity data is a first format, the memory device is configured to cause the control logic circuit to dump at least parity bits included in the third parity area to the first latch.

5. The memory device according to claim 3, wherein: When the format of the first parity data is a second format, the memory device is configured to cause the control logic circuit to at least dump parity bits included in at least one of the first parity region and a second parity region to the first latch.

6. The memory device according to claim 3, wherein: The control logic circuit further includes a parity generator configured to generate third parity data different from the first parity data, and The page buffer also includes a second latch configured to store the third parity data generated from the parity generator.

7. The memory device according to claim 6, wherein: When the format of the first parity data is a third format, the memory device is configured such that: the control logic circuit generates the third parity data through the parity generator, and the control logic circuit dumps the third parity data to the second latch.

8. The memory device according to claim 7, wherein: The third parity data is generated based on the first user data.

9. The memory device according to claim 1, wherein: The parity adjustment information includes information indicating a format and a size of parity data associated with the first memory region, and is generated based on reliability information of the first memory region.

10. The memory device according to claim 6, further comprising: An input / output circuit is configured to transmit data stored in the first latch and the second latch to the external device in response to a read command received from the external device.

11. A memory controller, the memory controller comprising: an error correction code engine configured to generate parity data corresponding to user data received from a host; as well as a parity controller including reliability information including information indicating the reliability of a plurality of memory regions included in the memory device, wherein the parity controller adjusts the size of the parity data based on the reliability information corresponding to the memory area in the plurality of memory areas where the user data is to be stored, and The memory controller is configured to write the adjusted parity data and the user data to the memory device.

12. The memory controller of claim 11, wherein: The parity data includes at least one parity area, The memory controller is configured such that: when the reliability information is a first write reference value, the parity controller determines the format of the parity data as a first write format, and when the reliability information is a second write reference value, determines the format of the parity data as a second write format, and When the format of the parity data is the second writing format, the number of parity areas included in the parity data is smaller than the number of parity areas when the format of the parity data is the first writing format.

13. The memory controller according to claim 11, wherein: The memory controller also includes a memory interface circuit configured to send the parity data and the user data to the memory device.

14. A storage device, comprising: a memory device configured to adjust a size of first parity data based on parity adjustment information and output the first parity data having the adjusted size; as well as a memory controller configured to control the operation of the memory device, Wherein, the memory device comprises: a memory cell array, the memory cell array comprising a plurality of memory regions; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; and a control logic circuit configured to receive the parity adjustment information from the memory controller and control the operation of the memory cell array, and Wherein, the memory controller comprises: a parity controller, the parity controller including reliability information including information indicating the reliability of the plurality of memory regions included in the memory device, and the parity controller being configured to: determining a format and a size of the first parity data based on the reliability information of a memory area where user data corresponding to the first parity data is to be stored, and The parity adjustment information indicating the determined format and size of the first parity data is provided to the memory device.

15. The storage device according to claim 14, wherein: The first parity data includes a first parity area, a second parity area, and a third parity area, the first parity area, the second parity area, and the third parity area have sizes different from each other, and The size of the first parity data dumped to the first latch varies according to a format of the first parity data indicated by the parity adjustment information.

16. The storage device according to claim 15, wherein: When the format of the first parity data is a first format, the storage apparatus is configured to cause the memory device to dump at least parity bits included in the third parity area to the first latch.

17. The storage device according to claim 15, wherein: When the format of the first parity data is a second format, the storage apparatus is configured to cause the memory device to at least dump parity bits included in at least one of the first parity region and the second parity region to the first latch.

18. The storage device according to claim 15, wherein: The control logic circuit further includes a parity generator configured to generate second parity data different from the first parity data, and The page buffer includes a second latch configured to store the second parity data generated from the parity generator.

19. The storage device according to claim 18, wherein: When the format of the first parity data is a third format, the storage apparatus is configured such that: the memory device generates the second parity data through the parity generator, and the memory device dumps the second parity data to the second latch.

20. The storage device according to claim 19, wherein: Second parity data is generated based on the user data.

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