Topological construction method for beta-type ultrahigh-gain boost converter

Abstract

The invention relates to the technical field of power electronics, in particular to a topological construction method of a beta-type ultrahigh-gain boost converter. The method comprises the following steps: acquiring a target voltage transformation parameter, and determining a main circuit type corresponding to a main circuit and a boost order corresponding to a boost circuit according to the target voltage transformation parameter; determining a boost circuit type corresponding to the boost circuit and a circuit connection strategy according to the boost order; and according to a circuit connection strategy, connecting a main body circuit corresponding to the main body circuit type and a boost circuit corresponding to the boost circuit type to obtain a converter corresponding to the target voltage conversion parameter. By the adoption of the scheme, systematic converter topology construction can be achieved, and the development efficiency of the converter is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to a topology construction method of a β-type ultra-high gain boost converter. Background Art

[0002] Today, photovoltaic power generation technology has been widely used in people's daily lives and in combination with other technologies. Taking most DC power conversion devices used in distributed photovoltaic power generation systems as an example, the input side of distributed photovoltaic power generation technology is that the solar photovoltaic array can output DC power with a voltage level of 20 to 40V, and through the boost DC converter, it can output DC power with a voltage level of 400V, and then realize grid-connected operation through the inverter. For this system, the boost DC converter plays a core role in connecting the upper and lower parts. However, the converters currently used lack a systematic topological construction method, and can only be developed according to the needs, with low development efficiency. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first objective of the present disclosure is to propose a β-type ultra-high gain boost converter topology construction method to achieve a systematic converter topology construction and improve the converter development efficiency.

[0005] The second objective of the present disclosure is to provide a β-type ultra-high gain boost converter topology construction device.

[0006] A third objective of the present disclosure is to provide an electronic device.

[0007] A fourth objective of the present disclosure is to provide a computer-readable storage medium.

[0008] A fifth object of the present disclosure is to provide a computer program product.

[0009] To achieve the above-mentioned purpose, the first embodiment of the present disclosure proposes a β-type ultra-high gain boost converter topology construction method, including:

[0010] Acquire a target voltage conversion parameter, and determine a main circuit type corresponding to the main circuit and a boost order corresponding to the boost circuit according to the target voltage conversion parameter;

[0011] Determining a boost circuit type and a circuit connection strategy corresponding to the boost circuit according to the boost order;

[0012] Connect the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type according to the circuit connection strategy to obtain the converter corresponding to the target voltage conversion parameter.

[0013] Optionally, after constructing the digital model corresponding to the target object, the method further includes:

[0014] In response to receiving a display instruction for the digital model, determine the instruction type corresponding to the display instruction;

[0015] Display the digital model according to the display strategy corresponding to the instruction type.

[0016] Optionally, the boost circuit type includes at least one of the following:

[0017] Positive gain type;

[0018] Negative gain type.

[0019] Optionally, the positive gain type includes a positive odd multiple gain type, and the boost circuit corresponding to the positive odd multiple gain type includes 2a - 1 first capacitors and 2a - 1 first diodes, where a is a positive integer; among them,

[0020] The 2a - 1 first diodes are connected in series in sequence, and the negative electrode of the (2a - 2)-th first diode is connected to the positive electrode of the (2a - 1)-th first diode;

[0021] For the 2a - 1 first capacitors, the connection point between the first end of the first capacitor at an even position and the positive electrode of the first diode at the first position is the first end of the boost circuit corresponding to the positive odd multiple gain type. The second end of the second first capacitor is respectively connected to the negative electrode of the second first diode and the positive electrode of the third first diode. The second end of the (2a - 2)-th first capacitor is respectively connected to the negative electrode of the (2a - 2)-th first diode and the positive electrode of the (2a - 1)-th first diode;

[0022] For the 2a - 1 first capacitors, the first capacitors at odd positions are connected in series in sequence, and the first end of the first capacitor at the first position is the second end of the boost circuit corresponding to the positive odd multiple gain type. The second end of the (2a - 3)-th first capacitor is respectively connected to the first end of the (2a - 1)-th first capacitor, the negative electrode of the (2a - 3)-th first diode, and the positive electrode of the (2a - 2)-th first diode. The connection point between the second end of the (2a - 1)-th first capacitor and the negative electrode of the (2a - 1)-th first diode is the third end of the boost circuit corresponding to the positive odd multiple gain type;

[0023] When the input voltage of the boost circuit corresponding to the positive odd - multiple gain type is at a positive level, all the first diodes at odd positions are in the conducting state, and all the first diodes at even positions are in the cut - off state;

[0024] When the input voltage of the boost circuit corresponding to the positive odd - multiple gain type is at a negative level, all the first diodes at odd positions are in the cut - off state, and all the first diodes at even positions are in the conducting state;

[0025] The output voltage of the boost circuit corresponding to the positive odd - multiple gain type is constantly 2a - 1 times the positive level.

[0026] Optionally, the positive gain type includes the positive even - multiple gain type. The boost circuit corresponding to the positive even - multiple gain type includes 2b second capacitors and 2b second diodes, where b is a positive integer; among them,

[0027] The 2b second diodes are connected in series in sequence, and the negative electrode of the (2b - 1)-th second diode is connected to the positive electrode of the 2b - th second diode;

[0028] The connection point between the first ends of the second capacitors at odd positions among the 2b second capacitors is the first end of the boost circuit corresponding to the positive even - multiple gain type. The second end of the first second capacitor is respectively connected to the negative electrode of the first second diode and the positive electrode of the second second diode. The second end of the (2b - 1)-th second capacitor is respectively connected to the negative electrode of the (2b - 1)-th second diode and the positive electrode of the 2b - th second diode;

[0029] The second capacitors at even positions among the 2b second capacitors are connected in series in sequence, and the connection point between the first end of the second second capacitor and the positive electrode of the first second diode is the second end of the boost circuit corresponding to the positive even - multiple gain type. The second end of the (2b - 2)-th second capacitor is respectively connected to the first end of the 2b - th second capacitor, the negative electrode of the (2b - 2)-th second diode, and the positive electrode of the (2b - 1)-th second diode. The connection point between the second end of the 2b - th second capacitor and the negative electrode of the 2b - th second diode is the third end of the boost circuit corresponding to the positive even - multiple gain type;

[0030] When the input voltage of the boost circuit corresponding to the positive even - multiple gain type is at a positive level, all the second diodes at odd positions are in the cut - off state, and all the second diodes at even positions are in the conducting state;

[0031] When the input voltage of the boost circuit corresponding to the positive even - multiple gain type is at a negative level, all the second diodes at odd positions are in the conducting state, and all the second diodes at even positions are in the cut - off state;

[0032] The output voltage of the boost circuit corresponding to the forward even - multiple gain type is constantly 2b times the positive level.

[0033] Optionally, the reverse gain type includes a reverse odd - multiple gain type. The boost circuit corresponding to the reverse odd - multiple gain type includes 2c - 1 third capacitors and 2c - 1 third diodes, where c is a positive integer. Among them,

[0034] The 2c - 1 third diodes are connected in series in sequence, and the anode of the (2c - 2) - th third diode is connected to the cathode of the (2c - 1) - th third diode.

[0035] For the third capacitors at even positions among the 2c - 1 third capacitors, the connection point between the first end of the third capacitor and the cathode of the first third diode is the first end of the boost circuit corresponding to the reverse odd - multiple gain type. The second end of the second third capacitor is respectively connected to the anode of the second third diode and the cathode of the third third diode. The second end of the (2c - 2) - th third capacitor is respectively connected to the anode of the (2c - 2) - th third diode and the cathode of the (2c - 1) - th third diode.

[0036] For the third capacitors at odd positions among the 2c - 1 third capacitors, they are connected in series in sequence. The first end of the first third capacitor is the second end of the boost circuit corresponding to the reverse odd - multiple gain type. The second end of the (2c - 3) - th third capacitor is respectively connected to the first end of the (2c - 1) - th third capacitor, the anode of the (2c - 3) - th third diode, and the cathode of the (2c - 2) - th third diode. The connection point between the second end of the (2c - 1) - th third capacitor and the anode of the (2c - 1) - th third diode is the third end of the boost circuit corresponding to the reverse odd - multiple gain type.

[0037] When the input voltage of the boost circuit corresponding to the reverse odd - multiple gain type is a positive level, all the third diodes at odd positions are in the cut - off state, and all the third diodes at even positions are in the conducting state.

[0038] When the input voltage of the boost circuit corresponding to the reverse odd - multiple gain type is a negative level, all the third diodes at odd positions are in the conducting state, and all the third diodes at even positions are in the cut - off state.

[0039] The output voltage of the boost circuit corresponding to the reverse odd - multiple gain type is constantly (2c - 1) times the negative level.

[0040] Optionally, the reverse gain type includes a reverse even - multiple gain type. The boost circuit corresponding to the reverse even - multiple gain type includes 2d fourth capacitors and 2d fourth diodes, where d is a positive integer. Among them,

[0041] The 2d fourth diodes are connected in series in turn, and the positive electrode of the (2d - 1)-th fourth diode is connected to the negative electrode of the 2d-th fourth diode;

[0042] The connection point between the first ends of the fourth capacitors at odd positions among the 2d fourth capacitors is the first end of the boost circuit corresponding to the reverse even multiple gain type. The second end of the first fourth capacitor is respectively connected to the positive electrode of the first fourth diode and the negative electrode of the second fourth diode. The second end of the (2d - 1)-th fourth capacitor is respectively connected to the positive electrode of the (2d - 1)-th fourth diode and the negative electrode of the 2d-th fourth diode;

[0043] The fourth capacitors at even positions among the 2d fourth capacitors are connected in series in turn, and the connection point between the first end of the second fourth capacitor and the negative electrode of the first fourth diode is the second end of the boost circuit corresponding to the reverse even multiple gain type. The second end of the (2d - 2)-th fourth capacitor is respectively connected to the first end of the 2d-th fourth capacitor, the positive electrode of the (2d - 2)-th fourth diode, and the negative electrode of the (2d - 1)-th fourth diode. The connection point between the second end of the 2d-th fourth capacitor and the positive electrode of the 2d-th fourth diode is the third end of the boost circuit corresponding to the reverse even multiple gain type;

[0044] When the input voltage of the boost circuit corresponding to the reverse even multiple gain type is at a positive level, all the fourth diodes at odd positions are in the conducting state, and all the fourth diodes at even positions are in the cutoff state;

[0045] When the input voltage of the boost circuit corresponding to the reverse even multiple gain type is at a negative level, all the fourth diodes at odd positions are in the cutoff state, and all the fourth diodes at even positions are in the conducting state;

[0046] The output voltage of the boost circuit corresponding to the reverse even multiple gain type is constantly 2d times the negative level.

[0047] Optionally, the converter further includes an input source and a load. When the boost circuit type includes the forward gain type or the reverse gain type, the circuit connection strategy includes at least one of the following:

[0048] The positive electrode of the input source is connected to the first end of the main circuit. The negative electrode of the input source is respectively connected to the third end of the main circuit, the second end of the boost circuit, and the second end of the load. The second end of the main circuit is connected to the first end of the boost circuit. The third end of the boost circuit is connected to the first end of the load;

[0049] The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the second end of the main circuit, the second end of the boost circuit, and the second end of the load, the third end of the main circuit is connected to the first end of the boost circuit, and the third end of the boost circuit is connected to the first end of the load.

[0050] Optionally, the converter further includes an input source and a load. When the boost circuit types include the forward gain type and the reverse gain type, the circuit connection strategy includes at least one of the following:

[0051] The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the third end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit. The second end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit. The third end of the forward gain boost circuit is connected to the first end of the load, and the third end of the reverse gain boost circuit is connected to the second end of the load, where the forward gain boost circuit is the boost circuit corresponding to the forward gain type, and the reverse gain boost circuit is the boost circuit corresponding to the reverse gain type;

[0052] The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the second end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit. The third end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit. The third end of the forward gain boost circuit is connected to the second end of the load, and the third end of the reverse gain boost circuit is connected to the first end of the load;

[0053] The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the third end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit. The second end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit. The third end of the forward gain boost circuit is connected to the second end of the load, and the third end of the reverse gain boost circuit is connected to the first end of the load;

[0054] The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the second end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit. The third end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit. The third end of the forward gain boost circuit is connected to the first end of the load, and the third end of the reverse gain boost circuit is connected to the second end of the load.

[0055] Optionally, when the target voltage conversion parameter is N / (1 - 2D), the main circuit selects a bipolar β-type circuit, where N is the boost order and D is the duty cycle in the steady state condition of the converter.

[0056] Optionally, the bipolar β-type circuit includes an inductor, a first switching transistor, a second switching transistor, a fifth diode, a sixth diode, and a fifth capacitor; wherein,

[0057] The first end of the inductor is the first end of the bipolar β-type circuit. The connection point between the second end of the inductor, the drain of the first switching transistor, and the anode of the fifth diode is the second end of the bipolar β-type circuit. The source of the first switching transistor is respectively connected to the first end of the fifth capacitor and the anode of the sixth diode. The cathode of the fifth diode is respectively connected to the second end of the fifth capacitor and the drain of the second switching transistor. The connection point between the source of the second switching transistor and the cathode of the sixth diode is the third end of the bipolar β-type circuit.

[0058] To achieve the above object, the second aspect embodiment of the present disclosure proposes a β-type ultra-high gain boost converter topology device, including:

[0059] A parameter acquisition unit, configured to acquire a target voltage conversion parameter, and determine the corresponding main circuit type of the main circuit and the boost order of the boost circuit according to the target voltage conversion parameter;

[0060] A strategy determination unit, configured to determine the corresponding boost circuit type of the boost circuit and the circuit connection strategy according to the boost order;

[0061] A circuit connection unit, configured to connect the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type according to the circuit connection strategy to obtain a converter corresponding to the target voltage conversion parameter.

[0062] To achieve the above object, the third aspect embodiment of the present disclosure proposes an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0063] The memory stores computer-executable instructions;

[0064] The processor executes the computer-executable instructions stored in the memory to implement the method shown in any one of the foregoing first aspects.

[0065] To achieve the above object, an embodiment of the fourth aspect of the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method shown in any one of the foregoing first aspects.

[0066] To achieve the above object, an embodiment of the fifth aspect of the present disclosure provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method shown in any one of the foregoing first aspects.

[0067] In summary, the method, device, equipment, and storage medium provided by the present disclosure obtain target voltage conversion parameters, and determine the main circuit type corresponding to the main circuit and the boost order corresponding to the boost circuit according to the target voltage conversion parameters; according to the boost order, determine the boost circuit type corresponding to the boost circuit and the circuit connection strategy; according to the circuit connection strategy, connect the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type to obtain a converter corresponding to the target voltage conversion parameters. Therefore, a systematic converter topology construction can be realized, and the development efficiency of the converter can be improved.

[0068] Additional aspects and advantages of the present disclosure will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The above and / or additional aspects and advantages of the present disclosure will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0070] Figure 1 is a schematic flowchart of a method for constructing a β-type ultra-high gain boost converter topology provided by an embodiment of the present disclosure;

[0071] Figure 2 is a schematic structural diagram of a boost circuit corresponding to a positive odd multiple gain type provided by an embodiment of the present disclosure;

[0072] Figure 3 is a theoretical waveform diagram of the operation of a boost circuit provided by an embodiment of the present disclosure;

[0073] Figure 4 is a schematic structural diagram of a boost circuit corresponding to a positive even multiple gain type provided by an embodiment of the present disclosure;

[0074] Figure 5 Schematic diagram of a boost circuit corresponding to a reverse odd - multiple gain type provided by an embodiment of the present disclosure;

[0075] Figure 6 Schematic diagram of a boost circuit corresponding to a reverse even - multiple gain type provided by an embodiment of the present disclosure;

[0076] Figure 7 Schematic diagram of the connection of the first circuit connection strategy provided by an embodiment of the present disclosure;

[0077] Figure 8 Schematic diagram of the connection of the second circuit connection strategy provided by an embodiment of the present disclosure;

[0078] Figure 9 Schematic diagram of the connection of the third circuit connection strategy provided by an embodiment of the present disclosure;

[0079] Figure 10 Schematic diagram of the connection of the fourth circuit connection strategy provided by an embodiment of the present disclosure;

[0080] Figure 11 Schematic diagram of the connection of the fifth circuit connection strategy provided by an embodiment of the present disclosure;

[0081] Figure 12 Schematic diagram of the connection of the sixth circuit connection strategy provided by an embodiment of the present disclosure;

[0082] Figure 13 Schematic diagram of the structure of a bipolar β - type circuit provided by an embodiment of the present disclosure;

[0083] Figure 14 Schematic diagram of the simulation result of a bipolar β - type circuit provided by an embodiment of the present disclosure;

[0084] Figure 15 Schematic diagram of the simulation result of a boost circuit provided by an embodiment of the present disclosure;

[0085] Figure 16 Schematic diagram of the simulation result of a Bβ - 4BC provided by an embodiment of the present disclosure;

[0086] Figure 17 Schematic diagram of the structure of a β - type ultra - high - gain boost converter topology construction device provided by an embodiment of the present disclosure. Detailed implementation manners

[0087] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, but should not be construed as limiting the present disclosure.

[0088] The present disclosure will be described in detail below in conjunction with specific embodiments.

[0089] As Figure 1 shown, Figure 1 FIG. is a schematic flowchart of a method for constructing a β-type ultra-high gain boost converter topology provided by an embodiment of the present disclosure. This method can be implemented depending on a computer program and can run on a device for constructing a β-type ultra-high gain boost converter topology. The computer program can be integrated into an application or run as an independent tool-type application.

[0090] Among them, the β-type ultra-high gain boost converter topology construction device can be an electronic device having the function of constructing a β-type ultra-high gain boost converter topology.

[0091] Among them, the method for constructing a β-type ultra-high gain boost converter topology can be executed by an electronic device.

[0092] Exemplarily, the method for constructing a β-type ultra-high gain boost converter topology includes the following steps:

[0093] S101, obtain target voltage conversion parameters, and determine the corresponding main circuit type of the main circuit and the boost order of the boost circuit according to the target voltage conversion parameters;

[0094] According to some embodiments, the target voltage conversion parameters refer to the voltage conversion parameters of the converter to be designed.

[0095] In some embodiments, the converter includes an input source, a main circuit, a boost circuit, and a load. Among them, the input source is used to provide an input voltage, the main circuit refers to the circuit in the converter responsible for transforming the voltage waveform of the input voltage; the boost circuit refers to the circuit in the converter responsible for performing voltage amplitude transformation.

[0096] According to some embodiments, the main circuit type refers to the type of the main circuit. The main circuit type includes but is not limited to bipolar β-type, capacitor clamped type based on interleaved parallel connection, parallel resonant bidirectional isolation type, etc.

[0097] In some embodiments, the boost order refers to the multiple of voltage amplitude transformation that the boost circuit needs to perform.

[0098] For example, when the target voltage conversion parameter is N / (1 - 2D), the main circuit can select a bipolar β-type circuit (Bβ). Here, N is the boost order, and D is the duty cycle in the steady state of the converter.

[0099] S102. Determine the boost circuit type and circuit connection strategy corresponding to the boost circuit according to the boost order.

[0100] According to some embodiments, the boost circuit type includes, but is not limited to, at least one of the following:

[0101] Forward gain type;

[0102] Reverse gain type.

[0103] That is to say, the boost circuit type corresponding to the boost circuit can be a forward gain type, a reverse gain type, a hybrid type combining a forward gain type and a reverse gain type, or a hybrid type combining a reverse gain type and a forward gain type.

[0104] In some embodiments, the boost circuit of the above type can be an ultra-high gain boost circuit with a gain greater than a gain threshold. Here, the gain threshold does not specifically refer to a certain fixed threshold.

[0105] It should be noted that by adopting at least one of the forward gain type and the reverse gain type as the boost circuit type, the flexibility of the converter topology can be improved. Secondly, by selecting an ultra-high gain boost circuit, a converter with a high gain and a wide voltage gain range can be constructed.

[0106] According to some embodiments, the forward gain type includes, but is not limited to, a forward odd multiple gain type, a forward even multiple gain type, etc. Among them, when the boost circuit of the forward odd multiple gain type adopts an ultra-high gain boost circuit, a forward odd multiple ultra-high gain circuit (FOUGC) can be obtained, and when the boost circuit of the forward even multiple gain type adopts an ultra-high gain boost circuit, a forward even multiple ultra-high gain circuit (FEUGC) can be obtained.

[0107] In some embodiments, Figure 2 This is a schematic structural diagram of a boost circuit corresponding to a forward odd multiple gain type provided by an embodiment of the present disclosure. As Figure 2 shown, the boost circuit corresponding to the forward odd multiple gain type includes 2a - 1 first capacitors C FO and 2a - 1 first diodes DFO ; wherein,

[0108] The 2a - 1 first diodes D FO are connected in series in sequence, and the negative electrode of the (2a - 2)th first diode D FO_2a-2 is connected to the positive electrode of the (2a - 1)th first diode D FO_2a-1 ;

[0109] The 2a - 1 first capacitors C FO Among them, for the first capacitors C at even positions FO The connection point between the first end of the first capacitor C and the positive electrode of the first diode D at the first position FO_1 is the first end of the boost circuit corresponding to the positive odd - multiple gain type (as shown at port 1 in Figure 2 ), the second end of the second first capacitor C FO_2 is respectively connected to the negative electrode of the second first diode D FO_2 , the positive electrode of the third first diode D FO_3 , the second end of the (2a - 2)th first capacitor C FO_2a-2 is respectively connected to the negative electrode of the (2a - 2)th first diode D FO_2a-2 , the positive electrode of the (2a - 1)th first diode D FO_2a-1 ;

[0110] The 2a - 1 first capacitors C FO Among them, for the first capacitors C at odd positions FO are connected in series in sequence, and the first end of the first capacitor C at the first position FO_1 is the second end of the boost circuit corresponding to the positive odd - multiple gain type (as shown at port 2 in Figure 2 ), the second end of the (2a - 3)th first capacitor C FO_2a-3 is respectively connected to the first end of the (2a - 1)th first capacitor C FO_2a-1 , the negative electrode of the (2a - 3)th first diode D FO_2a-3 , the positive electrode of the (2a - 2)th first diode D FO_2a-2 , the connection point between the second end of the (2a - 1)th first capacitor C FO_2a-1 and the negative electrode of the (2a - 1)th first diode D FO_2a-1 is the third end of the boost circuit corresponding to the positive odd - multiple gain type (as shown at port 3 in Figure 2 ).

[0111] It should be noted that Figure 3 is the theoretical waveform diagram of the operation of a boost circuit provided by an embodiment of the present disclosure. As Figure 3 shown, when the input voltage v input of the boost circuit corresponding to the positive odd - multiple gain type is at a positive level V i , all the first diodes D at odd positionsFO_2a-1 is in the conducting state, and all the first diodes D at even positions FO_2a are in the cut-off state; when the input voltage v of the boost circuit corresponding to the positive odd multiple gain type input is the negative level -V i , all the first diodes D at odd positions FO_2a-1 are in the cut-off state, and all the first diodes D at even positions FO_2a are in the conducting state. Therefore, when the input voltage v input is two-level (V i , -V i ), combining the above two cases, the output voltage of the boost circuit corresponding to the positive odd multiple gain type can be constantly 2a - 1 times of V i , that is to say, it can output any odd multiple of V i . Wherein, a is a positive integer, and the value of a can be determined by the boost order N. When 2a - 1 is greater than the gain threshold, the boost circuit corresponding to the positive odd multiple gain type is FOUGC.

[0112] In some embodiments, Figure 4 is a schematic structural diagram of a boost circuit corresponding to a positive even multiple gain type provided by an embodiment of the present disclosure. As Figure 4 shown, the boost circuit corresponding to the positive even multiple gain type includes 2b second capacitors C FE and 2b second diodes D FE ; wherein,

[0113] the 2b second diodes D FE are connected in series in sequence, and the negative electrode of the (2b - 1)-th second diode D FE_2b-1 is connected to the positive electrode of the 2b-th second diode D FE_2b ;

[0114] for the 2b second capacitors C FE , the connection point between the first ends of the second capacitors C at odd positions FE is the first end of the boost circuit corresponding to the positive even multiple gain type (as shown by port 1 in Figure 4 ), the second end of the first second capacitor C FE_1 is respectively connected to the negative electrode of the first second diode D FE_1 , the positive electrode of the second second diode D FE_2 , the second end of the (2b - 1)-th second capacitor C FE_2b-1 is respectively connected to the negative electrode of the (2b - 1)-th second diode D FE_2b-1 , the positive electrode of the 2b-th second diode D FE_2b ;

[0115] the 2b second capacitors CFE The second capacitor C of the even digits FE are connected in series in sequence, and the first terminal of the second capacitor C of the 2nd digit FE_2 and the connection point between the positive electrode of the second diode D of the 1st digit FE_1 is the second terminal of the boost circuit corresponding to the positive even multiple gain type (as shown in port 2 in Figure 4 ), the second terminals of the second capacitors C of the 2b - 2nd digits FE_2b-2 are respectively connected to the first terminal of the second capacitor C of the 2bth digit FE_2b , the negative electrode of the second diode D of the 2b - 2nd digit FE_2b-2 , the positive electrode of the second diode D of the 2b - 1st digit FE_2b-1 , the second terminal of the second capacitor C of the 2bth digit FE_2b and the connection point between the negative electrode of the second diode D of the 2bth digit FE_2b is the third terminal of the boost circuit corresponding to the positive even multiple gain type (as shown in port 3 in Figure 4 ).

[0116] It should be noted that, as shown in Figure 3 , when the input voltage v of the boost circuit corresponding to the positive even multiple gain type input is the positive level V i , all the second diodes D of the odd digits FE_2b-1 are in the cut-off state, and all the second diodes D of the even digits FE_2b are in the conducting state; when the input voltage v of the boost circuit corresponding to the positive even multiple gain type input is the negative level -V i , all the second diodes D of the odd digits FE_2b-1 are in the conducting state, and all the second diodes D of the even digits FE_2b are in the cut-off state. Therefore, when the input voltage v input is two-level (V i , -V i ), combining the above two situations, the output voltage of the boost circuit corresponding to the positive even multiple gain type is always 2b times of V i , that is to say, it can output any even multiple of V i . Among them, b is a positive integer, and the value of b can be determined by the boost order N. When 2b is greater than the gain threshold, the boost circuit corresponding to the positive even multiple gain type is FEUGC.

[0117] It is easy to understand that when the positive odd multiple gain type and the positive even multiple gain type are combined, the boost circuit corresponding to the positive gain type can output any integer multiple of V i . Therefore, the flexibility of the converter topology structure can be improved, and a converter with high gain and wide voltage gain range can be constructed.

[0118] According to some embodiments, the reverse gain type includes but is not limited to reverse odd times gain type, reverse even times gain type, etc. Among them, when the boost circuit of the reverse odd times gain type adopts an ultra-high gain boost circuit, a reverse odd times ultra-high gain circuit (ROUGC) can be obtained, and when the boost circuit of the reverse even times gain type adopts an ultra-high gain boost circuit, a reverse even times ultra-high gain circuit (REUGC) can be obtained.

[0119] In some embodiments, Figure 5 FIG. is a schematic structural diagram of a boost circuit corresponding to a reverse odd times gain type provided by an embodiment of the present disclosure. As Figure 5 shown, the boost circuit corresponding to the reverse odd times gain type includes 2c - 1 third capacitors C RO and 2c - 1 third diodes D RO ; where

[0120] the 2c - 1 third diodes D RO are connected in series in sequence, and the positive electrode of the (2c - 2)-th third diode D RO_2c-2 is connected to the negative electrode of the (2c - 1)-th third diode D RO_2c-1 ;

[0121] for the 2c - 1 third capacitors C RO among them, the first end of the third capacitor C at the even position RO is connected to the connection point between the negative electrode of the first third diode D RO_1 and is the first end of the boost circuit corresponding to the reverse odd times gain type (as shown at port 4 in Figure 5 ), the second end of the second third capacitor C RO_2 is respectively connected to the positive electrode of the second third diode D RO_2 and the negative electrode of the third third diode D RO_3 , the second end of the (2c - 2)-th third capacitor C RO_2c-2 is respectively connected to the positive electrode of the (2c - 2)-th third diode D RO_2c-2 and the negative electrode of the (2c - 1)-th third diode D RO_2c-1 ;

[0122] for the 2c - 1 third capacitors C RO among them, the third capacitors C at the odd positions RO are connected in series in sequence, and the first end of the first third capacitor C RO_1 is the second end of the boost circuit corresponding to the reverse odd times gain type (as shown inFigure 5 As shown at the middle port 5, the second end of the third capacitor C at the 2c - 3 position RO_2c-3 is respectively connected to the first end of the third capacitor C at the 2c - 1 position RO_2c-1 , the positive electrode of the third diode D at the 2c - 3 position RO_2c-3 , the negative electrode of the third diode D at the 2c - 2 position RO_2c-2 . The second end of the third capacitor C at the 2c - 1 position RO_2c-1 is connected to the connection point between the second end and the positive electrode of the third diode D at the 2c - 1 position RO_2c-1 to be the third end of the boost circuit corresponding to the reverse odd - multiple gain type (as shown at port 6 in Figure 5 ).

[0123] It should be noted that, as Figure 3 shown, when the input voltage v input of the boost circuit corresponding to the reverse odd - multiple gain type is at the positive level V i , all the third diodes D at the odd positions RO_2c-1 are in the cut - off state, and all the third diodes D at the even positions RO_2c are in the conducting state; when the input voltage v input of the boost circuit corresponding to the reverse odd - multiple gain type is at the negative level -V i , all the third diodes D at the odd positions RO_2c-1 are in the conducting state, and all the third diodes D at the even positions RO_2c are in the cut - off state. Therefore, when the input voltage v input is at two levels (V i , -V i ), combining the above two cases, the output voltage of the boost circuit corresponding to the reverse odd - multiple gain type is constantly 2c - 1 times of -V i , that is to say, it can output any odd multiple of -V i . Wherein, c is a positive integer, and the value of c can be determined by the boost order N. When 2c - 1 is greater than the gain threshold, the boost circuit corresponding to the reverse odd - multiple gain type is ROUGC.

[0124] In some embodiments Figure 6 , the following is a schematic structural diagram of a boost circuit corresponding to a reverse even - multiple gain type provided by an embodiment of the present disclosure. As Figure 6 shown, the boost circuit corresponding to the reverse even - multiple gain type includes 2d fourth capacitors C RE and 2d fourth diodes D RE ; wherein

[0125] the 2d fourth diodes D RE are connected in series in sequence, and the fourth diode D at the 2d - 1 position RE_2d-1The positive electrode of RE_2d is connected to the negative electrode of the fourth diode D at the 2d-th position;

[0126] The connection point between the first ends of the fourth capacitors C at the odd positions among the 2d fourth capacitors C RE is the first end of the boost circuit corresponding to the reverse even multiple gain type (as shown at port 4 in RE ), the second end of the fourth capacitor C at the 1st position Figure 6 is respectively connected to the positive electrode of the fourth diode D at the 1st position RE_1 and the negative electrode of the fourth diode D at the 2nd position RE_1 , the second end of the fourth capacitor C at the 2d - 1-th position RE_2 is respectively connected to the positive electrode of the fourth diode D at the 2d - 1-th position RE_2d-1 and the negative electrode of the fourth diode D at the 2d-th position RE_2d-1 ; RE_2d The fourth capacitors C at the even positions among the 2d fourth capacitors C

[0127] are connected in series in sequence, and the connection point between the first end of the fourth capacitor C at the 2nd position RE and the negative electrode of the fourth diode D at the 1st position RE is the second end of the boost circuit corresponding to the reverse even multiple gain type (as shown at port 5 in RE_2 ), the second end of the fourth capacitor C at the 2d - 2-th position RE_1 is respectively connected to the first end of the fourth capacitor C at the 2d-th position Figure 6 , the positive electrode of the fourth diode D at the 2d - 2-th position RE_2d-2 and the negative electrode of the fourth diode D at the 2d - 1-th position RE_2d , the connection point between the second end of the fourth capacitor C at the 2d-th position RE_2d-2 and the positive electrode of the fourth diode D at the 2d - 1-th position RE_2d-1 is the third end of the boost circuit corresponding to the reverse even multiple gain type (as shown at port 6 in RE_2d ). RE_2d It should be noted that, as shown in Figure 6 , when the input voltage v

[0128] of the boost circuit corresponding to the reverse even multiple gain type is at the positive level V Figure 3 , all the fourth diodes D at the odd positions input are in the conducting state, and all the fourth diodes D at the even positions i are in the cut-off state; when the input voltage v RE_2d-1 of the boost circuit corresponding to the reverse even multiple gain type is at the negative level -V RE_2d , all the fourth diodes D at the odd positions input are in the cut-off state, and all the fourth diodes D at the even positions i are in the conducting state; RE_2d-1 ​RE_2d is in the conducting state. Therefore, when the input voltage is v input is two-level (V i , -V i ), combining the above two cases, the output voltage of the boost circuit corresponding to this reverse even multiple gain type is constantly 2d times -V i , that is to say, it can output any even multiple of -V i . Wherein, d is a positive integer, and the value of d can be determined by the boost order N. When 2d is greater than the gain threshold, the boost circuit corresponding to this reverse even multiple gain type is REUGC.

[0129] It is easy to understand that when the reverse odd multiple gain type and the reverse even multiple gain type are combined, the boost circuit corresponding to the reverse gain type can output any integer multiple of -V i . Therefore, the flexibility of the converter topology can be improved, and a converter with high gain and wide voltage gain range can be constructed.

[0130] According to some embodiments, when the boost circuit type includes a forward gain type or a reverse gain type, the circuit connection strategy includes at least one of the following:

[0131] As Figure 7 shown, the positive pole of the input source is connected to the first end of the main circuit (such as Figure 7 port A shown in Figure 7 ), the negative pole of the input source is respectively connected to the third end of the main circuit (such as Figure 7 port C shown in Figure 7 ), the second end of the boost circuit (such as Figure 7 port 2 shown in Figure 7 ) and the second end of the load (such as Figure 7 port E shown in Figure 7 ), the second end of the main circuit (such as

[0132] port B shown in Figure 8 ) is connected to the first end of the boost circuit (such as Figure 8 port 1 shown in Figure 8 ), the third end of the boost circuit (such as Figure 8 port 3 shown in Figure 8 ) is connected to the first end of the load (such as Figure 8 port C shown in Figure 8is connected to the first terminal of the boost circuit (as shown by port 1 in Figure 8 ), and the third terminal of the boost circuit (as shown by port 3 in Figure 8 ) is connected to the first terminal of the load (as shown by port D in

[0133] According to some embodiments, when the boost circuit types include a forward gain type and a reverse gain type, the circuit connection strategy includes at least one of the following:

[0134] As Figure 9 shown, the positive pole of the input source is connected to the first terminal of the main circuit (as shown by port A in Figure 9 ), the negative pole of the input source is respectively connected to the third terminal of the main circuit (as shown by port C in Figure 9 ), the second terminal of the forward gain boost circuit (as shown by port 2 in Figure 9 ), the second terminal of the reverse gain boost circuit (as shown by port 5 in Figure 9 ), the second terminal of the main circuit (as shown by port B in Figure 9 ) is respectively connected to the first terminal of the forward gain boost circuit (as shown by port 1 in Figure 9 ) and the first terminal of the reverse gain boost circuit (as shown by port 4 in Figure 9 ), the third terminal of the forward gain boost circuit (as shown by port 3 in Figure 9 ) is connected to the first terminal of the load (as shown by port D in Figure 9 ), the third terminal of the reverse gain boost circuit (as shown by port 6 in Figure 9 ) is connected to the second terminal of the load (as shown by port E in Figure 9 ), where the forward gain boost circuit is the boost circuit corresponding to the forward gain type, and the reverse gain boost circuit is the boost circuit corresponding to the reverse gain type;

[0135] As Figure 10 shown, the positive pole of the input source is connected to the first terminal of the main circuit (as shown by port A in Figure 10 ), the negative pole of the input source is respectively connected to the second terminal of the main circuit (as shown by port B in Figure 10 ), the second terminal of the forward gain boost circuit (as shown by port 2 in Figure 10 ) and the second terminal of the reverse gain boost circuit (as shown by port 5 in Figure 10 ), the third terminal of the main circuit (as shown by port C in Figure 10 ) is respectively connected to the first terminal of the forward gain boost circuit (as shown by port 1 in Figure 10 ), the first terminal of the reverse gain boost circuit (as shown by port 4 in Figure 10 ), the third terminal of the forward gain boost circuit (as shown by port 3 in Figure 10 ) is connected to the second terminal of the load (as shown by port E in Figure 10is connected to the third terminal of the reverse gain boost circuit (such as the port E shown in Figure 10 the port 6 shown in Figure 10 is connected to the first terminal of the load (such as the port D shown in

[0136] such as Figure 11 shown, the positive pole of the input source is connected to the first terminal of the main circuit (such as the port A shown in Figure 11 is connected to the third terminal of the main circuit (such as the port C shown in Figure 11 the port 2 shown in Figure 11 is connected to the second terminal of the forward gain boost circuit (such as the port 5 shown in Figure 11 is connected to the second terminal of the reverse gain boost circuit (such as the port 5 shown in Figure 11 the port B shown in Figure 11 is connected to the first terminal of the forward gain boost circuit (such as the port 1 shown in Figure 11 is connected to the first terminal of the reverse gain boost circuit (such as the port 4 shown in Figure 11 the port 3 shown in Figure 11 is connected to the second terminal of the load (such as the port E shown in Figure 11 the port 6 shown in Figure 11 is connected to the first terminal of the load (such as the port D shown in

[0137] such as Figure 12 shown, the positive pole of the input source is connected to the first terminal of the main circuit (such as the port A shown in Figure 12 is connected to the second terminal of the main circuit (such as the port B shown in Figure 12 is connected to the second terminal of the forward gain boost circuit (such as the port 2 shown in Figure 12 is connected to the second terminal of the reverse gain boost circuit (such as the port 5 shown in Figure 12 is connected to the third terminal of the main circuit (such as the port C shown in Figure 12 is connected to the first terminal of the forward gain boost circuit (such as the port 1 shown in Figure 12 is connected to the first terminal of the reverse gain boost circuit (such as the port 4 shown in Figure 12 is connected to the third terminal of the forward gain boost circuit (such as the port 3 shown in Figure 12 is connected to the first terminal of the load (such as the port D shown in Figure 12 is connected to the third terminal of the reverse gain boost circuit (such as the port 6 shown in Figure 12 is connected to the second terminal of the load (such as the port E shown in Figure 12 is connected to the second terminal of the load (such as the port E shown in

[0138] Among them, such asFigures 7 to 12 As shown, the load can be, for example, a load resistor R L .

[0139] Among them, Figure 9 and Figure 10 In the circuit connection strategy shown, the forward gain boost circuit clamps the reverse gain boost circuit; Figure 11 and Figure 12 In the circuit connection strategy shown, the reverse gain boost circuit clamps the forward gain boost circuit.

[0140] S103. According to the circuit connection strategy, connect the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type to obtain a converter corresponding to the target voltage conversion parameter.

[0141] Taking a scenario as an example, in order to verify the correctness of the converter topology construction method provided in this embodiment, a 4 / (1 - 2D) times boost converter based on bipolar β-type circuit structure (Bβ-4BC) is used as an example for verification. It adopts Figure 9 the connection strategy shown, where the forward gain boost circuit uses double FEUGC and the reverse gain boost circuit uses double REUGC.

[0142] In some embodiments, as Figure 13 shown, the bipolar β-type circuit includes an inductor L, a first switch tube S1, a second switch tube S2, a fifth diode D1, a sixth diode D2, and a fifth capacitor C1; among them,

[0143] The first end of the inductor L is the first end of the bipolar β-type circuit (as shown by port A in Figure 13 ), and the connection point between the second end of the inductor L and the drain of the first switch tube S1 and the positive pole of the fifth diode D1 is the second end of the bipolar β-type circuit (as shown by port B in Figure 13 ). The drain of the first switch tube S1 is respectively connected to the first end of the fifth capacitor C1 and the positive pole of the sixth diode D2. The negative pole of the fifth diode D1 is respectively connected to the second end of the fifth capacitor C1 and the drain of the second switch tube S2. The connection point between the drain of the second switch tube S2 and the negative pole of the sixth diode D2 is the third end of the bipolar β-type circuit (as shown by port C in Figure 13 ).

[0144] It should be noted that when the first switch tube S1 and the second switch tube S2 are in the off state, the output voltage v BC between the second end and the third end of the bipolar β-type circuit has an amplitude of Vi ; When the first switching transistor S1 and the second switching transistor S2 are in the conducting state, the output voltage v between the second and third terminals of the bipolar β-type circuit BC has an amplitude of -V i .

[0145] According to some embodiments, theoretically, the parameters in this Bβ-4BC satisfy the following relational expressions:

[0146] V out = v CFE_2 + (-v CRE_2 ) = 2v C1 + 2v C1 = 4v C1

[0147]

[0148] Among them, V in is the output voltage of the input source, V out is the voltage across the load, V C1 is the steady-state voltage of the fifth capacitor C1, v C1 is the instantaneous voltage of the fifth capacitor C1, v CFE_2 is the voltage of the second capacitor C FE_2 in the second position of the double FEUGC, v CRE_2 is the voltage of the second capacitor C RE_2 in the second position of the double REUGC, v BC represents the voltage at port BC, M B-4BC is the gain of this Bβ-4BC, and D is the duty cycle of the first switching transistor S1 and the second switching transistor S2.

[0149] In some embodiments, the Bβ-4BC is verified by simulation. Among them, Table (1) shows the simulation parameters of the Bβ-4BC.

[0150] Table (1)

[0151] Parameter Name Parameter Label Parameter Value Parameter Name Parameter Label Parameter Value Input Source <![CDATA[V in > 30V Fifth Capacitor C1 80 μF Switching Frequency fs 100 kHz First Capacitor of the First Position in FEUGC <![CDATA[C FE_1 > 20 μF Duty Cycle D 0.35 Second Capacitor of the Second Position in FEUGC <![CDATA[C FE_2 > 20 μF Inductor L 200 μH Third Capacitor of the First Position in REUGC <![CDATA[C RE_1 > 20 μF Output Load <![CDATA[R L > 400 Ω Fourth Capacitor of the Second Position in REUGC <![CDATA[C RE_2 > 20 μF

[0152] The specific calculation processes are as follows respectively:

[0153]

[0154] Among them, P out is the output power across the load.

[0155] In addition, the voltage stresses of the first switching transistor S1, the second switching transistor S2, the fifth diode D1, and the sixth diode D2 are approximately equal to v C1 , that is, V out1 / 4, under the parameters of Table (1), the voltage stress of the first switching tube S1, the second switching tube S2, the fifth diode D1, and the sixth diode D2 is theoretically about 100V. The simulation results are as Figure 14 shown, from v ds_S1 , v ds_S2 , v D1 and v D2 waveforms, it can be obtained that the voltage stress of the first switching tube S1, the second switching tube S2, the fifth diode D1, and the sixth diode D2 is 100V, which is consistent with the theoretical analysis.

[0156] Furthermore, the voltage stress of the diodes in the boost circuit is about 2v C1 , that is, 1 / 2 of V out . Under the parameters of Table (1), the voltage stress of the diodes in the boost circuit is theoretically about 200V. The simulation results are as Figure 15 shown, from v DFE_D1 , v DFE_D2 , v DRE_D1 and v DRE_D2 waveforms, it can be obtained that the voltage stress of the diodes in the boost circuit is 200V, which is consistent with the theoretical analysis.

[0157] Secondly, as Figure 16 shown, under the working condition when the duty cycle D = 0.35, from v out and v in waveforms, its gain can be obtained as 13.3. The gain of this Bβ-4BC is theoretically 13.33. The simulation platform verifies the correctness of the theoretical analysis result, further proving that the Bβ-4BC of this application has the advantages of obtaining high gain at low duty cycle, continuous input current, wide voltage gain range, and low device voltage stress. The boost gain can reach 4 / (1 - 2D), thereby verifying the correctness of the converter topology construction method provided in this embodiment.

[0158] In summary, the method provided in this embodiment obtains the target voltage conversion parameters, determines the corresponding main circuit type of the main circuit and the boost order of the boost circuit according to the target voltage conversion parameters; determines the corresponding boost circuit type and circuit connection strategy of the boost circuit according to the boost order; and connects the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type according to the circuit connection strategy to obtain the converter corresponding to the target voltage conversion parameters. Therefore, systematic converter topology construction can be realized, and the development efficiency of the converter can be improved.

[0159] To implement the above embodiment, the present disclosure also proposes a β-type ultra-high gain boost converter topology construction device.

[0160] As Figure 17As shown, the β-type ultra-high gain boost converter topology device 1700 includes:

[0161] A parameter acquisition unit 1701, configured to acquire target voltage conversion parameters, and determine the corresponding main circuit type of the main circuit and the boost order of the boost circuit according to the target voltage conversion parameters;

[0162] A strategy determination unit 1702, configured to determine the corresponding boost circuit type of the boost circuit and the circuit connection strategy according to the boost order;

[0163] A circuit connection unit 1703, configured to connect the main circuit corresponding to the main circuit type and the boost circuit corresponding to the boost circuit type according to the circuit connection strategy, to obtain a converter corresponding to the target voltage conversion parameters.

[0164] It should be noted that the foregoing explanation of the embodiment of the β-type ultra-high gain boost converter topology construction method is also applicable to the β-type ultra-high gain boost converter topology device of this embodiment, and will not be elaborated here.

[0165] To implement the foregoing embodiments, the present disclosure also provides an electronic device, including: a processor, and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0166] To implement the foregoing embodiments, the present disclosure also provides a computer-readable storage medium, in which computer execution instructions are stored, and when the computer execution instructions are executed by a processor, they are used to implement the method provided in the foregoing embodiments.

[0167] To implement the foregoing embodiments, the present disclosure also provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method provided in the foregoing embodiments.

[0168] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in the present disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0169] It should be noted that personal information from users should be collected for legal and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and signing an agreement / authorization including authorizing the relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others with access to the personal information data comply with their privacy policies and procedures.

[0170] The present disclosure anticipates embodiments that allow users to selectively prevent the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, the risks can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of users.

[0171] In the description of the foregoing embodiments, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0172] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0173] Any process or method description shown in a flowchart or described otherwise herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0174] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0175] It should be understood that various parts of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0176] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0177] In addition, each functional unit in various embodiments of the present disclosure may be integrated into one processing module, may exist separately physically for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0178] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A β-type ultra-high gain boost converter topology construction method, characterized in that: include: Acquire a target voltage conversion parameter, and determine a main circuit type corresponding to the main circuit and a boost order corresponding to the boost circuit according to the target voltage conversion parameter; Determining a boost circuit type and a circuit connection strategy corresponding to the boost circuit according to the boost order; According to the circuit connection strategy, a main circuit corresponding to the main circuit type and a boost circuit corresponding to the boost circuit type are connected to obtain a converter corresponding to the target voltage conversion parameter.

2. The method according to claim 1, characterized in that The boost circuit type includes at least one of the following: Forward gain type; Inverse gain type.

3. The method according to claim 2, characterized in that The forward gain type includes a forward odd-number gain type, and the boost circuit corresponding to the forward odd-number gain type includes 2a-1 first capacitors and 2a-1 first diodes, where a is a positive integer; wherein, The 2a-1 first diodes are connected in series in sequence, and the cathode of the 2a-2 first diode is connected to the anode of the 2a-1 first diode; The connection point between the first end of the even-numbered first capacitor among the 2a-1 first capacitors and the anode of the 1st first diode is the first end of the boost circuit corresponding to the forward odd-numbered gain type, the second end of the 2nd first capacitor is respectively connected to the cathode of the 2nd first diode and the anode of the 3rd first diode, and the second end of the 2a-2nd first capacitor is respectively connected to the cathode of the 2a-2nd first diode and the anode of the 2a-1st first diode; The odd-numbered first capacitors in the 2a-1 first capacitors are connected in series in sequence, and the first end of the first capacitor at the 1st position is the second end of the boost circuit corresponding to the forward odd-numbered gain type, the second end of the first capacitor at the 2a-3th position is respectively connected to the first end of the first capacitor at the 2a-1th position, the cathode of the first diode at the 2a-3th position, and the anode of the first diode at the 2a-2th position, and the connection point between the second end of the first capacitor at the 2a-1th position and the cathode of the first diode at the 2a-1th position is the third end of the boost circuit corresponding to the forward odd-numbered gain type; When the input voltage of the boost circuit corresponding to the forward odd-numbered gain type is at a positive level, the first diodes of all odd-numbered bits are in a conducting state, and the first diodes of all even-numbered bits are in a cut-off state; When the input voltage of the boost circuit corresponding to the forward odd-numbered gain type is at a negative level, the first diodes of all odd-numbered bits are in a cut-off state, and the first diodes of all even-numbered bits are in a conducting state; The output voltage of the boost circuit corresponding to the forward odd-number gain type is always 2a-1 times the positive level.

4. The method according to claim 2, characterized in that: The forward gain type includes a forward even-number gain type, and the boost circuit corresponding to the forward even-number gain type includes 2b second capacitors and 2b second diodes, where b is a positive integer; wherein, The 2b second diodes are connected in series in sequence, and the cathode of the second diode at position 2b-1 is connected to the anode of the second diode at position 2b; The connection point between the first ends of the odd-numbered second capacitors in the 2b second capacitors is the first end of the boost circuit corresponding to the forward even-numbered gain type, the second end of the first second capacitor is respectively connected to the cathode of the first second diode and the anode of the second second diode, and the second end of the 2b-1 second capacitor is respectively connected to the cathode of the 2b-1 second diode and the anode of the 2b second diode; The even-numbered second capacitors in the 2b second capacitors are connected in series in sequence, and the connection point between the first end of the second capacitor at the 2nd position and the anode of the second diode at the 1st position is the second end of the boost circuit corresponding to the forward even-numbered gain type, the second end of the second capacitor at the 2b-2nd position is respectively connected to the first end of the second capacitor at the 2bth position, the cathode of the second diode at the 2b-2nd position, and the anode of the second diode at the 2b-1st position, and the connection point between the second end of the second capacitor at the 2bth position and the cathode of the second diode at the 2bth position is the third end of the boost circuit corresponding to the forward even-numbered gain type; When the input voltage of the boost circuit corresponding to the forward even-numbered gain type is at a positive level, all the second diodes of odd-numbered positions are in a cut-off state, and all the second diodes of even-numbered positions are in a conducting state; When the input voltage of the boost circuit corresponding to the forward even-numbered gain type is at a negative level, all the second diodes of odd-numbered positions are in a conducting state, and all the second diodes of even-numbered positions are in a cut-off state; The output voltage of the boost circuit corresponding to the forward even-multiple gain type is always 2b times the positive level.

5. The method according to claim 2, characterized in that: The reverse gain type includes a reverse odd-number gain type, and the boost circuit corresponding to the reverse odd-number gain type includes 2c-1 third capacitors and 2c-1 third diodes, where c is a positive integer; wherein, The 2c-1 third diodes are connected in series in sequence, and the anode of the 2c-2 third diode is connected to the cathode of the 2c-1 third diode; The connection point between the first end of the even-numbered third capacitor among the 2c-1 third capacitors and the cathode of the 1st third diode is the first end of the boost circuit corresponding to the reverse odd-numbered gain type, the second end of the 2nd third capacitor is respectively connected to the anode of the 2nd third diode and the cathode of the 3rd third diode, and the second end of the 2c-2nd third capacitor is respectively connected to the anode of the 2c-2nd third diode and the cathode of the 2c-1st third diode; The odd-numbered third capacitors in the 2c-1 third capacitors are connected in series in sequence, and the first end of the first third capacitor is the second end of the boost circuit corresponding to the reverse odd-numbered gain type, the second end of the 2c-3 third capacitor is respectively connected to the first end of the 2c-1 third capacitor, the positive electrode of the 2c-3 third diode, and the negative electrode of the 2c-2 third diode, and the connection point between the second end of the 2c-1 third capacitor and the positive electrode of the 2c-1 third diode is the third end of the boost circuit corresponding to the reverse odd-numbered gain type; When the input voltage of the boost circuit corresponding to the reverse odd-number gain type is at a positive level, the third diodes of all odd-numbered bits are in a cut-off state, and the third diodes of all even-numbered bits are in a conducting state; When the input voltage of the boost circuit corresponding to the reverse odd-number gain type is at a negative level, the third diodes of all odd-numbered bits are in a conducting state, and the third diodes of all even-numbered bits are in a cut-off state; The output voltage of the boost circuit corresponding to the reverse odd-number gain type is always 2c-1 times the negative level.

6. The method according to claim 2, characterized in that The reverse gain type includes a reverse even-number gain type, and the boost circuit corresponding to the reverse even-number gain type includes 2d fourth capacitors and 2d fourth diodes, where d is a positive integer; wherein, The 2d fourth diodes are connected in series in sequence, and the anode of the 2d-1th fourth diode is connected to the cathode of the 2dth fourth diode; The connection point between the first ends of the odd-numbered fourth capacitors in the 2d fourth capacitors is the first end of the boost circuit corresponding to the reverse even-numbered gain type, the second end of the first fourth capacitor is respectively connected to the anode of the first fourth diode and the cathode of the second fourth diode, and the second end of the 2d-1 fourth capacitor is respectively connected to the anode of the 2d-1 fourth diode and the cathode of the 2d fourth diode; The even-numbered fourth capacitors among the 2d fourth capacitors are connected in series in sequence, and the connection point between the first end of the 2nd fourth capacitor and the cathode of the 1st fourth diode is the second end of the boost circuit corresponding to the reverse even-numbered gain type, the second end of the 2d-2nd fourth capacitor is respectively connected to the first end of the 2dth fourth capacitor, the anode of the 2d-2nd fourth diode, and the cathode of the 2d-1st fourth diode, and the connection point between the second end of the 2dth fourth capacitor and the anode of the 2dth fourth diode is the third end of the boost circuit corresponding to the reverse even-numbered gain type; When the input voltage of the boost circuit corresponding to the reverse even-numbered gain type is at a positive level, all the fourth diodes of odd-numbered bits are in a conducting state, and all the fourth diodes of even-numbered bits are in a cut-off state; When the input voltage of the boost circuit corresponding to the reverse even-numbered gain type is at a negative level, all the fourth diodes of odd-numbered bits are in a cut-off state, and all the fourth diodes of even-numbered bits are in a conducting state; The output voltage of the boost circuit corresponding to the reverse even-number gain type is always 2d times the negative level.

7. The method according to claim 2, characterized in that The converter further includes an input source and a load, and when the boost circuit type includes the forward gain type or the reverse gain type, the circuit connection strategy includes at least one of the following: The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is connected to the third end of the main circuit, the second end of the boost circuit and the second end of the load respectively, the second end of the main circuit is connected to the first end of the boost circuit, and the third end of the boost circuit is connected to the first end of the load; The positive pole of the input source is connected to the first end of the main circuit, the negative pole of the input source is respectively connected to the second end of the main circuit, the second end of the boost circuit and the second end of the load, the third end of the main circuit is connected to the first end of the boost circuit, and the third end of the boost circuit is connected to the first end of the load.

8. The method according to claim 2, characterized in that: The converter further includes an input source and a load, and when the boost circuit type includes the forward gain type and the reverse gain type, the circuit connection strategy includes at least one of the following: The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the third end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit, the second end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit, the third end of the forward gain boost circuit is connected to the first end of the load, and the third end of the reverse gain boost circuit is connected to the second end of the load, wherein the forward gain boost circuit is a boost circuit corresponding to the forward gain type, and the reverse gain boost circuit is a boost circuit corresponding to the reverse gain type; The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the second end of the main circuit, the second end of the forward gain boost circuit and the second end of the reverse gain boost circuit, the third end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit, the third end of the forward gain boost circuit is connected to the second end of the load, and the third end of the reverse gain boost circuit is connected to the first end of the load; The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the third end of the main circuit, the second end of the forward gain boost circuit, and the second end of the reverse gain boost circuit, the second end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit, the third end of the forward gain boost circuit is connected to the second end of the load, and the third end of the reverse gain boost circuit is connected to the first end of the load; The positive electrode of the input source is connected to the first end of the main circuit, the negative electrode of the input source is respectively connected to the second end of the main circuit, the second end of the forward gain boost circuit and the second end of the reverse gain boost circuit, the third end of the main circuit is respectively connected to the first end of the forward gain boost circuit and the first end of the reverse gain boost circuit, the third end of the forward gain boost circuit is connected to the first end of the load, and the third end of the reverse gain boost circuit is connected to the second end of the load.

9. The method according to claim 1, characterized in that: When the target voltage conversion parameter is N / (1-2D), the main circuit selects a bipolar β-type circuit, wherein N is the boost order and D is the duty cycle of the converter in steady-state operation.

10. The method according to claim 1, characterized in that The bipolar β-type circuit includes an inductor, a first switch tube, a second switch tube, a fifth diode, a sixth diode and a fifth capacitor; wherein, The first end of the inductor is the first end of the bipolar β-type circuit, the connection point between the second end of the inductor and the drain of the first switching tube and the anode of the fifth diode is the second end of the bipolar β-type circuit, the source of the first switching tube is respectively connected to the first end of the fifth capacitor and the anode of the sixth diode, the cathode of the fifth diode is respectively connected to the second end of the fifth capacitor and the drain of the second switching tube, and the connection point between the source of the second switching tube and the cathode of the sixth diode is the third end of the bipolar β-type circuit.

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