Direct current conversion circuit and direct current conversion device

Abstract

A DC conversion circuit and a DC conversion device relate to a power converter. The DC conversion circuit includes a power transmission circuit and a jumper circuit. The power transmission circuit comprises a first branch circuit and a second branch circuit in a first state, and a third branch circuit and a fourth branch circuit in a second state. The first branch circuit and the third branch circuit comprise an inductor L1 and a capacitor CF1, and the second branch circuit and the fourth branch circuit comprise an inductor L2 and a capacitor CF2. The crossover circuit is configured to drive the power transmission circuit to be switched between a first state and a second state in an alternating conduction mode, so that the first branch is charged and the second branch is discharged when the power transmission circuit is in the first state; or when the power transmission circuit is in the second state, the third branch is charged, and the fourth branch is discharged.

Description

Technical Field

[0001] The present invention relates to a power converter, and more particularly to a DC conversion circuit and a DC conversion device. Background Art

[0002] In recent years, with the rapid development of artificial intelligence, CPUs and GPUs require high currents to achieve higher computing capabilities, which poses an important challenge to power management integrated circuits. As power consumption increases, the original 1V power bus has been replaced by a new energy bus with a voltage range from 3V to 5V to reduce the loss of on-board I 2 R. The evolution of distributed power architectures depends on the development of future high-performance, low-power processors. To support this process, the need for innovative power converters is imminent. These converters must achieve high efficiency and high power density while ensuring reliability and be able to operate under a variety of conditions. Summary of the Invention

[0003] The main technical problem to be solved by the present invention is to provide a DC conversion circuit with high efficiency and high power density and its corresponding DC conversion device.

[0004] According to a first aspect, in one embodiment, a DC conversion circuit is provided, comprising:

[0005] A power transmission circuit, the power transmission circuit including a first branch and a second branch in a first state, and a third branch and a fourth branch in a second state; the first branch and the third branch include an inductor L 1 and a capacitor C F1 , the second branch and the fourth branch include an inductor L 2 and a capacitor C F2 ;

[0006] A bridging circuit configured to drive the power transmission circuit to switch between the first state and the second state in an alternating conduction mode, such that in the first state of the power transmission circuit, the first branch is charged and the second branch is discharged; or, in the second state of the power transmission circuit, the third branch is charged and the fourth branch is discharged.

[0007] In one embodiment, the bridging circuit includes switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 and S 7 ;

[0008] The first end of the inductor L 1 is connected to the input voltage, and the inductor L1 The second end of which is connected to capacitor C F1 at its first end, and the second end of said capacitor C F1 is connected to the first end of switch S 6 at its first end, and the second end of said switch S 6 is used to connect to the load of the multi-channel hybrid power conversion device;

[0009] Said switch S 5 has its first end grounded, and the second end of said switch S 5 is connected to the first end of said capacitor C F2 at its first end, and the second end of said capacitor C F2 is connected to the first end of switch S 2 at its first end, and the second end of said switch S 2 is connected to the first end of inductor L 2 at its first end, and the second end of said inductor L 2 is connected to the load of the multi-channel hybrid power conversion device;

[0010] Said inductor L 1 also has its second end connected to the first end of switch S 1 at its first end, and the second end of said switch S 1 is connected to the second end of capacitor C F2 at its second end;

[0011] Said switch S 3 has its first end grounded, and the second end of said switch S 3 is connected to the first end of inductor L 2 at its first end;

[0012] Said switch S 4 has its first end connected to the second end of switch S 5 at its second end, and the second end of said switch S 4 is connected to the second end of inductor L 2 at its second end.

[0013] In one embodiment, in the first state of the power transmission circuit, switch S 2 , switch S 5 and switch S 6 are turned on, and switch S 1 , switch S 3 , switch S 4 and switch S 7 are turned off, so that inductor L 1 , capacitor C F1 and switch S 6 form a first branch, and switch S 5 , capacitor C F2 , switch S 2 and inductor L 2 form a second branch.

[0014] In one embodiment, the power transmission circuit further includes a fifth branch in the second state;

[0015] In the second state of the power transmission circuit, the bridging circuit turns on switches S 1 , switch S 3 , switch S 4 and switch S 7 , and turns off switches S 2 , switch S 5 and switch S 6 to cause inductor L 1 , switch S 1 , capacitor C F2 , and switch S 4 to form a third branch, switch S 3 and inductor L 2 to form a fourth branch, and switch S 7 , capacitor C F1 , capacitor C F2 and switch S 4 to form a fifth branch.

[0016] In one embodiment, the DC conversion circuit further includes capacitor C L and resistor R L . The first end of capacitor C L is connected to the second end of inductor L 2 , and the second end of capacitor C L is grounded; the second end of resistor R L is connected to the second end of inductor L 2 , and the second end of inductor L 2 is grounded.

[0017] According to a second aspect, in one embodiment, a DC conversion device is provided, including:

[0018] A DC conversion circuit, which adopts the DC conversion circuit described in any of the above embodiments;

[0019] A control module, including a clock module and a logic control module, where the clock module is used to generate a driving signal, and the logic control module drives the DC conversion circuit according to the clock signal.

[0020] In one embodiment, the clock module includes a clock generator, a PID controller, a ramp generator, and a duty cycle limiting module;

[0021] The non-inverting input terminal of the PID controller obtains a reference voltage, the inverting input terminal of the PID controller obtains an output voltage, and the output terminal of the PID controller is connected to the duty cycle limiting module;

[0022] The clock generator is connected to the ramp generator for outputting a first clock signal to the ramp generator. The ramp generator converts the first clock signal into a ramp signal and sends it to the duty cycle limiting module;

[0023] The clock generator is also connected to the duty cycle limiting module for outputting a second clock signal to the duty cycle limiting module.

[0024] In one embodiment, the duty cycle limiting module includes a D flip-flop, a first comparator, a second comparator, an OR gate, and an AND gate;

[0025] The input end of the D flip-flop obtains the second clock signal, and the output end of the D flip-flop is connected to the first input end of the OR gate;

[0026] The inverting input end of the first comparator is connected to the output end of the PID controller, the non-inverting input end of the first comparator obtains the ramp signal, the output end of the first comparator is connected to the second input end of the OR gate, and the output end of the OR gate is connected to the first input end of the AND gate;

[0027] The inverting input end of the second comparator obtains the DC level of the set duty cycle, the non-inverting input end of the second comparator obtains the ramp signal, and the output end of the second comparator is connected to the second input end of the AND gate.

[0028] In one embodiment, the DC conversion circuit further includes a capacitor C L and a resistor R L , one end of the capacitor C L is connected to the second end of the inductor L 2 , the second end of the capacitor C L is grounded; one end of the resistor R L is connected to the second end of the inductor L 2 , and the second end of the inductor L 2 is grounded.

[0029] In one embodiment, the DC conversion device further includes a signal generator. The output end of the AND gate is connected to the signal generator. The signal generator is used to generate a conduction signal for the bridging circuit in the DC conversion circuit, and the logic control module controls the DC conversion circuit to switch between a first state and a second state according to the conduction signal.

[0030] In one embodiment, the set duty cycle is 0.7.

[0031] According to the DC conversion circuit and the DC conversion device of the above embodiments, the DC conversion circuit includes a power transmission circuit and a bridging circuit. The power transmission circuit includes a first branch and a second branch in the first state, and a third branch and a fourth branch in the second state. The first branch and the third branch include an inductor L1 and capacitor C F1 The second branch and the fourth branch include an inductor L 2 and capacitor C F2 . The bridging circuit is configured to drive the power transmission circuit to switch between the first state and the second state in an alternating conduction mode. This application utilizes capacitor C F1 and capacitor C F2 as well as two alternately operating inductors to avoid negative voltages that may occur in the circuit, reducing the inductor current ripple in the DC conversion circuit while also reducing the voltage stress on the switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a circuit schematic diagram of a traditional buck converter;

[0033] Figure 2 is a circuit schematic diagram of an inductor - priority buck converter;

[0034] Figure 3 is a circuit schematic diagram of a passive stacked third - order buck converter;

[0035] Figure 4 is for L 2 SC converter;

[0036] Figure 5 is a structural schematic diagram of a DC conversion circuit in an embodiment;

[0037] Figure 6 is a circuit schematic diagram of the DC conversion circuit in the first state in an embodiment;

[0038] Figure 7 is a circuit schematic diagram of the DC conversion circuit in the second state in an embodiment;

[0039] Figure 8 is the steady - state waveform of the DC conversion circuit in an embodiment Figure 1 ;

[0040] Figure 9 is the steady - state waveform of the DC conversion circuit in an embodiment Figure 2 ;

[0041] Figure 10 is a curve graph of the normalized calculation of the V - A index in an embodiment;

[0042] Figure 11 is a circuit schematic diagram of the DC conversion circuit in an embodiment;

[0043] Figure 12 is a structural schematic diagram of a DC conversion device in another embodiment;

[0044] Figure 13 Schematic diagram of the clock module in one embodiment;

[0045] Figure 14 Schematic diagram of the duty cycle limiting module in one embodiment;

[0046] Figure 15 Simulation diagram of the output voltage drop caused by the inductor and the switch on-resistance in one embodiment;

[0047] Figure 16 Schematic diagram of the bootstrap circuit in one embodiment. Detailed implementation manners

[0048] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific implementation manners. Similar elements in different implementation manners adopt related similar element numbers. In the following implementation manners, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid overwhelming the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and general technical knowledge in the art.

[0049] In addition, the features, operations, or characteristics described in the specification can be combined in any appropriate manner to form various implementation manners. At the same time, the steps or actions in the method description can also be reordered or adjusted in an obvious manner by those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment and do not mean that they are necessary sequences, unless it is stated that a certain sequence must be followed.

[0050] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. And the "connection" and "coupling" mentioned in the present application, unless otherwise specified, both include direct and indirect connection (coupling).

[0051] Please refer to Figure 1, in a traditional buck converter, the periodic on and off during switching can cause the input current to be discontinuous. When the switch turns off, the current path is suddenly interrupted, and parasitic inductance will generate high-frequency voltage spikes due to the sudden change in current. These spikes will form common-mode noise through the power bus, and as the common connection path of the system, the low-impedance characteristic of the power bus will conduct electromagnetic interference to other sensitive circuit modules, resulting in a decrease in signal integrity or abnormal functions.

[0052] Please refer to Figure 2 , in the inductance-first topology, a main inductor (input inductor) is connected in series at the input. Its function is similar to a current source, making the input current continuous within the switching cycle. The input inductor supplies power to the load when the switch is on and maintains the current path through a freewheeling diode when it is off, avoiding sudden current changes. The rate of change of the input inductor current is determined by the inductance value and the operating frequency. A larger inductance value can significantly reduce the ripple. Since the input current is continuous and has a small ripple, there is no need for an additional large-capacity input capacitor to smooth the current, thus simplifying the circuit design.

[0053] Please refer to Figure 3 , the passive stacked third-order buck converter (PS3B) has a continuous input current and divides the inductor current into two parts, which can effectively reduce the conduction loss. In addition, this structure can provide a higher voltage conversion ratio. Theoretically, the output voltage V OUT can range from 0 to the input voltage V IN . However, since the two inductor currents rise and fall simultaneously, this results in a large inductor current ripple. In addition, the voltage across the flying capacitor C F is V IN , which causes high voltage stress on the inductor and the switch.

[0054] Please refer to Figure 4 , in the second-order series interleaved converter (L2SC), the two inductors work separately at alternating times to achieve interleaving of the inductor current. The current ripple borne by each inductor is shared, thus reducing the total inductor current ripple. However, it still generates high voltage stress on one of the switches and produces negative voltage.

[0055] Based on the above existing problems, the present application provides a DC conversion circuit and a DC conversion device. By introducing two flying capacitors and two inductors that work alternately, it can effectively avoid the negative voltage problem that may occur in the above topologies. In addition, the circuit topology of the present application further optimizes the overall efficiency by reducing the inductor current ripple, alleviating the voltage stress of the switching tube, and through a refined power management design, and can significantly reduce the conduction loss, and can maintain a high efficiency for 5V to 0.8V.

[0056] Please refer to Figure 5, in one embodiment, a DC conversion circuit 110 is provided. The DC conversion circuit 110 includes a power transmission circuit 111 and a bridging circuit 112.

[0057] In one embodiment, the power transmission circuit 111 includes a first branch and a second branch in a first state, and a third branch and a fourth branch in a second state. Among them, the first branch and the third branch include an inductor L 1 and a capacitor C F1 , the second branch and the fourth branch include an inductor L 2 and a capacitor C F2 .

[0058] In one embodiment, the first branch and the second branch of the power transmission circuit 111 in the first state, and the third branch and the fourth branch in the second state are connected through the bridging circuit 112 to ensure that the power transmission circuit 111 can be switched between the first state and the second state. Specifically, the bridging circuit 112 drives the power transmission circuit 111 to switch between the first state and the second state in an alternating conduction mode, so that when the power transmission circuit 111 is in the first state, the first branch is charged and the second branch is discharged; or, when the power transmission circuit 111 is in the second state, the third branch is discharged and the fourth branch is charged. The switching of the bridging circuit 112 can make the phases of the power transmission circuit 111 in the first state and the second state differ by a preset angle.

[0059] In one embodiment, the second state of the power transmission circuit 111 further includes a fifth branch, and a capacitor C is used in the fifth branch F1 to charge the capacitor C F2 so as to share the output current.

[0060] Specifically, the bridging circuit 112 includes switches S 1 , switches S 2 , switches S 3 , switches S 4 , switches S 5 , switches S 6 and switches S 7 . The first end of the inductor L 1 is connected to the input voltage V IN , the second end of the inductor L 1 is connected to the first end of the capacitor C F1 , the second end of the capacitor C F1 is connected to the first end of the switch S 6 , and the second end of the switch S 6 is used to connect to the load of the DC conversion circuit. The first end of the switch S 5 is grounded, and the second end of the switch S 5 is connected to the capacitor C F2The first end of capacitor C F2 The second end is connected to switch S 2 The first end of switch S 2 The second end is connected to inductor L 2 The first end of inductor L 2 The second end is connected to the load of the DC conversion circuit. Inductor L 1 The second end is also connected to switch S 1 The first end of switch S 1 The second end is connected to capacitor C F2 The second end. Switch S 3 The first end is grounded, switch S 3 The second end is connected to inductor L 2 The first end. Switch S 4 The first end is connected to switch S 5 The second end, switch S 4 The second end is connected to inductor L 2 The second end.

[0061] Please refer to Figure 6 , specifically, the bridging circuit 112 turns on switches S 2 , switch S 5 and switch S 6 , and turns off switches S 1 , switch S 3 , switch S 4 and switch S 7 to make the power transmission circuit 111 in the first state. In this first state, inductor L 1 , capacitor C F1 and switch S 6 are connected to form a first branch; switches S 5 , capacitor C F2 , switches S 2 and inductor L 2 are connected to form a second branch. In this first state of the power transmission circuit 111, inductor L 1 releases energy, and inductor L 2 stores energy.

[0062] Please refer to Figure 7 , the bridging circuit 112 can also turn on switches S 1 , switch S 3 , switch S 4 and switch S 7 , and turn off switches S 2 , switch S 5 and switch S 6 to make the power transmission circuit 111 in the second state. In this second state, inductor L 1 , switch S 1, capacitor C F2 and switch S 4 are connected to form a third branch; switch S 3 and inductor L2 are connected to form a fourth branch. The power transmission circuit 111 stores energy in inductor L1 and releases energy from inductor L2 in this second state. Switch S 7 , capacitor C F1 , capacitor C F2 and switch S 4 are connected to form a fifth branch.

[0063] In one embodiment, the DC conversion circuit further includes capacitor C L and resistor R L . The first end of capacitor C L is connected to the second end of inductor L 2 , and the second end of capacitor C L is grounded; the second end of resistor R L is connected to the second end of inductor L 2 , and the second end of inductor L 2 is grounded.

[0064] In one embodiment, in the power transmission circuit 111, according to the volt-second balance of the inductor and the ampere-second balance of the capacitor, the following can be obtained:

[0065]

[0066]

[0067] where VCR represents the voltage conversion ratio, V OUT represents the output voltage, V IN represents the input voltage, D represents the duty cycle, V CF1 represents the voltage across capacitor C F1 , and V CF2 represents the voltage across capacitor C F2 .

[0068] Capacitor C F1 and capacitor C F2 achieve charge and discharge balance between the first state and the second state, and the following can be obtained:

[0069]

[0070] where I L1 represents the current of inductor L 1 , I L2 represents the current of inductor L 2 , I OUT represents the output current, and D represents the duty cycle.

[0071] According to the above formula, V can be theoretically calculated. OUT The range of IN is from 0 to V

[0072] It should be noted that, please refer to Figure 8 and Figure 9 , where Φ1 and Φ2 respectively represent the first state and the second state. In the DC conversion circuit 110 provided by the present application, the voltage fluctuation at the node V LX1 is reduced to V OUT , and the voltage fluctuation at the node V LX2 is attenuated to V OUT / D. The voltage values calculated by V LX1 and V LX2 prove that the present application can avoid the appearance of negative voltage, improve the overall robustness, that is, the adaptability to external interference and abnormal working conditions.

[0073] In addition, when the inductor current I L1 and the inductor current I L2 gradually rise and fall in different time periods, their current waveforms are interleaved. When one inductor current rises, the other inductor current falls, thereby smoothing the overall current fluctuation. Finally, the current ripple of the entire circuit is significantly reduced. And, the present application interleaves the inductor currents and precisely controls the timing of the switches.

[0074] In order to more clearly show the efficiency and loss of the DC conversion circuit 110 in the present application, the DC conversion circuit 110 provided by the present application is compared with the third-order buck converter (PS3B) and the second-order series interleaved converter (L2SC). Please refer to Table 1.

[0075] Table 1 V-A metrics of PS3B, L2SC and 2L2C topologies

[0076]

[0077] In Table 1, 2L2C represents the DC conversion circuit 110 of the present application. The V-A metric is usually used to measure the conduction loss of the switching device in the power conversion process. It is the relationship between voltage and current, indicating the performance related to loss and conversion efficiency of the conversion device under specific load and voltage conditions. The smaller the V-A, the lower the conduction loss and the total loss, and the higher the conversion efficiency. According to Table 1, the V-A metric of the DC conversion circuit 110 of the present application is smaller than that of PS3B and L 2 SC.

[0078] In order to more clearly explain the low conduction loss of the present application, please refer to Figure 10 , with V IN = 4V, IOUT = 1 A, f = 2 MHz, L 1 = L 2 = L = 470 nH as a prerequisite, the V - A index is calculated by normalizing with the V - A of PS3B. For the 2L2C of this application, when VCR = 0.1, the V - A of 2L2C is 1.83 times smaller than the V - A of PS3B. It can also be observed that when VCR = 0.15, the V - A of 2L2C is 1.11 times smaller than the V - A of L 2 SC, which greatly reduces the conduction loss of the switch. Compared with PS3B and L 2 SC of this application, a smaller V - A means lower total loss and higher peak efficiency.

[0079] Please refer to Figure 11 , the DC conversion circuit 110 is designed using a 180 - nanometer BCD process, where BCD refers to the Bipolar - CMOS - DMOS process, which is a process integrating three different types of transistors (bipolar transistors, CMOS transistors, and DMOS transistors). The switch S2 uses two stacked 2 - VNMOS transistors to withstand a voltage stress of 2V OUT and the switch S3 is configured similarly to withstand V CF2 . The switches S1 and S4 to S7 are all 2 - V NMOS transistors. The inductance values of the two inductors are 470 nH, and the DC resistance (DCR) is 29 mΩ. The flying - capacitor C F1 and C F2 are both 10 μF, and the equivalent series resistance (ESR) is 10 mΩ.

[0080] Please refer to Figure 12 , in another embodiment, a DC conversion device 100 is provided, which includes a DC conversion circuit 110 and a control module 120. The control module 120 includes a clock module 121, a signal generator 122, a logic control module 123, and a bootstrap circuit 124. The clock module 121 is used to generate a driving signal, and the logic control module 123 drives the DC conversion circuit 110 according to the clock signal. Since the DC conversion circuit 110 has been described clearly in the above - mentioned embodiment, it will not be elaborated here.

[0081] Please refer to Figure 13, In one embodiment, the clock module 121 includes a clock generator 1211, a PID controller 1212, a ramp generator 1213, and a duty cycle limiting module 1214. The non-inverting input terminal of the PID controller 1212 obtains a reference voltage, the inverting input terminal of the PID controller 1212 obtains an output voltage, the PID controller 1212 generates an adjustment signal according to the difference between the reference voltage and the output voltage, and the output terminal of the PID controller 1212 is connected to the duty cycle limiting module 1214. The clock generator 1211 is connected to the ramp generator 1213 for outputting a first clock signal to the ramp generator 1213. The ramp generator 1213 converts the first clock signal into a ramp signal and sends it to the duty cycle limiting module 1214. The clock generator 1211 is also connected to the duty cycle limiting module 1214 for outputting a second clock signal to the duty cycle limiting module 1214.

[0082] Please refer to Figure 14 , In one embodiment, the duty cycle limiting module 1214 includes a D flip-flop 12141, a first comparator 12142, a second comparator 12143, an OR gate 12144, and an AND gate 12145.

[0083] In one embodiment, both the D terminal and the CLK terminal of the D flip-flop 12141 are connected to the clock module 124 to obtain a second clock signal, and the output terminal of the D flip-flop 12141 is connected to the first input terminal of the OR gate 12144. The output terminal of the D flip-flop 12141 outputs a signal S D_10 , the output terminal of the D flip-flop 12141 is also connected to a delay module, and the delay module is connected to the reset terminal of the D flip-flop 12141. The clock module 121 generates a second clock signal according to a preset frequency to control the state update of the D flip-flop 12141 to be phase-aligned with the ramp signal.

[0084] In one embodiment, the inverting input terminal of the first comparator 12142 is connected to the output terminal of the PID controller 1212, the non-inverting input terminal of the first comparator 12142 obtains the ramp signal, and the output terminal of the first comparator 12142 outputs a control signal S IN , the output terminal of the first comparator 12142 is connected to the second input terminal of the OR gate 12144, and the output terminal of the OR gate 12144 is connected to the first input terminal of the AND gate 12145.

[0085] In one embodiment, the inverting input terminal of the second comparator 12143 obtains a DC level (V D_70 ) of a set duty cycle, the non-inverting input terminal of the second comparator 12143 obtains the ramp signal, and the output terminal of the second comparator 12143 outputs a square wave signal S D_70, the output terminal of the second comparator 12143 is connected to the second input terminal of the AND gate 12145, and the output terminal of the AND gate is connected to the signal generator 122. The signal generator 122 is used to generate a conduction signal for the bridging circuit 112 in the DC conversion circuit 110. The logic control module 123 controls the DC conversion circuit 110 to switch between the first state and the second state according to the conduction signal.

[0086] In one embodiment, in Figure 14 the duty cycle limiting module 1214, in order to enforce a minimum duty cycle of 0.1, a clock signal S with a duty cycle of 0.1 is generated D_10 . When the rising edge of the control signal S IN of the first comparator 12142 arrives, the D flip-flop 12141 sets the signal S D_10 to high level. The output of the D flip-flop 12141 is fed back to the reset terminal of the D flip-flop 12141 through a delay module, causing the signal S D_10 to turn low after remaining high for 10% of the clock cycle. The control signal S IN and the signal S D_10 are OR-operated through the OR gate 12144 to ensure that the duty cycle remains above 0.1, thus maintaining the stable operation of the circuit. The maximum duty cycle limit is achieved by designing the DC level of the set duty cycle to match the ramp signal. After comparison with the ramp signal, a square wave signal S D_70 with the set duty cycle is generated. The duty cycle limiting module 1214 performs an AND operation on the square wave signal S D_70 and the signal obtained by the OR operation of the OR gate 12144 through the AND gate 12145 to ensure that the duty cycle remains below 0.7, generates the final control signal, and inputs it to the signal generator 122.

[0087] It should be noted that, please refer to Figure 15 , due to the DC resistance of the inductor and the on-resistance of the switch, the relationship between the output voltage V OUT and the duty cycle D is not monotonically increasing. Figure 15 shows the simulation results of the output voltage V IN when the input voltage V IN = 4V, the output currents are 0.3A, 1.0A, and 3.0A, and when the input voltage V OUT = 5V, the output current I OUT = 3A. The descending situation of V IN = 4V and V OUT = 1V, there are two possible duty cycles: at point A, D = 0.5; at point B, D = 0.85; when the duty cycle is between 0 and 0.7, the output voltage V OUTIt is monotonic with the change of the duty cycle. Therefore, the DC level (V D_70 ) obtained at the inverting input terminal of the second comparator 12143 is limited within 0.7.

[0088] Please refer to Figure 16 , in one embodiment, the logic control module 123 is connected to the bootstrap circuit 124, and the bootstrap circuit 124 provides a high voltage to drive the gate of a switching element, such as a MOSFET. The gate of the MOSFET usually requires a driving voltage higher than the input voltage to ensure that the switching element can be fully turned on, and the bootstrap circuit 124 provides the necessary high voltage drive for this purpose. Taking switches S 2 , switch S 4 and switch S 6 as examples, the voltage source directly charges the bootstrap capacitors C b2 , bootstrap capacitor C b4 and bootstrap capacitor C b6 , and provides sufficient voltage for the corresponding switches S 2 , switch S 4 and switch S 6 to turn them on. In the second state, capacitor C b2 provides sufficient voltage for capacitor C b1 to turn it on.

[0089] Those skilled in the art can understand that all or part of the functions of the above-mentioned methods can be implemented in a hardware manner or in a computer program manner. When all or part of the functions in the above-mentioned embodiments are implemented in a computer program manner, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions are realized by a computer executing the program. For example, the program is stored in the memory of the device, and when the processor executes the program in the memory, the above-mentioned all or part of the functions can be realized. In addition, when all or part of the functions in the above-mentioned embodiments are implemented in a computer program manner, the program can also be stored in a storage medium such as a server, another computer, magnetic disk, optical disk, flash drive or mobile hard disk, and is saved to the memory of the local device by downloading or copying, or the system of the local device is updated. When the processor executes the program in the memory, the above-mentioned all or part of the functions in the above-mentioned embodiments can be realized.

[0090] The above uses specific examples to elaborate on the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the technical field to which the present invention belongs, according to the idea of the present invention, several simple deductions, deformations or substitutions can also be made.

Claims

1. A DC conversion circuit, characterized in that, it includes: Power transmission circuit, the power transmission circuit includes a first branch and a second branch in a first state, and a third branch and a fourth branch in a second state; the first branch and the third branch include an inductor L 1 and a capacitor C F1 , the second branch and the fourth branch include an inductor L 2 and a capacitor C F2 ; A bridging circuit configured to drive the power transmission circuit to switch between a first state and a second state in an alternating conduction mode, so that in the first state of the power transmission circuit, the first branch is charged and the second branch is discharged; Or, in the second state of the power transmission circuit, the third branch is charged and the fourth branch is discharged.

2. The DC conversion circuit according to claim 1, characterized in that, The jumper circuit includes switch S 1 , switch S 2 , switch S 3 , switch S 4 , switch S 5 , switch S 6 and switch S 7 ; The inductor L 1 has its first end connected to the input voltage, and the inductor L 1 has its second end connected to the first end of the capacitor C F1 , and the second end of the capacitor C F1 is connected to the first end of the switch S 6 , and the second end of the switch S 6 is used to connect to the load of the multi-channel hybrid power conversion device; The switch S 5 has its first end grounded, and the second end of the switch S 5 is connected to the first end of the capacitor C F2 . The second end of the capacitor C F2 is connected to the first end of the switch S 2 . The second end of the switch S 2 is connected to the first end of the inductor L 2 . The second end of the inductor L 2 is connected to the load of the multi-channel hybrid power conversion device; The inductor L 1 has its second end also connected to the first end of the switch S 1 , and the second end of the switch S 1 is connected to the second end of the capacitor C F2 . The switch S 3 has its first end grounded, and the switch S 3 has its second end connected to the first end of an inductor L 2 . The switch S 4 has its first end connected to the second end of the switch S 5 whose second end is connected to the second end of the inductor L 4 2 2 .

3. The DC conversion circuit according to claim 2, characterized in that, The bypass circuit turns on switches S 2 , S 5 and S 6 , and turns off switches S 1 , S 3 , S 4 and S 7 , so that the inductor L 1 , the capacitor C F1 and the switch S 6 form a first branch, and the switch S 5 , the capacitor C F2 , the switch S 2 and the inductor L 2 form a second branch.

4. The DC conversion circuit according to claim 3, characterized in that, The power transmission circuit further includes a fifth branch in the second state; In the second state of the power transmission circuit, the bridging circuit turns on switches S 1 , switch S 3 , switch S 4 and switch S 7 , and turns off switches S 2 , switch S 5 and switch S 6 , so that inductor L 1 , switch S 1 , capacitor C F2 , and switch S 4 form a third branch, switch S 3 and inductor L 2 form a fourth branch, and switch S 7 , capacitor C F1 , capacitor C F2 and switch S 4 form a fifth branch.

5. The DC conversion circuit according to claim 4, characterized in that, The DC conversion circuit further includes a capacitor C L and a resistor R L . One end of the capacitor C L is connected to the second end of the inductor L 2 , and the second end of the capacitor C L is grounded; the second end of the resistor R L is connected to the second end of the inductor L 2 , and the second end of the inductor L 2 is grounded.

6. A DC conversion device, characterized in that, it includes: A DC conversion circuit that uses the DC conversion circuit according to any one of claims 1-5; A control module including a clock module and a logic control module, where the clock module is used to generate a driving signal, and the logic control module drives the DC conversion circuit according to the clock signal.

7. The DC conversion device according to claim 6, characterized in that, The clock module includes a clock generator, a PID controller, a ramp generator, and a duty cycle limiting module; The non-inverting input terminal of the PID controller obtains a reference voltage, the inverting input terminal of the PID controller obtains an output voltage, and the output terminal of the PID controller is connected to the duty cycle limiting module; The clock generator is connected to the ramp generator and is used to output a first clock signal to the ramp generator. The ramp generator converts the first clock signal into a ramp signal and sends it to the duty cycle limiting module; The clock generator is also connected to the duty cycle limiting module and is used to output a second clock signal to the duty cycle limiting module.

8. The DC conversion device according to claim 7, characterized in that, The duty cycle limiting module includes a D flip-flop, a first comparator, a second comparator, an OR gate, and an AND gate; The input terminal of the D flip-flop obtains the second clock signal, and the output terminal of the D flip-flop is connected to the first input terminal of the OR gate; The inverting input terminal of the first comparator is connected to the output terminal of the PID controller, the non-inverting input terminal of the first comparator obtains the ramp signal, the output terminal of the first comparator is connected to the second input terminal of the OR gate, and the output terminal of the OR gate is connected to the first input terminal of the AND gate; The inverting input terminal of the second comparator obtains a DC level of a set duty cycle, the non-inverting input terminal of the second comparator obtains the ramp signal, and the output terminal of the second comparator is connected to the second input terminal of the AND gate.

9. The DC conversion device according to claim 8, characterized in that, The DC conversion device further includes a signal generator. The output terminal of the AND gate is connected to the signal generator. The signal generator is used to generate a conduction signal for the bridging circuit in the DC conversion circuit, and the logic control module controls the DC conversion circuit to switch between the first state and the second state according to the conduction signal.

10. The DC conversion device according to claim 8, characterized in that, The set duty cycle is 0.7.

Images