Semiconductor structure, radio frequency amplifier, radio frequency front-end module and communication equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a radio frequency amplifier, a radio frequency front-end module and communication equipment, relates to the technical field of electronics, and is used for improving the linearity of the radio frequency amplifier. The radio frequency amplifier includes at least one first transistor and at least one second transistor. A first grid electrode of the first transistor is coupled with a second grid electrode of the second transistor; a first source electrode of the first transistor and a second source electrode of the second transistor are coupled with a reference ground voltage end, and a first drain electrode of the first transistor is coupled with a second drain electrode of the second transistor; the first transistor and the second transistor are connected in parallel equivalently. Wherein the threshold voltage of each first transistor is smaller than the threshold voltage of each second transistor, and the sum of the widths of the grids of at least one first transistor is larger than the sum of the widths of the grids of the second transistors with the same threshold voltage, so that the positive intermodulation signals of the first transistors and the negative intermodulation signals of the second transistors are exactly offset. Therefore, the linearity of the radio frequency amplifier is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and in particular, to a semiconductor structure, a radio frequency amplifier, a radio frequency front-end module, and a communication device. Background Art

[0002] Linearity is one of the important indicators for measuring the performance of a radio frequency amplifier. Taking a low noise amplifier (LNA) as an example, in a radio frequency front-end system, in order to reduce the influence of the signal reception sensitivity of the transmitting channel line on the receiving channel, the linearity of the low noise amplifier should be improved as much as possible. With the advent of the fifth generation mobile communication technology (5G), the requirements for the linearity of the low noise amplifier are getting higher and higher.

[0003] Therefore, the linearity of the radio frequency amplifier is a hot issue that has been continuously concerned by those skilled in the art. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor structure, a radio frequency amplifier, a radio frequency front-end module, and a communication device, which are used to improve the linearity of the radio frequency amplifier.

[0005] To achieve the above object, the present application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a semiconductor structure is provided, which is applied to a radio frequency amplifier; the semiconductor structure includes: a gate pad, a source pad, a drain pad, at least one first transistor, and at least one second transistor. Each first transistor includes a first gate, a first source, and a first drain, and the first gate is coupled to the gate pad, the first source is coupled to the source pad, and the first drain is coupled to the drain pad. Each second transistor includes a second gate, a second source, and a second drain, and the second gate is coupled to the gate pad, the second source is coupled to the source pad, and the second drain is coupled to the drain pad. Wherein, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the total gate width of at least one first transistor is greater than the total gate width of one or more second transistors having the same threshold voltage among at least one second transistor.

[0007] In the embodiments of the present application, the semiconductor structure includes a first transistor and a second transistor. The width of the first gate of the first transistor affects the amplitude of the total signal transmitted by the first transistor (including the main signal and the intermodulation signal), and the width of the second gate of the second transistor affects the amplitude of the total signal transmitted by the second transistor (including the main signal and the intermodulation signal). The threshold voltages of the first transistor and the second transistor affect the phase of the intermodulation signal output by the first transistor and the second transistor under the condition of the same gate voltage. In the present application, both the first gate and the second gate are coupled to the gate pad and receive the same gate bias voltage. Under the same gate bias voltage, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor. Therefore, the first transistor provides a negative intermodulation signal, and the second transistor provides a positive intermodulation signal. Although the positive intermodulation signal provided by the transistor under the same conditions is greater than the negative intermodulation signal, in the present application, the total width of the first gate is always set to be greater than the total width of the second gate, so that the first transistor and the second transistor can output two sets of equal and opposite intermodulation signals to achieve cancellation. Therefore, in the embodiments of the present application, by adopting the design of different threshold voltages, the effect of cancellation can be achieved by providing a same gate bias voltage to the first transistor and the second transistor. The design complexity of the semiconductor structure is low, the structure is simple, and the occupied area is small. Moreover, the stability of the threshold voltage difference is used to control the gate bias state, and the cancellation effect is stable.

[0008] In a possible implementation manner, the semiconductor structure includes a plurality of second transistors; the plurality of second transistors include a first group of second transistors and a second group of second transistors, and the threshold voltages of the second transistors in the first group are different from the threshold voltages of the second transistors in the second group.

[0009] By setting and matching second transistors with a variety of different threshold voltages, a better cancellation effect can be achieved in a certain region, that is, the width of the cancellation effective region is increased. In this way, the tolerance to process fluctuations and environmental conditions such as temperature is improved, so as to improve the process consistency in the production and processing process of the semiconductor structure. In addition, by setting second transistors with different threshold voltages and matching them with different numbers of second transistors, the linearity of the radio frequency amplifier can be improved within the range of the drain current from 40 mA / mm to 120 mA / mm.

[0010] In a possible implementation manner, the number of at least one first transistor is greater than the number of second transistors in the first group and greater than the number of second transistors in the second group. By changing the total gate width of the transistors through the number of transistors, the gate width of each transistor can be reduced, and the process difficulty can be simplified. When the semiconductor structure includes transistors with multiple threshold voltages, there is no inevitable relationship between the numbers of transistors with different threshold voltages.

[0011] In a possible implementation, the threshold voltages of at least one first transistor are the same, the threshold voltages of at least one second transistor are the same, and the number of at least one first transistor is greater than the number of at least one second transistor. By changing the total gate width of the transistors through the number of transistors, the gate width of each transistor can be reduced, simplifying the process difficulty.

[0012] In a possible implementation, the width of the first gate is equal to the width of the second gate. The gate widths of each transistor in the semiconductor structure are equal, and only the number of transistors is used to change the total gate width, with a simple process and high integration.

[0013] In a possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first gate is in Schottky contact with the first barrier layer, and the first source and the first drain are in Ohmic contact with the first barrier layer; the second gate is in Schottky contact with the second barrier layer, and the second source and the second drain are in Ohmic contact with the second barrier layer; the first thickness of the part of the first barrier layer in contact with the first gate is greater than the second thickness of the part of the second barrier layer in contact with the second gate. By changing the thicknesses of the first barrier layer and the second barrier layer, the threshold voltage of the first transistor is made less than the threshold voltage of the second transistor, with a simple process and easy implementation.

[0014] In a possible implementation, the value range of the difference between the first thickness and the second thickness is 1 nm - 6 nm. Setting the difference between the first thickness and the second thickness within the range of 1 nm - 6 nm can meet the requirement of different threshold voltages for the first transistor and the second transistor with a relatively low process difficulty.

[0015] In a possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first gate includes a first Schottky metal layer in Schottky contact with the first barrier layer, and the second gate includes a second Schottky metal layer in Schottky contact with the second barrier layer; the work function of the first Schottky metal layer is less than the work function of the second Schottky metal layer. By changing the materials of the first Schottky metal layer and the second Schottky metal layer, the threshold voltage of the first transistor is made less than the threshold voltage of the second transistor, with a simple process and easy implementation.

[0016] In a possible implementation, the value range of the difference between the work function of the second Schottky metal layer and the work function of the first Schottky metal layer is 0.1 eV - 0.4 eV. By setting the difference in work functions within the range of 0.1 eV - 0.4 eV, the material selection difficulty can be reduced.

[0017] In a possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first barrier layer includes a first gate metal diffusion region in Schottky contact with the first gate, the second barrier layer includes a second gate metal diffusion region in Schottky contact with the second gate, and a third thickness of the first gate metal diffusion region is less than a fourth thickness of the second gate metal diffusion region. By changing the thicknesses of the first gate metal diffusion region and the second gate metal diffusion region, the threshold voltage of the first transistor is made less than that of the second transistor, and the process is simple and easy to implement.

[0018] In a possible implementation, the value range of the difference between the fourth thickness and the third thickness is 1 nm - 6 nm. Setting the difference between the fourth thickness and the third thickness within the range of 1 nm - 6 nm can meet the requirement of different threshold voltages of the first transistor and the second transistor with relatively low process difficulty.

[0019] In a possible implementation, a first gate length of the first gate is less than a second gate length of the second gate. By changing the gate lengths of the first gate and the second gate, the threshold voltage of the first transistor is made less than that of the second transistor, and the process is simple and easy to implement.

[0020] In a possible implementation, the value range of the difference between the second gate length and the first gate length is 0.1 μm - 1 μm. Setting the difference between the second gate length and the first gate length within the range of 0.1 μm - 1 μm can meet the requirement of different threshold voltages of the first transistor and the second transistor with relatively low process difficulty.

[0021] In a possible implementation, the source pad includes a first pad and a second pad, the first source is coupled to the first pad, and the second source is coupled to the second pad. According to the layout requirements of the semiconductor structure, the source pad can be set to be one or more, and multiple pads can be coupled or not coupled to each other. The layout of the semiconductor structure is flexible and has a wide application range.

[0022] In a possible implementation, the semiconductor structure includes a plurality of first transistors and a plurality of second transistors; along a first direction, the first gates of the plurality of first transistors are arranged in sequence, and the first sources and the first drains are arranged alternately, and the first gate is located above the gap between the adjacent first source and the first drain; along the first direction, the second gates of the plurality of second transistors are arranged in sequence, and the second sources and the second drains are arranged alternately, and the second gate is located above the gap between the adjacent second source and the second drain; the first direction is the length direction of the first gate; along the width direction of the first gate, the gate pad and the drain pad are located on both sides of the first transistor. Since the gate pad and the drain pad usually transmit non-zero voltages, therefore, arranging the gate pad and the drain pad on the sides of the regions where the source, drain, and gate are located can reduce the parasitic parameters of the first transistor and the second transistor and optimize the performance of the first transistor and the second transistor.

[0023] In a possible implementation, there is a gap between the plurality of first transistors and the plurality of second transistors, and the source pad is located above the gap.

[0024] By arranging the source pad at the gap between the plurality of first transistors and the plurality of second transistors, the connection portions coupled to the first source and the connection portions coupled to the second source can be connected to the same source pad, reducing the number of source pads. Additionally, to reduce parasitic interference, the size of the above-mentioned gap is larger than the size of the source pad, and the larger gap can reduce the process difficulty of the plurality of first transistors and the plurality of second transistors.

[0025] In a possible implementation, the first pad is located on the side of the first transistor away from the second transistor, and the second pad is located on the side of the second transistor away from the first transistor.

[0026] By arranging the first pad outside the plurality of first transistors and the second pad outside the plurality of second transistors, there is no need to reserve a gap corresponding to the source pad between the plurality of first transistors and the plurality of second transistors, which can reduce the size of the gap between the plurality of first transistors and the plurality of second transistors, so as to reduce the occupied area of the first transistor and the second transistor and improve the integration degree of the semiconductor structure.

[0027] In a possible implementation, a first source and a second source are arranged between adjacent first gates and second gates. Then, the first transistor and the second transistor do not share a source or a drain, and the plurality of first transistors and the plurality of second transistors can be regarded as two independent core modules, reducing the associated difficulty.

[0028] In a possible implementation, a first source electrode is disposed between an adjacent first gate and second gate, and the first source electrode is multiplexed as a second source electrode; the source pad is located on a side of the first transistor away from the second transistor; or, the source pad is located on a side of the second transistor away from the first transistor. Then, the multiple first transistors and multiple second transistors can be regarded as a core module. This arrangement can reduce the gap between the first transistor and the second transistor, reduce the occupied area of the semiconductor structure, and improve the integration degree of the semiconductor structure.

[0029] In a second aspect of the embodiments of the present application, a radio frequency amplifier is provided, including a capacitor and the semiconductor structure according to any one of the first aspect; one end of the capacitor is coupled to the input end of the radio frequency amplifier, and the other end of the capacitor is coupled to the gate pad; the source pad is coupled to the reference ground voltage terminal, and the drain pad is coupled to the output end of the radio frequency amplifier. The radio frequency amplifier provided in the second aspect of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be elaborated here.

[0030] In a third aspect of the embodiments of the present application, a radio frequency front-end module is provided, including: a filter and a low-noise amplifier; the low-noise amplifier includes the radio frequency amplifier of the second aspect; the radio frequency input end of the radio frequency amplifier is coupled to the input end of the filter. The radio frequency front-end module provided in the third aspect of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be elaborated here.

[0031] In a fourth aspect of the embodiments of the present application, a communication device is provided, including the radio frequency front-end module of the third aspect and an antenna, and the antenna is coupled to the radio frequency front-end module. The communication device provided in the fourth aspect of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be elaborated here.

[0032] In a fifth aspect of the embodiments of the present application, a linear cancellation circuit is provided, including: a capacitor, a first end of the capacitor is coupled to the input end, and a second end of the capacitor is coupled to a first node; an amplification module, including at least one first transistor, a first gate of the first transistor is coupled to the first node; a cancellation module, including at least one second transistor, a second gate of the second transistor is coupled to the first node; a first source electrode of the first transistor and a second source electrode of the second transistor are both coupled to the reference ground voltage terminal, a first drain electrode of the first transistor is coupled to a second node, a second drain electrode of the second transistor is coupled to the second node, and the second node is coupled to the output end; wherein, a threshold voltage of the first transistor is less than a threshold voltage of each second transistor, and a total width of first gates of at least one first transistor is greater than a total width of second gates of at least one second transistor. The beneficial effects of the linear cancellation circuit provided in the fifth aspect of the present application are the same as those of the semiconductor structure of the first aspect, which will not be elaborated here. Brief Description of the Drawings

[0033] Figure 1 Schematic structural diagram of a communication device provided by an embodiment of the present application;

[0034] Figure 2 Schematic structural diagram of a radio frequency front-end module provided by an embodiment of the present application;

[0035] Figure 3A Schematic topological structure diagram of a linear cancellation circuit provided by an embodiment of the present application;

[0036] Figure 3B Schematic diagram of cancellation of gm3 and third-order intermodulation provided by an embodiment of the present application;

[0037] Figure 4 Schematic structural diagram of a linear cancellation circuit provided by an embodiment of the present application;

[0038] Figures 5 - 7 Schematic layout diagram of a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 8 and Figure 9 Schematic layout diagram of another semiconductor structure provided by an embodiment of the present application;

[0040] Figures 10 - 13 One provided by an embodiment of the present application Figure 6 Cross-sectional view in the direction of A1 - A2;

[0041] Figure 14 Schematic diagram of cancellation of gm3 and third-order intermodulation provided by an embodiment of the present application;

[0042] Figure 15A Schematic diagram of a method for obtaining OIP3 provided by an embodiment of the present application;

[0043] Figure 15B Schematic diagram of the OIP3 curve of an LNA provided by an embodiment of the present application. Detailed Description of the Embodiments

[0044] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0045] Hereinafter, terms such as "second", "first", etc. are only for convenience of description and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "second", "first", etc. may explicitly or implicitly include one or more such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0046] In addition, in the embodiments of the present application, orientation terms such as "upper", "lower", "left", "right", etc. may include but are not limited to being defined relative to the schematic placement of components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly with the change of the orientation of the components in the drawings.

[0047] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" may be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" may be direct contact or indirect contact through an intermediate medium.

[0048] In the embodiments of the present application, "and / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0049] In the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0050] The technical solution of the present application can be applied to various communication devices including power amplifiers. The communication device can be deployed on land, including indoor or outdoor, handheld or vehicle-mounted. It can also be deployed on water (such as ships, etc.). It can also be deployed in the air (such as airplanes, balloons, satellites, etc.). For example, the channel device can be a terminal, a base station or a routing device. For example, the terminal includes but is not limited to: mobile phone, tablet computer, laptop computer, handheld computer, mobile internet device (MID), wearable device (such as smart watch, smart bracelet, pedometer, etc.), vehicle-mounted device (such as car, bicycle, electric vehicle, airplane, ship, train, high-speed train, etc.), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (such as refrigerator, TV, air conditioner, electricity meter, etc.), smart robot, workshop device, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flying device (such as smart robot, hot air balloon, drone, airplane), radio frequency front-end module, etc.

[0051] Figure 1 FIG. 4 is a schematic structural diagram of a communication device provided by an embodiment of the present application. The communication device is described by taking a mobile phone as an example. The communication device includes: a radio frequency (RF) front-end module 101, a memory 102, a processor 103, a sensor component 104, a multimedia component 105, a power supply component 106, and an input / output interface 107.

[0052] Next, in conjunction with Figure 1 each component of the mobile phone will be specifically introduced:

[0053] The radio frequency front-end module 101 can be used for receiving and transmitting signals during information reception or call. Specifically, after receiving the downlink information of the communication device, it is given to the processor 103 for processing, and the uplink data is sent to the communication device.

[0054] The memory 102 can be used to store data, software programs, and modules. The mobile phone may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0055] The processor 103 is the control center of the mobile phone, connecting various parts of the entire device using various interfaces and lines. By running or executing software programs and / or modules stored in the memory 102, and by invoking data stored in the memory 102, it performs various functions of the mobile phone and processes data, thereby providing overall monitoring of the mobile phone.

[0056] The sensor assembly 104 includes one or more sensors for providing status evaluations of various aspects of the mobile phone. Among them, the sensor assembly 104 may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor. Through the sensor assembly 104, acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the mobile phone can be detected. In addition, the sensor assembly 104 may also include a light sensor for use in imaging applications.

[0057] The multimedia component 105 provides a screen that serves as an output interface between the mobile phone and the user. The screen can be a touch panel, and when the screen is a touch panel, it can be implemented as a touch screen to receive input signals from the user. In addition, the multimedia component 105 also includes at least one camera. For example, the multimedia component 105 includes a front camera and / or a rear camera.

[0058] The power supply component 106 is used to supply power to various components of the mobile phone. The power supply component 106 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the mobile phone.

[0059] The input / output interface 107 provides an interface between the processor 103 and the peripheral interface module. For example, the peripheral interface module can be a keyboard, a mouse, etc.

[0060] Although not shown, the mobile phone may further include an audio component, a communication module, etc. For example, the audio component includes a microphone, a speaker, etc., and the communication module may include one or more of a wireless fidelity (WiFi) module, a Bluetooth module, a near field communication (NFC) module, a global navigation satellite system (GNSS) module, or a frequency modulation (FM) module. Details are not described herein again in the embodiments of the present application. Those skilled in the art can understand that Figure 1 the mobile phone structure shown in

[0061] Figure 2 is not a limitation on the mobile phone and may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0062] Exemplarily, as Figure 2 shown, the RF front-end module 101 includes, but is not limited to, an RF switch, a duplexer, a filter, a power amplifier (PA), a low noise amplifier (LNA), etc.

[0063] The RF front-end module 101 may include a transmitter (TX) channel and a receiver (RX) channel. The transmitter TX channel includes a PA and a filter. The RF input end of the PA is coupled to a digital-to-analog converter (DAC), and the RF output end of the PA is coupled to the input end of the filter. The receiver channel includes an LNA and a filter. The output end of the filter is coupled to the RF input end of the LNA, and the RF output end of the LNA is coupled to an analog-to-digital converter (ADC).

[0064] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of the RF signals of the transmitter TX / receiver RX channels, and the RF switch is responsible for switching between the transmitter TX channel and the receiver RX channel.

[0065] The baseband signal is transmitted to the transmitter TX channel via a transceiver. The transmitter TX channel amplifies the received RF signal and outputs it to an antenna, which then transmits it. The PA is responsible for amplifying the RF signal of the transmitter TX channel, and the filter is responsible for filtering the RF signal of the transmitter TX channel.

[0066] It should be noted that in the case where an electronic device includes multiple antennas, one antenna can correspond to one PA, one antenna can correspond to multiple PAs, or multiple antennas can share one PA. The application scenarios in the related art are all applicable to the embodiments of the present application.

[0067] The receiving channel RX receives the radio frequency signal from the antenna. The radio frequency signal is amplified by the receiving channel RX and then output, and is transmitted to the baseband through the transceiver. The LNA is responsible for amplifying the radio frequency signal of the receiving channel RX, and the filter is responsible for filtering the radio frequency signal of the receiving channel RX.

[0068] Among them, the antenna frequencies applicable to the embodiments of the present application can include relatively high-bandwidth requirements such as the sub6G band. Of course, other bands such as the sub3G band and the WIFI band (such as the 2.4G band, 5G band, 6G band) are also applicable.

[0069] In the radio frequency front-end module 101, the transmitting channel TX and the receiving channel RX operate at different frequencies, and the antenna is shared through a duplexer. In order to reduce the influence of the signal leaked from the transmitting channel TX into the receiving channel RX on the receiving sensitivity, the linearity of the LNA should be improved as much as possible.

[0070] Figure 3A It is a schematic diagram of the topological structure of a linear cancellation circuit provided for the embodiments of the present application.

[0071] In this field, there are various methods to improve the linearity of the LNA. Circuit linear cancellation design is a simple and effective means. As Figure 3A shown, the linear cancellation circuit includes a first transistor M1, a second transistor M2, a first capacitor C1, and a second capacitor C2.

[0072] The first transistor M1 includes a first gate G1, a first source S1, and a first drain D1. The second transistor M2 includes a second gate G2, a second source S2, and a second drain D2. The first capacitor C1 is coupled between the radio frequency input terminal RFi of the LNA and the first gate G1, and the second capacitor C2 is coupled between the radio frequency input terminal RFi of the LNA and the second gate G2. The first source S1 and the second source S2 are both coupled to the reference ground voltage terminal GND. The first drain D1 and the second drain D2 are combined at the node A and then coupled to the radio frequency output terminal RFo of the LNA. The first transistor M1 serves as the main amplification transistor, and the second transistor M2 serves as the cancellation transistor.

[0073] The voltage of the first gate G1 in the first transistor M1 is Vg1, and the voltage of the second gate G2 in the second transistor M2 is Vg2. By controlling the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2, the first transistor M1 and the second transistor M2 can be in different bias states, and the first transistor M1 and the second transistor M2 can generate completely equal and opposite intermodulation signals. The first transistor M1 and the second transistor M2 are connected in parallel, and the intermodulation signals generated by the first transistor M1 and the intermodulation signals generated by the second transistor M2 are cancelled at node A and then output from the RF output terminal RFo.

[0074] Figure 3B It is a schematic diagram of the cancellation of gm3 and third-order intermodulation provided by the embodiment of the present application.

[0075] Taking the third-order intermodulation (IM3) signal as an example, the IM3 signal is related to the third-order transconductance (gm3) of the transistor. As Figure 3B shown, the abscissa is the gate voltage and the ordinate is the third-order transconductance of the transistor. The dotted line is the third-order transconductance curve gm3 of the first transistor M1 M1 , the dashed line is the third-order transconductance curve gm3 of the second transistor M2 M2 , and the solid line is the combined third-order transconductance curve gm3 after the first transistor M1 and the second transistor M2 are combined M1 +gm3 M2 . In the effective cancellation area (usually the range where the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 are located when the LNA is working normally), cancellation is achieved through two equal and opposite third-order intermodulation signals generated by the first transistor M1 and the second transistor M2, resulting in an improvement in the linearity of the LNA.

[0076] Although the design principle of the linear cancellation circuit is relatively simple, there will be many problems in the actual application process. The control of the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 is the most critical link to achieve the cancellation goal.

[0077] As Figure 3A shown, a control method is to externally connect a first voltage source to the first gate G1 and a second voltage source to the second gate G2. The first voltage source and the second voltage source can accurately control the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2. However, two additional power supply voltages need to be added during the application process, which will increase the system cost.

[0078] In another solution, a voltage divider resistor on the chip is used to implement a voltage source to provide two different gate voltages, which can reduce the supply voltage. However, the commonly used resistors on the chip in the current industry have a large temperature coefficient, resulting in a large influence of the design using the voltage divider resistor on the ambient temperature. At high and low temperatures, the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 may deviate from the optimal cancellation operating point, resulting in a possible weakening, disappearance, or even deterioration of the cancellation effect.

[0079] In addition, Figure 3A The actual effect of the linear cancellation design shown is also affected by the process consistency of the two transistors, the first transistor M1 and the second transistor M2, so the device yield is low.

[0080] The embodiments of the present application provide a linear cancellation circuit. The linear cancellation circuit can be applied to the above LNA, and the linear cancellation circuit can also be applied to any radio frequency amplifier that requires high linearity. When the radio frequency amplifier provided by the present application is applied to the communication device provided by the embodiments of the present application, the communication device can be any communication device that requires a radio frequency amplifier with high linearity. The linear cancellation circuit provided by the embodiments of the present application is not limited to being applied to the LNA and the communication device including the LNA. The above is only an example using the LNA.

[0081] Figure 4 FIG. is a schematic structural diagram of a linear cancellation circuit provided by an embodiment of the present application.

[0082] As Figure 4 shown, the linear cancellation circuit includes a capacitor C, an amplification module, and a cancellation module.

[0083] The first end of the capacitor C is coupled to the input end I of the linear cancellation circuit, and the second end of the capacitor C is coupled to the first node A1. The capacitor C is used to block the DC signal and pass the AC signal. The capacitor C can be understood as a DC-blocking capacitor.

[0084] The amplification module includes at least one first transistor M1, Figure 4 Taking the amplification module including one first transistor M1 as an example for illustration. Each first transistor M1 includes a first gate G1, a first source S1, and a first drain D1. The first gate G1 of the first transistor M1 is coupled to the first node A1.

[0085] The cancellation module includes at least one second transistor M2, Figure 4 Taking the amplification module including one second transistor M2 as an example for illustration. Each second transistor M2 includes a second gate G2, a second source S2, and a second drain D2. The second gate G2 of the second transistor M2 is also coupled to the first node A1.

[0086] The first source S1 of the first transistor M1 and the second source S2 of the second transistor M2 are both coupled to the reference ground voltage terminal GND. For example, the first source S1 and the second source S2 are both coupled to the third node A3, and then the third node A3 is coupled to the reference ground voltage terminal GND. Or, for example, the first source S1 is coupled to the reference ground voltage terminal GND, and the second source S2 is also coupled to the reference ground voltage terminal GND, but the first source S1 and the second source S2 are not coupled to each other. In the embodiments of the present application, the case where the first source S1 and the second source S2 are coupled is taken as an example for illustration.

[0087] The first drain D1 of the first transistor M1 is coupled to the second node A2, and the second drain D2 of the second transistor M2 is also coupled to the second node A2. The second node A2 is coupled to the output terminal O of the linear cancellation circuit D.

[0088] That is to say, the first transistor M1 and the second transistor M2 are coupled in parallel, and the first gate G1 of the first transistor M1 and the second gate G2 of the second transistor M2 both receive the bias voltage of the first node A1. That is, the voltage Vg1 of the first gate G1 is equal to the voltage Vg2 of the second gate G2.

[0089] However, the threshold voltage of each first transistor M1 is less than the threshold voltage of each second transistor M2. For example, the difference between the threshold voltage of the first transistor M1 and the threshold voltage of the second transistor M2 is greater than 0.1V.

[0090] For example, the cancellation module includes a plurality of second transistors M2, and the threshold voltages of the plurality of second transistors M2 are equal, and the threshold voltages of the plurality of first transistors M1 are equal. Then, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2.

[0091] Or, for example, the cancellation module includes a plurality of second transistors M2, and the threshold voltages of the plurality of second transistors M2 are not equal, and the threshold voltages of the plurality of first transistors M1 are equal. Then, the threshold voltage of the first transistor M1 is less than the minimum threshold voltage among the plurality of second transistors M2.

[0092] In some embodiments, the amplification module includes a plurality of first transistors M1, and the threshold voltages of the plurality of first transistors M1 are equal. The first transistor M1 and the second transistor M2 in the linear cancellation circuit can be divided by the threshold voltage.

[0093] Moreover, the total width of the first gates G1 of at least one first transistor M1 is greater than the total width of one or more second gates G2 having the same threshold voltage among at least one second transistor M2.

[0094] The total gate width of at least one first transistor M1 (the total width of the first gate G1) can be understood as follows: when the amplification module includes one first transistor M1, the width of the first gate G1 of this first transistor M1 is the total gate width of at least one first transistor M1. When the amplification module includes multiple first transistors M1, the sum of the widths of the multiple first transistors M1 is the total gate width of at least one first transistor M1's first gate G1.

[0095] Similarly, the total gate width of one or more second transistors M2 with the same threshold voltage among at least one second transistor M2 (the total width of the second gate G2) can be understood as follows: when the amplification module includes one second transistor M2, the width of the second gate G2 of this second transistor M2 is the total gate width of one or more second gates G2 with the same threshold voltage. When the amplification module includes multiple second transistors M2 and the threshold voltages of the multiple second transistors M2 are the same, the sum of the widths of the second gates G2 of the multiple second transistors M2 is the total gate width of one or more second gates G2 with the same threshold voltage. The total gate width of at least one first transistor M1's first gate G1 is greater than the total gate width of the second gates G2 of the multiple second transistors M2. When the threshold voltages of the multiple second transistors M2 are different, the sum of the widths of one or more second transistors M2 with the same threshold voltage is the value of one sum of widths, and each value of the sum of widths is less than the total gate width of at least one first transistor M1's first gate G1. However, the sum of multiple sums of widths is not necessarily less than the total gate width of at least one first transistor M1's first gate G1.

[0096] In some embodiments, the first transistor M1 and the second transistor M2 are high electron mobility transistors (HEMTs).

[0097] In other embodiments, the first transistor M1 and the second transistor M2 are pseudomorphic high electron mobility transistors (pHEMTs).

[0098] Next, the structures of the amplification module and the cancellation module in the linear cancellation circuit will be schematically described.

[0099] Figures 5 - 7 This is a layout schematic diagram of a semiconductor structure provided by an embodiment of the present application.

[0100] An embodiment of the present application further provides a semiconductor structure, which can be applied to the radio frequency amplifier provided by the embodiment of the present application. As Figure 5 shown, the semiconductor structure includes a gate pad G, a source pad S, a drain pad D, at least one first transistor M1, and at least one second transistor M2. The gate pad G, the source pad S, the drain pad D, at least one first transistor M1, and at least one second transistor M2 can be disposed on a substrate, for example.

[0101] Figure 5 Taking the semiconductor structure including ten first transistors M1 and six second transistors M2 as an example for illustration, the number of first transistors M1 in the semiconductor structure can be determined by the number of first gates G1, and the number of second transistors M2 in the semiconductor structure can be determined by the number of second gates G2.

[0102] Each first transistor M1 includes a first gate G1, a first source S1, and a first drain D1, and the first gate G1 is coupled to the gate pad G, the first source S1 is coupled to the source pad S, and the first drain D1 is coupled to the drain pad D. Then, in the case where the semiconductor structure includes multiple first transistors M1, the multiple first transistors M1 are equivalent to being coupled in parallel.

[0103] Each second transistor M2 includes a second gate G2, a second source S2, and a second drain D2, and the second gate G2 is coupled to the gate pad G, the second source S2 is coupled to the source pad S, and the second drain D2 is coupled to the drain pad D. Then, in the case where the semiconductor structure includes multiple second transistors M2, the multiple second transistors M2 are equivalent to being coupled in parallel.

[0104] In addition, the first gate G1 and the second gate G2 are both coupled to the gate pad G, the first source S1 and the second source S2 are both coupled to the source pad S, and the first drain D1 and the second drain D2 are both coupled to the drain pad D. Then, it is equivalent that the first transistor M1 and the second transistor M2 are also in a parallel coupling relationship. That is, in the semiconductor structure, at least one first transistor M1 and at least one second transistor M2 are coupled in parallel. If the semiconductor structure includes multiple first transistors M1, the multiple first transistors M1 are also coupled in parallel. If the semiconductor structure includes multiple second transistors M2, the multiple second transistors M2 are also coupled in parallel.

[0105] In some embodiments, the first gate G1 and the second gate G2 are fabricated in the same layer and with the same material in the same process, the first source S1 and the second source S2 are fabricated in the same layer and with the same material in the same process, and the first drain D1 and the second drain D2 are fabricated in the same layer and with the same material in the same process. For example, the first source S1 and the first drain D1 can also be fabricated in the same layer and with the same material in the same process.

[0106] Exemplarily, multiple first gates G1 and multiple second gates G2 are directly connected in parallel at the gate layer, and then transferred to be coupled to the gate pad G through vias. Multiple first drains D1 and multiple second drains D2 are directly connected in parallel at the drain layer, and then transferred to be coupled to the drain pad D through vias. Multiple first sources S1 are transferred to other layers through vias (small squares within the projection of the first source S1), and are coupled to the connection part (dashed box) located in other layers to achieve the parallel connection of multiple first sources S1. Similarly, multiple second sources S2 are transferred to other layers through vias (small squares within the projection of the second source S2), and are coupled to the connection part (dashed box) located in other layers to achieve the parallel connection of multiple second sources S2. Then, the transfer part is transferred to be coupled to the source pad S through vias.

[0107] In some embodiments, such as Figure 5 and Figure 6 shown, the semiconductor structure includes a source pad S, and both the first source S1 and the second source S2 are coupled to the source pad S.

[0108] In other embodiments, such as Figure 7 shown, the source pad S includes a first pad S-1 and a second pad S-2. The first source S1 is coupled to the first pad S-1, and the second source S2 is coupled to the second pad S-2. Of course, although the semiconductor structure includes the first pad S-1 and the second pad S-2, the first source S1 and the second source S2 are not coupled. However, the first pad S-1 and the second pad S-2 are coupled to the voltage terminals that transmit the same signal. Eventually, the first source S1 and the second source S2 receive the same source bias voltage, which is equivalent to the coupling of the first source S1 and the second source S2. For example, both the first pad S-1 and the second pad S-2 are coupled to the reference ground voltage terminal GND. Eventually, both the first source S1 and the second source S2 receive the reference ground voltage of the reference ground voltage terminal GND.

[0109] Of course, the above illustrations of the gate pad G, the source pad S, and the drain pad D are only for illustration and are not subject to any limitations, as long as the first gate G1 and the second gate G2 receive the same gate bias voltage, the first source S1 and the second source S2 receive the same source bias voltage, and the intermodulation signals output by the first drain D1 and the intermodulation signals output by the second drain D2 are cancelled out.

[0110] In some embodiments, such as Figure 5 shown, the first direction X is the direction of the length of the first gate G1, and the first direction X is also the direction from the first source S1 to the first drain D1. The second direction Y is the direction of the width of the first gate G1. The first gate G1 and the second gate G2 are arranged along the first direction X, or in other words, along the first direction X, the first gate G1 and the second gate G2 are adjacent to each other.

[0111] In some embodiments, the semiconductor structure includes a plurality of first transistors M1 and a plurality of second transistors M2.

[0112] The first gates G1 of the plurality of first transistors M1 are arranged in sequence along the first direction X. For example, the plurality of first gates G1 are arranged at equal intervals along the first direction X.

[0113] The second gates G2 of the plurality of second transistors M2 are arranged in sequence along the first direction X. For example, the plurality of second gates G2 are arranged at equal intervals along the first direction X.

[0114] Overall, the plurality of first gates G1 and the plurality of second gates G2 are arranged along the first direction X. It can be, as Figure 5 shown, the plurality of first gates G1 are distributed in the first region, and the plurality of second gates G2 are distributed in the second region. It can also be that the first gates G1 and the second gates G2 are arranged in a mixed manner. This is only an illustration in the embodiments of the present application.

[0115] Please continue to refer to Figure 5 , in some embodiments, along the first direction X, the first source S1 and the first drain D1 are arranged alternately. The projection of the first gate G1 on the substrate is located between the projection of the adjacent first source S1 on the substrate and the projection of the first drain D1 on the substrate. For example, the first gate G1 is located above the gap between the adjacent first source S1 and the first drain D1.

[0116] Then, two adjacent first transistors M1 share the first source S1 or share the first drain D1. The number of the first sources S1 is less than the number of the first gates G1, and the number of the first drains D1 is also less than the number of the first gates G1. Taking Figure 5 as an example, the first first transistor M1 and the second first transistor M1 from left to right share the first drain D1, and the second first transistor M1 and the third first transistor M1 share the first source S1. Of course, the first source S1 and the first drain D1 are arranged alternately. From left to right, it can be Figure 5 that the first source S1 is arranged first, and then the first drain D1 is arranged. It can also be that the first drain D1 is arranged first, and then the first source S1 is arranged.

[0117] In some embodiments, along the first direction X, the second source S2 and the second drain D2 are arranged alternately. The projection of the second gate G2 on the substrate is located between the projection of the adjacent second source S2 on the substrate and the projection of the second drain D2 on the substrate. For example, the second gate G2 is located above the gap between the adjacent second source S2 and the second drain D2.

[0118] Then, two adjacent second transistors M2 share the second source S2 or share the second drain D2. The number of second sources S2 is less than the number of second gates G2, and the number of second drains D2 is also less than the number of second gates G2. For Figure 5 example, the first second transistor M2 and the second second transistor M2 from left to right share the second drain D2, and the second second transistor M2 and the third second transistor M2 share the second source S2. Of course, the second sources S2 and the second drains D2 are arranged alternately. From left to right, it can be Figure 5 that the second source S2 is arranged first, and then the second drain D2. It can also be that the second drain D2 is arranged first, and then the second source S2.

[0119] In some embodiments, the widths of each first gate G1 are equal. In some embodiments, the widths of each second gate G2 are equal. In some embodiments, the width of the first gate G1 is equal to the width of the second gate G2. This can simplify the design and reduce the process difficulty.

[0120] In some embodiments, along the second direction Y, the gate pad G and the drain pad D are located on both sides of the first transistor M1. Of course, the specific positions of the gate pad G and the drain pad D in the embodiments of the present application are not limited. Taking the gate pad G as an example, along the second direction Y, the gate pad G can be located on one side of the first gate G1. However, from the first direction X, the gate pad G can be close to the first region where multiple first gates G1 are arranged, the gate pad G can also be close to the second region where multiple second gates G2 are arranged, and the gate pad G can also be located between the first region and the second region.

[0121] Since the gate pad G and the drain pad D usually transmit non-zero voltages, setting the gate pad G and the drain pad D on the sides of the regions where the source, drain, and gate are located can reduce the parasitic parameters of the first transistor M1 and the second transistor M2 and optimize the performance of the first transistor M1 and the second transistor M2.

[0122] In some embodiments, as Figure 5 shown, there is a gap between multiple first transistors M1 and multiple second transistors M2, and the projection of the source pad S on the substrate is located within the gap. For example, from the cross-sectional view, the source pad S can be located above the gap.

[0123] It is equivalent to saying that multiple first transistors M1 and multiple second transistors M2 are two separate arranged plates, and the two only share the gate pad G, the source pad S, and the drain pad D.

[0124] Then, the first transistor M1 and the second transistor M2 do not share the source or the drain. For Figure 5For example, a first source electrode S1 and a second source electrode S2 are provided between adjacent first gate G1 and second gate G2, and there is a gap between the first source electrode S1 and the second source electrode S2. Of course, according to different arrangement manners, a first drain D1 and a second drain D2 may also be provided between adjacent first gate G1 and second gate G2. Or, a first source electrode S1 and a second drain D2 may also be provided between adjacent first gate G1 and second gate G2. Or, a first drain D1 and a second source electrode S2 may also be provided between adjacent first gate G1 and second gate G2.

[0125] By disposing the source pad S at the gap between the plurality of first transistors M1 and the plurality of second transistors M2, the connection portions coupled to the first source electrode S1 and the connection portions coupled to the second source electrode S2 can be connected to the same source pad S, reducing the number of source pads S. In addition, to reduce parasitic interference, the size of the above-mentioned gap is larger than the size of the source pad S, and the larger gap can reduce the process difficulty of the plurality of first transistors M1 and the plurality of second transistors M2.

[0126] In some other embodiments, as Figure 6 shown, there is a gap between the plurality of first transistors M1 and the plurality of second transistors M2, and the source pad S includes a first pad S-1 and a second pad S-2. The first pad S-1 is located on the side of the first transistor M1 away from the second transistor M2, and the second pad S-2 is located on the side of the second transistor M2 away from the first transistor M1.

[0127] By disposing the first pad S-1 outside the plurality of first transistors M1 and the second pad S-2 outside the plurality of second transistors M2, without reserving the gap corresponding to the source pad S between the plurality of first transistors M1 and the plurality of second transistors M2, the size of the gap between the plurality of first transistors M1 and the plurality of second transistors M2 can be reduced, so as to reduce the occupied area of the first transistor M1 and the second transistor M2 and improve the integration degree of the semiconductor structure.

[0128] In still some other embodiments, as Figure 7 shown, a first source electrode S1 is provided between adjacent first gate G1 and second gate G2, and the first source electrode S1 is multiplexed as the second source electrode S2.

[0129] Or, a first source electrode S1 is provided between adjacent first gate G1 and second gate G2, and the first drain D1 is multiplexed as the second drain D2.

[0130] Then, it can be said that the plurality of first transistors M1 and the plurality of second transistors M2 can be regarded as an integral block.

[0131] A plurality of gates are arranged in sequence along the first direction X. Some of the gates serve as the first gate G1, and the remaining gates serve as the second gate G2. A plurality of sources and a plurality of drains are arranged alternately along the first direction. The source and drain located on both sides of the first gate G1 serve as the first source S1 and the first drain D1, and the source and drain located on both sides of the second gate G2 serve as the second source S2 and the second drain D2. If the element between adjacent first gate G1 and second gate G2 is a source, then the first gate G1 and the second gate G2 share this source. If the element between adjacent first gate G1 and second gate G2 is a drain, then the first gate G1 and the second gate G2 share this drain.

[0132] Exemplarily, the source pad S is located on the side of the first transistor M1 away from the second transistor M2. Alternatively, exemplarily, the source pad S is located on the side of the second transistor M2 away from the first transistor M1. Since there is no reserved gap between the first transistor M1 and the second transistor M2, then, the source pad S can only be arranged on the side of the first transistor M1 and the second transistor M2 along the first direction X.

[0133] This arrangement can reduce the gap between the first transistor M1 and the second transistor M2, reduce the occupied area of the semiconductor structure, and improve the integration degree of the semiconductor structure.

[0134] The above design method of the first transistor M1 and the second transistor M2 is illustrated, and the physical characteristics of the first transistor M1 and the second transistor M2 will be described below.

[0135] In some embodiments, the total width of the first gates G1 of at least one first transistor M1 is greater than the total width of the second gates G2 of at least one second transistor M2 with the same threshold voltage.

[0136] Among them, the total width of the first gates G1 of at least one first transistor M1 can be understood as follows: in the case where the amplification module includes one first transistor M1, the width of the first gate G1 of this first transistor M1 is the total width of the first gates G1 of at least one first transistor M1. In the case where the amplification module includes a plurality of first transistors M1, the sum of the widths of the plurality of first transistors M1 is the total width of the first gates G1 of at least one first transistor M1.

[0137] Similarly, the total width of the second gates G2 with the same threshold voltage in at least one second transistor M2 can be understood as follows: when the amplification module includes one second transistor M2, the width of the second gate G2 of this second transistor M2 is the total width of the second gates G2 of at least one second transistor M2. When the amplification module includes multiple second transistors M2, when the threshold voltages of the multiple second transistors M2 are the same, the total width of the first gates G1 of at least one first transistor M1 is greater than the total width of the second gates G2 of the multiple second transistors M2. When the threshold voltages of the multiple second transistors M2 are different, the total width of each type of second transistor M2 with the same threshold voltage is less than the total width of the first gates G1 of at least one first transistor M1.

[0138] The width of the first gate G1 is the dimension of the first gate G1 along the second direction Y, and the total width of the multiple first gates G1 is the sum of the dimensions of the multiple first gates G1 along the second direction Y.

[0139] In some embodiments, the semiconductor structure includes multiple first transistors M1 connected in parallel and multiple second transistors M2 connected in parallel.

[0140] When the total width of the gates is fixed, multiple transistors with small gate widths have better radio frequency performance and lower processing difficulty than a single transistor with a large gate width.

[0141] In some embodiments, the threshold voltage of the first transistor M1 is less than the threshold voltage of each second transistor M2.

[0142] Exemplarily, when the semiconductor structure includes multiple first transistors M1, the threshold voltages of the multiple first transistors M1 are the same.

[0143] Exemplarily, the semiconductor structure includes one second transistor M2, and the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2.

[0144] Alternatively, exemplarily, the semiconductor structure includes multiple second transistors M2.

[0145] For example, if the threshold voltages of the multiple second transistors M1 are the same, then the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2. Optionally, the width of the first gate G1 is equal to the width of the second gate G2, and the number of at least one first transistor M1 (i.e., the total number of the first transistors M1) is greater than the number of at least one second transistor M2 (i.e., the total number of the second transistors M2).

[0146] Alternatively, for example, if the threshold voltages of multiple second transistors M2 are different, then the threshold voltage of the first transistor M1 is less than the threshold voltage of each second transistor M2. That is to say, the threshold voltage of the first transistor M1 is less than the minimum threshold voltage of the multiple second transistors M2.

[0147] Figure 8 and Figure 9 is a layout schematic diagram of another semiconductor structure provided by an embodiment of the present application.

[0148] In some embodiments, as Figure 8 shown, the multiple second transistors M2 include a first group of second transistors M2 and a second group of second transistors M2, and the threshold voltages of the second transistors M2 in the first group are different from the threshold voltages of the second transistors M2 in the second group.

[0149] Then, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistors M2 in the first group, and the threshold voltage of the first transistor M1 is also less than the threshold voltage of the second transistors M2 in the second group.

[0150] Of course, the multiple second transistors M2 may further include a third group or more groups of second transistors M2, and the threshold voltages of the second transistors M2 in each group are different.

[0151] The embodiment of the present application does not limit the number of second transistors M2 included in each group, and the number of second transistors M2 in each group is related to the threshold voltage of the second transistors M2 in that group.

[0152] Exemplarily, as Figure 8 shown, the semiconductor structure includes ten first transistors M1 and three groups of second transistors M2.

[0153] The first group includes three second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the first group and the threshold voltage of the first transistor M1 is 0.12V. The second group includes one second transistor M2, and the difference between the threshold voltage of the second transistors M2 in the second group and the threshold voltage of the first transistor M1 is 0.16V. The third group includes four second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the third group and the threshold voltage of the first transistor M1 is 0.22V.

[0154] Or, exemplarily, as Figure 9 shown, the semiconductor structure includes ten first transistors M1 and three groups of second transistors M2.

[0155] The first group includes four second transistors M2, and the difference between the threshold voltage of the second transistor M2 in the first group and the threshold voltage of the first transistor M1 is 0.22V. The second group includes two second transistors M2, and the difference between the threshold voltage of the second transistor M2 in the second group and the threshold voltage of the first transistor M1 is 0.32V. The third group includes four second transistors M2, and the difference between the threshold voltage of the second transistor M2 in the third group and the threshold voltage of the first transistor M1 is 0.42V.

[0156] Of course, the embodiments of the present application do not limit the grouping of multiple second transistors M2. Multiple second transistors M2 can be divided into multiple groups, and it is only necessary that the threshold voltages of the second transistors M2 in different groups are different. The number of second transistors M2 included in each group is also not limited, and it can be adaptively set in combination with the threshold voltage of the second transistor M2. In addition, the second transistors M2 belonging to the same group are not limited to being arranged adjacent to each other in sequence. Figure 8 and Figure 9 is only a schematic illustration. It is determined whether the second transistors M2 belong to the same group by the threshold voltage of the second transistors M2, rather than by the position. Similarly, it is determined whether it is the first transistor M1 or the second transistor M2 by the threshold voltage, rather than by the position.

[0157] By arranging second transistors M2 with multiple different threshold voltages in combination, a good cancellation effect can be achieved in a certain area, that is, the width of the cancellation effective area is increased, thereby improving the tolerance to process fluctuations and environmental conditions such as temperature, and improving the process consistency in the semiconductor structure production and processing process. In addition, by setting second transistors M2 with different threshold voltages and combining them with different numbers of second transistors M2, the linearity of the radio frequency amplifier can be improved within the range of drain current from 40 mA / mm to 120 mA / mm.

[0158] When the second transistors M2 are divided into multiple groups, the total width of the first gates G1 of the first transistor M1 is greater than the total width of the second gates G2 of the second transistors M2 in the first group. The total width of the first gates G1 of the first transistor M1 is also greater than the total width of the second gates G2 of the second transistors M2 in the second group. However, the total width of the first gates G1 of the first transistor M1 is not necessarily greater than the total width of the second gates G2 of all the second transistors M2.

[0159] Exemplarily, such as Figure 8 and Figure 9As shown, the number of at least one first transistor M1 (i.e., the total number of first transistors M1) is greater than the number of second transistors M2 in the first group, greater than the number of second transistors M2 in the second group, and greater than the number of second transistors M2 in the third group. However, as Figure 9 shown, the total number of first transistors M1 is not necessarily greater than the total number of second transistors M2. The total number of first transistors M1 may be greater than, equal to, or less than the total number of second transistors M2.

[0160] In an embodiment of the present application, the semiconductor structure includes a first transistor M1 and a second transistor M2. The width of the first gate G1 of the first transistor M1 affects the amplitude of the total signal transmitted by the first transistor M1 (including the main signal and the negative intermodulation signal), and the width of the second gate G1 of the second transistor M2 affects the amplitude of the total signal transmitted by the second transistor M2 (including the main signal and the positive intermodulation signal). The threshold voltages of the first transistor M1 and the second transistor M2 affect the phase of the intermodulation signal output by the first transistor M1 and the second transistor M2 under the condition of the same gate voltage. In the present application, the first gate G1 and the second gate G2 are both coupled to the gate pad G and receive the same gate bias voltage. Under the same gate bias voltage, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2. Therefore, the first transistor M1 provides a negative intermodulation signal, and the second transistor M2 provides a positive intermodulation signal. Although the positive intermodulation signal provided by the transistor under the same conditions is greater than the negative intermodulation signal, in the present application, the total width of the first gate G1 is always set to be greater than the total width of the second gate G2, so that the first transistor M1 and the second transistor M2 can output two groups of equal and opposite intermodulation signals to achieve cancellation. Therefore, in the embodiment of the present application, by adopting the design of different threshold voltages, the effect of cancellation can be achieved by providing the first transistor M1 and the second transistor M2 with a same gate bias voltage. The design complexity of the semiconductor structure is low, the structure is simple, and the occupied area is small. Moreover, the stability of the threshold voltage difference is used to control the gate bias state, and the cancellation effect is stable.

[0161] Next, a schematic description of the method for realizing different threshold voltages of the first transistor M1 and the second transistor M2 will be given.

[0162] Figures 10 - 13 This is a Figure 6 cross-sectional view taken along the A1 - A2 direction provided by an embodiment of the present application.

[0163] In some embodiments, such as Figure 10As shown, the first transistor M1 further includes a first substrate 11, a first channel layer 12, and a first barrier layer 13 that are sequentially stacked on the first substrate 11. The first channel layer 12 and the first barrier layer 13 form a heterojunction. The second transistor M2 further includes a second substrate 21, a second channel layer 22, and a second barrier layer 23 that are sequentially stacked on the second substrate 21. The second channel layer 22 and the second barrier layer 23 form a heterojunction.

[0164] Exemplarily, the first substrate 11 and the second substrate 21 are an integrally formed structure, the first channel layer 12 and the second channel layer 22 are an integrally formed structure, and the first barrier layer 13 and the second barrier layer 23 are an integrally formed structure.

[0165] The material of the first substrate 11 is, for example, a silicon (Si) substrate or a silicon carbide (SiC) substrate.

[0166] The material of the first channel layer 12 may include, for example, one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), scandium aluminum nitride (ScAlN), and gallium arsenide (GaAs).

[0167] The material of the first barrier layer 13 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, ScAlN, and GaAs.

[0168] In some embodiments, the first barrier layer 13 further includes a first gate metal diffusion region 131, and the material of the first gate metal diffusion region 131 is different from the material of other regions in the first barrier layer 13. The first gate metal diffusion region 131 is located below the first gate G1 and makes a Schottky contact with the first gate G1.

[0169] The first gate G1 makes a Schottky contact with the first barrier layer 13, and the first source S1 and the first drain D1 make an ohmic contact with the first barrier layer 13.

[0170] The first transistor M1 can be a HEMT device, or the first transistor M1 can also be a pHEMT device. Depending on the type of the transistor, the materials selected for the first channel layer 12 and the first barrier layer 13 are also different.

[0171] In some embodiments, the material of the first gate G1 can be, for example, Au or Pd.

[0172] In some embodiments, the materials of the first source electrode S1 and the first drain electrode D1 can be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence, that is, Ti / Al / Ni / Au. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 can be a Ti layer, an Al layer, a platinum (Pt) layer, and an Au layer stacked in sequence, that is, Ti / Al / Pt / Au. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 can be a Ti layer, a tantalum (Ta) layer, and a Ti layer stacked in sequence, that is, Ti / Ta / Ti. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 can be Au or palladium (Pd).

[0173] Of course, the structure included in the first transistor M1 in the embodiments of the present application is only a schematic illustration, and the structures of HEMT devices and pHEMT devices in the related art are applicable to the first transistor M1 in the embodiments of the present application. By way of example, the first transistor M1 may further include structures such as a nucleation layer, a buffer layer, a capping layer, and a field plate, which are not limited in the embodiments of the present application.

[0174] For the structure of the second transistor M2, reference may be made to the relevant description of the first transistor M1, which will not be elaborated here.

[0175] In some embodiments, the second barrier layer 23 includes a second gate metal contact region 231, and the material of the second gate metal contact region 231 is different from the materials of other regions in the second barrier layer 23. The second gate metal contact region 231 is located below the second gate G2 and is in Schottky contact with the second gate G2.

[0176] The second gate G2 is in Schottky contact with the second barrier layer 23, and the second source electrode S2 and the second drain electrode D2 are in ohmic contact with the second barrier layer 23.

[0177] In some embodiments, as Figure 10 shown, a first thickness H1 of a portion of the first barrier layer 13 in contact with the first gate G1 is greater than a second thickness H2 of a portion of the second barrier layer 23 in contact with the second gate G2.

[0178] By way of example, the value range of the difference between the first thickness H1 and the second thickness H2 is 1 nm - 6 nm. For example, the difference between the first thickness H1 and the second thickness H2 takes values of 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm.

[0179] When the semiconductor structure includes second transistors M2 with multiple threshold voltages, the thicknesses of different portions of the second barrier layer 23 in contact with different second gates G2 can be different.

[0180] By changing the thicknesses of the first barrier layer 13 and the second barrier layer 23, the threshold voltage of the first transistor M1 is made smaller than the threshold voltage of the second transistor M2, and the process is simple and easy to implement.

[0181] In some other embodiments, as Figure 11 shown, the first gate G1 includes a stacked multi-layer metal layer. Figure 11 Taking the first gate G1 including a first Schottky metal layer G1-1 in contact with the first barrier layer 13 and a first upper metal layer G1-2 as an example for illustration. The second gate G2 includes a stacked multi-layer metal layer, Figure 11 taking the second gate G2 including a second Schottky metal layer G2-1 in Schottky contact with the second barrier layer 23 and a second upper metal layer G2-2.

[0182] Among them, the work function of the first Schottky metal layer G1-1 is less than that of the second Schottky metal layer G2-1. The materials of the first upper metal layer G1-2 and the second upper metal layer G2-2 may be the same or different.

[0183] Exemplarily, the value range of the difference between the work function of the second Schottky metal layer G2-2 and the work function of the first Schottky metal layer G1-2 is 0.1 eV - 0.4 eV. For example, the value of the difference between the work function of the second Schottky metal layer G2-2 and the work function of the first Schottky metal layer G1-2 is 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, 0.3 eV, 0.35 eV, 0.4 eV.

[0184] For example, the material of the first Schottky metal layer G1-1 is platinum (Pt) and the work function is 5.65 eV. The material of the second Schottky metal layer G2-1 is nickel (Ni) and the work function is 5.15 eV.

[0185] By changing the materials of the first Schottky metal layer G1-1 and the second Schottky metal layer G2-1, the threshold voltage of the first transistor M1 is made smaller than the threshold voltage of the second transistor M2, and the process is simple and easy to implement.

[0186] In yet another embodiment, as Figure 12 shown, the third thickness H3 of the first gate metal diffusion region 131 is less than the fourth thickness H4 of the second gate metal contact region 231.

[0187] Exemplarily, the value range of the difference between the fourth thickness H4 and the third thickness H3 is 1 nm - 6 nm. The value of the difference between the fourth thickness H4 and the third thickness H3 is 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm.

[0188] By changing the thicknesses of the first gate metal diffusion region 131 and the second gate metal contact region 231, the threshold voltage of the first transistor M1 is made smaller than the threshold voltage of the second transistor M2. The process is simple and easy to implement.

[0189] In yet another embodiment, as Figure 13 shown, the first gate length L1 of the first gate G1 is less than the second gate length L2 of the second gate G2.

[0190] Exemplarily, the value range of the difference between the second gate length L2 and the first gate length L1 is 0.1 um - 1 um. For example, the difference between the second gate length L2 and the first gate length L1 is 0.1 um, 0.2 um, 0.3 um, 0.4 um, 0.5 um, 0.6 um, 0.7 um, 0.8 um, 0.9 um, 1 um.

[0191] By changing the gate lengths of the first gate G1 and the second gate G2, the threshold voltage of the first transistor M1 is made smaller than the threshold voltage of the second transistor M2. The process is simple and easy to implement.

[0192] When the semiconductor structure provided by the embodiment of the present application is applied to a radio frequency amplifier, a DC blocking capacitor can be coupled between the radio frequency input end of the radio frequency amplifier and the gate pad G, and after the first drain D1 and the second drain D2 are coupled, they are coupled to the output end of the radio frequency amplifier. Of course, other peripheral circuits can also be included. The structures of radio frequency amplifiers in the related art are all applicable to the embodiments of the present application. The embodiments of the present application only change the structures of the amplification module and the cancellation module in the radio frequency amplifier.

[0193] As Figure 14 shown, in the embodiment of the present application, by designing the threshold voltages of the first transistor M1 and the second transistor M2 to be different, it is possible to reduce gm3 within the transistor operating region, and the amplitude of the third-order intermodulation signal decreases, thereby achieving the same linearity improvement effect as the cancellation circuit. As Figure 14 shown, through simulation, it is found that the cancelled signal output by the semiconductor structure provided by the embodiment of the present application is basically close to 0 near the gate voltage of -3.3V, and the effect of linearity improvement can be achieved.

[0194] For example, when the semiconductor structure provided by the embodiment of the present application is applied to an LNA, the output third order intercept point (OIP3) is commonly used in the art to describe the linearity of the LNA. As Figure 15AAs shown in the figure, the abscissa is the input power and the ordinate is the output power. The value of OIP3 is obtained from the radio frequency input-output curve of the LNA by the plotting method. Two curves are plotted. The solid line is the plot of the amplified signal power against the input power at the input frequency, and the dashed line is the plot of the third-order intermodulation signal against the input power. In the logarithmic coordinate system, the linear amplified signal curve shows a straight line with a slope of 1 (solid line), and the third-order intermodulation signal curve shows a straight line with a slope of 3 (dashed line). The output signal power corresponding to their intersection point is the OIP3 value. As Figure 15B shown, the abscissa is the drain current and the ordinate is OIP3. The solid line is the OIP3 curve of the LNA provided by the embodiment of the present application, and the dashed line is the OIP3 curve of the LNA in the related art. The OIP3 of the LNA provided by the present application can improve the transistor linearity, and the OIP3 is increased by more than 5 dB.

[0195] As mentioned above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, it is applied to a radio frequency amplifier; the semiconductor structure includes: a gate pad; a source pad; a drain pad; at least one first transistor; each of the first transistors includes a first gate, a first source, and a first drain, and the first gate is coupled to the gate pad, the first source is coupled to the source pad, and the first drain is coupled to the drain pad; at least one second transistor; each of the second transistors includes a second gate, a second source, and a second drain, and the second gate is coupled to the gate pad, the second source is coupled to the source pad, and the second drain is coupled to the drain pad; wherein, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the total gate width of the at least one first transistor is greater than the total gate width of one or more of the second transistors having the same threshold voltage.

2. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure includes a plurality of the second transistors; the plurality of the second transistors include a first group of second transistors and a second group of second transistors, and the threshold voltage of the second transistors in the first group is different from the threshold voltage of the second transistors in the second group.

3. The semiconductor structure according to claim 2, characterized in that, the number of the at least one first transistor is greater than the number of the second transistors in the first group and greater than the number of the second transistors in the second group.

4. The semiconductor structure according to claim 1, characterized in that, the threshold voltages of the at least one first transistor are the same, the threshold voltages of the at least one second transistor are the same, and the number of the at least one first transistor is greater than the number of the at least one second transistor.

5. The semiconductor structure according to any one of claims 2-4, characterized in that, the width of the first gate is equal to the width of the second gate.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first gate is in Schottky contact with the first barrier layer, and the first source and the first drain are in Ohmic contact with the first barrier layer; the second gate is in Schottky contact with the second barrier layer, and the second source and the second drain are in Ohmic contact with the second barrier layer; a first thickness of a portion of the first barrier layer in contact with the first gate is greater than a second thickness of a portion of the second barrier layer in contact with the second gate.

7. The semiconductor structure according to claim 6, characterized in that, the value range of the difference between the first thickness and the second thickness is 1nm - 6nm.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; The first gate includes a first Schottky metal layer that makes a Schottky contact with the first barrier layer, and the second gate includes a second Schottky metal layer that makes a Schottky contact with the second barrier layer; the work function of the first Schottky metal layer is less than the work function of the second Schottky metal layer.

9. The semiconductor structure according to claim 8, wherein, the value range of the difference between the work function of the second Schottky metal layer and the work function of the first Schottky metal layer is 0.1 eV - 0.4 eV.

10. The semiconductor structure according to any one of claims 1 - 9, wherein, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first barrier layer includes a first gate metal diffusion region that makes a Schottky contact with the first gate, the second barrier layer includes a second gate metal diffusion region that makes a Schottky contact with the second gate, and a third thickness of the first gate metal diffusion region is less than a fourth thickness of the second gate metal diffusion region.

11. The semiconductor structure according to claim 10, wherein, the value range of the difference between the fourth thickness and the third thickness is 1 nm - 6 nm.

12. The semiconductor structure according to any one of claims 1 - 11, wherein, a first gate length of the first gate is less than a second gate length of the second gate.

13. The semiconductor structure according to claim 12, wherein, the value range of the difference between the second gate length and the first gate length is 0.1 μm - 1 μm.

14. The semiconductor structure according to any one of claims 1 - 13, wherein, the source pad includes a first pad and a second pad, the first source is coupled to the first pad, and the second source is coupled to the second pad.

15. The semiconductor structure according to any one of claims 1 - 14, wherein, the semiconductor structure includes a plurality of first transistors and a plurality of second transistors; along a first direction, the first gates of the plurality of first transistors are arranged in sequence, the first sources and the first drains are arranged alternately, and the first gate is located above a gap between adjacent first source and first drain; along the first direction, the second gates of the plurality of second transistors are arranged in sequence, the second sources and the second drains are arranged alternately, and the second gate is located above a gap between adjacent second source and second drain; the first direction is the length direction of the first gate; along the width direction of the first gate, the gate pad and the drain pad are located on both sides of the first transistor.

16. The semiconductor structure according to claim 15, wherein, there is a gap between the plurality of first transistors and the plurality of second transistors, and the source pad is located above the gap.

17. The semiconductor structure according to claim 15, wherein, the first pad is located on a side of the first transistor away from the second transistor, and the second pad is located on a side of the second transistor away from the first transistor.

18. The semiconductor structure according to claim 16 or 17, wherein, the first source electrode and the second source electrode are disposed between the adjacent first gate electrode and the second gate electrode.

19. The semiconductor structure according to claim 15, wherein, the first source electrode is disposed between the adjacent first gate electrode and the second gate electrode, and the first source electrode is multiplexed as the second source electrode; the source electrode pad is located on a side of the first transistor away from the second transistor; or, the source electrode pad is located on a side of the second transistor away from the first transistor.

20. A radio frequency amplifier, wherein, comprising a capacitor and the semiconductor structure according to any one of claims 1-19; one end of the capacitor is coupled to an input end of the radio frequency amplifier, and the other end of the capacitor is coupled to the gate electrode pad; the source electrode pad is coupled to a reference ground voltage terminal, and the drain electrode pad is coupled to an output end of the radio frequency amplifier.

21. A radio frequency front-end module, wherein, comprising: a filter and a low-noise amplifier; the low-noise amplifier comprises the radio frequency amplifier according to claim 20; a radio frequency input end of the radio frequency amplifier is coupled to an input end of the filter.

22. A communication device, wherein, comprising the radio frequency front-end module according to claim 21 and an antenna, and the antenna is coupled to the radio frequency front-end module.

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