Differential signal generation circuit

Abstract

This application discloses a differential signal generation circuit. The differential signal generation circuit includes: an oscillator that generates multiple clock signals; a duty cycle adjustment module that adjusts the duty cycle of each clock signal to obtain multiple clock signals; and a logic module that provides phase-complementary differential signal pairs based on the multiple clock signals. The oscillator includes N stages of interconnected inverters, and the output ends of the N stages of inverters provide multiple clock signals, each with an initial phase difference. The differential signal generation circuit of this application has high precision and a simple circuit structure.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly, to a differential signal generating circuit. Background Art

[0002] Differential signals are a pair of electrical signals with the same amplitude and opposite phases. They have the advantages of anti-interference, suppression of common-mode interference, and improved signal integrity. They are widely used in high-speed data transmission, audio and video transmission, and analog and digital signal processing.

[0003] Currently, differential signals are typically generated using a differential inverter structure or an additional single-ended-to-differential conversion structure. However, the differential inverter structure increases circuit complexity and layout matching difficulties, while also increasing power consumption and layout area. The differential signal generated by the single-ended-to-differential conversion structure is imprecise and suffers from significant process variation, making it unsuitable for high-speed, high-precision circuits. Furthermore, in low-voltage applications, the duty cycle of the signals generated by both of these solutions deviates significantly from 50%, hindering subsequent signal processing.

[0004] Therefore, it is desired to provide an improved differential signal generating circuit to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a differential signal generating circuit to generate accurate differential signals, simplify the circuit and save costs.

[0006] According to one aspect of the present invention, a differential signal generation circuit is provided, comprising: an oscillator for generating a plurality of clock signals; and a logic module for providing a differential signal pair with complementary phases based on the plurality of clock signals, wherein the oscillator comprises N stages of inverters connected to each other, N being greater than 0 and an integer multiple of 3, and the output ends of the N stages of inverters providing the plurality of clock signals, wherein the plurality of clock signals have an initial phase difference.

[0007] Optionally, the initial phase difference is 360 / N°.

[0008] Optionally, the N-stage inverter includes a first inverter, a second inverter and a third inverter connected in parallel between the signal source and the reference ground, the multiple clock signals include a first signal, a second signal and a third signal, the control end of the first inverter is connected to the output end of the third inverter, the control end of the second inverter is connected to the output end of the first inverter, the control end of the third inverter is connected to the output end of the second inverter, the output end of the first inverter provides the first signal, the output end of the second inverter provides the second signal, and the output end of the third inverter provides the third signal.

[0009] Optionally, each of the inverters includes: a first switching tube and a second switching tube connected in series between the signal source and the reference ground, the control ends of the first switching tube and the second switching tube are connected to each other and serve as the control end of the inverter, the first current end of the first switching tube is connected to the signal source, the second current end of the first switching tube is connected to the first current end of the second switching tube, the second current end of the second switching tube is connected to the reference ground, and the connection node between the second current end of the first switching tube and the first current end of the second switching tube serves as the output end of the inverter.

[0010] Optionally, the method further includes: a duty cycle adjustment module connected between the oscillator and the logic module, and configured to adjust the duty cycle of each of the clock signals respectively.

[0011] Optionally, the duty cycle adjustment module includes a plurality of sub-adjustment modules corresponding to the plurality of clock signals, so as to adjust the duty cycles of the plurality of clock signals to within a predetermined range respectively.

[0012] Optionally, each of the sub-adjustment modules includes: a duty cycle detection circuit, which obtains a detection signal representing the duty cycle of the clock signal according to the clock signal; and a duty cycle adjustment circuit, which adjusts the duty cycle of the clock signal according to the detection signal.

[0013] Optionally, the duty cycle detection circuit includes a first resistor and a first capacitor and a second capacitor connected in series between a voltage source and a reference ground, wherein a first end of the first resistor receives the clock signal, and a second end of the first resistor is connected to a series node of the first and second capacitors and provides the detection signal. The duty cycle adjustment circuit includes a fourth inverter, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, and an eighth switch transistor, wherein the third switch transistor and the fourth switch transistor are sequentially connected in series between the voltage source and the reference ground, and the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, and the eighth switch transistor are sequentially connected in series between the voltage source and the reference ground. The clock signal is connected to the control terminals of the third switch transistor, the fourth switch transistor, the fifth switch transistor, and the eighth switch transistor through the fourth inverter, and the detection signal is connected to the control terminals of the sixth switch transistor and the seventh switch transistor. The series node between the third switch transistor and the fourth switch transistor is connected to the series node between the sixth switch transistor and the seventh switch transistor and provides a calibrated clock signal.

[0014] Optionally, the clock signal is corrected by adjusting driving capabilities of the sixth switching tube and the seventh switching tube.

[0015] Optionally, the logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter, the multiple clock signals include a first signal, a second signal and a third signal, the fifth inverter receives the first signal, the sixth inverter receives the third signal, the seventh inverter receives the second signal, the output end of the fifth inverter is connected to the output end of the sixth inverter and connected to the input end of the eighth inverter, the output end of the seventh inverter is connected to the input end of the ninth inverter, and the eighth inverter and the ninth inverter provide the differential signal pair.

[0016] The differential signal generating circuit provided by the present invention can generate accurate differential signals by utilizing an oscillator structure, and has a simple circuit structure and low cost.

[0017] Furthermore, the present application addresses the problem of duty cycle deviation in low-voltage applications by using a duty cycle adjustment circuit with a simple structure to perform correction, thereby further increasing the accuracy of the differential signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 shows a block diagram of a differential signal generating circuit according to an embodiment of the present invention;

[0020] Figure 2 FIG2 shows a circuit diagram of a differential signal generating circuit according to an embodiment of the present invention;

[0021] Figure 3 shows a circuit diagram of a sub-adjustment module according to an embodiment of the present invention;

[0022] Figure 4 FIG. 4 shows a signal waveform diagram of a differential signal generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0024] Many specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0025] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices, and the embodiment of the present application is not limited to this.

[0026] The following describes an embodiment of the differential signal generating circuit provided by the present application in conjunction with the accompanying drawings.

[0027] Figure 1 FIG. 4 shows a block diagram of a differential signal generating circuit according to an embodiment of the present invention.

[0028] like Figure 1 As shown, the differential signal generating circuit 100 includes an oscillator 110 and a logic module 120, and optionally, further includes a duty cycle adjusting module 130. The differential signal generating circuit 100 can generate a differential signal with high precision.

[0029] Oscillator 110 is used to generate multiple clock signals (hereinafter referred to as initial clock signal clk_p); duty cycle adjustment module 130 is used to adjust the duty cycle of each clock signal (hereinafter referred to as calibration clock signal clk_d); and logic module 120 is used to provide a phase-complementary differential signal pair based on the multiple clock signals. In some embodiments, when the initial clock signal clk_p provided by oscillator 110 is highly accurate, such as in high-voltage applications, duty cycle adjustment module 130 can be omitted, and logic module 120 directly provides the phase-complementary differential signal pair based on the multiple initial clock signals clk_p. In other embodiments, when the initial clock signal clk_p provided by oscillator 110 is less accurate, such as in low-voltage applications, logic module 120 provides the phase-complementary differential signal pair based on the calibration clock signal clk_d provided by oscillator 110.

[0030] In an embodiment of the present invention, the multiple initial clock signals clk_p generated by the oscillator 110 have an initial phase difference. For example, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. The logic module 120 synthesizes these three initial clock signals clk_p or the calibration clock signals clk_d corresponding to these three initial clock signals clk_p to generate a high-precision differential signal. In an alternative embodiment, the oscillator 110 generates N initial clock signals clk_p, where N is greater than 0 and an integer multiple of 3, and the initial phase difference between two adjacent initial clock signals clk_p is 360° / N. The logic module 120 selects three initial clock signals clk_p with a phase difference of 120° from the N initial clock signals clk_p or the calibration clock signals clk_d corresponding to these three initial clock signals clk_p for signal processing to obtain a differential signal.

[0031] Therefore, the embodiment of the present invention provides a high-precision three-terminal differential structure differential signal generating circuit, Figure 2-4 The circuit structure of the differential signal generating circuit according to the embodiment of the present invention is described in detail.

[0032] Figure 2 FIG2 shows a circuit diagram of a differential signal generating circuit according to an embodiment of the present invention; Figure 3 shows a circuit diagram of a sub-adjustment module according to an embodiment of the present invention; Figure 4 FIG. 1 shows a signal waveform diagram of a differential signal generating circuit according to an embodiment of the present invention. Figure 2 In FIG. 1 , the oscillator 110 only uses three inverters to generate three initial clock signals clk_p. It should be understood that Figure 2 The number of inverters shown is only an illustrative example, and the structure of the oscillator 110 of the present application is not limited thereto. The oscillator 110 provided in the embodiment of the present application may include N inverters to generate N initial clock signals clk_p, where N is greater than 0 and an integer multiple of 3.

[0033] like Figure 2 As shown, the differential signal generating circuit 100 includes an oscillator 110, a logic module 120, and a duty cycle adjustment module 130. The differential signal generating circuit 100 can generate a differential signal with high precision. In some optional embodiments, the duty cycle adjustment module 130 can be omitted.

[0034] The oscillator 110 is configured to generate multiple initial clock signals clk_p. The oscillator 110 includes N stages of interconnected inverters, where N is greater than 0 and an integer multiple of 3. The output terminals of the N stages of inverters provide multiple clock signals clk, each of which has an initial phase difference. For example, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. For another example, the oscillator 110 generates N initial clock signals clk_p, where N is greater than 0 and an integer multiple of 3, and the initial phase difference between two adjacent initial clock signals clk_p is 360° / N.

[0035] In this embodiment, the oscillator 110 includes N-stage inverters, which include a first inverter 111, a second inverter 112, and a third inverter 113 connected in parallel between a signal source and a reference ground. The multiple initial clock signals clk_p include a first signal P1, a second signal P2, and a third signal P3. The control end of the first inverter 111 is connected to the output end of the third inverter 113, the control end of the second inverter 112 is connected to the output end of the first inverter 111, and the control end of the third inverter 113 is connected to the output end of the second inverter 112. The output end of the first inverter 111 provides the first signal P1, the output end of the second inverter 112 provides the second signal P2, and the output end of the third inverter 113 provides the third signal P3.

[0036] As an example, the first inverter 111, the second inverter 112, and the third inverter 113 have identical structures, each including a first switch M1 and a second switch M2. In each inverter, the first switch M1 and the second switch M2 are connected in series between a signal source S1 and a reference ground GND. The signal source S1 can be a current source or a voltage source. The control terminals of the first switch M1 and the second switch M2 are connected to each other and serve as the control terminal of the inverter. The first current terminal of the first switch M1 is connected to the signal source S1, the second current terminal of the first switch M1 is connected to the first current terminal of the second switch M2, and the second current terminal of the second switch M2 is connected to the reference ground GND. The connecting node of the second current terminal of the first switch M1 and the first current terminal of the second switch M2 serves as the output terminal of the inverter. The first switch M1 and the second switch M2 are of opposite types. For example, the first switch M1 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the second switch M2 is a P-type MOSFET.

[0037] The duty cycle adjustment module 130 is connected to the oscillator 110 and receives three initial clock signals clk_p with an initial phase difference. The duty cycle adjustment module 130 adjusts the duty cycles of the three initial clock signals clk_p to obtain three calibrated clock signals clk_d, and transmits the calibrated clock signals clk_d to the logic module 120. The duty cycle adjustment module 130 can obtain three calibrated clock signals clk_d with duty cycles within a predetermined range. Because the duty cycle adjustment module 130 calibrates the duty cycles of the three initial clock signals clk_p to essentially the same degree, the three calibrated clock signals clk_d still have the initial phase difference. In this embodiment, the predetermined range is, for example, 40%-60%. Ideally, the duty cycle of the calibrated clock signal clk_d is approximately 50%.

[0038] In this embodiment, the duty cycle adjustment module 130 includes a plurality of sub-adjustment modules 131 corresponding to the plurality of initial clock signals clk_p, so as to adjust the duty cycles of the plurality of initial clock signals clk_p to within a predetermined range respectively.

[0039] As an example, each sub-adjustment module 131 includes a duty cycle detection circuit 131a and a duty cycle adjustment circuit 131b. The duty cycle detection circuit 131a obtains a detection signal V2 representing the duty cycle of the initial clock signal clk_p based on the initial clock signal clk_p. The duty cycle adjustment circuit 131b adjusts the duty cycle of the initial clock signal clk_p based on the detection signal V2 to obtain a calibrated clock signal clk_d.

[0040] Please refer to Figure 3 Duty cycle detection circuit 131a includes a first resistor R1 and first and second capacitors C1 and C2 connected in series between a voltage source VCC and a reference ground GND. A first end of first resistor R1 receives the initial clock signal clk_p, while a second end of first resistor R1 is connected to the series junction of first and second capacitors C1 and C2, providing a detection signal V2. Duty cycle detection circuit 131a converts the duty cycle information of initial clock signal clk_p into a voltage signal (i.e., detection signal V2) through an RC filter structure. A low duty cycle of initial clock signal clk_p results in a low detection signal V2, while a high duty cycle of initial clock signal clk_p results in a high detection signal V2. Therefore, the amplitude of detection signal V2 can represent the duty cycle of initial clock signal clk_p.

[0041] The duty cycle adjustment circuit 131b includes a fourth inverter I4, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, and an eighth switch M8. The third switch M3 and the fourth switch M4 are sequentially connected in series between a voltage source VCC and a reference ground GND. The fifth switch M5, the sixth switch M6, the seventh switch M7, and the eighth switch M8 are sequentially connected in series between the voltage source VCC and the reference ground GND. The initial clock signal clk_p is converted through the fourth inverter I4 to obtain an intermediate clock signal V1. The intermediate clock signal V1 is connected to the control terminals of the third switch M3, the fourth switch M4, the fifth switch M5, and the eighth switch M8. The detection signal V2 is connected to the control terminals of the sixth switch M6 and the seventh switch M7. The series node between the third switch M3 and the fourth switch M4 and the series node between the sixth switch M6 and the seventh switch M7 are connected to provide the calibration clock signal clk_d. The third switch M3 and the fourth switch M4 are of opposite types. The third switch M3, the fifth switch M5, and the sixth switch M6 are of the same type. The fourth switch M4, the seventh switch M7, and the eighth switch M8 are of the same type. For example, the third switch M3, the fifth switch M5, and the sixth switch M6 are N-type MOSFETs, and the fourth switch M4, the seventh switch M7, and the eighth switch M8 are P-type MOSFETs.

[0042] In some embodiments, in order to obtain a calibrated clock signal clk_d with a duty cycle closer to 50%, the initial clock signal clk_p is calibrated by adjusting the driving capabilities of the sixth switch M6 and the seventh switch M7.

[0043] Logic module 120 provides a phase-complementary differential signal pair based on multiple clock signals. In some embodiments, when the initial clock signal clk_p provided by oscillator 110 is highly accurate, such as in high-voltage applications, duty cycle adjustment module 130 can be omitted, and logic module 120 directly provides a phase-complementary differential signal pair based on the multiple initial clock signals clk_p. In other embodiments, when the initial clock signal clk_p provided by oscillator 110 is less accurate, such as in low-voltage applications, logic module 120 provides a phase-complementary differential signal pair based on the calibration clock signal clk_d provided by oscillator 110.

[0044] In this embodiment, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. The logic module 120 synthesizes these three initial clock signals clk_p or the calibration clock signals clk_d corresponding to these three initial clock signals clk_p to generate a high-precision differential signal. In an alternative embodiment, the oscillator 110 generates N initial clock signals clk_p, where N is greater than 0 and an integer multiple of 3, and the initial phase difference between two adjacent initial clock signals clk_p is 360° / N. The logic module 120 selects three initial clock signals clk_p with a phase difference of 120° from the N initial clock signals clk_p or the calibration clock signals clk_d corresponding to these three initial clock signals clk_p for signal processing to obtain a differential signal.

[0045] As an example, the logic module 120 includes a fifth inverter I5, a sixth inverter I6, a seventh inverter I7, an eighth inverter I8, and a ninth inverter I9. The multiple clock signals (the initial clock signal clk_p or the calibration clock signal clk_d) include a first signal D1, a second signal D2, and a third signal D3. The fifth inverter I5 receives the first signal D1, the sixth inverter I6 receives the third signal D3, and the seventh inverter I7 receives the second signal D2. The output end of the fifth inverter I5 is connected to the output end of the sixth inverter I6 and is connected to the input end of the eighth inverter I8. The output end of the seventh inverter I7 is connected to the input end of the ninth inverter I9. The output ends of the eighth inverter I8 and the ninth inverter I9 provide the differential signal pair P5 and P7.

[0046] Specifically, please refer to Figure 4 Oscillator 110 or duty cycle adjustment module 130 provides first signal D1, second signal D2, and third signal D3 with an initial phase difference of 120°. Fifth inverter I5 and sixth inverter I6 receive first signal D1 and third signal D3, respectively, and invert them to form signal P4. Seventh inverter I7 receives second signal D2 and inverts it to form signal P6. Eighth inverter I8 receives signal P4 and inverts it to form signal P5. Ninth inverter I9 receives signal P6 and inverts it to form signal P7. Signals P5 and P7 are a pair of differential signals with the same amplitude and opposite phases. That is, the phase difference between signals P5 and P7 is 180°.

[0047] Some examples of the differential signal generating circuit according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto and may be extended and modified in other ways.

[0048] For example, it should be understood that the reference ground in the aforementioned embodiments may be replaced by other non-zero reference potentials (having positive or negative voltage amplitudes) or controlled varying reference signals in alternative embodiments.

[0049] For another example, the capacitors and resistors provided in the embodiments of the present application may be lumped parameter capacitor elements and resistor elements, or may be other equivalent elements with similar functions to capacitors and resistors. The equivalent structures described here include, but are not limited to, structures that can provide impedance and / or capacitive impedance, such as microstrip lines, varactors, and conductor structures with certain patterns.

[0050] At the same time, those skilled in the art will appreciate that, in conjunction with the various exemplary structures and methods described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used for each structure or reasonable variations of the structure to achieve the described functions, but such implementations should not be considered beyond the scope of this application. Furthermore, it should be understood that the connection relationships between the various components of the amplifier in the aforementioned figures in the embodiments of this application are for illustrative purposes only and do not impose any limitations on the embodiments of this application.

[0051] In summary, the embodiments of the present invention provide a differential signal generating circuit that can generate accurate differential signals by using a basic oscillator structure and a logic module, and has a simple circuit structure and low cost.

[0052] In some optional embodiments, the present application addresses the problem of duty cycle easily offset in low voltage applications and uses a simple duty cycle adjustment circuit to perform correction, thereby further increasing the accuracy of the differential signal.

[0053] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0054] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A differential signal generating circuit, comprising: an oscillator for generating a plurality of clock signals, wherein the oscillator comprises N stages of inverters connected to each other, N being greater than 0 and an integer multiple of 3, the output ends of the N stages of inverters providing the plurality of clock signals, and the plurality of clock signals having an initial phase difference between them; and a logic module, providing a differential signal pair with complementary phases according to the plurality of clock signals, The logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter. The plurality of clock signals include a first signal, a second signal and a third signal, The fifth inverter receives the first signal, the sixth inverter receives the third signal, and the seventh inverter receives the second signal. The output terminal of the fifth inverter is connected to the output terminal of the sixth inverter and is also connected to the input terminal of the eighth inverter. The output terminal of the seventh inverter is connected to the input terminal of the ninth inverter, The eighth inverter and the ninth inverter provide the differential signal pair.

2. The differential signal generating circuit according to claim 1, wherein: The initial phase difference is 360 / N°.

3. The differential signal generating circuit according to claim 1, wherein: The N-stage inverters include a first inverter, a second inverter, and a third inverter connected in parallel between a signal source and a reference ground, and the multiple clock signals include a first signal, a second signal, and a third signal. The control terminal of the first inverter is connected to the output terminal of the third inverter, the control terminal of the second inverter is connected to the output terminal of the first inverter, and the control terminal of the third inverter is connected to the output terminal of the second inverter. The output terminal of the first inverter provides the first signal, the output terminal of the second inverter provides the second signal, and the output terminal of the third inverter provides the third signal.

4. The differential signal generating circuit according to any one of claims 1 to 3, wherein: Each of the inverters comprises: A first switching tube and a second switching tube are connected in series between a signal source and a reference ground, control terminals of the first switching tube and the second switching tube are connected to each other and serve as the control terminal of the inverter, a first current terminal of the first switching tube is connected to the signal source, a second current terminal of the first switching tube is connected to the first current terminal of the second switching tube, a second current terminal of the second switching tube is connected to the reference ground, and a connection node between the second current terminal of the first switching tube and the first current terminal of the second switching tube serves as the output terminal of the inverter.

5. The differential signal generating circuit according to claim 1 , further comprising: The duty cycle adjustment module is connected between the oscillator and the logic module, and is used to adjust the duty cycle of each of the clock signals respectively.

6. The differential signal generating circuit according to claim 5, wherein: The duty cycle adjustment module includes a plurality of sub-adjustment modules corresponding to the plurality of clock signals, so as to adjust the duty cycles of the plurality of clock signals to within a predetermined range respectively.

7. The differential signal generating circuit according to claim 6, wherein: Each of the sub-adjustment modules includes: a duty cycle detection circuit, configured to obtain a detection signal representing the duty cycle of the clock signal based on the clock signal; and The duty cycle adjustment circuit adjusts the duty cycle of the clock signal according to the detection signal.

8. The differential signal generating circuit according to claim 7, wherein: The duty cycle detection circuit includes a first resistor and a first capacitor and a second capacitor connected in series between a voltage source and a reference ground, wherein a first end of the first resistor receives the clock signal, and a second end of the first resistor is connected to a series node of the first capacitor and the second capacitor and provides the detection signal; The duty cycle adjustment circuit includes a fourth inverter, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The third switch and the fourth switch are connected in series between a voltage source and a reference ground, respectively. The fifth switch, the sixth switch, the seventh switch, and the eighth switch are connected in series between the voltage source and the reference ground, respectively. The clock signal is connected to the control terminals of the third switch, the fourth switch, the fifth switch, and the eighth switch through the fourth inverter. The detection signal is connected to the control terminals of the sixth switch and the seventh switch. The series node between the third and fourth switches is connected to the series node between the sixth and seventh switches to provide a calibrated clock signal.

9. The differential signal generating circuit according to claim 8, wherein: The clock signal is corrected by adjusting the driving capabilities of the sixth switching tube and the seventh switching tube.

Images