Signal acquisition circuit and signal acquisition equipment
By grounding the common mode output end of the first-stage fully differential op amp module and adjusting the output signal using the baseline conditioning module, the baseline drift problem when a single-ended input signal is solved, and efficient signal acquisition without noise increases is achieved.
Patent Information
- Application Number
- CN202510109980.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-30
AI Technical Summary
In the field of digital acquisition technology, when a single-ended input signal passes through the first-stage fully differential op amp, if the source signal is not connected, baseline drifting is likely to occur, and existing solutions increase hardware costs or increase link noise.
A signal acquisition circuit is designed, including an input module, a first-level fully differential op amp module, a baseline conditioning module and a signal acquisition module. By grounding the common mode output terminal of the first-level fully differential op amp module and adjusting the output signal using the baseline conditioning module, baseline conditioning without adding an additional op amp is achieved.
It effectively suppresses baseline drift, reduces link noise, increases ENOB of the acquisition link without increasing hardware costs.
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Figure CN120074523A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital acquisition technology, and particularly to a signal acquisition circuit and a signal acquisition device. Background Art
[0002] In the current field of digital acquisition technology, when processing a single-ended input signal and the first-stage input stage uses an FDA (Fully Differential Amplifier), if the source signal is not connected, the acquisition link often encounters a significant baseline drift problem. This is mainly because when the single-ended input of the FDA is disconnected, the mismatch of its input impedance causes the common-mode voltage to feedback to the input terminal, resulting in a voltage difference between the two input terminals, thereby causing baseline drift.
[0003] To address this problem, traditionally two solutions are often adopted: One solution is to add a stage of general-purpose operational amplifier before the FDA to achieve impedance transformation, but this method not only increases the hardware cost but also introduces additional noise, deteriorates the signal-to-noise ratio, and increases harmonic distortion; Another solution is to add another stage of FDA between the FDA and the ADC for signal correction. However, this also brings an increase in cost and an increase in link noise, ultimately resulting in a reduction in the ENOB (Effective Number of Bits) of the acquisition link.
[0004] Therefore, how to effectively suppress baseline drift without increasing link noise is a technical problem that urgently needs to be solved at present. Summary of the Invention
[0005] The main purpose of this application is to provide a signal acquisition circuit and a signal acquisition device, aiming to effectively suppress baseline drift without increasing link noise.
[0006] To achieve the above object, this application provides a signal acquisition circuit, which includes an input module, a first-stage fully differential amplifier module, a baseline conditioning module, and a signal acquisition module;
[0007] The signal source terminal of the input module is electrically connected to the non-inverting input terminal of the first-stage fully differential amplifier module, the output terminal of the first-stage fully differential amplifier module is electrically connected to the signal acquisition module through the baseline conditioning module, and the common-mode output terminal of the first-stage fully differential amplifier module is grounded.
[0008] In an embodiment, the baseline conditioning module includes a first output conditioning unit and a second output conditioning unit;
[0009] The input end of the first output conditioning unit is electrically connected to the non-inverting output end of the first-stage fully differential operational amplifier module, and the output end of the first output conditioning unit is electrically connected to the first acquisition end of the signal acquisition module;
[0010] The input end of the second output conditioning unit is electrically connected to the inverting output end of the first-stage fully differential operational amplifier module, and the output end of the second output conditioning unit is electrically connected to the second acquisition end of the signal acquisition module; wherein,
[0011] The non-inverting output end and the inverting output end of the first-stage fully differential operational amplifier module constitute the output end of the first-stage fully differential operational amplifier module.
[0012] In one embodiment, the first output conditioning unit includes a first resistor, a second resistor, a first capacitor, and a first current source;
[0013] The first end of the first resistor is electrically connected to the non-inverting output end of the first-stage fully differential operational amplifier module, and the second end of the first resistor is electrically connected to the first end of the first capacitor and the first acquisition end of the signal acquisition module respectively;
[0014] The first end of the second resistor is electrically connected to the first end of the first capacitor, the second end of the second resistor is grounded through the first current source, and the second end of the first capacitor is grounded.
[0015] In one embodiment, the second output conditioning unit includes a third resistor, a fourth resistor, a second capacitor, and a second current source;
[0016] The first end of the third resistor is electrically connected to the inverting output end of the first-stage fully differential operational amplifier module, and the second end of the third resistor is electrically connected to the first end of the second capacitor and the second acquisition end of the signal acquisition module respectively;
[0017] The first end of the fourth resistor is electrically connected to the first end of the second capacitor, the second end of the fourth resistor is grounded through the second current source, and the second end of the second capacitor is grounded.
[0018] In one embodiment, the first-stage fully differential operational amplifier module includes a differential operational amplifier unit, a positive feedback unit, and a negative feedback unit;
[0019] The positive input end of the differential operational amplifier unit is electrically connected to the first end of the positive feedback unit and the signal source end of the input module respectively, and the second end of the positive feedback unit is electrically connected to the first output end of the differential operational amplifier unit;
[0020] The negative input terminal of the differential operational amplifier unit is electrically connected to the first end of the negative feedback unit, and the second end of the negative feedback unit is electrically connected to the second output terminal of the differential operational amplifier unit; wherein,
[0021] The positive input terminal of the differential operational amplifier unit constitutes the in-phase input terminal of the first-stage fully differential operational amplifier module, the first output terminal of the differential operational amplifier unit constitutes the in-phase output terminal of the first-stage fully differential operational amplifier module, and the second output terminal of the differential operational amplifier unit constitutes the anti-phase output terminal of the first-stage fully differential operational amplifier module.
[0022] In an embodiment, the signal acquisition circuit further includes a bias calibration module. The differential operational amplifier unit includes a differential operational amplifier, a first terminal connection resistor, a second terminal connection resistor, a fifth resistor, and a sixth resistor;
[0023] The in-phase input terminal of the differential operational amplifier is electrically connected to the signal source terminal of the input module through the fifth resistor. The first end of the first terminal connection resistor is electrically connected between the fifth resistor and the signal source terminal of the input module, and the second end of the first terminal connection resistor is grounded. The first end of the positive feedback unit is electrically connected between the in-phase input terminal of the differential operational amplifier and the fifth resistor, and the second end of the positive feedback unit is electrically connected to the first output terminal of the differential operational amplifier;
[0024] The anti-phase input terminal of the differential operational amplifier is electrically connected to the bias calibration module through the sixth resistor. The first end of the second terminal connection resistor is electrically connected between the sixth resistor and the bias calibration module, and the second end of the second terminal connection resistor is grounded. The common-mode voltage terminal of the differential operational amplifier constitutes the common-mode output terminal of the first-stage fully differential operational amplifier module and is grounded. The first end of the negative feedback unit is electrically connected between the anti-phase input terminal of the differential operational amplifier and the sixth resistor, and the second end of the negative feedback unit is electrically connected to the second output terminal of the differential operational amplifier; wherein,
[0025] The in-phase input terminal of the differential operational amplifier constitutes the positive input terminal of the differential operational amplifier unit, the anti-phase input terminal of the differential operational amplifier constitutes the negative input terminal of the differential operational amplifier unit, the first output terminal of the differential operational amplifier constitutes the first output terminal of the differential operational amplifier unit, and the second output terminal of the differential operational amplifier constitutes the second output terminal of the differential operational amplifier unit.
[0026] In an embodiment, the positive feedback unit includes a first feedback resistor, and the negative feedback unit includes a second feedback resistor;
[0027] The first end of the first feedback resistor constitutes the first end of the positive feedback unit and is electrically connected between the in-phase input terminal of the differential operational amplifier and the fifth resistor;
[0028] The second end of the first feedback resistor forms the second end of the positive feedback unit and is electrically connected to the first output end of the differential operational amplifier;
[0029] The first end of the second feedback resistor forms the first end of the negative feedback unit and is electrically connected between the inverting input end of the differential operational amplifier and the sixth resistor;
[0030] The second end of the second feedback resistor forms the second end of the negative feedback unit and is electrically connected to the second output end of the differential operational amplifier.
[0031] In one embodiment, the bias calibration module includes a seventh resistor, an operational amplifier, and a digital-to-analog converter;
[0032] The first end of the seventh resistor is electrically connected to the first end of the second-terminal connection resistor, the second end of the seventh resistor is electrically connected to the output end of the operational amplifier, the inverting input end of the operational amplifier is electrically connected between the second end of the seventh resistor and the output end of the operational amplifier, and the non-inverting input end of the operational amplifier is electrically connected to the digital-to-analog converter.
[0033] In one embodiment, the input module includes an AC signal source and an eighth resistor;
[0034] The first end of the AC signal source forms the signal source end of the input module and is electrically connected to the non-inverting input end of the first-stage fully differential operational amplifier module through the eighth resistor, and the second end of the AC signal source is grounded.
[0035] In addition, to achieve the above object, the present application further provides a signal acquisition device, and the signal acquisition device includes the signal acquisition circuit described in any one of the above.
[0036] The signal acquisition circuit provided by the present application integrates an input module, a first-stage fully differential operational amplifier module, a baseline conditioning module, and a signal acquisition module, and realizes effective suppression of baseline drift while not increasing link noise. Specifically, the present application directly electrically connects the signal source end of the input module to the non-inverting input end of the first-stage fully differential operational amplifier module, and grounds the common-mode output end of the first-stage fully differential operational amplifier module, thereby solving the baseline offset caused by the impedance mismatch between the non-inverting end impedance and the inverting end impedance of the first-stage fully differential operational amplifier module; Next, the baseline conditioning module is electrically connected between the output end of the first-stage fully differential operational amplifier module and the signal acquisition module. Without adding an additional operational amplifier, only through the baseline conditioning module, the output of the first-stage fully differential operational amplifier module meets the input range of the signal acquisition module, thereby realizing the normal operation of the link of the signal acquisition circuit, effectively reducing the link noise, and effectively improving the ENOB of the acquisition link. Brief Description of the Drawings
[0037] Figure 1 Schematic diagram of the signal acquisition circuit structure involved in the solution of the embodiment of the present application;
[0038] Figure 2 Block diagram of the signal acquisition circuit structure involved in the solution of the embodiment of the present application;
[0039] Figure 3 Schematic diagram of the signal acquisition circuit involved in the solution of the embodiment of the present application;
[0040] Figure 4 Schematic diagram of the signal acquisition device structure involved in the solution of the embodiment of the present application;
[0041] Figure 5 Schematic diagram of the structure of the terminal device involved in the solution of the embodiment of the present application.
[0042] Explanation of the reference numerals in the drawings: 10, input module; 20, first-stage fully differential operational amplifier module; 30, baseline conditioning module; 40, signal acquisition module; 21, differential operational amplifier unit; 22, positive feedback unit; 23, negative feedback unit; 31, first output conditioning unit; 32, second output conditioning unit; R1, first resistor; R2, second resistor; C1, first capacitor; 310, first current source; R3, third resistor; R4, fourth resistor; C1, second capacitor; 320, second current source; U1, differential operational amplifier; RT1, first termination resistor; RT2, second termination resistor; R5, fifth resistor; R6, sixth resistor; Rf1, first feedback resistor; Rf2, second feedback resistor; R7, seventh resistor; U2, operational amplifier; 51, digital-to-analog converter; AC1, AC signal source; R8, eighth resistor.
[0043] The realization, functional features and advantages of the purpose of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed Embodiments
[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0045] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.
[0046] In addition, if the descriptions such as "first" and "second" are involved in the embodiments of the present application, these descriptions of "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.
[0047] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.
[0048] In the current field of digital acquisition technology, when processing a single-ended input signal and the first-stage input stage uses an FDA (Fully Differential Amplifier), if the source signal is not connected, the acquisition link often encounters a significant baseline drift problem. This is mainly because when the single-ended input of the FDA is disconnected, the mismatch of its input impedance causes the common-mode voltage to be fed back to the input terminal, thereby generating a voltage difference between the two input terminals, which in turn causes baseline drift.
[0049] To address this problem, traditionally two solutions are often adopted: One solution is to add a stage of general-purpose op-amp before the FDA to achieve impedance transformation, but this method not only increases the hardware cost but also introduces additional noise, deteriorates the signal-to-noise ratio, and increases harmonic distortion; Another solution is to add another stage of FDA between the FDA and the ADC for signal correction. However, this also brings an increase in cost and an increase in link noise, ultimately resulting in a reduction in the ENOB (Effective Number of Bits) of the acquisition link.
[0050] Therefore, how to effectively suppress baseline drift without increasing link noise is a technical problem that urgently needs to be solved at present.
[0051] In summary, to solve the above technical problems, the embodiments of the present application provide a signal acquisition circuit, as shown in Figure 1 shown Figure 1 is a schematic structural diagram of the signal acquisition circuit involved in the solution of the embodiments of the present application.
[0052] The signal acquisition circuit of the present application includes an input module 10, a first-stage fully differential operational amplifier module 20, a baseline conditioning module 30, and a signal acquisition module 40; the signal source terminal of the input module 10 is electrically connected to the non-inverting input terminal of the first-stage fully differential operational amplifier module 20, the output terminal of the first-stage fully differential operational amplifier module 20 is electrically connected to the signal acquisition module 40 through the baseline conditioning module 30, and the common-mode output terminal of the first-stage fully differential operational amplifier module 20 is grounded.
[0053] In this embodiment, a reference voltage Vref is generally connected to the common-mode output terminal of the traditional first-stage fully differential operational amplifier module 20 to meet the input voltage range of the subsequent signal acquisition module 40. When the signal source terminal of the input module 10 is disconnected from the non-inverting input terminal of the first-stage fully differential operational amplifier module 20, that is, when the single-ended input signal provided by the input module 10 is disconnected, if the common-mode output terminal of the first-stage fully differential operational amplifier module 20 is connected to the reference voltage Vref, due to the mismatch of the input impedance, the common-mode voltage Vref will be fed back to the non-inverting input terminal of the first-stage fully differential operational amplifier module 20, causing a voltage difference between the non-inverting input terminal and the inverting input terminal to generate a large DC voltage, thereby generating a baseline offset. To effectively suppress the baseline drift, the present application grounds the common-mode output terminal of the first-stage fully differential operational amplifier module 20, which can prevent the common-mode voltage Vref from being fed back to the two input terminals of the first-stage fully differential operational amplifier module 20 (i.e., the non-inverting input terminal and the inverting input terminal of the first-stage fully differential operational amplifier module 20) when the single-ended input signal is disconnected. That is to say, grounding the common-mode output terminal of the first-stage fully differential operational amplifier module 20 can provide a low-impedance path, making the common-mode voltage Vref unable to affect the two input terminals of the first-stage fully differential operational amplifier module 20, so that the differential signal output by the first-stage fully differential operational amplifier module 20 will not generate a baseline offset; Next, the present application introduces a baseline conditioning module 30 between the output terminal of the first-stage fully differential operational amplifier module 20 and the signal acquisition module 40, achieving the purpose of adjusting the differential signal output by the first-stage fully differential operational amplifier module 20 to meet the input range of the signal acquisition module 40 without adding an additional operational amplifier, thereby avoiding the cost and link noise problems brought by adding an additional operational amplifier, not only saving the cost of the signal acquisition circuit, but also effectively reducing the link noise and improving the ENOB of the acquisition link, thus ensuring the accuracy of the signals acquired by the subsequent signal acquisition module 40.
[0054] It should be noted that the input module 10 is configured to provide a single-ended input signal to the first-stage fully differential operational amplifier module 20; the first-stage fully differential operational amplifier module 20 is configured to convert the single-ended input signal received at its non-inverting input terminal into a differential signal and then output it.
[0055] Further, in some feasible embodiments, the baseline conditioning module 30 includes a first output conditioning unit 31 and a second output conditioning unit 32; the input end of the first output conditioning unit 31 is electrically connected to the in-phase output end of the first-stage fully differential operational amplifier module 20, and the output end of the first output conditioning unit 31 is electrically connected to the first acquisition end of the signal acquisition module 40; the input end of the second output conditioning unit 32 is electrically connected to the anti-phase output end of the first-stage fully differential operational amplifier module 20, and the output end of the second output conditioning unit 32 is electrically connected to the second acquisition end of the signal acquisition module 40; wherein, the in-phase output end and the anti-phase output end of the first-stage fully differential operational amplifier module 20 constitute the output end of the first-stage fully differential operational amplifier module 20.
[0056] In this embodiment, the baseline conditioning module 30 provided in the present application is composed of a first output conditioning unit 31 and a second output conditioning unit 32. The first output conditioning unit 31 and the second output conditioning unit 32 are respectively connected to the in-phase output end and the anti-phase output end of the first-stage fully differential operational amplifier module 20, and then transmit the conditioned differential signal to the signal acquisition module 40, so as to achieve accurate adjustment of the differential signal to meet the input range requirements of the signal acquisition module 40 without adding an additional operational amplifier, effectively reducing the cost and link noise.
[0057] It should be noted that a differential signal can be understood as a pair of electrical signals that are equal in amplitude and 180° out of phase (i.e., in opposite directions). Exemplarily, the electrical signal at the in-phase output end of the first-stage fully differential operational amplifier module 20 and the electrical signal at the anti-phase output end of the first-stage fully differential operational amplifier module 20 constitute the differential signal.
[0058] In a specific embodiment, the first output conditioning unit 31 is responsible for receiving the electrical signal from the in-phase output end of the first-stage fully differential operational amplifier module 20, and appropriately conditioning the electrical signal at the in-phase output end of the first-stage fully differential operational amplifier module 20 and then transmitting it to the first acquisition end of the signal acquisition module 40. Similarly, the second output conditioning unit 32 processes the signal from the anti-phase output end of the first-stage fully differential operational amplifier module 20 and transmits the conditioned result to the second acquisition end of the signal acquisition module 40, which not only ensures that the differential signal can accurately meet the input range requirements of the signal acquisition module 40 after passing through the baseline conditioning module 30, but also does not introduce an additional operational amplifier during the whole process, thereby effectively reducing the system cost and link noise and improving the efficiency and accuracy of signal processing.
[0059] Further, in some other feasible embodiments, referring to Figure 3 , Figure 3Schematic diagram of the signal acquisition circuit involved in the solution of the embodiment of the present application. The first output conditioning unit 31 includes a first resistor R1, a second resistor R2, a first capacitor C1, and a first current source 310; the first end of the first resistor R1 is electrically connected to the non-inverting output terminal of the first-stage fully differential operational amplifier module 20, and the second end of the first resistor R1 is respectively electrically connected to the first end of the first capacitor C1 and the first acquisition terminal of the signal acquisition module 40; the first end of the second resistor R2 is electrically connected to the first end of the first capacitor C1, the second end of the second resistor R2 is grounded through the first current source 310, and the second end of the first capacitor C1 is grounded.
[0060] In this embodiment, the first output conditioning unit 31 integrates a first resistor R1, a second resistor R2, a first capacitor C1, and a first current source 310. The first output conditioning unit 31 directly obtains an electrical signal from the non-inverting output terminal of the first-stage fully differential operational amplifier module 20 through the first resistor R1, and uses the RC network formed by the first capacitor C1 and the second resistor R2 for filtering, effectively smoothing the high-frequency noise in the electrical signal. At the same time, the cooperation of the first current source 310 and the second resistor R2 provides a stable DC bias for the signal acquisition circuit, further enhancing the stability and accuracy of the signal. Next, the electrical signal output from the non-inverting output terminal of the first-stage fully differential operational amplifier module 20 is conditioned by the first output conditioning unit 31 and then transmitted to the first acquisition terminal of the signal acquisition module 40, which not only meets the requirements of the signal acquisition module 40 for the input signal range, but also significantly improves the purity and reliability of the signal, thereby optimizing the performance of the entire signal processing link.
[0061] In a specific embodiment, in the DC analysis scenario, since the common-mode output pin VCOM of the differential operational amplifier U1 (i.e., the common-mode voltage terminal of the differential operational amplifier U1) is grounded, when the single-ended input signal provided by the input module 10 is disconnected, no voltage difference will be generated between the two input terminals of the differential operational amplifier U1, so there will be no problem of baseline drift. In addition, the common-mode voltage is added by using the voltage division of the first resistor R1 to meet the input common-mode range of the subsequent ADC, that is, the voltage Va at point a = VCOM (i.e., the input common-mode voltage of the signal acquisition module 40), and then the first resistor R1 can be calculated.
[0062] Further, in some feasible embodiments, referring to Figure 3, the second output conditioning unit 32 includes a third resistor R3, a fourth resistor R4, a second capacitor C2, and a second current source 320; a first end of the third resistor R3 is electrically connected to an inverting output end of the first-stage fully differential operational amplifier module 20, and a second end of the third resistor R3 is electrically connected to a first end of the second capacitor C2 and a second acquisition end of the signal acquisition module 40 respectively; a first end of the fourth resistor R4 is electrically connected to the first end of the second capacitor C2, a second end of the fourth resistor R4 is grounded through the second current source 320, and a second end of the second capacitor C2 is grounded.
[0063] In this embodiment, the second output conditioning unit 32 integrates the third resistor R3, the fourth resistor R4, the second capacitor C2, and the second current source 320 to form an efficient and stable signal processing path. The second output conditioning unit 32 directly captures the electrical signal from the inverting output end of the first-stage fully differential operational amplifier module 20 and transmits it through the third resistor R3 between the second capacitor C2 and the second acquisition end of the signal acquisition module 40. During this process, the RC filter network composed of the second capacitor C2 and the fourth resistor R4 plays a key role, effectively filtering out high-frequency noise and clutter in the electrical signal, making the electrical signal smoother and purer. At the same time, the ingenious combination of the second current source 320 and the fourth resistor R4 provides a constant current reference for the circuit, further enhancing the stability and anti-interference ability of the signal. After this series of conditioning, the finally output conditioned electrical signal not only meets the requirements of the signal acquisition module 40 for high-quality input, but also significantly improves the performance and reliability of the entire signal processing system, providing a more accurate and reliable signal basis for subsequent data analysis.
[0064] In a specific embodiment, in the AC analysis scenario, since the output impedances of the first current source 310 and the second current source 320 are high impedances, there is no voltage division, ensuring that the voltage input to the signal acquisition module 40 (i.e., the analog-to-digital converter, ADC) does not attenuate and the gain of the differential operational amplifier U1 (i.e., the FDA) remains unchanged. In addition, the first capacitor C1 and the second resistor R2, as well as the second capacitor C2 and the fourth resistor R4, can form low-pass filters for filtering out noise. Exemplarily, the calculation method of the -3dB bandwidth of the low-pass filter composed of the first capacitor C1 and the second resistor R2 is shown in the following formula, and the first capacitor C1 can be calculated according to the required bandwidth of the link:
[0065]
[0066] where, BW -3dB represents the -3dB bandwidth, R 1 represents the resistance value of the first resistor R1, R 2 represents the resistance value of the first resistor R1, C 1Represents the capacitance value of the first capacitor C1.
[0067] Further, in some other feasible embodiments, referring to Figure 3 , the first-stage fully differential operational amplifier module 20 includes a differential operational amplifier unit 21, a positive feedback unit 22, and a negative feedback unit 23; the positive input terminal of the differential operational amplifier unit 21 is electrically connected to the first end of the positive feedback unit 22 and the signal source terminal of the input module 10 respectively, and the second end of the positive feedback unit 22 is electrically connected to the first output terminal of the differential operational amplifier unit 21; the negative input terminal of the differential operational amplifier unit 21 is electrically connected to the first end of the negative feedback unit 23, and the second end of the negative feedback unit 23 is electrically connected to the second output terminal of the differential operational amplifier unit 21; wherein, the positive input terminal of the differential operational amplifier unit 21 constitutes the non-inverting input terminal of the first-stage fully differential operational amplifier module 20, the first output terminal of the differential operational amplifier unit 21 constitutes the non-inverting output terminal of the first-stage fully differential operational amplifier module 20, and the second output terminal of the differential operational amplifier unit 21 constitutes the inverting output terminal of the first-stage fully differential operational amplifier module 20.
[0068] In this embodiment, the first-stage fully differential operational amplifier module 20 integrates the differential operational amplifier unit 21, the positive feedback unit 22, and the negative feedback unit 23, realizing the efficient amplification and precise processing of single-ended input signals. The non-inverting input terminal of the first-stage fully differential operational amplifier module 20 is directly connected to the signal source terminal of the input module 10, and at the same time, the positive feedback unit 22 is introduced, thereby enhancing the sensitivity and response speed of the single-ended input signal, enabling weak signals to be effectively amplified. The negative input terminal of the differential operational amplifier unit 21 is connected to the negative feedback unit 23, forming a closed-loop feedback system, effectively suppressing the non-linear distortion and gain fluctuation in the circuit, and ensuring the stability and accuracy of the output signal.
[0069] It should be noted that the positive input terminal of the differential operational amplifier unit 21 constitutes the non-inverting input terminal of the first-stage fully differential operational amplifier module 20, which can provide an amplified signal consistent with the single-ended input signal; the second output terminal of the differential operational amplifier unit 21 constitutes the inverting output terminal of the first-stage fully differential operational amplifier module 20 to output an amplified signal with a phase opposite to that of the single-ended input signal, which not only improves the anti-interference ability of the signal, but also enables the output signal to have a higher dynamic range and a lower noise level, providing a high-quality signal basis for subsequent signal conditioning and acquisition, and greatly enhancing the performance and reliability of the entire signal processing system.
[0070] Further, in some feasible embodiments, referring to Figure 3, the signal acquisition circuit further includes a bias calibration module. The differential operational amplifier unit 21 includes a differential operational amplifier U1, a first termination resistor RT1, a second termination resistor RT2, a fifth resistor R5, and a sixth resistor R6. The non-inverting input terminal of the differential operational amplifier U1 is electrically connected to the signal source terminal of the input module 10 through the fifth resistor R5. The first terminal of the first termination resistor RT1 is electrically connected between the fifth resistor R5 and the signal source terminal of the input module 10, and the second terminal of the first termination resistor RT1 is grounded. The first terminal of the positive feedback unit 22 is electrically connected between the non-inverting input terminal of the differential operational amplifier U1 and the fifth resistor R5, and the second terminal of the positive feedback unit 22 is electrically connected to the first output terminal of the differential operational amplifier U1. The inverting input terminal of the differential operational amplifier U1 is electrically connected to the bias calibration module through the sixth resistor R6. The first terminal of the second termination resistor RT2 is electrically connected between the sixth resistor R6 and the bias calibration module, and the second terminal of the second termination resistor RT2 is grounded. The common-mode voltage terminal of the differential operational amplifier U1 constitutes the common-mode output terminal of the first-stage fully differential operational amplifier module 20 and is grounded. The first terminal of the negative feedback unit 23 is electrically connected between the inverting input terminal of the differential operational amplifier U1 and the sixth resistor R6, and the second terminal of the negative feedback unit 23 is electrically connected to the second output terminal of the differential operational amplifier U1. Among them, the non-inverting input terminal of the differential operational amplifier U1 constitutes the positive input terminal of the differential operational amplifier unit 21, the inverting input terminal of the differential operational amplifier U1 constitutes the negative input terminal of the differential operational amplifier unit 21, the first output terminal of the differential operational amplifier U1 constitutes the first output terminal of the differential operational amplifier unit 21, and the second output terminal of the differential operational amplifier U1 constitutes the second output terminal of the differential operational amplifier unit 21.
[0071] In this embodiment, the first terminal of the first termination resistor RT1 is electrically connected between the fifth resistor R5 and the signal source terminal of the input module 10, which can make the input impedance of the signal acquisition circuit match the output impedance of the signal source; the first terminal of the second termination resistor RT2 is electrically connected between the sixth resistor R6 and the bias calibration module, which can also make the input impedance of the signal acquisition circuit match the output impedance of the signal source.
[0072] Further, in some other feasible embodiments, refer to Figure 3, the positive feedback unit 22 includes a first feedback resistor Rf1, and the negative feedback unit 23 includes a second feedback resistor Rf2; the first end of the first feedback resistor Rf1 constitutes the first end of the positive feedback unit 22 and is electrically connected between the non-inverting input terminal of the differential operational amplifier U1 and the fifth resistor R5; the second end of the first feedback resistor Rf1 constitutes the second end of the positive feedback unit 22 and is electrically connected to the first output terminal of the differential operational amplifier U1; the first end of the second feedback resistor Rf2 constitutes the first end of the negative feedback unit 23 and is electrically connected between the inverting input terminal of the differential operational amplifier U1 and the sixth resistor R6; the second end of the second feedback resistor Rf2 constitutes the second end of the negative feedback unit 23 and is electrically connected to the second output terminal of the differential operational amplifier U1.
[0073] In this embodiment, the positive feedback unit 22 provided in the present application is the first feedback resistor Rf1, and the negative feedback unit 23 is the second feedback resistor Rf2, which significantly optimizes the performance of the differential operational amplifier U1. Specifically, the first feedback resistor Rf1 connects the non-inverting input terminal of the differential operational amplifier U1 to the first output terminal, forming a positive feedback path, which helps to enhance the gain of the circuit. Especially in application scenarios where weak signals need to be amplified or the circuit sensitivity needs to be improved, the introduction of positive feedback can significantly enhance the signal amplification effect. At the same time, positive feedback can also improve the frequency response of the circuit to a certain extent, making the performance of the circuit more stable within a specific frequency band. On the other hand, the second feedback resistor Rf2 connects the inverting input terminal of the differential operational amplifier U1 to the second output terminal, forming a negative feedback path, which can effectively reduce the distortion and noise of the circuit and improve the linearity and stability of the circuit. Through negative feedback, the output signal of the signal acquisition circuit will be fed back to the input terminal and subtracted from the original input signal, thereby reducing the output error caused by nonlinear elements or external environment changes, enabling the differential operational amplifier U1 to maintain a stable output within a wider input range, and enhancing the anti-interference ability and adaptability of the signal acquisition circuit.
[0074] Further, in some feasible embodiments, referring to Figure 3 , the bias calibration module includes a seventh resistor R7, an operational amplifier U2, and a digital-to-analog converter 51; the first end of the seventh resistor R7 is electrically connected to the first end of the resistor RT2, the second end of the seventh resistor R7 is electrically connected to the output terminal of the operational amplifier U2, the inverting input terminal of the operational amplifier U2 is electrically connected between the second end of the seventh resistor R7 and the output terminal of the operational amplifier U2, and the non-inverting input terminal of the operational amplifier U2 is electrically connected to the digital-to-analog converter 51.
[0075] In this embodiment, the bias calibration module integrates a seventh resistor R7, an operational amplifier U2, and a digital-to-analog converter 51, achieving the calibration of the offset voltage of the differential operational amplifier U1. The digital-to-analog converter 51 outputs an accurate analog voltage according to a preset digital signal. This voltage is sent to the operational amplifier U2 as a bias voltage, and then used to calibrate the offset voltage of the differential operational amplifier U1. This not only significantly reduces the inherent offset voltage of the differential operational amplifier U1, improves the accuracy and linearity of the circuit, but also enhances the robustness of the circuit against factors such as temperature changes and component aging, providing more stable and reliable amplification performance for the entire signal processing system.
[0076] Furthermore, in some other feasible embodiments, referring to Figure 3 , the input module 10 includes an AC signal source AC1 and an eighth resistor R8; the first end of the AC signal source AC1 constitutes the signal source end of the input module 10 and is electrically connected to the non-inverting input terminal of the first-stage fully differential operational amplifier module 20 through the eighth resistor R8, and the second end of the AC signal source AC1 is grounded.
[0077] In this embodiment, the input module 10 realizes the precise regulation and efficient transmission of a single-ended input signal by integrating the AC signal source AC1 and the eighth resistor R8. The first end of the AC signal source AC1 serves as the signal source end of the input module 10 and is connected to the non-inverting input terminal of the first-stage fully differential operational amplifier module 20 via the eighth resistor R8, which not only ensures the stable input of the single-ended input signal but also protects the first-stage fully differential operational amplifier module 20 from damage by excessive current through the current-limiting effect of the eighth resistor R8. At the same time, the second end of the AC signal source AC1 is grounded, providing a stable potential reference for the single-ended input signal and further improving the accuracy and integrity of the signal.
[0078] In summary, the signal acquisition circuit provided in this application uses a baseline conditioning module 30 built based on resistors, capacitors, and current sources to eliminate baseline drift in a hardware manner, solving the problem that a large baseline drift occurs in the acquisition link when the source end is not connected to a signal in the case of a single-ended input signal and the first-stage input stage being a fully differential operational amplifier. The baseline conditioning module 30 has a simple structure and does not require an additional operational amplifier. It only realizes the normal operation of the link through the series-parallel connection of resistors and capacitors, while reducing the link noise, improving the ENOB, and increasing the dynamic input range.
[0079] In addition, referring to Figure 4 , Figure 4 is a schematic structural diagram of a signal acquisition device related to the embodiment solution of this application. This application also provides a signal acquisition device, and the signal acquisition device includes the signal acquisition circuit described in any one of the above.
[0080] In addition, this application also provides a terminal device. Please refer to Figure 5, Figure 5 It is a schematic structural diagram of a terminal device involved in the solution of an embodiment of the present application. The terminal device in the embodiment of the present application may specifically be a device that runs a driver program of a signal acquisition circuit locally.
[0081] As Figure 5 shown, the terminal device in the embodiment of the present application may include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard). Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).
[0082] The memory 1005 is provided on the main body of the terminal device. A program is stored on the memory 1005, and when the program is executed by the processor 1001, corresponding operations are realized. The memory 1005 is also used to store parameters for the terminal device to use. The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0083] Those skilled in the art can understand that Figure 5 the structure of the terminal device shown in does not constitute a limitation on the terminal device, and it may include more or fewer components than shown in the figure, or combine some components, or have different component arrangements.
[0084] As Figure 5 shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a driver program of the signal acquisition circuit of the terminal device.
[0085] In Figure 5 the terminal device shown, the processor 1001 may be used to call the driver program of the signal acquisition circuit of the terminal device stored in the memory 1005.
[0086] It should be noted that in this document, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or system. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or system comprising that element.
[0087] The serial numbers of the embodiments of the present application above are for description only and do not represent the superiority or inferiority of the embodiments.
[0088] From the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) as described above and includes several instructions for causing a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.
[0089] The above are only the preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.
Claims
1. A signal acquisition circuit, characterized in that: The signal acquisition circuit includes an input module, a first-stage fully differential operational amplifier module, a baseline conditioning module and a signal acquisition module; The signal source end of the input module is electrically connected to the in-phase input end of the first-stage fully differential operational amplifier module, the output end of the first-stage fully differential operational amplifier module is electrically connected to the signal acquisition module through the baseline conditioning module, and the common-mode output end of the first-stage fully differential operational amplifier module is grounded.
2. The signal acquisition circuit according to claim 1, characterized in that: The baseline conditioning module includes a first output conditioning unit and a second output conditioning unit; The input end of the first output conditioning unit is electrically connected to the in-phase output end of the first-stage fully differential operational amplifier module, and the output end of the first output conditioning unit is electrically connected to the first acquisition end of the signal acquisition module; The input end of the second output conditioning unit is electrically connected to the out-of-phase output end of the first-stage fully differential operational amplifier module, and the output end of the second output conditioning unit is electrically connected to the second acquisition end of the signal acquisition module; wherein, The in-phase output end of the first-stage fully differential operational amplifier module and the out-of-phase output end of the first-stage fully differential operational amplifier module constitute the output end of the first-stage fully differential operational amplifier module.
3. The signal acquisition circuit according to claim 2, characterized in that: The first output conditioning unit includes a first resistor, a second resistor, a first capacitor and a first current source; The first end of the first resistor is electrically connected to the in-phase output end of the first-stage fully differential operational amplifier module, and the second end of the first resistor is electrically connected to the first end of the first capacitor and the first acquisition end of the signal acquisition module respectively; A first end of the second resistor is electrically connected to a first end of the first capacitor, a second end of the second resistor is grounded through the first current source, and a second end of the first capacitor is grounded.
4. The signal acquisition circuit according to claim 2, characterized in that: The second output conditioning unit includes a third resistor, a fourth resistor, a second capacitor and a second current source; The first end of the third resistor is electrically connected to the inverting output end of the first-stage fully differential operational amplifier module, and the second end of the third resistor is electrically connected to the first end of the second capacitor and the second acquisition end of the signal acquisition module respectively; A first end of the fourth resistor is electrically connected to a first end of the second capacitor, a second end of the fourth resistor is grounded through the second current source, and a second end of the second capacitor is grounded.
5. The signal acquisition circuit according to claim 1, characterized in that: The first-stage fully differential operational amplifier module includes a differential operational amplifier unit, a positive feedback unit and a negative feedback unit; The positive input terminal of the differential operational amplifier unit is electrically connected to the first terminal of the positive feedback unit and the signal source terminal of the input module respectively, and the second terminal of the positive feedback unit is electrically connected to the first output terminal of the differential operational amplifier unit; The negative input terminal of the differential operational amplifier unit is electrically connected to the first terminal of the negative feedback unit, and the second terminal of the negative feedback unit is electrically connected to the second output terminal of the differential operational amplifier unit; wherein, The positive input end of the differential operational amplifier unit constitutes the in-phase input end of the first-stage fully differential operational amplifier module, the first output end of the differential operational amplifier unit constitutes the in-phase output end of the first-stage fully differential operational amplifier module, and the second output end of the differential operational amplifier unit constitutes the inverting output end of the first-stage fully differential operational amplifier module.
6. The signal acquisition circuit according to claim 5, characterized in that: The signal acquisition circuit further includes a bias calibration module, and the differential operational amplifier unit includes a differential operational amplifier, a first termination resistor, a second termination resistor, a fifth resistor, and a sixth resistor; The non-inverting input terminal of the differential operational amplifier is electrically connected to the signal source terminal of the input module through the fifth resistor, the first end of the first termination resistor is electrically connected between the fifth resistor and the signal source terminal of the input module, the second end of the first termination resistor is grounded, the first end of the positive feedback unit is electrically connected between the non-inverting input terminal of the differential operational amplifier and the fifth resistor, and the second end of the positive feedback unit is electrically connected to the first output terminal of the differential operational amplifier; The inverting input terminal of the differential operational amplifier is electrically connected to the bias calibration module through the sixth resistor, the first end of the second termination resistor is electrically connected between the sixth resistor and the bias calibration module, the second end of the second termination resistor is grounded, the common mode voltage terminal of the differential operational amplifier constitutes the common mode output terminal grounding of the first-stage fully differential operational amplifier module, the first end of the negative feedback unit is electrically connected between the inverting input terminal of the differential operational amplifier and the sixth resistor, and the second end of the negative feedback unit is electrically connected to the second output terminal of the differential operational amplifier; wherein, The non-inverting input terminal of the differential operational amplifier constitutes the positive input terminal of the differential operational amplifier unit, the inverting input terminal of the differential operational amplifier constitutes the negative input terminal of the differential operational amplifier unit, the first output terminal of the differential operational amplifier constitutes the first output terminal of the differential operational amplifier unit, and the second output terminal of the differential operational amplifier constitutes the second output terminal of the differential operational amplifier unit.
7. The signal acquisition circuit according to claim 6, characterized in that: The positive feedback unit includes a first feedback resistor, and the negative feedback unit includes a second feedback resistor; The first end of the first feedback resistor constitutes the first end of the positive feedback unit and is electrically connected between the non-inverting input terminal of the differential operational amplifier and the fifth resistor; The second end of the first feedback resistor constitutes the second end of the positive feedback unit and is electrically connected to the first output end of the differential operational amplifier; The first end of the second feedback resistor constitutes the first end of the negative feedback unit and is electrically connected between the inverting input terminal of the differential operational amplifier and the sixth resistor; The second end of the second feedback resistor constitutes the second end of the negative feedback unit and is electrically connected to the second output end of the differential operational amplifier.
8. The signal acquisition circuit according to claim 6, characterized in that: The bias calibration module includes a seventh resistor, an operational amplifier and a digital-to-analog converter; The first end of the seventh resistor is electrically connected to the first end of the second termination resistor, the second end of the seventh resistor is electrically connected to the output end of the operational amplifier, the inverting input end of the operational amplifier is electrically connected between the second end of the seventh resistor and the output end of the operational amplifier, and the non-inverting input end of the operational amplifier is electrically connected to the digital-to-analog converter.
9. The signal acquisition circuit according to claim 1, characterized in that: The input module includes an AC signal source and an eighth resistor; The first end of the AC signal source constitutes the signal source end of the input module, and is electrically connected to the in-phase input end of the first-stage fully differential operational amplifier module through the eighth resistor. The second end of the AC signal source is grounded.
10. A signal acquisition device, characterized in that: The signal acquisition device comprises the signal acquisition circuit according to any one of claims 1 to 9.