PAM3 transmitter, method of operating same, and electronic device including same

Abstract

A 3-level pulse amplitude modulation (PAM3) transmitter, an operation method of the PAM3 transmitter, and an electronic device including the PAM3 transmitter are provided. The PAM3 transmitter includes a driver configured to convert input data into a PAM3 signal, an eye monitor circuit electrically connected to an output terminal of the driver and configured to monitor an upper eye pattern and a lower eye pattern of the PAM3 signal, and a duty cycle adjustment circuit configured to adjust a duty cycle of the input data provided to the driver.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Korean Patent Application No. 10 - 2023 - 0171814, filed with the Korean Intellectual Property Office on November 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to an electronic device, and more particularly, to a three - level pulse amplitude modulation (PAM3) transmitter, an operation method of the PAM3 transmitter, and an electronic apparatus including the PAM3 transmitter. Background art

[0004] As the operating speed of systems including semiconductor devices has become faster and technologies for semiconductor integrated circuits have been developed, it may be required that semiconductor memory devices output or store data at a higher speed. Accordingly, synchronous memory devices capable of inputting / outputting data while synchronizing with an input system clock to input / output data at high speed have been developed. However, even with synchronous memory devices, it may not be sufficient to meet the required data input / output speed, and thus double data rate (DDR) synchronous memory devices have been developed, in which data is input to / output from the DDR memory device at each of the rising and falling edges of the system clock.

[0005] In recent years, pulse amplitude modulation (PAM) methods have been actively studied to meet the requirements of high - capacity and high - speed data transmission. In communication, the interconnection (i.e., the channel) between a transmitter and a receiver may distort a signal. To compensate for the distortion of the signal generated from the channel, a transmitter may use a circuit for performing an eye monitoring operation. Summary of the invention

[0006] Embodiments of the present inventive concept provide a PAM3 transmitter that outputs a three - level pulse amplitude modulation (PAM3) signal, an operation method of the PAM3 transmitter, and an electronic device including the PAM3 transmitter, in which distortion of the PAM3 signal is compensated by feeding back the PAM3 signal and monitoring an eye diagram to adjust a duty cycle of an input data signal to a driver.

[0007] According to an aspect of the present inventive concept, there is provided a PAM3 transmitter including a driver configured to convert input data into a PAM3 signal, an eye monitor circuit electrically connected to an output terminal of the driver and configured to monitor an upper eye diagram and a lower eye diagram of the PAM3 signal, and a duty cycle adjustment circuit configured to adjust a duty cycle of the input data provided to the driver.

[0008] According to another aspect of the inventive concept, there is provided an electronic device including a PAM3 transmitter and a PAM3 receiver. The PAM3 transmitter includes: a serializer configured to receive data and convert the received data into serial data; a duty cycle adjustment circuit configured to receive a pull-up enable signal, a pull-down enable signal, and the serial data, and output input data in response thereto; a driver configured to convert the input data into a PAM3 signal; and an eye monitor circuit electrically connected to an output terminal of the driver and configured to monitor an upper eye diagram and a lower eye diagram of the PAM3 signal and generate a duty cycle adjustment signal in response thereto, wherein the duty cycle adjustment circuit is further configured to output the input data with an adjusted duty cycle based on the duty cycle adjustment signal.

[0009] According to another aspect of the inventive concept, there is provided an operation method of a PAM3 transmitter. The operation method includes receiving data and converting the received data into input data including serial data, converting the input data into a PAM3 signal, monitoring an upper eye diagram and a lower eye diagram of the PAM3 signal, determining whether the upper eye diagram and the lower eye diagram of the PAM3 signal are asymmetric with each other, and adjusting a duty cycle of the input data based on whether the upper eye diagram and the lower eye diagram of the PAM3 signal are asymmetric with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B is a block diagram showing a three-level pulse amplitude modulation (PAM3) transmitter according to an embodiment;

[0012] Figure 2 is a diagram showing PAM3 signal levels based on a PAM3 transmitter according to an embodiment;

[0013] Figure 3A and Figure 3B is a circuit diagram of a duty cycle adjustment (DCA) circuit according to an embodiment;

[0014] Figure 4A and Figure 4B is a circuit diagram of a driver according to an embodiment;

[0015] Figure 5A and Figure 5B is a block diagram showing a PAM3 transmitter according to an embodiment;

[0016] Figure 6A and Figure 6B is a block diagram showing a PAM3 transmitter according to an embodiment;

[0017] Figure 7is a diagram showing an operation method of a DCA circuit according to an embodiment;

[0018] Figure 8 and Figure 9 is a diagram showing an eye diagram of an eye monitor circuit according to an embodiment;

[0019] Figure 10 is a diagram showing an operation method of a DCA circuit according to an embodiment;

[0020] Figure 11 and Figure 12 is a diagram showing an eye diagram of an eye monitor circuit according to an embodiment;

[0021] Figure 13 is a diagram showing an operation method of a DCA circuit according to an embodiment;

[0022] Figure 14 is a flowchart showing an operation method of a PAM3 transmitter according to an embodiment; and

[0023] Figure 15 is a block diagram showing a system including a memory device according to an embodiment. Detailed Description

[0024] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like components, and their repeated description is omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Note that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment may be combined in any way and / or combination.

[0025] Figure 1A and Figure 1B is a block diagram showing a three-level pulse amplitude modulation (PAM3) transmitter 10 according to an embodiment.

[0026] Referring Figure 1A , the PAM3 transmitter 10 may include a serializer 100, a duty cycle adjustment (DCA) circuit 300, a driver 400, an eye monitor circuit 500, and an output pad 600.

[0027] The PAM3 transmitter 10 may be a transmitter configured to transmit a signal modulated according to N-level pulse amplitude modulation (hereinafter referred to as PAM-N, where N is a natural number greater than or equal to 3). For example, the PAM3 transmitter 10 may transmit / receive signals by using the PAM3 method. The PAM3 transmitter 10 may generate a PAM3 signal S_PAM3 that can represent 3-bit data loaded on 2 symbols by using 3 levels, and may output the generated PAM3 signal S_PAM3 through the output pad 600. Refer to Figure 1B and / or Figure 2 Describe a method of generating the PAM3 signal S_PAM3 by using the PAM3 transmitter 10.

[0028] The PAM-N method may be a modulation method for transmitting multiple bits during one unit interval. Here, the unit interval may correspond to the symbol period of the signal for transmitting one symbol. For example, when modulating data by using the PAM-N method, multiple data bit information may be included in one symbol. Hereinafter, embodiments of the present disclosure will be described based on the PAM3 method.

[0029] In some embodiments, when transmitting the PAM3 signal S_PAM3, the PAM3 transmitter 10 may be configured to sufficiently ensure the eye opening height and eye opening width of the PAM3 signal S_PAM3, and at the same time may be configured to effectively consume power.

[0030] The PAM3 transmitter 10 according to some embodiments of the present inventive concept may have enhanced linearity, and may monitor the PAM3 signal S_PAM3 by using the eye monitor circuit 500, and the DCA circuit 300 may output the PAM3 signal S_PAM3 in which sufficient eye opening height and sufficient eye opening width are ensured.

[0031] The serializer 100 may convert data into serial data S_data having a continuous data column format. The serializer 100 may convert the data into serial data S_data in response to a clock signal CLK received from an external source. That is, the serializer 100 may convert the data received through the data bus into serial data S_data. For example, the serial data S_data may include a series of symbols, each symbol having a unit interval (UI). Here, the data may be provided from a processor or a baseband unit (such as various data processing blocks). The serial data S_data may be output by the serializer 100 in the form of 2 consecutive bits.

[0032] The DCA circuit 300 may output input data I_data by receiving the serial data S_data. The DCA circuit 300 may receive a pull-up enable signal generated from an external source (Figure 3A and Figure 3B ENPU) and a pull - down enable signal ( Figure 3A and Figure 3B ENPD). The calculation method for generating the pull - up enable signal ENPU and the pull - down enable signal ENPD of the DCA circuit 300 can vary depending on the configuration of the driver 400.

[0033] The driver 400 can receive the input data I_data output from the DCA circuit 300. The driver 400 can convert the input data I_data into a PAM3 signal S_PAM3. The driver 400 can generate a PAM3 signal S_PAM3 corresponding to the input data I_data. The driver 400 can output the generated PAM3 signal S_PAM3 through the output pad 600. The output terminal of the driver 400 can be connected to the eye monitor circuit 500.

[0034] The eye monitor circuit 500 can monitor the first eye diagram and the second eye diagram of the PAM3 signal S_PAM3 output by the driver 400. For example, the first eye diagram can be the upper eye diagram of the PAM3 signal S_PAM3, and the second eye diagram can be the lower eye diagram of the PAM3 signal S_PAM3. The eye monitor circuit 500 can check whether skewing occurs in the eye diagram pattern by monitoring the eye opening height and the eye opening width of the PAM3 signal S_PAM3. For example, the eye monitor circuit 500 can compare the size of the upper eye diagram of the PAM3 signal S_PAM3 with the size of the lower eye diagram of the PAM3 signal S_PAM3. When the sizes of the upper eye diagram and the lower eye diagram are different from each other, a duty - cycle adjustment signal dcas can be generated and provided to the DCA circuit 300.

[0035] The DCA circuit 300 can receive the duty - cycle adjustment signal dcas generated by the eye monitor circuit 500. The DCA circuit 300 can adjust the duty cycle of the serial data S_data. When the eye monitor circuit 500 compares the first eye diagram with the second eye diagram and there is an asymmetric comparison, the DCA circuit 300 can adjust the duty cycle of the input data I_data provided to the driver 400, and the driver 400 can receive the input data I_data whose duty cycle has been adjusted. The following refers to Figure 7 Describe a method for adjusting the duty cycle of the input data I_data by using the DCA circuit 300.

[0036] The DCA circuit 300 can adjust the duty cycle of the serial data S_data to generate input data I_data with an adjusted duty cycle, and the input data I_data is provided to the driver 400 to output a PAM3 signal in which the upper eye characteristics and the lower eye characteristics of the PAM3 signal S_PAM3 are enhanced. Thus, according to some embodiments, the DCA circuit 300 can adjust the duty cycle of the input data I_data provided to the driver 400 by adjusting the duty cycle of the serial data S_data and generating the input data I_data as the serial data S_data with an adjusted duty cycle. Therefore, the input data I_data includes the serial data S_data with the duty cycle adjustment applied to the serial data S_data.

[0037] The DCA circuit 300 can generate input data I_data with an adjusted duty cycle, and the input data I_data is provided to the driver 400 such that the size of the upper eye diagram and the size of the lower eye diagram are equal to each other. For example, the DCA circuit 300 can adjust the height of the upper and lower eye diagrams / or the width of the eye opening diagram.

[0038] Reference Figure 1B , the PAM3 transmitter 10 can include a first data path DP1, a second data path DP2, an eye monitor circuit 500, and an output pad 600. The first data path DP1 can include a first serializer 101, a first DCA circuit 301, and a first driver 401. The second data path DP2 can include a second serializer 102, a second DCA circuit 302, and a second driver 402.

[0039] Reference Figure 1B , Figure 1A The serializer 100, the DCA circuit 300, the driver 400, and the eye monitor circuit 500 of

[0040] For example, Figure 1A the serializer 100 of Figure 1A can include a first serializer 101 and a second serializer 102, and Figure 1A the DCA circuit 300 of Figure 1A can include a first DCA circuit 301 and a second DCA circuit 302, and Figure 1A the driver 400 of Figure 1AThe input data I_data may include first input data I_data1 and second input data I_data2, and Figure 1A the PAM3 signal S_PAM3 may include first PAM3 signal 1_PAM3 and second PAM3 signal 2_PAM3.

[0041] The first serializer 101 may convert the first data data1 into first serial data S_data1 in the form of a continuous data column in response to a clock signal CLK received from the outside.

[0042] The first DCA circuit 301 may output the first input data I_data1 by receiving the first serial data S_data1. The first DCA circuit 301 may generate the first input data I_data1 with an adjusted duty cycle in response to receiving the first serial data S_data1 and a duty cycle adjustment signal dcas1 generated by the eye monitor circuit 500.

[0043] The first driver 401 may output the first PAM3 signal I_PAM3 in response to receiving the first input data I_data1. The first driver 401 may convert the first input data I_data1 into the first PAM3 signal 1_PAM3. The first driver 401 may generate the first PAM3 signal I_PAM3 corresponding to the first input data I_data1.

[0044] The second serializer 102 may convert the second data data2 into second serial data S_data2 in the form of a continuous data column in response to a clock signal CLK received from the outside.

[0045] The second DCA circuit 302 may output the second input data I_data2 by receiving the second serial data S_data2. The second DCA circuit 302 may generate the second input data I_data2 with an adjusted duty cycle in response to receiving the second serial data S_data2 and a duty cycle adjustment signal dcas2 generated by the eye monitor circuit 500.

[0046] The second driver 402 may output the second PAM3 signal 2_PAM3 in response to receiving the second input data I_data2. The second driver 402 may convert the second input data I_data2 into the second PAM3 signal 2_PAM3. The second driver 402 may generate the second PAM3 signal 2_PAM3 corresponding to the second input data I_data2.

[0047] The first data path DP1 can output a first PAM3 signal 1_PAM3, and the second data path DP2 can output a second PAM3 signal 2_PAM3. The output pad 600 can combine the first PAM3 signal 1_PAM3 and the second PAM3 signal 2_PAM3 to output a PAM3 signal S_PAM3.

[0048] Figure 2 is a diagram showing the PAM3 signal levels of a PAM3 transmitter according to an embodiment.

[0049] Figure 2 shows the voltage levels of a PAM3 signal S_PAM3 based on PAM3 with three voltage levels. However, this is an embodiment preset for ease of description, and the embodiment is not limited thereto, and it will be fully understood that the embodiments of the present disclosure can be applied to the levels of data signals based on PAMn with n or more levels.

[0050] Reference Figure 2 , the PAM3 signal S_PAM3 can be mapped to the lowest first level V0, the middle second level V1, and the highest third level V2. In addition, in the eye diagram of the PAM3 signal S_PAM3, the signal of the output PAM3 signaling method can support three levels, and 3-bit data can be sent to two symbols. For example, in the PAM3 signal method, three levels can result in two eye diagrams.

[0051] Reference Figure 1B and Figure 2 , for example, when the first PAM3 signal 1_PAM3 is "0" and the second PAM3 signal 2_PAM3 is "0", the PAM3 signal S_PAM3 can be mapped to the lowest first level V0. When the first PAM3 signal 1_PAM3 is "0" and the second PAM3 signal 2_PAM3 is "1", the PAM3 signal S_PAM3 can be mapped to the second level V1 as the middle level, and when the first PAM3 signal 1_PAM3 is "1" and the second PAM3 signal 2_PAM3 is "0", the PAM3 signal S_PAM3 can be mapped to the second level V1 as the middle level. When the first PAM3 signal 1_PAM3 is "1" and the second PAM3 signal 2_PAM3 is "1", the PAM3 signal S_PAM3 can be mapped to the highest third level V2.

[0052] In this specification, for ease of description, based on Figure 2The embodiments of the present disclosure will be described by way of example of the levels of the PAM3 signal S_PAM3 shown. The mapping between the PAM3 signal S_PAM3 and the levels V0 to V2 may vary depending on the coding method, and it will be understood that the embodiments of the present disclosure may be applied to the PAM3 signal S_PAM3 by using different coding methods.

[0053] Figure 3A and Figure 3B FIG. is a circuit diagram showing DCA circuits 301 and 302 according to an embodiment.

[0054] Referring Figure 3A , the first DCA circuit 301 may include a first transistor T11, a second transistor T21, a third transistor T31, and a fourth transistor T41.

[0055] A power supply voltage VDD may be applied to one end of the first transistor T11, and the other end of the first transistor T11 may be electrically connected to the third transistor T31. One end of the second transistor T21 may be connected to the fourth transistor T41, and a ground voltage VSS may be applied to the other end of the second transistor T21.

[0056] The gate terminals of the third transistor T31 and the fourth transistor T41 may be electrically connected to a first node N11, one end of the third transistor T31 may be electrically connected to the first transistor T11, and the other end of the third transistor T31 may be electrically connected to a second node N21. One end of the fourth transistor T41 may be electrically connected to the second node N21, and the other end of the fourth transistor T41 may be electrically connected to the second transistor T21.

[0057] The gate of the first transistor T11 may receive a pull-up enable signal ENPU. For example, the first transistor T11 may control the rising edge of the input data I_data based on the pull-up enable signal ENPU. The gate of the second transistor T21 may receive a pull-down enable signal ENPD. For example, the second transistor T21 may control the falling edge of the input data I_data based on the pull-down enable signal ENPD. A method of controlling the rising edge and the falling edge of the first input data I_data1 will be described below with reference to Figure 7 the change in the voltage levels of the pull-up enable signal ENPU input to the gate terminal of the first transistor T11 and the pull-down enable signal ENPD input to the second transistor T21.

[0058] The first node N11 may receive first serial data S_data1 output from a serializer ( Figure 1B 101). The second node N21 may output the first input data I_data1.

[0059] The first transistor T11 and the third transistor T31 may include P-channel metal-oxide semiconductor (PMOS) transistors, and the second transistor T21 and the fourth transistor T4 may include N-channel metal-oxide semiconductor (NMOS) transistors.

[0060] Reference Figure 3B , the second DCA circuit 302 may include a first transistor T12, a second transistor T22, a third transistor T32, and a fourth transistor T42.

[0061] A power supply voltage VDD may be applied to one end of the first transistor T12, and the other end of the first transistor T12 may be electrically connected to the third transistor T32. One end of the second transistor T22 may be electrically connected to the fourth transistor T42, and a ground voltage VSS may be applied to the other end of the second transistor T22.

[0062] The gate terminals of the third transistor T32 and the fourth transistor T42 may be electrically connected to a first node N12, one end of the third transistor T32 may be electrically connected to the first transistor T12, and the other end of the third transistor T32 may be electrically connected to a second node N22. One end of the fourth transistor T42 may be electrically connected to the second node N22, and the other end of the fourth transistor T42 may be electrically connected to the second transistor T22.

[0063] The gate of the first transistor T12 may receive a pull-up enable signal ENPU. For example, the first transistor T12 may control the rising edge of the second input data I_data2 based on the pull-up enable signal ENPU. The gate of the second transistor T22 may receive a pull-down enable signal ENPD. For example, the second transistor T22 may control the falling edge of the second input data I_data2 based on the pull-down enable signal ENPD. The following will refer to Figure 7 Describe a method of controlling the rising edge and the falling edge of the second input data I_data2 based on changes in the voltage levels of the pull-up enable signal ENPU input to the gate terminal of the first transistor T12 and the pull-down enable signal ENPD input to the second transistor T22.

[0064] The first node N12 may receive the second serial data S_data2 output from the serializer ( Figure 1B 102). The second node N21 may output the second input data I_data2.

[0065] The first transistor T12 and the third transistor T32 may include PMOS transistors, and the second transistor T22 and the fourth transistor T42 may include NMOS transistors.

[0066] Figure 4A andFigure 4B is a circuit diagram showing drivers 401 and 402 according to an embodiment.

[0067] Reference Figure 4A , the first driver 401 may include a first transistor T51, a second transistor T61, a first resistor R11, and a second resistor R21.

[0068] A power supply voltage VDD may be applied to one end of the first transistor T51, and the other end of the first transistor T51 may be electrically connected to the first resistor R11. One end of the second transistor T61 may be electrically connected to the second resistor R21, and a ground voltage VSS may be applied to the other end of the second transistor T61.

[0069] One end of the first resistor R11 may be electrically connected to the fifth transistor T51, and the other end of the first resistor R11 may be electrically connected to a first node N31. One end of the second resistor R21 may be electrically connected to the third node N31, and the other end of the second resistor R21 may be electrically connected to the sixth transistor T61.

[0070] The gates of the first transistor T51 and the second transistor T61 may receive a first input data I_data1. The first node N31 may output a first PAM3 signal 1_PAM3. For example, the first transistor T51 and the second transistor T61 of the first driver 401 may control the rising edge or the falling edge of the first PAM3 signal 1_PAM3.

[0071] The first transistor T51 may include a PMOS transistor, and the second transistor T61 may include an NMOS transistor. The first resistor R11 and the second resistor R21 may be voltage dividing resistors.

[0072] Reference Figure 4B , the second driver 402 may include a first transistor T52, a second transistor T62, a first resistor R12, and a second resistor R22.

[0073] A power supply voltage VDD may be applied to one end of the first transistor T52, and the other end of the first transistor T52 may be electrically connected to the first resistor R12. One end of the second transistor T62 may be electrically connected to the second resistor R22, and a ground voltage VSS may be applied to the other end of the second transistor T62.

[0074] One end of the first resistor R12 may be electrically connected to the first transistor T52, and the other end of the first resistor R12 may be electrically connected to a first node N32. One end of the second resistor R22 may be electrically connected to the third node N32, and the other end of the second resistor R22 may be electrically connected to the second transistor T62.

[0075] The gates of the first transistor T52 and the second transistor T62 may receive the second input data I_data2. The first node N32 may output the second PAM3 signal 2_PAM3. For example, the first transistor T52 and the second transistor T62 of the second driver 402 may control the rising edge or the falling edge of the second PAM3 signal 2_PAM3.

[0076] The first transistor T52 may include a PMOS transistor, and the second transistor T62 may include an NMOS transistor. The first resistor R12 and the second resistor R22 may be voltage-dividing resistors.

[0077] Figure 5A and Figure 5B is a block diagram showing the PAM3 transmitter 10a according to an embodiment. Figure 5A is a diagram schematically showing the PAM3 transmitter 10a, and Figure 5B is a diagram showing in detail Figure 5A the configuration of the PAM3 transmitter 10a. Redundant descriptions regarding Figure 1A and Figure 1B as well as Figure 4A and Figure 4B will be omitted.

[0078] Referring to Figure 5A and Figure 5B , the PAM3 transmitter 10a may include a first serializer 101, a second serializer 102, a first DCA circuit group 310, a second DCA circuit group 320, a first driver 401, a second driver 402, an eye monitor circuit 500, and an output pad 600.

[0079] The first DCA circuit group 310 may include a plurality of DCA circuits, and the second DCA circuit 302 may include a plurality of DCA circuits. For example, the first DCA circuit group 310 may include two DCA circuits (according to the examples of Figure 5A and Figure 5B , the first PMOS control circuit 310a and the first NMOS control circuit 310b), and the second DCA circuit group 320 may include two DCA circuits (according to the examples of Figure 5A and Figure 5B , the second PMOS control circuit 320a and the second NMOS control circuit 320b). For example, the plurality of DCA circuits may be arranged in parallel in the first DCA circuit group 310, and the plurality of DCA circuits may be arranged in parallel in the second DCA circuit group 320. Each of the first PMOS control circuit 310a, the first NMOS control circuit 310b, the second PMOS control circuit 320a, and the second NMOS control circuit 320b may be associated with reference Figure 3A andFigure 3B The described DCA circuits 301 and 302 are implemented substantially identically.

[0080] The eye monitor circuit 500 can provide a first DCA signal dcas1 to the first DCA circuit group 310 and can provide a second DCA signal dcas2 to the second DCA circuit group 320.

[0081] The first DCA circuit 301 can receive first serial data S_data1 and can output first input data I_data1. The first input data I_data1 can include first PMOS input data I_data1_a and first NMOS input data I_data1_b. More specifically, the first PMOS control circuit 310a can receive the first serial data S_data1 and can output the first PMOS input data I_data1_a. The first NMOS control circuit 310b can receive the first serial data S_data1 and can output the first NMOS input data I_data1_b. The first DCA circuit group 310 can adjust the duty cycle of the first input data I_data1 to output a signal with an adjusted duty cycle to the first driver 401. More specifically, the first PMOS control circuit 301a can adjust the duty cycle of the first PMOS input data I_data1_a to output a signal with an adjusted duty cycle to the first driver 401. The first NMOS control circuit 310b can adjust the duty cycle of the first NMOS input data I_data1_b to output a signal with an adjusted duty cycle to the first driver 401. Input data signals I_data1_a and I_data1_b with adjusted duty cycles are respectively generated by adjusting the duty cycle of the first serial data S_data1.

[0082] Refer together Figures 4A to 5B, the first driver 401 can receive the first input data I_data1 through the gate terminals of the first transistor T51 and the second transistor T61. More specifically, the first driver 401 can receive the first PMOS input data I_data1_a and allow the first PMOS input data I_data1_a to be applied to the gate terminal of the first transistor T51. In addition, the first driver 401 can receive the first NMOS input data I_data1_b and allow the first NMOS input data I_data1_b to be applied to the gate terminal of the second transistor T61. The first driver 401 can output the first PAM3 signal 1_PAM3 through the first node N31. The second DCA circuit group 320 can receive the second serial data S_data2 and can output the second input data I_data2. The second input data I_data2 can include the second PMOS input data I_data2_a and the second NMOS input data I_data2_b. More specifically, the second PMOS control circuit 320a can receive the second serial data S_data2 and can output the second PMOS input data I_data2_a. The second NMOS control circuit 320b can receive the second serial data S_data2 and can output the second NMOS input data I_data2_b. The second DCA circuit group 320 can adjust the duty cycle of the second input data I_data2 to output a signal with an adjusted duty cycle to the second driver 402. More specifically, the second PMOS control circuit 320a can adjust the duty cycle of the second PMOS input data I_data2_a to output a signal with an adjusted duty cycle to the second driver 402. The second NMOS control circuit 320b can adjust the duty cycle of the second NMOS input data I_data2_b to output a signal with an adjusted duty cycle to the second driver 402. Input data signals I_data2_a and I_data2_b with adjusted duty cycles are respectively generated by adjusting the duty cycle of the second serial data S_data2.

[0083] Refer to together Figures 4A to 5B, the second driver 402 may receive the second input data I_data2 through the gate terminals of the first transistor T52 and the second transistor T62. More specifically, the second driver 402 may receive the second PMOS input data I_data2_a and allow the second PMOS input data I_data2_a to be applied to the gate terminal of the first transistor T52. In addition, the second driver 402 may receive the second NMOS input data I_data2_b and allow the second NMOS input data I_data2_b to be applied to the gate terminal of the second transistor T62. The second driver 402 may output the second PAM3 signal 2_PAM3 through the first node N32.

[0084] As a result of adjusting the duty cycle of the first input data I_data1 provided to the first driver 401 and the duty cycle of the second input data I_data2 provided to the second driver 402 by using each of the first DCA circuit group 310 and the second DCA circuit group 320, respectively, the size of the upper eye diagram and the size of the lower eye diagram of the PAM3 signal S_PAM3 may be equal to or approximately equal to each other.

[0085] Figure 6A and Figure 6B is a block diagram showing a PAM3 transmitter 10b according to an embodiment. Figure 6A is a diagram schematically showing the PAM3 transmitter 10b, and Figure 6B is a diagram showing in detail Figure 6A the configuration of the PAM3 transmitter 10b. Redundant descriptions regarding Figure 1A and Figure 1B , Figure 4A and Figure 4B as well as Figure 5A and Figure 5B will be omitted.

[0086] Referring to Figure 6A , the PAM3 transmitter 10b may include a serializer 100, a DCA circuit 300, a driver 400, an eye monitor circuit 500, and an output pad 600.

[0087] Figure 6A The difference between Figure 5A , Figure 5B is that the DCA circuit 300 jointly adjusts the duty cycle of the input data I_data and provides a signal with the adjusted duty cycle to the driver 400, so that a PAM3 signal can be output, in which the upper eye diagram and the lower eye diagram of the PAM3 signal S_PAM3 are improved.

[0088] Referring to Figure 6B, the PAM3 transmitter 10b may include a first serializer 101, a second serializer 102, a first DCA circuit 301, a second DCA circuit 302, a first driver 401, a second driver 402, an eye monitor circuit 500, and an output pad 600. Different from Figure 5A and Figure 5B , an input data I_data may be input to one of the drivers (i.e., the first driver 401 or the second driver 402). More specifically, the same signal (i.e., the first input data I_data1 output from the first DCA circuit 301) may be input to the first transistor T51 and the second transistor T61 of the first driver 401. In addition, the same signal (i.e., the second input data I_data2 output from the second DCA circuit 302) may be input to the first transistor T52 and the second transistor T62 of the second driver 402.

[0089] The eye monitor circuit 500 may provide a first DCA signal dcas1 to the first DCA circuit 301 and may provide a second DCA signal dcas2 to the second DCA circuit 302.

[0090] As a result of adjusting the duty cycle of the first input data I_data1 provided to the first driver 401 and the duty cycle of the second input data I_data2 provided to the second driver 402 by using each of the first DCA circuit 301 and the second DCA circuit 302, respectively, the size of the upper eye diagram and the size of the lower eye diagram of the PAM3 signal S_PAM3 may be equal to or approximately equal to each other.

[0091] Figure 7 is a diagram for describing an operation method of the DCA circuit 300 according to an embodiment.

[0092] Referring to Figure 7 , a method of adjusting the duty cycle of the first input data I_data1 and the duty cycle of the second input data I_data2 by using the first DCA circuit 301 and the second DCA circuit 302 is shown.

[0093] Referring together to Figure 3A and Figure 7 , by increasing the driving force of the first transistor T11, the rising edge of the first input data I_data1 may move to the left on the time axis. The duty cycle of the first input data I_data1 may be increased. Conversely, by decreasing the driving force of the first transistor T11, the rising edge of the first input data I_data1 may move to the right on the time axis. The duty cycle of the first input data I_data1 may be decreased.

[0094] By increasing the driving force of the second transistor T21, the falling edge of the first input data I_data1 can be shifted leftward on the time axis. The duty ratio of the first input data I_data1 can be decreased. Conversely, by decreasing the driving force of the second transistor T21, the rising edge of the first input data I_data1 can be shifted rightward on the time axis. The duty ratio of the first input data I_data1 can be increased.

[0095] To increase or decrease the driving force of a transistor (the first transistor T11 or the second transistor T21), the magnitude of the voltage applied to the gate of the transistor can also be changed. By increasing the magnitude of the voltage applied to the gate of the transistor (i.e., the magnitude of the pull-up enable signal ENPU or the pull-down enable signal ENPD), the driving force can be increased, and by decreasing the magnitude of the voltage applied to the gate of the transistor (i.e., the magnitude of the pull-up enable signal ENPU or the pull-down enable signal ENPD), the driving force can be decreased.

[0096] In other embodiments, each of the first transistor T11 and the second transistor T21 may include a plurality of unit transistors connected in parallel with each other. The driving force of each of the first transistor T11 and the second transistor T21 may be substantially proportional to the number of on states of the unit transistors included in each of the first transistor T11 and the second transistor T21. In this case, the pull-up enable signal ENPU may be a code for determining the number of unit transistors to be turned on included in the first transistor T11, and the pull-down enable signal ENPD may be a code for determining the number of unit transistors to be turned on included in the second transistor T21.

[0097] Referring together Figure 3B and Figure 7 , by increasing the voltage level of the pull-up enable signal ENPU to be input to the first transistor T12, the rising edge of the second input data I_data2 can be shifted leftward on the time axis. The duty ratio of the second input data I_data2 can be increased. Conversely, by decreasing the voltage level of the pull-up enable signal ENPU input to the first transistor T12, the rising edge of the second input data I_data2 can be shifted rightward on the time axis. The duty ratio of the second input data I_data2 can be decreased.

[0098] By increasing the voltage level of the pull - down enable signal ENPD input to the second transistor T22, the falling edge of the second input data I_data2 can be shifted leftward on the time axis. The duty cycle of the second input data I_data2 can be reduced. Conversely, by decreasing the voltage level of the pull - down enable signal ENPD input to the second transistor T22, the falling edge of the second input data I_data2 can be shifted rightward on the time axis. The duty cycle of the second input data I_data2 can be increased.

[0099] To increase or decrease the driving force of a transistor (the first transistor T12 or the second transistor T22), the magnitude of the voltage applied to the gate of the transistor can be changed. By increasing the magnitude of the voltage applied to the gate of the transistor (i.e., the magnitude of the pull - up enable signal ENPU or the pull - down enable signal ENPD), the driving force can be increased, and by decreasing the magnitude of the voltage applied to the gate of the transistor (i.e., the magnitude of the pull - up enable signal ENPU or the pull - down enable signal ENPD), the driving force can be decreased.

[0100] In other embodiments, each of the first transistor T12 and the second transistor T22 may include a plurality of unit transistors. The driving force of each of the first transistor T12 and the second transistor T22 can be substantially proportional to the number of on - state unit transistors included in each of the first transistor T12 and the second transistor T22. In this case, the pull - up enable signal ENPU can be a code for determining the number of unit transistors to be turned on included in the first transistor T12, and the pull - down enable signal ENPD can be a code for determining the number of unit transistors to be turned on included in the second transistor T22.

[0101] Figure 8 and Figure 9 is a diagram showing an eye diagram of the eye monitor circuit 500 according to an embodiment. Figure 10 is a diagram showing an operation method of the DCA circuit 300 according to an embodiment.

[0102] Reference Figure 8 , the PAM3 signal S_PAM3 can represent a situation where the rise time tr is greater than the fall time rf such that the degradation of the lower eye diagram is more severe than the degradation of the upper eye diagram. Referring to Figure 9 , when the second voltage level V1 of the PAM3 signal S_PAM3 approaches the first voltage level V0 (or when the second voltage level V1 decreases), the size of the upper eye diagram can be greater than the size of the lower eye diagram. The situation where the size of the upper eye diagram and the size of the lower eye diagram are not the same and the size of one of the upper eye diagram and the lower eye diagram is greater than the other can be referred to as an asymmetric eye diagram.

[0103] The following will refer to Figure 10 Describe with reference toFigure 8 And Figure 9 A method for enhancing an asymmetric eye diagram when the deterioration of the current eye diagram described is more severe than that of the upper eye diagram or the size of the lower eye diagram is smaller than that of the upper eye diagram.

[0104] Refer together to Figure 3A , Figure 5A , Figure 5B , Figure 6A , Figure 6B And Figure 10 , the eye monitor circuit 500 can receive the PAM3 signal S_PAM3 and can monitor the eye diagram of the received PAM3 signal S_PAM3. The eye monitor circuit 500 can output the first DCA signal dcas1 to the first DCA circuit 301 to enhance the asymmetric eye diagram as shown in Figure 8 And Figure 9 . The first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 in response to the first DCA signal dcas1.

[0105] In an embodiment, the first transistor T11 of the first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 based on the pull-up enable signal ENPU. Based on the description of reference Figure 7 , by increasing the driving force of the first transistor T11, the duty cycle of the first input data I_data1 can be increased. That is, the duty cycle of the first input data I_data1 output from the first DCA circuit 301 can be increased.

[0106] In an embodiment, the second transistor T21 of the first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 based on the pull-down enable signal ENPD. Based on the description of reference Figure 7 , by reducing the driving force of the second transistor T21, the duty cycle of the first input data I_data1 can be increased. That is, the duty cycle of the first input data I_data1 output from the first DCA circuit 301 can be increased. The gate terminals of the first transistor T51 and the second transistor T61 of the first driver 401 can receive the first input data I_data1 with an increased duty cycle. The first transistor T51 can slowly adjust the rising edge of the first PAM3 signal 1_PAM3, and the second transistor T61 can quickly adjust the falling edge of the first PAM3 signal 1_PAM3. Here, the slow adjustment of the rising edge can mean moving the rising edge to the right on the time axis, as shown in Figure 10 , and the quick adjustment of the falling edge can mean moving the falling edge to the left on the time axis, as shown in Figure 10 .

[0107] By using the first transistor T51 and the second transistor T61 of the first driver 401, the first input data I_data1 can be received, and the rising edge of the first PAM3 signal 1_PAM3 can be adjusted slowly, and the falling edge of the first PAM3 signal 1_PAM3 can be adjusted quickly, so that the first PAM3 signal 1_PAM3 can be output in a balanced manner.

[0108] The above method of increasing the duty cycle of the first input data I_data1 can be basically equally applied to the second DCA circuit 302. That is, when the PAM3 signal S_PAM3 has an asymmetric eye diagram in which the degradation of the lower eye diagram is more serious than that of the upper eye diagram or the size of the lower eye diagram is smaller than that of the upper eye diagram, the duty cycle of the second input data I_data2 output from the second DCA circuit 302 can also be increased based on the second DCA signal dcas2. Therefore, the second PAM3 signal 2_PAM3 can also be output in a balanced manner.

[0109] Refer to together Figure 3B 、 Figure 5A 、 Figure 5B and Figure 10 , the eye monitor circuit 500 can receive the PAM3 signal S_PAM3 and can monitor the eye diagram of the received PAM3 signal S_PAM3. As Figure 8 and Figure 9 shown, when the degradation of the lower eye diagram is more serious than that of the upper eye diagram or the size of the lower eye diagram is smaller than that of the upper eye diagram, the eye monitor circuit 500 can output the second DCA signal dcas2 to the second DCA circuit group 320 to enhance the asymmetric eye diagram. The second CA circuit 320 can adjust the duty cycle of the second input data I_data2 in response to the second DCA signal dcas2. More specifically, the duty cycle of the second PMOS input data I_data2_a and / or the second NMOS input data I_data_b can be adjusted.

[0110] The second DCA circuit group 320 can include a second PMOS control circuit 320a and a second NMOS control circuit 320b. Each of the second PMOS control circuit 320a and the second NMOS control circuit 320b can have the same as Figure 3BThe configuration of the second DCA circuit 302 shown is substantially the same configuration. In an embodiment, the first transistor T12 of the second PMOS control circuit 320a can adjust the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a based on the pull-up enable signal ENPU. More specifically, the duty cycle of the second PMOS input data I_data2_a can be increased by increasing the driving force of the first transistor T12. That is to say, the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a can be increased.

[0111] In an embodiment, the second transistor T22 of the second PMOS control circuit 320a can adjust the duty cycle of the second PMOS input data I_data2_a based on the pull-down enable signal ENPD. More specifically, the duty cycle of the second PMOS input data I_data2_a can be increased by reducing the driving force of the second transistor T22. That is to say, the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a can be increased.

[0112] To increase the duty cycle of the second PMOS input data I_data2_a described above, the increase in the driving force of the first transistor T12 and the decrease in the driving force of the second transistor T22 in the second PMOS circuit 320a can be optionally or simultaneously performed according to different embodiments.

[0113] In an embodiment, the first transistor T12 of the second NMOS control circuit 320b can adjust the duty cycle of the second PMOS input data I_data2_a output from the second NMOS control circuit 320b based on the pull-up enable signal ENPU. More specifically, the duty cycle of the second NMOS input data I_data2_b can be increased by increasing the driving force of the first transistor T12. That is to say, the duty cycle of the second NMOS input data I_data2_b output from the second NMOS control circuit 320b can be increased.

[0114] In an embodiment, the second transistor T22 of the second NMOS control circuit 320b can adjust the duty cycle of the second NMOS input data I_data2_b based on the pull-down enable signal ENPD. More specifically, the duty cycle of the second NMOS input data I_data2_b can be increased by reducing the driving force of the second transistor T22. That is to say, the duty cycle of the second NMOS input data I_data2_b output from the second NMOS control circuit 320b can be increased.

[0115] To increase the duty cycle of the second NMOS input data I_data2_b, the increase in the driving force of the first transistor T12 and the decrease in the driving force of the second transistor T22 in the second NMOS circuit 320b can be optionally or simultaneously performed according to different embodiments.

[0116] The gate terminals of the first transistor T52 and the second transistor T62 of the second driver 402 can receive the second input data I_data2 with an increased duty cycle. More specifically, the first transistor T52 can slowly adjust the rising edge of the second PAM3 signal 2_PAM3 based on the second PMOS input data I_data2_a with an increased duty cycle, and the second transistor T62 can quickly adjust the falling edge of the second PAM3 signal 2_PAM3 based on the second NMOS input data I_data2_b with an increased duty cycle. By using the first transistor T52 and the second transistor T62 of the second driver 402, the second input data I_data2 can be received, the rising edge of the second PAM3 signal 2_PAM3 can be slowly adjusted, and the falling edge of the second PAM3 signal 2_PAM3 can be quickly adjusted, so that the second PAM3 signal 1_PAM3 can be output in a balanced manner.

[0117] The method of increasing the duty cycle of the above-mentioned second input data I_data2 (i.e., the second PMOS input data I_data2_a and the second NMOS input data I_data2_b) can also be basically applied to the first DCA circuit group 310. That is, when the PAM3 signal S_PAM3 has an asymmetric eye diagram in which the degradation of the lower eye diagram is more serious than that of the upper eye diagram or the size of the lower eye diagram is smaller than that of the upper eye diagram, the duty cycle of the first input data I_data1 output from the first DCA circuit group 310 can also be increased based on the first DCA signal dcas1. Therefore, the first PAM3 signal 1_PAM3 can also be output in a balanced manner.

[0118] Therefore, the first PAM3 signal 1_PAM3 and the second PAM3 signal 2_PAM3 can be output in a balanced manner, so that the degradation of the eye diagram of the PAM3 signal S_PAM3 can be reduced, and the sizes of the upper eye diagram and the lower eye diagram can be the same.

[0119] Figure 11 and Figure 12 are diagrams showing eye diagrams for illustrating the operation method of a PAM3 transmitter according to an embodiment. Figure 13 is a diagram for illustrating the operation method of a DCA circuit according to an embodiment.

[0120] Reference Figure 11, the PAM3 signal S_PAM3 can represent a situation where the rise time tr is greater than the fall time rf, making the degradation of the upper eye diagram more severe than that of the lower eye diagram. Refer to Figure 12 , when the second voltage level V1 of the PAM3 signal S_PAM3 is close to the third voltage level V2 (or when the second voltage level V1 is rising), the size of the upper eye diagram can be smaller than that of the lower eye diagram. Here, the situation where the pattern degradation of the PAM3 signal S_PAM3 is severe may imply the level mismatch rate (RLM).

[0121] Refer to the following Figure 13 for a description of Figure 11 and Figure 12 the method for enhancing the asymmetric eye diagram when the degradation of the upper eye diagram is more severe than that of the lower eye diagram or the size of the upper eye diagram is smaller than that of the lower eye diagram.

[0122] Refer to together Figure 3A 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B and Figure 13 , the eye monitor circuit 500 can receive the PAM3 signal S_PAM3 and can monitor the eye diagram of the received PAM3 signal S_PAM3. The eye monitor circuit 500 can output the first DCA signal dcas1 to the first DCA circuit 301 to enhance the asymmetric eye diagram as shown in Figure 11 and Figure 12 . The first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 in response to the first DCA signal dcas1.

[0123] In an embodiment, the second transistor T21 of the first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 based on the pull - down enable signal ENPD. By increasing the driving force of the second transistor T21 based on the description in Figure 7 , the duty cycle of the first input data I_data1 can be reduced. That is, the duty cycle of the first input data I_data1 output from the first DCA circuit 301 can be reduced.

[0124] In an embodiment, the first transistor T11 of the first DCA circuit 301 can adjust the duty cycle of the first input data I_data1 based on the pull - up enable signal ENPU. By reducing the driving force of the first transistor T11 based on the description in Figure 7 , the duty cycle of the first input data I_data1 can be reduced. That is, the duty cycle of the first input data I_data1 output from the first DCA circuit 301 can be reduced.

[0125] The gate terminals of the first transistor T51 and the second transistor T61 of the first driver 401 may receive first input data I_data1 with a reduced duty cycle. The first transistor T51 may quickly adjust the rising edge of the first PAM3 signal 1_PAM3, and the second transistor T61 may slowly adjust the falling edge of the first PAM3 signal 1_PAM3. Here, the quick adjustment of the rising edge may mean that the rising edge moves to the left on the time axis, as Figure 13 shown, and the slow adjustment of the falling edge may mean that the falling edge moves to the right on the time axis, as Figure 13 shown.

[0126] By using the first transistor T51 and the second transistor T61 of the first driver 401, the first input data I_data1 may be received, the rising edge of the first PAM3 signal 1_PAM3 may be quickly adjusted, and the falling edge of the first PAM3 signal 1_PAM3 may be slowly adjusted, such that the first PAM3 signal 1_PAM3 may be output in a balanced manner.

[0127] The method of reducing the duty cycle of the first input data I_data1 described above may be basically applied to the second DCA circuit 302. That is, when the PAM3 signal S_PAM3 has an asymmetric eye diagram in which the degradation of the upper eye diagram is more severe than that of the lower eye diagram and the size of the upper eye diagram is smaller than that of the lower eye diagram, the duty cycle of the second input data I_data2 output from the second DCA circuit 302 may also be reduced based on the second DCA signal dcas2. Accordingly, the second PAM3 signal 2_PAM3 may also be output in a balanced manner.

[0128] Referring together to Figure 3B 、 Figure 5A 、 Figure 5B and Figure 13 , the eye monitor circuit 500 may receive the PAM3 signal S_PAM3 and may monitor the eye diagram of the received PAM3 signal S_PAM3. As Figure 11 and Figure 12 shown, when the degradation of the upper eye diagram is more severe than that of the lower eye diagram and the size of the upper eye diagram is smaller than that of the lower eye diagram, the eye monitor circuit 500 may output the second DCA signal dcas2 to the second DCA circuit group 320 to enhance the asymmetric eye diagram. The second CA circuit 320 may adjust the duty cycle of the second input data I_data2 in response to the second DCA signal dcas2. More specifically, the duty cycle of the second PMOS input data I_data2_a and / or the second NMOS input data I_data_b may be adjusted.

[0129] The second set of DCA circuits 320 may include a second PMOS control circuit 320a and a second NMOS control circuit 320b. Each of the second PMOS control circuit 320a and the second NMOS control circuit 320b may have a configuration substantially the same as that of the second DCA circuit 302 shown in Figure 3B . In an embodiment, the second transistor T22 of the second NMOS control circuit 320b may adjust the duty cycle of the second NMOS input data I_data2_b output from the second NMOS control circuit 320b based on a pull-down enable signal ENPD. More specifically, the duty cycle of the second NMOS input data I_data2_b may be reduced by increasing the driving force of the second transistor T22. That is, the duty cycle of the second NMOS input data I_data2_b output from the second NMOS control circuit 320b may be reduced.

[0130] In an embodiment, the first transistor T12 of the second NMOS control circuit 320b may adjust the duty cycle of the second NMOS input data I_data2_b based on a pull-up enable signal ENPU. More specifically, the duty cycle of the second NMOS input data I_data2_b may be reduced by decreasing the driving force of the first transistor T12. That is, the duty cycle of the second NMOS input data I_data2_b output from the second NMOS control circuit 320b may be reduced.

[0131] To reduce the duty cycle of the second NMOS input data I_data2_b described above, increasing the driving force of the second transistor T22 and decreasing the driving force of the first transistor T12 in the second NMOS circuit 320b may be optionally or simultaneously performed according to different embodiments.

[0132] In an embodiment, the second transistor T22 of the second PMOS control circuit 320a may adjust the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a based on a pull-down enable signal ENPD. More specifically, the duty cycle of the second PMOS input data I_data2_b may be reduced by increasing the driving force of the second transistor T22. That is, the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a may be reduced.

[0133] In an embodiment, the first transistor T12 of the second PMOS control circuit 320a may adjust the duty cycle of the second PMOS input data I_data2_a based on the pull-up enable signal ENPU. More specifically, the duty cycle of the second PMOS input data I_data2_a may be reduced by reducing the driving force of the first transistor T12. That is, the duty cycle of the second PMOS input data I_data2_a output from the second PMOS control circuit 320a may be reduced.

[0134] To reduce the duty cycle of the second PMOS input data I_data2_a, the increase in the driving force of the second transistor T22 and the decrease in the driving force of the first transistor T12 in the second PMOS circuit 320a may be optionally or simultaneously performed according to different embodiments.

[0135] The gate terminals of the first transistor T52 and the second transistor T62 of the second driver 402 may receive the second input data I_data2 with a reduced duty cycle. More specifically, the first transistor T52 may quickly adjust the rising edge of the second PAM3 signal 2_PAM3 based on the second PMOS input data I_data2_a with a reduced duty cycle, and the second transistor T62 may slowly adjust the falling edge of the second PAM3 signal 2_PAM3 based on the second NMOS input data I_data2_b with a reduced duty cycle. By using the first transistor T52 and the second transistor T62 of the second driver 402, the second input data I_data2 may be received, the rising edge of the second PAM3 signal 2_PAM3 may be quickly adjusted, and the falling edge of the second PAM3 signal 2_PAM3 may be slowly adjusted, so that the second PAM3 signal 1_PAM3 may be output in a balanced manner.

[0136] The method of reducing the duty cycle of the above second input data I_data2 (i.e., the second PMOS input data I_data2_a and the second NMOS input data I_data2_b) may also be basically applied to the first DCA circuit group 310. That is, when the PAM3 signal S_PAM3 has an asymmetric eye diagram in which the degradation of the upper eye diagram is more serious than that of the lower eye diagram and the size of the upper eye diagram is smaller than that of the lower eye diagram, the duty cycle of the first input data I_data1 output from the first DCA circuit group 310 may also be reduced based on the first DCA signal dcas1. Therefore, the first PAM3 signal 1_PAM3 may also be output in a balanced manner.

[0137] Therefore, the first PAM3 signal 1_PAM3 and the second PAM3 signal 2_PAM3 can be output in a balanced manner, such that the degradation of the eye diagram of the PAM3 signal S_PAM3 can be reduced, and the size of the upper eye diagram and the size of the lower eye diagram can be the same or substantially the same.

[0138] Figure 14 is a flowchart showing an operation method of the PAM3 transmitter 10 according to an embodiment.

[0139] Reference Figure 14 , the PAM3 transmitter 10 can receive data and convert the data into serial data (S110). For example, referring to Figure 1A , the serializer 100 can convert the data into serial data S_data having a continuous data column format.

[0140] The DCA circuit 300 can receive the serial data S_data and receive a pull-up enable signal and a pull-down enable signal. For example, referring to Figure 1A , the DCA circuit 300 can receive the serial data S_data and receive a pull-up enable signal ( Figure 3A and Figure 3B ENPU of Figure 3A and Figure 3B ENPD of

[0141] The driver 400 can convert the input data I_data into a PAM3 signal (S130). For example, referring to Figure 1A , the driver 400 can convert the input data I_data into a PAM3 signal S_PAM3.

[0142] The eye monitor circuit 500 can monitor the upper eye diagram and the lower eye diagram of the PAM3 signal S_PAM3. For example, referring to Figure 1A and Figure 1B , the eye monitor circuit 500 can monitor the first eye diagram and the second eye diagram of the PAM3 signal S_PAM3. The eye monitor circuit 500 can compare the size of the upper eye diagram of the PAM3 signal S_PAM3 with the size of the lower eye diagram.

[0143] The eye monitor circuit 500 can compare whether the size of the upper eye diagram and the size of the lower eye diagram are asymmetric with each other (S150). When the size of the upper eye diagram and the size of the lower eye diagram are symmetric with each other (No of S150), the operation S140 can be performed again.

[0144] On the contrary, when the size of the upper eye diagram and the size of the lower eye diagram are asymmetric with each other (Yes of S150), the DCA circuit 300 can adjust the duty cycle (S160). For example, referring to Figure 1A, based on the DCA signal dcas generated by the eye monitor circuit 500, the DCA circuit 300 can adjust the duty cycle of the input data I_data to provide data with an adjusted duty cycle to the driver 400, so that the driver 400 can receive the input data I_data with the adjusted duty cycle and can output the PAM3 signal S_PAM3. That is, the driver 400 can output a PAM3 signal, where the upper eye diagram and the lower eye diagram of the PAM3 signal S_PAM3 are enhanced. After the operation S160 is completed, the method can return to the operation S140 so that the monitoring of the eye diagram of the PAM3 signal can be continuously performed.

[0145] Figure 15 is a block diagram showing a system including a memory device according to an embodiment.

[0146] Reference Figure 15 , the system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, dynamic random access memories (DRAMs) 1500a and 1500b, flash memories 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (hereinafter referred to as "AP") 1800. The system 1000 can be implemented with a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system 1000 can also be implemented with a server or a PC.

[0147] The camera 1100 can capture a still image or a moving image according to the user's control, and can store the captured image / image data, or can send the stored image / image data to the display 1200. The audio processor 1300 can process the audio data included in the flash memories 1600a and 1600b or the content of the network.

[0148] The modem 1400 can modulate and send signals for wired / wireless data transmission and reception, and can demodulate the signals to restore their original signals on the receiving side. The I / O devices 1700a and 1700b can include devices providing digital input and / or output functions, such as a universal serial bus (USB) or a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, etc.

[0149] The AP 1800 can control the overall operation of the system 1000. The AP 1800 can control the display 1200 such that a part of the content stored in the flash memories 1600a and 1600b can be displayed on the display 1200. When the I / O devices 1700a and 1700b receive user input, the AP 1800 can perform control operations corresponding to the user input. The AP 1800 can include an accelerator block as a dedicated circuit for artificial intelligence (AI) data operation, or can include an accelerator chip 1820 separate from the AP 1800. The DRAM 1500b can be additionally mounted on the accelerator block or the accelerator chip 1820. The accelerator can be a functional block that performs a specific function of the AP 1800 and includes a graphics processing unit (GPU) as a functional block for performing graphics data processing, a neural processing unit (NPU) for performing AI computing and inference, and a data processing unit (DPU) as a block for data transmission.

[0150] The system 1000 can include multiple DRAMs 1500a and 1500b. The AP 1800 can control the DRAMs 1500a and 1500b through command and mode register MRS settings suitable for the Joint Electron Device Engineering Council (JEDEC) standard specifications, or can set DRAM interface regulations to use inherent functions (such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions), and can perform communication. For example, the AP 1800 can communicate with the DRAM 1500a through an interface suitable for JEDEC standard specifications, and can set new DRAM interface regulations to control the DRAM 1500b of the accelerator with a higher bandwidth than the DRAM 1500a, and can perform communication.

[0151] Figure 15 Only the DRAMs 1500a and 1500b are shown. However, the embodiments are not limited thereto, and any memory (such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM) can be available only when the bandwidth, response speed, and voltage conditions of the AP 1800 or the accelerator chip 1820 are satisfied. The DRAMs 1500a and 1500b can have relatively small latency and bandwidth compared to the I / O devices 1700a and 1700b or the flash memories 1600 and 1600b. The DRAMs 1500A and 1500B can be initialized when the system 1000 is powered on, and the operating system and application data can be loaded to be used as a temporary storage location for the operating system and application data, or as an execution space for various software codes.

[0152] In DRAMs 1500a and 1500b, arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or fast Fourier transform (FFT) operations can be performed. Additionally, functions for performance used in inference operations can be executed within DRAMs 1500a and 1500b. Here, inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm can include operations for training a model with various data and interference operations for generating inferences or classifications based on the input data using the trained model. In an embodiment, an image captured by the user's camera 1100 can be signal-processed and stored in DRAM 1500b, and the accelerator block or accelerator chip 1820 can perform AI data operations for recognizing data by using the data stored in DRAM 1500b and the functions for generating inferences therefrom.

[0153] System 1000 can include multiple storage devices or multiple flash memories having a larger capacity than DRAMs 1500a and 1500b. The accelerator block or accelerator chip 1820 can perform training operations and AI data operations by using flash memories 1600a and 1600b. In an embodiment, flash memories 1600a and 1600b can perform the training operations and interference AI data operations performed by AP 1800 and / or accelerator chip 1820 by using the arithmetic operation devices provided in the memory controller 1610. Flash memories 1600a and 1600b can store photos captured by the camera 1100, or can store data transmitted via a data network. For example, flash memories 1600a and 1600b can store augmented reality / virtual reality, high definition (HD), or ultra-high definition (UHD) content.

[0154] In system 1000, DRAMs 1500a and 1500b can include a PAM3 transmitter ( Figure 1A and Figure 1B of 10). The PAM3 transmitter can determine whether skewing occurs in the eye diagram by monitoring the eye opening height and eye opening width of the PAM3 signal. The appearance of the eye diagram can be seen by comparing the size of the upper eye diagram of the PAM3 signal with the size of the lower eye diagram of the PAM3 signal. When the size of the upper eye diagram of the PAM3 signal and the size of the lower eye diagram of the PAM3 signal are different from each other or are asymmetric with each other, the PAM3 transmitter can adjust the duty cycle of the upper eye diagram and / or the lower eye diagram to output a PAM3 signal whose upper eye diagram and lower eye diagram are enhanced.

[0155] As described above, the embodiments have been disclosed in the drawings and the specification. Although the embodiments have been described using specific examples herein, this is for the purpose of illustrating the exemplary embodiments of the present disclosure and is not used to limit the scope of the present disclosure described in the claims. Therefore, those of ordinary skill in the art will understand that various modifications and examples are possible. Accordingly, the true technical protection scope of the present disclosure should be determined by the scope of the appended claims.

[0156] Although the inventive concept has been specifically shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A 3-level pulse amplitude modulation (PAM3) transmitter, comprising: A driver configured to convert input data into a PAM3 signal; an eye monitor circuit electrically connected to the output terminal of the driver and configured to monitor an upper eye diagram and a lower eye diagram of the PAM3 signal; as well as The duty cycle adjustment circuit is configured to adjust the duty cycle of the input data provided to the driver.

2. The PAM3 transmitter according to claim 1, wherein: The input data includes serial data, and the 3-level PAM3 transmitter further includes: A serializer is configured to receive data and convert the received data into the serial data, wherein the duty cycle adjustment circuit is further configured to receive a pull-up enable signal and a pull-down enable signal and adjust the duty cycle of the serial data in response to the pull-up enable signal and the pull-down enable signal.

3. The PAM3 transmitter according to claim 2, wherein: The duty cycle adjustment circuit comprises: a first transistor configured to receive the pull-up enable signal; a second transistor configured to receive the pull-down enable signal; and The third transistor and the fourth transistor are configured to receive the serial data output from the serializer.

4. The PAM3 transmitter according to claim 3, wherein: The duty cycle adjustment circuit is further configured to adjust a rising edge of the serial data by adjusting a driving force of the first transistor based on the pull-up enable signal, and to adjust a falling edge of the serial data by adjusting a driving force of the second transistor based on the pull-down enable signal.

5. The PAM3 transmitter according to claim 4, wherein: The driving force of the first transistor is adjusted to move the rising edge of the serial data in a first direction on the time axis, and the driving force of the second transistor is adjusted to move the falling edge of the serial data in a second direction on the time axis to adjust the duty cycle of the input data.

6. The PAM3 transmitter according to claim 5, wherein: The driving force of the first transistor is adjusted to move the rising edge of the serial data in the second direction on the time axis, and the driving force of the second transistor is adjusted to move the falling edge of the serial data in the first direction on the time axis to adjust the duty cycle of the input data.

7. The PAM3 transmitter according to claim 2, wherein: The driver comprises: A first transistor configured to receive the input data; and The second transistor is configured to receive the input data.

8. The PAM3 transmitter according to claim 7, wherein: The driver comprises: a first resistor electrically connected to one end of the first transistor; and A second resistor is electrically connected to one end of the second transistor.

9. The PAM3 transmitter according to claim 1, wherein: The eye monitor circuit is configured to generate a duty cycle adjustment signal and provide the duty cycle adjustment signal to the duty cycle adjustment circuit when an upper eye pattern and a lower eye pattern of the PAM3 signal are asymmetric to each other.

10. The PAM3 transmitter according to claim 1, wherein: The eye monitor circuit is further configured to compare a size of the upper eye pattern with a size of the lower eye pattern and generate a duty cycle adjustment signal for the input data based on the comparison.

11. The PAM3 transmitter according to claim 10, wherein: The duty cycle adjustment circuit is further configured to receive the duty cycle adjustment signal and adjust a duty cycle of the input data provided to the driver.

12. An electronic device comprising: 3-level pulse amplitude modulation PAM3 transmitter; as well as PAM3 receiver, Wherein, the PAM3 transmitter includes: a serializer configured to receive data and convert the received data into serial data, a duty cycle adjustment circuit configured to receive a pull-up enable signal, a pull-down enable signal, and the serial data, and output input data in response to the pull-up enable signal, the pull-down enable signal, and the serial data; A driver configured to convert the input data into a PAM3 signal; and an eye monitor circuit electrically connected to the output terminal of the driver and configured to monitor an upper eye pattern and a lower eye pattern of the PAM3 signal and generate a duty cycle adjustment signal in response to the upper eye pattern and the lower eye pattern of the PAM3 signal, The duty cycle adjustment circuit is configured to output the input data with the duty cycle adjusted based on the duty cycle adjustment signal.

13. The electronic device according to claim 12, wherein: The duty cycle adjustment circuit comprises: a first transistor configured to receive the pull-up enable signal; a second transistor configured to receive the pull-down enable signal; and The third transistor and the fourth transistor are configured to receive the serial data generated by the serializer, Wherein, the first transistor and the third transistor include P-channel metal oxide semiconductor (PMOS) transistors, and The second transistor and the fourth transistor include N-channel metal oxide semiconductor (NMOS) transistors.

14. The electronic device according to claim 13, wherein: The duty cycle adjustment circuit is also configured to adjust the driving force of the first transistor to move the rising edge of the input data in a first direction on the time axis, thereby adjusting the duty cycle of the input data, and to adjust the driving force of the second transistor to move the falling edge of the input data in a second direction on the time axis, thereby adjusting the duty cycle of the input data.

15. The electronic device according to claim 12, wherein: The driver comprises: A first transistor configured to receive the input data; A second transistor configured to receive the input data; and a first resistor electrically connected to one end of the first transistor; and a second resistor electrically connected to one end of the second transistor, and The first transistor comprises a PMOS transistor, and the second transistor comprises an NMOS transistor.

16. The electronic device according to claim 12, wherein: The eye monitor circuit is also configured to compare the size of the upper eye pattern with the size of the lower eye pattern, and generate a duty cycle adjustment signal for adjusting the duty cycle of the input data based on the comparison, and the duty cycle adjustment circuit is also configured to receive the duty cycle adjustment signal and adjust the duty cycle of the input data in response to the duty cycle adjustment signal.

17. The electronic device according to claim 12, wherein: The eye monitor circuit is further configured to generate a duty cycle adjustment signal and provide the duty cycle adjustment signal to the duty cycle adjustment circuit when the upper eye pattern and the lower eye pattern of the PAM3 signal are asymmetric to each other.

18. A method for operating a 3-level pulse amplitude modulation (PAM3) transmitter, the method comprising: receiving data and converting the received data into input data including serial data; Convert the input data into a PAM3 signal; Monitoring an upper eye diagram and a lower eye diagram of the PAM3 signal; determining whether the upper eye diagram and the lower eye diagram of the PAM3 signal are asymmetric to each other; as well as The duty cycle of the input data is adjusted based on whether the upper eye pattern and the lower eye pattern of the PAM3 signal are asymmetric to each other.

19. The operating method according to claim 18, wherein: The adjusting of the duty cycle of the input data includes adjusting the duty cycle of the input data by moving a falling edge of the input data to the right on a time axis and by moving a rising edge of the input data to the left on the time axis.

20. The operating method according to claim 18, wherein: The adjusting of the duty cycle of the input data includes adjusting the duty cycle of the input data by moving a falling edge of the input data to the left on a time axis and by moving a rising edge of the input data to the right on the time axis.

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