Semiconductor structure and method of manufacturing the same, memory

Abstract

This disclosure relates to a semiconductor structure and its fabrication method, and a memory. The method includes: providing a substrate and forming a stacked structure on the substrate; the stacked structure includes sacrificial layers and dielectric layers alternately stacked along a direction perpendicular to the substrate; etching the stacked structure to form etching trenches and word line trenches extending along a first direction, the word line trenches being located on opposite sides of the etching trenches and communicating with the etching trenches; the first direction being parallel to the upper surface of the substrate; forming virtual word lines within the word line trenches; forming word line release holes on opposite sides of the word line trenches; removing the virtual word lines based on the word line release holes to release the word line trenches; forming a word line structure and a preset channel layer within the word line trenches, the word line structure including a word line conductive layer and a gate dielectric layer surrounding the word line conductive layer, the preset channel layer surrounding the gate dielectric layer; and removing the preset channel layer exposed by the word line release holes. This method can reduce etching difficulty, simplify the process flow, and eliminate the influence of parasitic channels.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and manufacturing technology, and in particular to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] In the field of integrated circuit design and manufacturing technology, as process dimensions shrink, the aspect ratio of capacitors in memory increases exponentially, making memory process miniaturization increasingly difficult. Researchers are constructing three-dimensional structures to effectively address the challenges of process miniaturization, enabling the production of more chips per unit wafer area, achieving higher integration density and larger storage capacity, thereby reducing costs. Therefore, three-dimensional memory structures have gradually become one of the important research directions in memory technology.

[0003] However, the traditional manufacturing processes currently used to manufacture 3D memory are difficult to etch, have complex processes, and are prone to generating parasitic channels, which affects the further improvement of the structure and performance of 3D memory. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, as well as a memory, which can at least reduce etching difficulty, simplify the process flow, and eliminate the influence of parasitic channels.

[0005] To address the aforementioned technical problems and other issues, according to some embodiments, one aspect of this disclosure provides a method for fabricating a semiconductor structure, which in some embodiments includes:

[0006] A substrate is provided, and a stacked structure is formed on the substrate; the stacked structure includes sacrificial layers and dielectric layers that are alternately stacked along a direction perpendicular to the substrate.

[0007] The etched stack structure forms etched grooves and word line trenches extending along a first direction. The word line trenches are located on opposite sides of the etched grooves and are connected to the etched grooves. The first direction is parallel to the upper surface of the substrate.

[0008] Virtual character lines are formed within the character line grooves;

[0009] Character line release holes are formed on both sides opposite to the character line groove;

[0010] Virtual word lines are removed based on word line release holes to release word line grooves;

[0011] A word line structure and a preset channel layer are formed in the word line trench. The word line structure includes a word line conductive layer and a gate dielectric layer covering the outer periphery of the word line conductive layer. The preset channel layer covers the outer periphery of the gate dielectric layer.

[0012] Remove the preset channel layer exposed by the word line release hole to form a channel layer, the channel layers being spaced apart along the first direction.

[0013] In some embodiments, the etching trench divides the stacked structure into sub-stacked structures spaced apart along a second direction, the second direction being perpendicular to the first direction and parallel to the upper surface of the substrate; after forming virtual word lines in the word line trench and before forming word line release holes on opposite sides of the word line trench, the method further includes:

[0014] Fill the etching groove with bit line material layer;

[0015] The bit line material layer and sub-stack structure are etched to form multiple bit line isolation trenches and multiple capacitor release holes; each bit line isolation trench extends along a second direction, and the multiple bit line isolation trenches are spaced apart along a first direction to form multiple bit lines spaced apart along the first direction; the multiple capacitor release holes are spaced apart along the first direction and are correspondingly provided with the bit line isolation trenches.

[0016] A first filling dielectric layer is formed, which fills the bit line isolation groove and capacitor release hole;

[0017] The formation of word line release holes on both sides opposite to the word line groove includes: forming word line release holes within the first filling medium layer on both sides opposite to the word line groove.

[0018] In some embodiments, after forming the first filling dielectric layer and before forming word line release holes on opposite sides of the word line trench, the method further includes:

[0019] Remove the retained sacrificial layer to form a capacitor aperture;

[0020] A capacitor structure is formed inside the capacitor hole.

[0021] In some embodiments, after forming the first filling dielectric layer and before removing the retained sacrificial layer to form the capacitor hole, the method further includes: removing a portion of the sub-stack structure to expose a portion of the upper surface of the substrate on the side of the sub-stack structure away from the etch trench.

[0022] The capacitor structure includes a lower electrode layer, a capacitor dielectric layer located on the surface of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer; the capacitor structure is also located on the exposed upper surface of the substrate, and multiple capacitor structures located on the same side of the etching trench share the upper electrode layer.

[0023] In some embodiments, a character line structure and a preset channel layer are formed within the character line groove, including:

[0024] A word line conductive material layer, a gate dielectric material layer, and a channel material layer are formed in both the word line release hole and the word line trench.

[0025] Remove the word line conductive material layer, gate dielectric material layer, and channel material layer located within the word line release hole to form the word line structure and the preset channel layer.

[0026] In some embodiments, forming a virtual character line within the character line groove includes: forming an amorphous carbon layer within the character line groove as a virtual character line.

[0027] In some embodiments, the sacrificial layer comprises a silicon nitride layer, and the dielectric layer comprises a silicon oxide layer.

[0028] In some embodiments, after removing the preset channel layer exposed by the word line release hole, a removal gap is formed; after removing the preset channel layer exposed by the word line release hole, the method further includes:

[0029] A second filling medium layer is formed, which fills the word line release hole and removes the gap.

[0030] According to some embodiments, another aspect of this disclosure provides a semiconductor structure including a substrate, a word line structure, and a channel layer; a dielectric layer is formed on the substrate at intervals along a direction perpendicular to the substrate, and an etching trench and a word line trench extending along a first direction, the word line trench being located on opposite sides of the etching trench and communicating with the etching trench; the first direction is parallel to the upper surface of the substrate; the word line structure is located within the word line trench, the word line structure including a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer; the channel layers are arranged at intervals along the first direction and covering a portion of the periphery of the gate dielectric layer.

[0031] In some embodiments, bit lines and bit line isolation structures are provided in the etching trench at intervals along a second direction. The second direction is perpendicular to the first direction and parallel to the upper surface of the substrate. The bit line isolation structure includes a first filling dielectric layer and a second filling dielectric layer. The first filling dielectric layer is located between adjacent bit lines, and the second filling dielectric layer is located on both sides of the first filling dielectric layer.

[0032] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures; the capacitor structures are located on the side of the word line trench away from the etch trench and extend along a first direction; the capacitor structure includes a lower electrode layer, a capacitor dielectric layer located on the surface of the lower electrode layer and an upper electrode layer located on the surface of the capacitor dielectric layer; the lower electrode layer is in contact with the channel layer; the capacitor structure is also located on the exposed upper surface of the substrate, and the plurality of capacitor structures located on the same side of the etch trench share the upper electrode layer.

[0033] According to some embodiments, another aspect of this disclosure provides a memory including the semiconductor structure described above.

[0034] The embodiments disclosed herein may have, or at least have, the following advantages:

[0035] In this embodiment, by etching a stacked structure, etching trenches and word line trenches extending along a first direction are formed, reducing the difficulty of the etching process. Furthermore, by forming virtual word lines within the word line trenches and word line release holes on opposite sides of the word line trenches, and then removing the virtual word lines based on the word line release holes to release the word line trenches, channel layer deposition in narrow slits is avoided, further reducing process difficulty. Additionally, a word line structure is formed within the word line trenches, including a word line conductive layer and a gate dielectric layer surrounding the word line conductive layer. Channel layers are spaced apart along the first direction, covering a portion of the gate dielectric layer, thereby forming a horizontal Channel-All-Around (CAA) structure. This helps save on structural size and process stacking, increasing device storage density. Subsequently, the channel layer exposed by the word line release holes is removed to eliminate the influence of parasitic channels. Thus, this embodiment simplifies the process flow and improves memory performance. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figure 2 This is a top view schematic diagram of the structure obtained in step 10 of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0039] Figure 3 Figure (a) in the middle is Figure 2 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 2 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 2 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 2 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0040] Figure 4 This is a top view schematic diagram of the structure obtained in step 21 of a method for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

[0041] Figure 5 Figure (a) in the middle is Figure 4 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 2The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 2 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 2 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0042] Figure 6 This is a three-dimensional structural diagram of the structure obtained in step 22 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0043] Figure 7 for Figure 6 A top view of the structure shown;

[0044] Figure 8 Figure (a) in the middle is Figure 7 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 7 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 7 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 7 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0045] Figure 9 This is a three-dimensional structural diagram of the structure obtained in step 23 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0046] Figure 10 for Figure 9 A top view of the structure shown;

[0047] Figure 11 Figure (a) in the middle is Figure 10 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 10 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 10 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 10 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0048] Figure 12 This is a three-dimensional structural diagram of the structure obtained in step 311 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0049] Figure 13 for Figure 12 A top view of the structure shown;

[0050] Figure 14 Figure (a) in the middle is Figure 13 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 13The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 13 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 13 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0051] Figure 15 This is a three-dimensional structural diagram of the structure obtained in step 312 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0052] Figure 16 for Figure 15 A top view of the structure shown;

[0053] Figure 17 Figure (a) in the middle is Figure 16 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 16 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 16 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 16 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0054] Figure 18 This is a three-dimensional structural diagram of the structure obtained in step 41 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0055] Figure 19 for Figure 18 A top view of the structure shown;

[0056] Figure 20 Figure (a) in the middle is Figure 19 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 19 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 19 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 19 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0057] Figure 21 This is a three-dimensional structural diagram of the structure obtained in step 42 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0058] Figure 22 for Figure 21 A top view of the structure shown;

[0059] Figure 23 Figure (a) in the middle is Figure 22 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 22The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 22 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 22 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0060] Figure 24 This is a three-dimensional structural diagram of the structure obtained in step 43 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0061] Figure 25 for Figure 24 A top view of the structure shown;

[0062] Figure 26 Figure (a) in the middle is Figure 25 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 25 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 25 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 25 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0063] Figure 27 This is a three-dimensional structural diagram of the structure obtained in step 44 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0064] Figure 28 for Figure 27 A top view of the structure shown;

[0065] Figure 29 Figure (a) in the middle is Figure 28 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 28 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 28 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 28 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0066] Figure 30 This is a three-dimensional structural diagram of the structure obtained in step 45 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0067] Figure 31 for Figure 30 A top view of the structure shown;

[0068] Figure 32 Figure (a) in the middle is Figure 31 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 31Figure 31 shows a cross-sectional view of the structure along the bb' direction; (c) shows a cross-sectional view of the structure along the cc' direction; and (d) shows a cross-sectional view of the structure shown in Figure 31. Figure 31 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0069] Figure 33 This is a three-dimensional structural diagram of the structure obtained in step 46 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0070] Figure 34 for Figure 33 A top view of the structure shown;

[0071] Figure 35 Figure (a) in the middle is Figure 34 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 34 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 34 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 34 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0072] Figure 36 This is a three-dimensional structural diagram of the structure obtained in step 51 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0073] Figure 37 for Figure 36 A top view of the structure shown;

[0074] Figure 38 Figure (a) in the middle is Figure 37 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 37 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 37 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 37 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0075] Figure 39 This is a three-dimensional structural diagram of the structure obtained in step 70 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0076] Figure 40 for Figure 39 A top view of the structure shown;

[0077] Figure 41 Figure (a) in the middle is Figure 40 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 40 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 40 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 40 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0078] Figure 42 This is a three-dimensional structural diagram of the structure obtained in step 81 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0079] Figure 43 for Figure 42 A top view of the structure shown;

[0080] Figure 44 Figure (a) in the middle is Figure 43 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 43 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 43 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 43 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0081] Figure 45 This is a three-dimensional structural diagram of the structure obtained in step 82 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0082] Figure 46 for Figure 45 A top view of the structure shown;

[0083] Figure 47 Figure (a) in the middle is Figure 46 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 46 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 46 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 46 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0084] Figure 48 This is a three-dimensional structural diagram of the structure obtained in step 90 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0085] Figure 49 for Figure 48 A top view of the structure shown;

[0086] Figure 50 Figure (a) in the middle is Figure 49 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 49 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 49The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 49 A schematic diagram of the cross-section of the structure shown along the dd' direction;

[0087] Figure 51 This is a three-dimensional structural diagram of the structure obtained in step 100 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0088] Figure 52 for Figure 51 A top view of the structure shown;

[0089] Figure 53 Figure (a) in the middle is Figure 52 The diagram shows a cross-sectional view of the structure along the aa' direction. Figure (b) is... Figure 52 The cross-sectional schematic diagram of the structure shown is along the bb' direction. Figure (c) is... Figure 52 The diagram shows a cross-section of the structure along the cc' direction. Figure (d) is... Figure 52 A schematic diagram of the cross-section of the structure shown along the dd' direction.

[0090] Explanation of reference numerals in the attached figures:

[0091] 1. Substrate; 2. Stacked structure; 201. Sub-stacked structure; 21. Sacrificial layer; 22. Dielectric layer;

[0092] E1, Etching groove; G1, Word line groove; G2, Bit line isolation groove; H1, Word line release hole; H2, Capacitor release hole; H3, Capacitor hole; S1, Removal gap;

[0093] 3. Word line structure; 301. Virtual word line; 3011. Virtual word line material layer; 31. Word line conductive layer; 311. Word line conductive material layer; 32. Gate dielectric layer; 321. Gate dielectric material layer; 4. Bit line; 401. Bit line material layer; 41. Bit line isolation structure; 411. First filling dielectric layer; 412. Second filling dielectric layer; 5. Channel layer; 501. Channel material layer; 51. Preset channel layer; 6. Capacitor structure; 61. Lower electrode layer; 62. Capacitor dielectric layer; 63. Upper electrode layer; 71. First mask layer; 72. Second mask layer; 73. Patterned photoresist layer. Detailed Implementation

[0094] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0095] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0096] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When using “comprising,” “having,” and “including” as described herein, another component may be added unless explicitly qualified terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0097] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0098] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0099] Please refer to Figure 1 According to some embodiments, this disclosure provides a semiconductor structure and a method for fabricating the same, the method comprising:

[0100] S10: Provide a substrate and form a stacked structure on the substrate; the stacked structure includes sacrificial layers and dielectric layers alternately stacked along the direction perpendicular to the substrate;

[0101] S20: Etching stack structure to form etching trenches and word line trenches extending along a first direction, the word line trenches being located on opposite sides of the etching trenches and connected to the etching trenches; the first direction is parallel to the upper surface of the substrate;

[0102] S30: A virtual character line is formed within the character line groove;

[0103] S50: Character line release holes are formed on both sides opposite to the character line groove;

[0104] S70: Remove virtual word lines based on word line release holes to release word line grooves;

[0105] S80: A word line structure and a preset channel layer are formed in the word line trench. The word line structure includes a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer. The preset channel layer covers the periphery of the gate dielectric layer.

[0106] S90: Remove the preset channel layer exposed by the word line release hole to form a channel layer, the channel layers being spaced apart along the first direction.

[0107] In the semiconductor structure fabrication method of the above embodiments, etching the stacked structure forms etching trenches and word line trenches extending along the first direction, reducing the difficulty of the etching process. Furthermore, by forming virtual word lines within the word line trenches and word line release holes on opposite sides of the word line trenches, and then removing the virtual word lines based on the word line release holes to release the word line trenches, channel layer deposition in narrow slits is avoided, reducing process difficulty. Additionally, a word line structure is formed within the word line trenches, including a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer. Channel layers are spaced apart along the first direction, covering a portion of the gate dielectric layer, thereby forming a horizontal Channel-All-Around (CAA) structure, which helps save on structural size and process stacking, thereby increasing the device's storage density. Subsequently, the channel layer exposed by the word line release holes is removed to eliminate the influence of parasitic channels. Thus, the embodiments of this disclosure simplify the process flow and improve memory performance.

[0108] In some embodiments, step S30, forming a virtual word line within the word line groove, includes:

[0109] S31: An amorphous carbon layer is formed within the character line groove to serve as a virtual character line.

[0110] In some embodiments, the etching trench divides the stacked structure into sub-stacked structures spaced apart along a second direction, the second direction being perpendicular to the first direction and parallel to the upper surface of the substrate; step S30, after forming virtual word lines in the word line trench, and step S50, before forming word line release holes on opposite sides of the word line trench, further includes:

[0111] S41: Fill the etching groove with bit line material layer;

[0112] S42: Etch bit line material layer and sub-stack structure to form multiple bit line isolation trenches and multiple capacitor release holes; each bit line isolation trench extends along the second direction, and the multiple bit line isolation trenches are spaced apart along the first direction to form multiple bit lines spaced apart along the first direction; the multiple capacitor release holes are spaced apart along the first direction and are correspondingly provided with the bit line isolation trenches.

[0113] S43: Form a first filling dielectric layer, which fills the bit line isolation groove and capacitor release hole;

[0114] Step S50, forming word line release holes on both sides opposite to the word line groove includes:

[0115] S51: A word line release hole is formed in the first filling medium layer on both sides of the word line groove.

[0116] In some embodiments, after forming the first filling dielectric layer in step S43 and before forming word line release holes on opposite sides of the word line trench in step S51, the method further includes:

[0117] S45: Remove the retained sacrificial layer to form a capacitor hole;

[0118] S46: A capacitor structure is formed inside the capacitor hole.

[0119] In some embodiments, after step S43, forming the first filling dielectric layer, and before step S45, removing the retained sacrificial layer to form the capacitor via, the method further includes:

[0120] S44: Remove part of the sub-stack structure to expose part of the upper surface of the substrate on the side of the sub-stack structure away from the etching trench;

[0121] The capacitor structure includes a lower electrode layer, a capacitor dielectric layer located on the surface of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer; the capacitor structure is also located on the exposed upper surface of the substrate, and multiple capacitor structures located on the same side of the etching trench share the upper electrode layer.

[0122] In some embodiments, step S80, forming a character line structure and a preset channel layer within the character line groove, includes:

[0123] S81: A word line conductive material layer, a gate dielectric material layer, and a channel material layer are formed in both the word line release hole and the word line trench;

[0124] S82: Remove the word line conductive material layer, gate dielectric material layer, and channel material layer located in the word line release hole to form a word line structure and a preset channel layer.

[0125] In some embodiments, the sacrificial layer comprises a silicon nitride layer, and the dielectric layer comprises a silicon oxide layer.

[0126] In some embodiments, after removing the preset channel layer exposed by the word line release hole in step S90, a removal gap is formed; after removing the preset channel layer exposed by the word line release hole in step S90, the method further includes:

[0127] Step S100: Form a second filling medium layer, which fills the word line release hole and removes the gap.

[0128] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0129] To more clearly illustrate the fabrication methods of the memory cells provided in the above embodiments, please refer to the following... Figures 2 to 53 Understand some embodiments of this application.

[0130] This application does not specifically limit the constituent material of substrate 1. As an example, substrate 1 can be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multi-layer structure. For example, substrate 1 can be such as silicon (Si) substrate 1, silicon germanium (SiGe) substrate 1, silicon germanium carbon (SiGeC) substrate 1, silicon carbide (SiC) substrate 1, gallium arsenide (GaAs) substrate 1, indium arsenide (InAs) substrate 1, indium phosphide (InP) substrate 1, or other III / V semiconductor substrate 1 or II / VI semiconductor substrate 1. Alternatively, for example, substrate 1 can be a layered substrate 1 including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0131] Please refer to Figures 2 to 3 In step S10, a stacked structure 2 is formed on the substrate 1; the stacked structure 2 includes a sacrificial layer 21 and a dielectric layer 22 that are alternately stacked along the direction perpendicular to the substrate 1.

[0132] For example, the bottom layer and the top layer of the stacked structure 2 are both dielectric layers 22.

[0133] It is understood that those skilled in the art can set the number of layers of the stacked structure 2 according to their needs to obtain three-dimensional memory with different stacking layers.

[0134] In some embodiments, the sacrificial layer 21 includes a silicon nitride layer, and the dielectric layer 22 includes a silicon oxide layer.

[0135] Please refer to Figures 4 to 11In step S20, the stacked structure 2 is etched to form an etching trench E1 extending along a first direction and a word line trench G1. The word line trench G1 is located on opposite sides of the etching trench E1 and is connected to the etching trench E1 to reduce the difficulty of the etching process. The first direction is parallel to the upper surface of the substrate 1. For example, the first direction can be as follows: Figure 4 Y direction shown in .

[0136] In some embodiments, step S20 may include:

[0137] S21: As Figures 4 to 5 As shown, a first mask layer 71, a second mask layer 72, and a photoresist (PR) layer are sequentially formed on the stacked structure 2. The photoresist layer is exposed and developed to form a first pattern within the photoresist layer, thereby forming a patterned photoresist layer 73. The first pattern defines the position of the etching trench E1.

[0138] S22: As Figures 6 to 8 As shown, the first mask layer 71 and the second mask layer 72 are etched based on the first pattern to transfer the first pattern into the first mask layer 71 and the second mask layer 72, and the patterned photoresist layer 73 is removed; then the stacked structure 2 is etched based on the first pattern in the first mask layer 71 and the second mask layer 72 to form an etching trench E1 extending along the first direction, and the remaining first mask layer 71 and the second mask layer 72 are removed;

[0139] The etching trench E1 divides the stacked structure 2 into sub-stacked structures 201 arranged at intervals along the second direction. The second direction is perpendicular to the first direction and parallel to the upper surface of the substrate 1.

[0140] For example, the first direction can be as follows: Figure 6 The X direction is shown in the diagram.

[0141] S23: As Figures 9 to 11 As shown, the sidewalls of the sacrificial layer 21 are etched based on the etching trench E1 to form a word line trench G1 extending in the first direction;

[0142] For example, in step S23, the sidewalls of the sacrificial layer 21 can be etched using a lateral etching process, thereby more precisely controlling the morphology of the word line trench G1 obtained by etching.

[0143] Please refer to Figures 12 to 17 Step S30: A virtual word line 301 is formed in the word line groove G1;

[0144] In some embodiments, step S30 includes:

[0145] S31: An amorphous carbon layer is formed in the word line groove G1 as a virtual word line 301.

[0146] For example, step S31 may include:

[0147] S311: As Figures 12 to 14 As shown, a virtual word line material layer 3011 is deposited, and the virtual word line material layer 3011 fills the etched groove E1 and the word line trench G1;

[0148] For example, the virtual character line material layer 3011 includes an amorphous carbon layer.

[0149] S312: As Figures 15 to 17 As shown, the virtual word line material layer 3011 located in the etching groove E1 is removed to form the virtual word line 301.

[0150] Please refer to Figures 18 to 23 In some embodiments, after step S30, forming a virtual word line 301 in the word line groove G1, and before step S50, forming word line release holes H1 on opposite sides of the word line groove G1, the method further includes:

[0151] S41: As Figures 18 to 20 As shown, the bit line material layer 401 is filled into the etching groove E1;

[0152] For example, the material of bit line material layer 401 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicon nitride, or combinations thereof.

[0153] S42: As Figures 21 to 23 As shown, the bit line material layer 401 and the sub-stack structure 201 are etched to form multiple bit line isolation trenches G2 and multiple capacitor release holes H2.

[0154] The bit line material layer 401 is etched to form a plurality of bit line isolation trenches G2 that expose virtual word lines 301. Each bit line isolation trench G2 extends along the second direction, and the plurality of bit line isolation trenches G2 are spaced apart along the first direction. The remaining bit line material layer 401 forms a plurality of bit lines 4 spaced apart along the first direction.

[0155] The etched sub-stack structure 201 forms a plurality of capacitor release holes H2 that expose virtual word lines 301. The plurality of capacitor release holes H2 are arranged at intervals along the first direction and are corresponding to the bit line isolation grooves G2.

[0156] For example, a one-time etching process can be used to simultaneously etch the bit line material layer 401 and the sub-stack structure 201 to form multiple bit line isolation trenches G2 and multiple capacitor release holes H2, or a step-by-step etching process can be used to etch the bit line material layer 401 separately to form multiple bit line isolation trenches G2 and etch the sub-stack structure 201 separately to form multiple capacitor release holes H2.

[0157] It should be added that the “single etching process” mentioned in some embodiments of this disclosure can be understood as: etching based on the pattern of the same mask to form the same pattern; and is not limited to a specific etching method. For example, it can be implemented by dry etching, by wet etching, or by a combination of dry etching and wet etching, etc.

[0158] For example, step S42 can use anisotropic etching to etch the bit line material layer 401 and the sub-stack structure 201. Anisotropic etching can selectively etch the material in a preset crystal orientation or crystal plane direction, while leaving very few or almost no etching traces in other directions. Using anisotropic etching in this step can make the morphology of the obtained structure more accurate and controllable.

[0159] S43: As Figures 24 to 26 As shown, a first filling dielectric layer 411 is formed, and the first filling dielectric fills the bit line isolation groove G2 and the capacitor release hole H2.

[0160] For example, the first filling dielectric layer 411 can be made of a material with a larger etching selectivity than the sacrificial layer 21, so as to better remove the sacrificial layer 21 in subsequent processes. For example, the first filling dielectric layer 411 can be made of the same or similar material as the dielectric layer 22, and the first filling dielectric layer 411 can also be a silicon oxide layer.

[0161] In some embodiments, after forming the first filling dielectric layer 411, step S43 further includes:

[0162] S44: As Figures 27 to 29 As shown, a portion of the sub-stack structure 201 is removed to expose a portion of the upper surface of the substrate 1 on the side of the sub-stack structure 201 away from the etching trench E1, thereby expanding the subsequent process window.

[0163] S45: As Figures 30 to 32 As shown, the retained sacrificial layer 21 is removed to form a capacitor hole H3; the capacitor hole H3 exposes part of the sidewall of the virtual word line 301;

[0164] For example, the retained sacrificial layer 21 can be removed using a wet etching process.

[0165] S46: As Figures 33 to 35As shown, a lower electrode layer 61, a capacitor dielectric layer 62, and an upper electrode layer 63 are sequentially formed within the capacitor hole H3. The lower electrode layer 61 covers the sidewall of the capacitor hole H3 and part of the exposed sidewall of the virtual word line 301. The capacitor dielectric layer 62 covers the lower electrode layer 61 and also covers the side surface of the sub-stack structure 201. The upper electrode layer 63 is located on the surface of the capacitor dielectric layer 62 and fills the capacitor hole H3. The capacitor structure 6 is also located on the exposed upper surface of the substrate 1. Multiple capacitor structures 6 located on the same side of the etching trench E1 share the upper electrode layer 63.

[0166] For example, the material of the upper electrode is the same as or similar to the material of the lower electrode. For instance, the materials of the upper and lower electrodes are selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, tungsten titanate, tungsten nitride, titanium nitride, titanium silicon nitride, titanium carbide, polycrystalline silicon, or combinations thereof.

[0167] For example, the material of the capacitor dielectric layer 62 can be selected as a high-K dielectric material to increase the capacitance value per unit area of ​​the capacitor, including at least one of zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium zirconium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx).

[0168] Please refer to Figures 36 to 38 Step S50, forming word line release holes H1 on both sides opposite to the word line groove G1 includes:

[0169] S51: As Figures 36 to 38 As shown, word line release holes H1 are formed in the first filling medium layer 411 on both sides of the word line groove G1;

[0170] For example, the word line release hole H1 exposes the sidewalls of the virtual word line 301 opposite each other along the second direction and the sidewalls of the capacitor structure 6 opposite each other along the first direction, in order to expand the process window for subsequent removal of the virtual word line 301.

[0171] Please refer to Figures 39 to 41 In step S70, the virtual word line 301 is removed based on the word line release hole H1 to release the word line groove G1. Since the word line release hole H1 is located on both sides of the word line groove G1, both side walls of the virtual word line 301 are exposed by the word line release hole H1, thereby enabling the virtual word line 301 to be removed more effectively and reducing the difficulty of the process.

[0172] Please refer to Figures 42 to 50 In some embodiments, step S80 involves forming a word line structure 3 and a preset channel layer 51 within the word line trench G1. The word line structure 3 includes a word line conductive layer 31 and a gate dielectric layer 32 surrounding the word line conductive layer 31. The preset channel layer 51 surrounds the gate dielectric layer 32. Step S80 may include:

[0173] S81: As Figures 42 to 44 As shown, a word line conductive material layer 311, a gate dielectric material layer 321, and a channel material layer 501 are formed in both the word line release hole H1 and the word line trench G1. Since the word line release hole H1 and the word line trench G1 provide sufficient space for the deposition of the channel material layer 501, the deposition of the channel material layer 501 in narrow slits is avoided, thus reducing the difficulty of the process.

[0174] For example, the channel material layer 501 can be made of a metal oxide, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the semiconductor structure is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the semiconductor structure meets the requirements. Those skilled in the art can adjust the material according to the actual situation.

[0175] S82: As Figures 45 to 47 As shown, the word line conductive material layer 311, the gate dielectric material layer 321, and the channel material layer 501 located in the word line release hole H1 are removed to form the word line structure 3 and the preset channel layer 51.

[0176] In step S82, the word line structure 3 includes a word line conductive layer 31 and a gate dielectric layer 32 covering the periphery of the word line conductive layer 31. A preset channel layer 51 covers the periphery of the gate dielectric layer 32 so that a horizontal channel-all-around (CAA) structure can be formed, which is beneficial to save structural size and process stacking, thereby increasing the storage density of the device.

[0177] For example, the constituent materials of the word line conductive layer 31 include, but are not limited to, one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0178] For example, the material of the gate dielectric layer 32 may include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, carbide (silicon carbide), or combinations thereof. Exemplarily, high-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0179] Please refer to Figures 48 to 50 In some embodiments, step S90 involves removing the preset channel layer exposed by the word line release hole H1 to form a channel layer 5, the channel layers 5 being spaced apart along the first direction and forming a removal gap S1 to eliminate the influence of parasitic channels.

[0180] Please refer to Figures 51 to 53 After step S90, which involves removing the preset channel layer exposed by the word line release hole H1 to form the channel layer 5, the method further includes:

[0181] Step S100: Form a second filling medium layer 412, the second filling medium layer 412 fills the word line release hole H1 and removes the gap S1;

[0182] For example, the second filling dielectric layer 412 may be made of the same or similar material as the first filling dielectric layer 411. For instance, the second filling dielectric layer 412 may also be a silicon oxide layer.

[0183] The second filling medium layer 412 located between adjacent bit lines 4 and in the word line release hole H1, together with the first filling medium layer 411 retained between adjacent bit lines 4, can form a bit line isolation structure 41. That is, the first filling medium layer 411 and the second filling medium layer 412 located in the bit line isolation groove G2 can together form a bit line isolation structure 41.

[0184] Based on the same inventive concept, please refer to Figures 51 to 53 This disclosure also provides a semiconductor structure in some embodiments, which is fabricated using the methods described in the above embodiments. This semiconductor structure possesses all the technical advantages of the above-described semiconductor structure fabrication methods, and will not be detailed here.

[0185] The semiconductor structure includes a substrate 1, a word line structure 3, and a channel layer 5. A dielectric layer 22 is formed on the substrate 1 at intervals along a direction perpendicular to the substrate 1, and an etching trench E1 and a word line trench G1 extending along a first direction. The word line trench G1 is located on opposite sides of the etching trench E1 and is connected to the etching trench E1. The first direction is parallel to the upper surface of the substrate 1. The word line structure 3 is located in the word line trench G1. The word line structure 3 includes a word line conductive layer 31 and a gate dielectric layer 32 covering the periphery of the word line conductive layer 31. The channel layers 5 are arranged at intervals along the first direction and cover part of the periphery of the gate dielectric layer 32.

[0186] In some embodiments, bit lines 4 and bit line isolation structures 41 are arranged at intervals along a second direction in the etching trench. The second direction is perpendicular to the first direction and parallel to the upper surface of the substrate 1. The bit line isolation structure 41 includes a first filling dielectric layer 411 and a second filling dielectric layer 412. The first filling dielectric layer 411 is located between adjacent bit lines 4, and the second filling dielectric layer 412 is located on both sides of the first filling dielectric layer 411.

[0187] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures 6; the capacitor structures 6 are located on the side of the word line trench G1 away from the etching trench E1 and extend along a first direction; the capacitor structure 6 includes a lower electrode layer 61, a capacitor dielectric layer 62 located on the surface of the lower electrode layer 61 and an upper electrode layer 63 located on the surface of the capacitor dielectric layer 62; the lower electrode layer 61 is in contact with the channel layer 5; the capacitor structure 6 is also located on the exposed upper surface of the substrate 1, and the plurality of capacitor structures 6 located on the same side of the etching trench E1 share the upper electrode layer 63.

[0188] In some embodiments, a memory including the semiconductor structure described above is also provided.

[0189] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0190] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0191] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0192] The above embodiments are merely illustrative of several implementation methods of this disclosure, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a stacked structure is formed on the substrate; the stacked structure includes sacrificial layers and dielectric layers alternately stacked along a direction perpendicular to the substrate; The stacked structure is etched to form etch grooves and word line trenches extending along a first direction. The word line trenches are located on opposite sides of the etch grooves and are connected to the etch grooves. The first direction is parallel to the upper surface of the substrate. A virtual character line is formed within the character line groove; Word line release holes are formed on both sides opposite to the word line groove; The virtual word line is removed based on the word line release hole to release the word line groove; A word line structure and a preset channel layer are formed in the word line trench. The word line structure includes a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer. The preset channel layer covers the periphery of the gate dielectric layer. Remove the preset channel layer exposed by the word line release hole to form a channel layer, the channel layers being spaced apart along the first direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching trench divides the stacked structure into sub-stacked structures spaced apart along a second direction, which is perpendicular to the first direction and parallel to the upper surface of the substrate. After forming a virtual character line within the character line groove, and before forming character line release holes on opposite sides of the character line groove, the method further includes: The etching groove is filled with a bit line material layer; The bit line material layer and the sub-stack structure are etched to form a plurality of bit line isolation trenches and a plurality of capacitor release holes; each bit line isolation trench extends along the second direction, and the plurality of bit line isolation trenches are spaced apart along the first direction to form a plurality of bit lines spaced apart along the first direction; the plurality of capacitor release holes are spaced apart along the first direction and are correspondingly disposed to the bit line isolation trenches. A first filling dielectric layer is formed, which fills the bit line isolation groove and the capacitor release hole; Forming word line release holes on opposite sides of the word line groove includes: forming the word line release holes within the first filling medium layer on opposite sides of the word line groove.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, After the first filling medium layer is formed, and before the word line release holes are formed on both sides opposite to the word line groove, the method further includes: Remove the retained sacrificial layer to form a capacitor aperture; A capacitor structure is formed within the capacitor hole.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After forming the first filling dielectric layer, and before removing the retained sacrificial layer to form the capacitor via, the method further includes: removing a portion of the sub-stack structure to expose a portion of the upper surface of the substrate on the side of the sub-stack structure away from the etch trench; The capacitor structure includes a lower electrode layer, a capacitor dielectric layer located on the surface of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer; the capacitor structure is also located on the exposed upper surface of the substrate, and multiple capacitor structures located on the same side of the etching trench share the upper electrode layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, A character line structure and a preset channel layer are formed within the character line groove, including: A word line conductive material layer, a gate dielectric material layer, and a channel material layer are formed in both the word line release hole and the word line trench. Remove the word line conductive material layer, the gate dielectric material layer, and the channel material layer located within the word line release hole to form the word line structure and the preset channel layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming virtual character lines within the character line groove includes: An amorphous carbon layer is formed within the word line groove to serve as the virtual word line.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sacrificial layer includes a silicon nitride layer, and the dielectric layer includes a silicon oxide layer.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, After removing the preset channel layer exposed by the word line release hole, a removal gap is formed; After removing the preset channel layer exposed by the word line release hole, the method further includes: A second filling medium layer is formed, which fills the word line release hole and the removal gap.

9. A semiconductor structure, characterized in that, include: A substrate having dielectric layers stacked at intervals along a direction perpendicular to the substrate, and etching trenches and word line trenches extending along a first direction, wherein the word line trenches are located on opposite sides of the etching trenches and are connected to the etching trenches. The first direction is parallel to the upper surface of the substrate; A word line structure is located within the word line trench, and the word line structure includes a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer; The channel layers are arranged at intervals along the first direction and cover a portion of the periphery of the gate dielectric layer; The character line groove has character line release holes on both sides opposite to each other; The plurality of channel layers arranged at intervals in the first direction are formed based on the patterned preset channel layers of the corresponding word line release holes; two adjacent channel layers in the first direction are isolated by a second filling medium layer that fills the removal gap formed by the corresponding word line release hole and the patterned preset channel layer.

10. The semiconductor structure according to claim 9, characterized in that, The etching trench is provided with bit lines and bit line isolation structures arranged at intervals along a second direction, the second direction being perpendicular to the first direction and parallel to the upper surface of the substrate; The bit line isolation structure includes a first filling dielectric layer and a second filling dielectric layer, wherein the first filling dielectric layer is located between adjacent bit lines, and the second filling dielectric layer is located on both sides of the first filling dielectric layer.

11. The semiconductor structure according to claim 9, characterized in that, It also includes multiple capacitor structures; the capacitor structures are located on the side of the word line groove away from the etching groove and extend along a first direction; The capacitor structure includes a lower electrode layer, a capacitor dielectric layer located on the surface of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer; the lower electrode layer is in contact with the channel layer; the capacitor structure is also located on the exposed upper surface of the substrate, and multiple capacitor structures located on the same side of the etching trench share the upper electrode layer.

12. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 9-11.

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