Memory, preparation method thereof and electronic equipment

Abstract

The invention relates to a memory, a preparation method thereof and electronic equipment. The memory includes a substrate; the plurality of storage units are stacked on the substrate along a direction vertical to the substrate; the storage unit comprises a read transistor and a write transistor; the read transistor comprises a first gate, a first semiconductor layer and a storage gate, and the write transistor comprises a second gate and a second semiconductor layer; the read word line is located on the substrate, and the first grid electrode of the read transistor is a part of the read word line; the writing word line is located on the substrate, and the second grid electrode of the writing transistor is a part of the writing word line; the bit line comprises a first part and a second part which are connected; the first part of the bit line is arranged on one side, far away from the write transistor, of the first grid electrode and is connected with the first semiconductor layer; and the second part of the bit line is arranged on one side, far away from the reading transistor, of the second semiconductor layer and is connected with the second semiconductor layer. The memory has relatively high storage performance and use reliability.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design and manufacturing technologies, and particularly to a memory, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technologies, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, such that any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements for current products. Summary of the Invention

[0004] Based on this, embodiments of the present application provide a memory, a method for manufacturing the same, and an electronic device, which are beneficial to improving the storage performance and usage reliability of the memory.

[0005] On the one hand, according to some embodiments, the present application provides a memory, including:

[0006] A substrate;

[0007] A plurality of memory cells; the plurality of memory cells are stacked on the substrate along a direction perpendicular to the substrate; each memory cell includes a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer, and a storage gate, and the write transistor includes a second gate and a second semiconductor layer;

[0008] A read word line, located on the substrate and extending along a direction perpendicular to the substrate; the first gate of the read transistor is a part of the read word line;

[0009] A write word line, located on the substrate and spaced apart from the read word line, the write word line extending along a direction perpendicular to the substrate; the second gate of the write transistor is a part of the write word line;

[0010] A bit line, including a connected first part and a second part; the first part of the bit line is disposed on a side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second part of the bit line is disposed on a side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer;

[0011] Wherein, the storage gate is located on a side of the first semiconductor layer facing away from the first gate.

[0012] In some embodiments, the first semiconductor layer has a second surface close to the substrate and a first surface away from the substrate in a direction perpendicular to the substrate, and the first portion of the bit line is located on the first surface; the second semiconductor layer has a first side and a second side opposite to each other in a direction parallel to the substrate, and the second portion of the bit line is located on the second side of the second semiconductor layer.

[0013] In some embodiments, the memory further comprises: a connection line;

[0014] The connection line is located on one side of the read transistor in a direction parallel to the substrate and on the first side and the second side of the second semiconductor layer; the connection line is integrally connected to the second portion of the bit line.

[0015] In some embodiments, the read word line surrounds a sidewall of the first semiconductor layer, and the second semiconductor layer surrounds a sidewall of the write word line.

[0016] In some embodiments, the memory further comprises: a ground line;

[0017] The grounding line is located beside the read word line and is parallel to the read word line; the grounding line is connected to the first semiconductor layer.

[0018] In some embodiments, the ground wire includes a main body and a plurality of branch parts;

[0019] The branch portion extends from the main portion in a direction parallel to the substrate, and a surface of the branch portion close to the substrate and a surface of the branch portion far from the substrate are both connected to the first semiconductor layer.

[0020] In some embodiments, the first semiconductor layer is in a ring shape, and the first semiconductor layer surrounds the storage gate.

[0021] On the other hand, the present application also provides a method for preparing a memory according to some embodiments, including:

[0022] providing a substrate;

[0023] A plurality of memory cells are formed on the substrate and stacked in a direction perpendicular to the substrate; the memory cells include a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart and distributed in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer and a memory gate, and the write transistor includes a second gate and a second semiconductor layer; wherein the memory gate is located on a side of the first semiconductor layer away from the first gate;

[0024] A read word line extending in a direction perpendicular to the substrate is formed on the substrate; a part of the read word line serves as the first gate of the read transistor;

[0025] A write word line spaced apart from the read word line is formed on the substrate; the write word line extends in a direction perpendicular to the substrate, and a part of the write word line serves as the second gate of the write transistor;

[0026] A bit line is formed; the bit line includes a connected first part and a second part; the first part of the bit line is formed on a side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second part of the bit line is formed on a side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer.

[0027] In some embodiments, after providing the substrate, the method for manufacturing the memory further includes:

[0028] A stacked structure is formed on the substrate; the stacked structure includes multiple insulating material layers and multiple conductive material layers alternately stacked in a direction perpendicular to the substrate;

[0029] Forming the first gate, the first semiconductor layer, and the read word line includes:

[0030] Etching the insulating material layer to form an etching groove for the read transistor; conformally covering the inner wall of the etching groove for the read transistor with the first semiconductor layer;

[0031] A filling dielectric layer is formed in the etching groove for the read transistor;

[0032] Etching the filling dielectric layer to form a receiving groove for the read word line; filling and forming the read word line in the receiving groove for the read word line; the first gate is the part of the read word line corresponding to the first semiconductor layer.

[0033] In some embodiments, after forming the first gate, the first semiconductor layer, and the read word line, the manufacturing method further includes:

[0034] Etching the stacked structure to form an etching groove for the write transistor and a defining hole for the write word line; the etching groove for the write transistor is located in the conductive material layer, surrounds the defining hole for the write word line, and is in communication with the defining hole for the write word line;

[0035] Conformally covering the inner wall of the etching groove for the write transistor with the second semiconductor layer, and filling the second gate in the etching groove for the write transistor;

[0036] Forming the write word line in the defining hole for the write word line.

[0037] In some embodiments, the second semiconductor layer is formed to have opposite first and second sides in a direction parallel to the substrate, and a second portion of the bit line is formed on the second side of the second semiconductor layer.

[0038] In some embodiments, forming the bit line includes:

[0039] Etching the filling dielectric layer and a part of the first semiconductor layer to expose a second surface of the first semiconductor layer close to the substrate side, forming a first bit line accommodation groove; forming a first portion of the bit line in the first bit line accommodation groove.

[0040] On the other hand, the present application also provides an electronic device according to some embodiments, including the memory provided in any previous embodiment.

[0041] The memory, its manufacturing method, and the electronic device provided by the embodiments of the present application may / at least have the following advantages:

[0042] In the embodiments of the present application, two transistors (a read transistor and a write transistor) are used as a storage unit, and a storage gate is used to store charges, implementing a storage unit with a two-transistor zero-capacitor (also referred to as 2T0C) structure. Compared with the related art, the storage capacitor is omitted, which is beneficial to improving the structural integration degree, reducing leakage and refresh time; since the storage gate is used instead of the storage capacitor, compared with the traditional memory where the charges in the storage capacitor will be lost during data reading (also referred to as destructive reading), in the embodiments of the present application, no charge loss will occur during data reading, realizing non-destructive reading, making the memory have higher read-write flexibility, improving the use reliability and access efficiency of the memory, and further improving the storage performance and use reliability of the memory.

[0043] Moreover, in the embodiments of the present application, the read transistor includes a first gate and a storage gate. The read transistor adopts a double-gate structure, which is beneficial to improving the gate control ability of the read transistor, reducing the subthreshold swing, thereby improving the switching ratio of the read transistor, and further improving the electrical performance of the memory. In the embodiments of the present application, the bit line is set to include a connected first portion and a second portion. The first portion of the bit line is connected to the read transistor, and the second portion is connected to the write transistor. Compared with the related art where a read bit line and a write bit line are respectively set, the embodiments of the present application can reduce the number of bit lines, enabling the memory to achieve a higher structural density, and being beneficial to layout design, especially for layout design in a narrow space, thereby further improving the practicability of the memory. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0045] Figure 1 Schematic three-dimensional structure diagram of a memory provided by some embodiments of the present application;

[0046] Figure 2 Schematic three-dimensional structure diagram of a memory provided by other embodiments of the present application;

[0047] Figure 3 For Figure 2 Schematic rear view structure diagram of the structure shown;

[0048] Figure 4 Figure (a) in is the schematic structure diagram of a memory provided by some embodiments of the present application; Figure 4 Figure (b) in is Figure 4 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in in the aa' direction; Figure 4 Figure (c) in is Figure 4 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in in the bb' direction; Figure 4 Figure (d) in is Figure 4 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in in the cc' direction; Figure 4 Figure (e) in is Figure 4 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in in the dd' direction;

[0049] Figure 5 Equivalent circuit diagram of a memory provided by some embodiments of the present application;

[0050] Figure 6 Schematic flow chart of a method for manufacturing a memory provided by some embodiments of the present application;

[0051] Figure 7 Schematic flow chart of forming a first gate, a first semiconductor layer, and a read word line in the method for manufacturing a memory provided by some embodiments of the present application;

[0052] Figure 8 Schematic flow chart of forming a second gate, a second semiconductor layer, and a write word line in the method for manufacturing a memory provided by some embodiments of the present application;

[0053] Figure 9Figure (a) in [description] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming a stacked structure in the method for manufacturing a memory provided by some embodiments of the present application; Figure 9 Figure (b) in [description] is Figure 9 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [description]; Figure 9 Figure (c) in [description] is Figure 9 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [description]; Figure 9 Figure (d) in [description] is Figure 9 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [description];

[0054] Figure 10 Figure (a) in [description] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming a first mask in the method for manufacturing a memory provided by some embodiments of the present application; Figure 10 Figure (b) in [description] is Figure 10 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [description]; Figure 10 Figure (c) in [description] is Figure 10 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [description]; Figure 10 Figure (d) in [description] is Figure 10 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [description]; Figure 10 Figure (e) in [description] is Figure 10 a schematic top view structure diagram of the structure shown in Figure (a) in [description];

[0055] Figure 11 Figure (a) in [description] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming a second storage unit definition groove in the method for manufacturing a memory provided by some embodiments of the present application; Figure 11 Figure (b) in [description] is Figure 11 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [description]; Figure 11 Figure (c) in [description] is Figure 11 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [description]; Figure 11 Figure (d) in [description] is Figure 11 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [description];

[0056] Figure 12 Figure (a) in [description] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming a storage unit isolation layer in the method for manufacturing a memory provided by some embodiments of the present application; Figure 12 Figure (b) in [description] is Figure 12 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [description]; Figure 12 Figure (c) in [description] isFigure 12 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 12 Figure (d) in Figure 12 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0057] Figure 13 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the second mask in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 13 Figure (b) in Figure 13 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 13 Figure (c) in Figure 13 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 13 Figure (d) in Figure 13 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction; Figure 13 Figure (e) in Figure 13 Schematic top view structure diagram of the structure shown in Figure (a);

[0058] Figure 14 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the support etching groove in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 14 Figure (b) in Figure 14 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 14 Figure (c) in Figure 14 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 14 Figure (d) in Figure 14 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0059] Figure 15 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the support groove in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 15 Figure (b) in Figure 15 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 15 Figure (c) in Figure 15 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 15 Figure (d) in Figure 15 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0060] Figure 16Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the initial support layer in the memory preparation method provided by some embodiments of the present application; Figure 16 Figure (b) in this is Figure 16 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 16 Figure (c) in this is Figure 16 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 16 Figure (d) in this is Figure 16 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this;

[0061] Figure 17 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the third mask in the memory preparation method provided by some embodiments of the present application; Figure 17 Figure (b) in this is Figure 17 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 17 Figure (c) in this is Figure 17 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 17 Figure (d) in this is Figure 17 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this; Figure 17 Figure (e) in this is Figure 17 a schematic top view structure diagram of the structure shown in Figure (a) in this;

[0062] Figure 18 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the read transistor etching groove in the memory preparation method provided by some embodiments of the present application; Figure 18 Figure (b) in this is Figure 18 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 18 Figure (c) in this is Figure 18 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 18 Figure (d) in this is Figure 18 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this;

[0063] Figure 19 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the read transistor accommodation groove in the memory preparation method provided by some embodiments of the present application; Figure 19 Figure (b) in this is Figure 19 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 19 Figure (c) in this isFigure 19 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 19 Figure (d) in Figure 19 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0064] Figure 20 Figure (a) in shows a schematic cross-sectional structure diagram of the structure obtained after forming the first semiconductor layer in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 20 Figure (b) in Figure 20 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 20 Figure (c) in Figure 20 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 20 Figure (d) in Figure 20 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0065] Figure 21 Figure (a) in shows a schematic cross-sectional structure diagram of the structure obtained after forming the filling dielectric layer in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 21 Figure (b) in Figure 21 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 21 Figure (c) in Figure 21 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 21 Figure (d) in Figure 21 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0066] Figure 22 Figure (a) in shows a schematic cross-sectional structure diagram of the structure obtained after forming the fourth mask in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 22 Figure (b) in Figure 22 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 22 Figure (c) in Figure 22 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 22 Figure (d) in Figure 22 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction; Figure 22 Figure (e) in Figure 22 Top view structure diagram of the structure shown in Figure (a);

[0067] Figure 23Figure (a) in [this document] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the ground wire etching groove in the method for manufacturing a memory provided by some embodiments of the present application; Figure 23 Figure (b) in [this document] is Figure 23 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [this document]; Figure 23 Figure (c) in [this document] is Figure 23 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [this document]; Figure 23 Figure (d) in [this document] is Figure 23 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [this document];

[0068] Figure 24 Figure (a) in [this document] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the ground wire accommodating groove in the method for manufacturing a memory provided by some embodiments of the present application; Figure 24 Figure (b) in [this document] is Figure 24 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [this document]; Figure 24 Figure (c) in [this document] is Figure 24 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [this document]; Figure 24 Figure (d) in [this document] is Figure 24 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [this document];

[0069] Figure 25 Figure (a) in [this document] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the ground wire in the method for manufacturing a memory provided by some embodiments of the present application; Figure 25 Figure (b) in [this document] is Figure 25 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [this document]; Figure 25 Figure (c) in [this document] is Figure 25 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [this document]; Figure 25 Figure (d) in [this document] is Figure 25 a schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in [this document];

[0070] Figure 26 Figure (a) in [this document] is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the fifth mask in the method for manufacturing a memory provided by some embodiments of the present application; Figure 26 Figure (b) in [this document] is Figure 26 a schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in [this document]; Figure 26 Figure (c) in [this document] is Figure 26 a schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in [this document]; Figure 26 Figure (d) in [this document] isFigure 26 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction; Figure 26 Figure (e) in Figure 26 Schematic top-view structure diagram of the structure shown in Figure (a) in

[0071] Figure 27 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the read word line isolation groove in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 27 Figure (b) in Figure 27 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 27 Figure (c) in Figure 27 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 27 Figure (d) in Figure 27 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0072] Figure 28 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the read word line isolation layer in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 28 Figure (b) in Figure 28 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 28 Figure (c) in Figure 28 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 28 Figure (d) in Figure 28 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0073] Figure 29 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the sixth mask in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 29 Figure (b) in Figure 29 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 29 Figure (c) in Figure 29 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 29 Figure (d) in Figure 29 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction; Figure 29 Figure (e) in Figure 17 Schematic top-view structure diagram of the structure shown in Figure (a);

[0074] Figure 30Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the first gate etching groove in the memory preparation method provided by some embodiments of the present application; Figure 30 Figure (b) in this is Figure 30 the schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 30 Figure (c) in this is Figure 30 the schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 30 Figure (d) in this is Figure 30 the schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this;

[0075] Figure 31 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the first gate accommodation groove in the memory preparation method provided by some embodiments of the present application; Figure 31 Figure (b) in this is Figure 31 the schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 31 Figure (c) in this is Figure 31 the schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 31 Figure (d) in this is Figure 31 the schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this;

[0076] Figure 32 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the first gate dielectric layer in the memory preparation method provided by some embodiments of the present application; Figure 32 Figure (b) in this is Figure 32 the schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 32 Figure (c) in this is Figure 32 the schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 32 Figure (d) in this is Figure 32 the schematic cross-sectional structure diagram in the dd' direction of the structure shown in Figure (a) in this;

[0077] Figure 33 Figure (a) in this is a schematic cross-sectional structure diagram in the aa' direction of the structure obtained after forming the read word line in the memory preparation method provided by some embodiments of the present application; Figure 33 Figure (b) in this is Figure 33 the schematic cross-sectional structure diagram in the bb' direction of the structure shown in Figure (a) in this; Figure 33 Figure (c) in this is Figure 33 the schematic cross-sectional structure diagram in the cc' direction of the structure shown in Figure (a) in this; Figure 33 Figure (d) in this isFigure 33 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0078] Figure 34 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the seventh mask in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 34 Figure (b) in is Figure 34 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 34 Figure (c) in is Figure 34 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 34 Figure (d) in is Figure 34 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction; Figure 34 Figure (e) in is Figure 34 Top view structure diagram of the structure shown in Figure (a);

[0079] Figure 35 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the first partition groove in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 35 Figure (b) in is Figure 35 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 35 Figure (c) in is Figure 35 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 35 Figure (d) in is Figure 35 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0080] Figure 36 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the first partition layer in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 36 Figure (b) in is Figure 36 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 36 Figure (c) in is Figure 36 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 36 Figure (d) in is Figure 36 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0081] Figure 37 Figure (a) in is the schematic cross-sectional structure diagram of the structure obtained after forming the eighth mask in the preparation method of the memory provided by some embodiments of the present application in the aa' direction; Figure 37Figure (b) in Figure 37 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 37 Figure (c) in Figure 37 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 37 Figure (d) in Figure 37 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 37 Figure (e) in Figure 37 is a schematic top view structure diagram of the structure shown in Figure (a) in

[0082] Figure 38 Figure (a) in Figure 38 is a schematic cross-sectional structure diagram of the structure obtained after forming the first bit line accommodation groove in the memory preparation method provided by some embodiments of the present application in the aa' direction; Figure 38 Figure (b) in Figure 38 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 38 in the bb' direction; Figure 38 Figure (c) in Figure 38 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in

[0083] Figure 39 Figure (a) in Figure 39 is a schematic cross-sectional structure diagram of the structure obtained after forming the first bit line material layer in the memory preparation method provided by some embodiments of the present application in the aa' direction; Figure 39 Figure (b) in Figure 39 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 39 in the bb' direction; Figure 39 Figure (c) in Figure 39 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in

[0084] Figure 40 Figure (a) in Figure 40 is a schematic cross-sectional structure diagram of the structure obtained after forming the first part of the bit line in the memory preparation method provided by some embodiments of the present application in the aa' direction; Figure 40 Figure (b) in Figure 40 is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in Figure 40 in the bb' direction; Figure 40 Figure (c) in Figure 40Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the dd' direction;

[0085] Figure 41 FIG. (a) in is a schematic cross-sectional structure diagram of the structure obtained after forming the ninth mask in the preparation method of the memory provided in some embodiments of the present application in the aa' direction; Figure 41 FIG. (b) in is Figure 41 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the bb' direction; Figure 41 FIG. (c) in is Figure 41 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the cc' direction; Figure 41 FIG. (d) in is Figure 41 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the dd' direction; Figure 41 FIG. (e) in is Figure 41 Top view structure diagram of the structure shown in FIG. (a);

[0086] Figure 42 FIG. (a) in is a schematic cross-sectional structure diagram of the structure obtained after forming the write word line defining hole in the preparation method of the memory provided in some embodiments of the present application in the aa' direction; Figure 42 FIG. (b) in is Figure 42 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the bb' direction; Figure 42 FIG. (c) in is Figure 42 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the cc' direction; Figure 42 FIG. (d) in is Figure 42 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the dd' direction;

[0087] Figure 43 FIG. (a) in is a schematic cross-sectional structure diagram of the structure obtained after forming the write transistor accommodating groove in the preparation method of the memory provided in some embodiments of the present application in the aa' direction; Figure 43 FIG. (b) in is Figure 43 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the bb' direction; Figure 43 FIG. (c) in is Figure 43 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the cc' direction; Figure 43 FIG. (d) in is Figure 43 Schematic cross-sectional structure diagram of the structure shown in FIG. (a) in the dd' direction;

[0088] Figure 44 FIG. (a) in is a schematic cross-sectional structure diagram of the structure obtained after forming the second semiconductor material layer, the second gate dielectric material layer and the second gate material layer in the preparation method of the memory provided in some embodiments of the present application in the aa' direction;Figure 44[[END Figure (b) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of bb'; ​ Figure (c) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of cc';

[0089] ​ Figure (a) in ​ is a schematic cross-sectional structure diagram of the structure obtained after forming the second gate in the memory preparation method provided by some embodiments of the present application in the direction of aa'; ​ Figure (b) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of bb'; ​ Figure (c) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in

[0090] ​ the direction of cc'; ​ Figure (a) in ​ is a schematic cross-sectional structure diagram of the structure obtained after forming the second semiconductor layer and the second gate dielectric layer in the memory preparation method provided by some embodiments of the present application in the direction of aa'; ​ Figure (b) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of bb'; ​ Figure (c) in

[0091] ​ is a schematic cross-sectional structure diagram of the structure obtained after forming the second isolation layer in the memory preparation method provided by some embodiments of the present application in the direction of aa'; ​ Figure (b) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of bb'; ​ Figure (c) in ​ is a schematic cross-sectional structure diagram of the structure shown in Figure (a) in ​ the direction of cc';

[0092] ​ Figure (a) in [reference] is a schematic cross-sectional structure view in the aa' direction of the structure obtained after forming the second isolation layer in the method for manufacturing a memory provided by some embodiments of the present application; ​ Figure (b) in [reference] is ​ a schematic cross-sectional structure view in the bb' direction of the structure shown in Figure (a) in [reference]; ​ Figure (c) in [reference] is ​ a schematic cross-sectional structure view in the cc' direction of the structure shown in Figure (a) in [reference]; ​ Figure (d) in [reference] is ​ a schematic cross-sectional structure view in the dd' direction of the structure shown in Figure (a) in [reference];

[0093] ​ Figure (a) in [reference] is a schematic cross-sectional structure view in the aa' direction of the structure obtained after forming the tenth mask in the method for manufacturing a memory provided by some embodiments of the present application; ​ Figure (b) in [reference] is ​ a schematic cross-sectional structure view in the bb' direction of the structure shown in Figure (a) in [reference]; ​ Figure (c) in [reference] is ​ a schematic cross-sectional structure view in the cc' direction of the structure shown in Figure (a) in [reference]; ​ Figure (d) in [reference] is ​ a schematic cross-sectional structure view in the dd' direction of the structure shown in Figure (a) in [reference]; ​ Figure (e) in [reference] is ​ a schematic top view structure of the structure shown in Figure (a) in [reference];

[0094] ​ Figure (a) in [reference] is a schematic cross-sectional structure view in the aa' direction of the structure obtained after removing the initial support layer formed in the support etching groove in the method for manufacturing a memory provided by some embodiments of the present application; ​ Figure (b) in [reference] is ​ a schematic cross-sectional structure view in the bb' direction of the structure shown in Figure (a) in [reference]; ​ Figure (c) in [reference] is ​ a schematic cross-sectional structure view in the cc' direction of the structure shown in Figure (a) in [reference]; ​ Figure (d) in [reference] is ​ a schematic cross-sectional structure view in the dd' direction of the structure shown in Figure (a) in [reference];

[0095] ​ Figure (a) in [reference] is a schematic cross-sectional structure view in the aa' direction of the structure obtained after removing the initial support layer in each support groove in the method for manufacturing a memory provided by some embodiments of the present application; ​ Figure (b) in [reference] is ​Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; ​ Figure (c) in ​ Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; ​ Figure (d) in ​ Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0096] ​ Figure (a) in shows the schematic cross-sectional structure diagram of the obtained structure after disconnecting the side of the first semiconductor layer close to the write transistor in the aa' direction in the manufacturing method of the memory provided by some embodiments of the present application; ​ Figure (b) in ​ Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 52 Figure (c) in Figure 52 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 52 Figure (d) in Figure 52 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0097] Figure 53 Figure (a) in shows the schematic cross-sectional structure diagram of the obtained structure after forming the support layer in the aa' direction in the manufacturing method of the memory provided by some embodiments of the present application; Figure 53 Figure (b) in Figure 53 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 53 Figure (c) in Figure 53 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 53 Figure (d) in Figure 53 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction;

[0098] Figure 54 Figure (a) in shows the schematic cross-sectional structure diagram of the obtained structure after forming the second protective layer in the aa' direction in the manufacturing method of the memory provided by some embodiments of the present application; Figure 54 Figure (b) in Figure 54 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the bb' direction; Figure 54 Figure (c) in Figure 54 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the cc' direction; Figure 54 Figure (d) in Figure 54 Schematic cross-sectional structure diagram of the structure shown in Figure (a) in the dd' direction.

[0099] Explanation of reference numerals:

[0100] U, storage cell; T1, read transistor; T2, write transistor; RWL, read word line; WWL, write word line; BL, bit line; BL1, first part of the bit line; BL1', first bit line material layer; BL2, second part of the bit line; CL, connection line; GND, ground wire; E1, first storage cell definition groove; E2, second storage cell definition groove; E3, support etching groove; E4, support groove; E5, read transistor etching groove; E6, read transistor accommodation groove; E7, ground wire etching groove; E8, ground wire accommodation groove; E9, read word line isolation groove; E10, first gate etching groove; E11, first gate accommodation groove; E12, first partition groove; E13, first bit line accommodation groove; E14, write word line definition hole; E15, write transistor accommodation groove; t, groove; 1, substrate; 2, stacked structure; 201, insulating material layer; 202, conductive material layer; 203, first etching stop layer; 204a, first hard mask material layer; 204b, second hard mask material layer; 204c, third hard mask material layer; 204d, fourth hard mask material layer; 204e, fifth hard mask material layer; 204f, sixth hard mask material layer; 205a, first anti-reflection layer; 205b, second anti-reflection layer; 205c, third anti-reflection layer; 205d, fourth anti-reflection layer; 205e, fifth anti-reflection layer; 205f, sixth anti-reflection layer; 206a, first mask; 206b, second mask; 206c, third mask; 206d, fourth mask; 206e, fifth mask; 206f, sixth mask; 206g, seventh mask; 206h, eighth mask; 207, storage cell isolation layer; 208, initial support layer; 209, support layer; 21, first gate; 211, first gate dielectric layer; 212, filling dielectric layer; 213, read word line isolation layer; 214, first isolation layer; 22, first semiconductor layer; 23, storage gate; 231, storage gate dielectric layer; 301, second etching stop layer; 302a, ninth hard mask material layer; 302b, tenth hard mask material layer; 303a, ninth anti-reflection layer; 303b, tenth anti-reflection layer; 304a, ninth mask; 304b, tenth mask; 31, second gate; 31', second gate material layer; 311, second gate dielectric layer; 311', second gate dielectric material layer; 32, second semiconductor layer; 32', second semiconductor material layer; 33, second isolation layer; 4, first protective layer; 5, second protective layer. Detailed implementation manners

[0101] To facilitate an understanding of the present application, the present application will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0102] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application.

[0103] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or intervening elements or layers may be present. It should be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, semiconductor layers, and / or portions, these elements, components, regions, layers, semiconductor layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, semiconductor layer, or portion from another element, component, region, layer, semiconductor layer, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, semiconductor layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first semiconductor layer may be referred to as the second semiconductor layer, and similarly, the second semiconductor layer may be referred to as the first semiconductor layer; the first semiconductor layer and the second semiconductor layer are different semiconductor layers.

[0104] Spatial relationship terms such as "on" may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "on" another element or feature will be oriented "under" the other element or feature. Thus, the exemplary term "on" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0105] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0106] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, the types, quantities and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0107] Due to the deficiencies of the manufacturing process, the traditional 3D memory structure will cause loss of charge in the storage capacitor during data reading (also known as destructive reading), and the read-write flexibility is poor, resulting in degradation of the reliability and access efficiency of the memory, thus affecting the further improvement of the 3D memory structure and performance.

[0108] In view of the above deficiencies in the prior art, the present application provides a memory, a method for manufacturing the same, and an electronic device, which are beneficial to improving the storage performance and reliability of the memory. The detailed content will be elaborated in the subsequent embodiments.

[0109] On the one hand, according to some embodiments, the present application provides a memory.

[0110] Please refer to Figure 1 , in some embodiments, the memory may specifically include a substrate 1, a plurality of memory cells U, a read word line RWL, a write word line WWL, and a bit line BL.

[0111] As Figure 4 shown in FIG. (a) of Figure 4 FIG. (b) of Figure 4 FIG. (c) of Figure 4 and FIG. (d) of

[0112] The read word line RWL is located on the substrate 1 and extends in a direction perpendicular to the substrate 1; the first gate 21 of the read transistor T1 is a part of the read word line RWL.

[0113] The write word line WWL is located on the substrate 1 and is distributed at intervals from the read word line RWL. The write word line WWL extends in a direction perpendicular to the substrate 1; the second gate 31 of the write transistor T2 is a part of the write word line WWL.

[0114] The bit line BL includes a connected first part BL1 and a second part BL2. The first part BL1 of the bit line can be arranged on a side of the first gate 21 away from the write transistor T2 and is connected to the first semiconductor layer 22. The second part BL2 of the bit line is arranged on a side of the second semiconductor layer 32 away from the read transistor T1 and is connected to the second semiconductor layer 32.

[0115] In the memory provided in the above embodiment, two transistors (the read transistor T1 and the write transistor T2) are used as the storage unit U, and the storage gate 23 is used to store charges, realizing a storage unit U with a two-transistor zero-capacitor (also called 2T0C) structure. Compared with the related technology, the storage capacitor is omitted, which is beneficial to improving the structure integration degree, reducing leakage and refresh time; since the storage gate 23 is used instead of the storage capacitor, compared with the traditional memory, the charge in the storage capacitor will be lost during data reading (also called destructive reading). The above memory will not cause loss of charge during data reading, realizing non-destructive reading, making the memory have higher read-write flexibility, improving the use reliability and access efficiency of the memory, and further improving the storage performance and use reliability of the memory.

[0116] Moreover, in the memory provided in the above embodiment, the read transistor T1 includes the first gate 21 and the storage gate 23. The read transistor T1 adopts a double-gate structure, which is beneficial to improving the gate control ability of the read transistor T1, reducing the subthreshold swing, thereby improving the switching ratio of the read transistor T1, and further improving the electrical performance of the memory. In the memory provided in the above embodiment, the bit line BL is set to include a connected first part BL1 and a second part BL2. The first part BL1 of the bit line is connected to the read transistor T1, and the second part BL2 is connected to the write transistor T2. Compared with separately setting the read bit line and the write bit line in the related technology, the above memory can reduce the number of bit lines, enabling the memory to achieve a higher structure density and being beneficial to layout design, especially for layout design in a narrow space, thereby further improving the practicability of the memory.

[0117] As an example, as Figure 2 and Figure 3 shown, the first parts BL1 of multiple bit lines arranged in different layers in a direction perpendicular to the substrate 1 can form a stepped shape.

[0118] Figure 5 This is the equivalent circuit of the memory with a 2T0C structure in the embodiments of the present application. In the embodiments of the present application, the storage gate 23 can be used to store charges, corresponding to the storage node SN in Figure 5 the

[0119] In some embodiments, as shown in FIG. (a) in Figure 4 , FIG. (b) in Figure 4 , FIG. (c) in Figure 4 and FIG. (d) in Figure 4 , the first semiconductor layer 22 has a second surface close to the substrate 1 and a first surface away from the substrate 1 in the direction perpendicular to the substrate 1. The first part BL1 of the bit line is located on the first surface. The second semiconductor layer 32 has opposite first and second sides in the direction parallel to the substrate 1, and the second part BL2 of the bit line is located on the second side of the second semiconductor layer 32.

[0120] Please continue to refer to Figure 1 and Figure 4 . In some embodiments, the memory may further include a connection line CL.

[0121] The connection line CL is located on one side of the read transistor T1 in the direction parallel to the substrate 1, and is located on the first side and the second side of the second semiconductor layer 32.

[0122] In some embodiments, the connection line CL can be integrally connected to the second part BL2 of the bit line.

[0123] Please continue to refer to Figure 1 . In some embodiments, the read word line RWL can surround the sidewall of the first semiconductor layer 22, and the second semiconductor layer 32 can surround the sidewall of the write word line WWL.

[0124] Please continue to refer to Figure 1 and Figure 4 . In some embodiments, the memory may further include a ground wire GND. The ground wire GND can be located beside the read word line RWL and is parallel to the read word line RWL. The ground wire GND is connected to the first semiconductor layer 22.

[0125] In some embodiments, the ground wire GND can include a main body portion and a plurality of branch portions.

[0126] Among them, the branch portions extend from the main body portion in the direction parallel to the substrate 1, and the surfaces of the branch portions close to and away from the substrate 1 are both connected to the first semiconductor layer 22.

[0127] As an example, both the surface of the branch portion close to the substrate 1 and the surface away from the substrate 1 are connected to the first semiconductor layer 22. In this way, it is beneficial to reduce the contact resistance between the ground wire GND and the first semiconductor layer 22.

[0128] In some embodiments, the first semiconductor layer 22 may be annular, and the first semiconductor layer 22 surrounds the storage gate 23. In this way, it is beneficial to improve the gate control ability of the memory.

[0129] On the other hand, according to some embodiments, the present application also provides a method for manufacturing a memory.

[0130] Please refer to Figure 6 , in some embodiments, the method for manufacturing the memory may specifically include the following steps:

[0131] S110: Provide a substrate.

[0132] S120: Form a plurality of memory cells stacked in a direction perpendicular to the substrate on the substrate; the memory cells include a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer, and a storage gate, and the write transistor includes a second gate and a second semiconductor layer; wherein, the storage gate is located on a side of the first semiconductor layer away from the first gate.

[0133] S130: Form a read word line extending in a direction perpendicular to the substrate on the substrate; use a part of the read word line as the first gate of the read transistor.

[0134] S140: Form a write word line spaced apart from the read word line on the substrate; the write word line extends in a direction perpendicular to the substrate, and use a part of the write word line as the second gate of the write transistor.

[0135] S150: Form a bit line; the bit line includes a connected first part and a second part; the first part of the bit line is formed on a side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second part of the bit line is formed on a side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer.

[0136] In the manufacturing method provided in the above embodiments, two transistors (a read transistor and a write transistor) are formed to constitute a memory cell, and a storage gate is used to store charges, implementing a memory cell with a dual-transistor zero-capacitance (also known as 2T0C) structure. Compared with the related art, the storage capacitor is omitted, which is beneficial to improving the structure integration degree, reducing leakage and refresh time. Since the storage gate is used instead of the storage capacitor, compared with the traditional memory where the charges in the storage capacitor are lost during data reading (also known as destructive reading), the memory prepared in the above embodiments will not cause charge loss during data reading, achieving non-destructive reading, making the memory have higher read-write flexibility, improving the use reliability and access efficiency of the memory, and further enhancing the storage performance and use reliability of the memory.

[0137] Moreover, in the memory prepared in the above embodiments, the read transistor includes a first gate and a storage gate. The read transistor adopts a dual-gate structure, which is beneficial to improving the gate control ability of the read transistor, reducing the subthreshold swing, thereby increasing the switching ratio of the read transistor, and further improving the electrical performance of the memory. In the above embodiments, the bit line is formed to include a first part and a second part connected to each other. The first part of the bit line is connected to the read transistor, and the second part is connected to the write transistor. Compared with separately setting a read bit line and a write bit line in the related art, adopting the above embodiments can reduce the number of bit lines, enabling the memory to achieve a higher structure density and being beneficial to layout design, especially for layout design in a narrow space, thereby also improving the practicality of the memory.

[0138] Please refer to Figure 7 , in some embodiments, after providing the substrate, the manufacturing method of the memory further includes: forming a stacked structure on the substrate. The stacked structure includes multiple insulating material layers and multiple conductive material layers alternately stacked along the direction perpendicular to the substrate.

[0139] In some embodiments, the process of forming the first gate, the first semiconductor layer, and the read word line may specifically include the following steps:

[0140] S210: Etch the insulating material layer to form an etch groove for the read transistor; conformally cover the inner wall of the etch groove for the read transistor with the first semiconductor layer.

[0141] S220: Form a filling dielectric layer in the etch groove for the read transistor.

[0142] S230: Etch the filling dielectric layer to form a receiving groove for the read word line; fill and form the read word line in the receiving groove for the read word line; the first gate is the part of the read word line corresponding to the first semiconductor layer.

[0143] Please refer to Figure 8 , in some embodiments, after forming the first gate, the first semiconductor layer, and the read word line, the manufacturing method further includes:

[0144] S310: Etch the stacked structure to form a write transistor accommodating groove and a write word line defining hole; the write transistor accommodating groove is located within the conductive material layer, surrounding the periphery of the write word line defining hole and communicating with the write word line defining hole.

[0145] S320: Conformally cover a second semiconductor layer on the inner wall of the write transistor accommodating groove, and fill a second gate in the write transistor accommodating groove.

[0146] S330: Form a write word line in the write word line defining hole.

[0147] It should be noted that although Figures 6 to 8 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figures 6 to 8 at least a part of the steps in

[0148] include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps. Figures 9 to 54 To more clearly illustrate the preparation methods in some of the above embodiments, please refer to the following in combination with Figure 4 to understand some embodiments of the present application. It should be noted that in the embodiments of the present application, the directions of aa', bb', cc', and dd' are referred to

[0149] In step S110, as shown in Figure 9 (a) in Figure 9 (b) in Figure 9 (c) in Figure 9 (d) in

[0150] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator, etc.

[0151] Please refer to the following in combination with Figures 9 to 54 Understand that in step S120, a plurality of memory cells U are formed on the substrate 1 and stacked in a direction perpendicular to the substrate 1. The memory cell U includes a read transistor T1 and a write transistor T2. The read transistor T1 and the write transistor T2 in the same memory cell U are spaced apart in a direction parallel to the substrate 1. Among them, the read transistor T1 specifically may include a first gate 21, a first semiconductor layer 22, and a storage gate 23. The storage gate 23 is located on a side of the first semiconductor layer 22 away from the first gate 21; the write transistor T2 may include a second gate 31 and a second semiconductor layer 32.

[0152] In step S130, a read word line RWL is formed on the substrate 1 and extends in a direction perpendicular to the substrate 1, and a part of the read word line RWL is used as the first gate 21 of the read transistor T1.

[0153] In step S140, a write word line WWL is formed on the substrate 1 and is spaced apart from the read word line RWL. The write word line WWL extends in a direction perpendicular to the substrate 1, and a part of the write word line WWL is used as the second gate 31 of the write transistor T2.

[0154] In step S150, a bit line BL is formed. The bit line BL includes a connected first part BL1 and a second part BL2. The first part BL1 of the bit line is formed on a side of the first gate 21 away from the write transistor T2 and is connected to the first semiconductor layer 22; the second part BL2 of the bit line is formed on a side of the second semiconductor layer 32 away from the read transistor T1 and is connected to the second semiconductor layer 32.

[0155] The following is in combination with Figures 9 to 54 , and an exemplary description of the processes of steps S120 to S150 in some embodiments is given.

[0156] Exemplarily, after providing the substrate 1, a stacked structure 2 is formed on the substrate 1. Please continue to refer to Figure 9 Figure (a) in Figure 9 Figure (b) inFigure 9 Figure (c) in Figure 9 Figure (d) in, the stacking structure 2 may specifically include a plurality of insulating material layers 201 and a plurality of conductive material layers 202 stacked alternately along the direction of the vertical substrate 1.

[0157] It can be understood that the number of the conductive material layers 202 can be set according to the number of the storage units in the stacked multiple storage units, and one layer of storage units can be formed in each conductive material layer 202. The lowermost layer of the stacking structure 2 can be an insulating material layer 201 or a conductive material layer 202, which is allowed. In the embodiments of the present application, the lowermost layer of the stacking structure 2 is an insulating material layer 201 for exemplary illustration.

[0158] In the embodiments of the present application, the constituent material of the insulating material layer 201 is not specifically limited. As an example, the constituent material of the insulating material layer 201 may include but is not limited to silicon dioxide (SiO 2 ). In the embodiments of the present application, the manner of forming the insulating material layer 201 is not specifically limited either. As an example, the insulating material layer 201 can be formed by but is not limited to the plasma enhanced chemical vapor deposition (PECVD) process. The insulating material layer 201 can at least be used to provide support and isolation functions in subsequent manufacturing processes.

[0159] In the embodiments of the present application, the constituent material of the conductive material layer 202 is not specifically limited. As an example, the constituent material of the conductive material layer 202 may include but is not limited to titanium nitride (TiN). In the embodiments of the present application, the manner of forming the conductive material layer 202 is not specifically limited either. As an example, the conductive material layer 202 can be formed by but is not limited to the physical vapor deposition (PVD) process, the atomic layer deposition (ALD) process, or the chemical vapor deposition (CVD) process.

[0160] Please refer to Figure 10 Figure (a) in Figure 10 Figure (b) in Figure 10 Figure (c) in Figure 10 Figure (d) in Figure 10In Figure (e), after forming the stacked structure 2, a first etch stop layer 203, a first hard mask material layer 204a, and a first anti-reflection layer 205a are sequentially formed on the stacked structure 2 from bottom to top along the direction perpendicular to the substrate 1, and a first mask (also referred to as a photomask) 206a is formed on the surface of the first anti-reflection layer 205a away from the substrate 1. Among them, the first mask 206a has a first photomask pattern, and the first photomask pattern can be used to define the position and shape of the storage unit in the direction parallel to the substrate 1.

[0161] The embodiments of the present application do not specifically limit the constituent material of the first etch stop layer 203. As an example, the constituent material of the first etch stop layer 203 may include but is not limited to silicon nitride (SiN). The embodiments of the present application also do not specifically limit the method of forming the first etch stop layer 203. As an example, the first etch stop layer 203 can be formed by but is not limited to atomic layer deposition process and chemical vapor deposition process. The first etch stop layer 203 can at least be used as a stop layer when the obtained structure is planarized by a chemical mechanical polishing (CMP) process in subsequent processes.

[0162] The embodiments of the present application do not specifically limit the constituent material of the first hard mask material layer 204a. As an example, the constituent material of the first hard mask material layer 204a may include but is not limited to carbon. The embodiments of the present application also do not specifically limit the method of forming the first hard mask material layer 204a. As an example, the first hard mask material layer 204a can be formed by but is not limited to plasma enhanced chemical vapor deposition process. Exemplarily, in subsequent processes, the first photomask pattern of the first mask 206a can be transferred to the first hard mask material layer 204a through a lithography process to form a hard mask layer.

[0163] The embodiments of the present application do not specifically limit the constituent material of the first anti-reflection layer 205a. As an example, the constituent material of the first anti-reflection layer 205a may include but is not limited to silicon oxynitride (SiON). The embodiments of the present application also do not specifically limit the method of forming the first anti-reflection layer 205a. As an example, the first anti-reflection layer 205a can be formed by but is not limited to plasma enhanced chemical vapor deposition process.

[0164] Please refer to Figure 11 Figure (a) in Figure 11 Figure (b) in Figure 11 Figure (c) in Figure 11In FIG. (d), using the first mask 206a as a mask, the first anti-reflection layer 205a and the first hard mask material layer 204a are etched. The first anti-reflection layer 205a and the first hard mask material layer 204a covered by the first mask 206a are retained, and the first anti-reflection layer 205a and the first hard mask material layer 204a not covered by the first mask 206a are removed, thereby transferring the first mask pattern of the first mask 206a to the first anti-reflection layer 205a and the first hard mask material layer 204a. The retained first hard mask material layer 204a serves as the first hard mask layer. Subsequently, using the first hard mask layer as a mask, the first etch stop layer 203 and the stacked structure 2 are etched to form, within the stacked structure 2, first memory cell defining trenches E1 extending in the second direction (e.g., the Y direction) and spaced apart in the first direction (e.g., the X direction), and second memory cell defining trenches E2 extending in the first direction (e.g., the X direction) and spaced apart in the second direction (e.g., the Y direction).

[0165] It can be understood that the first memory cell defining trenches E1 and the second memory cell defining trenches E2 can define the positions and shapes of the memory cells within the stacked structure 2.

[0166] The embodiments of the present application do not specifically limit the manner of etching the first etch stop layer 203 and the stacked structure 2. By way of example, but not limited to, a dry etch process can be used to etch the first etch stop layer 203 and the stacked structure 2.

[0167] Please refer to Figure 12 FIG. (a) in Figure 12 FIG. (b) in Figure 12 FIG. (c) in and Figure 12 FIG. (d) in, a memory cell isolation layer 207 is formed within the first memory cell defining trenches E1 and the second memory cell defining trenches E2 to isolate adjacent memory cells in subsequent manufacturing processes.

[0168] The embodiments of the present application do not specifically limit the constituent materials of the memory cell isolation layer 207. By way of example, the constituent materials of the memory cell isolation layer 207 can include, but are not limited to, silicon dioxide. The embodiments of the present application do not specifically limit the manner of forming the memory cell isolation layer 207. By way of example, the memory cell isolation layer 207 can be formed using the following steps:

[0169] A storage cell isolation material layer is formed in the first storage cell definition groove E1 and the second storage cell definition groove E2, and on the surface of the stacking structure 2 by a deposition process, and the deposition process may be, for example, an atomic layer deposition process and / or a spin-on dielectric layer (SOD) process; then an annealing process is performed to anneal and densify the storage cell isolation material layer filled in the first storage cell definition groove E1 and the second storage cell definition groove E2, so as to achieve a better isolation effect. Then, the storage cell isolation material layer formed on the surface of the stacking structure 2 is removed, and the storage cell isolation material layer filled in the first storage cell definition groove E1 and the second storage cell definition groove E2 is retained as the storage cell isolation layer 207. Exemplarily, the storage cell isolation layer 207 may be planarized by a chemical mechanical polishing process to improve the surface flatness and thickness uniformity of the storage cell isolation layer 207.

[0170] As mentioned above, in the process of planarizing the memory cell isolation layer 207 by using the chemical mechanical polishing process, the first etch stop layer 203 can be used as a stop layer.

[0171] See also Figure 13 Figure (a) in Figure 13 Figure (b) in Figure 13 Figure (c) in Figure 13 Figure (d) and Figure 13 In FIG. (e), a second hard mask material layer 204b and a second anti-reflection layer 205b are sequentially stacked from bottom to top along a direction perpendicular to the substrate 1 on the surface of the first etch stop layer 203 and the memory cell isolation layer 207 away from the substrate 1, and a second mask plate 206b is formed on the surface of the second anti-reflection layer 205b away from the substrate 1. The second mask plate 206b has a second mask pattern therein, and the second mask pattern can be used to define the position and shape of the supporting etching groove in the subsequent process.

[0172] For example, the second hard mask material layer 204b, the second anti-reflection layer 205b and the second mask plate 206b may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a and the first mask plate 206a, and are not described in detail herein.

[0173] See also Figure 14 Figure (a) in Figure 14 Figure (b) in Figure 14 Figure (c) and Figure 14In FIG. (d), using the second mask 206b as a mask, the second anti-reflection layer 205b and the second hard mask material layer 204b are etched. The second anti-reflection layer 205b and the second hard mask material layer 204b covered by the second mask 206b are retained, and the second anti-reflection layer 205b and the second hard mask material layer 204b not covered by the second mask 206b are removed, thereby transferring the second mask pattern of the second mask 206b to the second anti-reflection layer 205b and the second hard mask material layer 204b. The retained second hard mask material layer 204b serves as the second hard mask layer. Thereafter, using the second hard mask layer as a mask, the first etch stop layer 203 and the stack structure 2 are etched to form support etch grooves E3 extending in the second direction (e.g., the Y direction) and spaced apart in the first direction (e.g., the X direction) within the stack structure 2.

[0174] Exemplarily, the method of etching the first etch stop layer 203 and the stack structure 2 may refer to the method of etching the first etch stop layer 203 and the stack structure 2 in the foregoing steps, which will not be elaborated herein.

[0175] Please refer to Figure 15 FIG. (a) in Figure 15 FIG. (b) in Figure 15 FIG. (c) in Figure 15 FIG. (d) in

[0176] In the embodiments of the present application, the method of etching the insulating material layer 201 is not specifically limited. As an example, a lateral etching process may be used, but is not limited to, to circumferentially remove a portion of the insulating material layer 201 based on the support etch grooves E3.

[0177] Please refer to Figure 16 FIG. (a) in Figure 16 FIG. (b) in Figure 16 FIG. (c) in Figure 16 FIG. (d) in

[0178] In the embodiments of the present application, the constituent material of the initial support layer 208 is not specifically limited. As an example, the constituent material of the initial support layer 208 may include, but is not limited to, high-k dielectric materials (dielectric constant greater than 3.9).

[0179] The embodiment of the present application does not specifically limit the method for forming the initial support layer 208. As an example, the initial support layer 208 may be filled in the support etching groove E3 and the support groove E4 by using, but not limited to, an atomic layer deposition process. As an example, the initial support layer 208 may be formed by the following steps:

[0180] A support material layer is formed in the support etch grooves E3 and E4 and on the surface of the stacked structure 2 by a deposition process, and the deposition process may be, for example, an atomic layer deposition process; then, the support material layer formed on the surface of the stacked structure 2 is removed, and the support material layer filled in the support etch grooves E3 and E4 is retained as the initial support layer 208. Exemplarily, a chemical mechanical polishing process may be used to planarize the initial support layer 208, so that the surface of the initial support layer 208 away from the substrate 1 is flush with the first etch stop layer 203, so as to improve the surface flatness and thickness uniformity of the initial support layer 208.

[0181] Please combine the following Figures 17 to 33 It is understood that in some embodiments, the process of forming the first gate 21 , the first semiconductor layer 22 and the read word line RWL can be specifically expressed as the following steps S210 - S230 .

[0182] In step S210 , the insulating material layer 201 is etched to form a read transistor etching groove E5 ; the first semiconductor layer 22 is conformally covered on the inner wall of the read transistor etching groove E5 .

[0183] As an example, step S210 may specifically include the following steps:

[0184] like Figure 17 Figure (a) in Figure 17 Figure (b) in Figure 17 Figure (c) in Figure 17 Figure (d) and Figure 17 As shown in FIG. (e), a third hard mask material layer 204c and a third anti-reflection layer 205c are sequentially stacked from bottom to top along a direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207 and the initial support layer 208 away from the substrate 1, and a third mask plate 206c is formed on the surface of the third anti-reflection layer 205c away from the substrate 1. The third mask plate 206c has a third mask pattern therein, and the third mask pattern can be used to define the position and shape of the read transistor etching groove E5 in the subsequent process.

[0185] For example, the third hard mask material layer 204c, the third anti-reflection layer 205c and the third mask plate 206c may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a and the first mask plate 206a, and are not described in detail herein.

[0186] As shown in Figure 18 Figure (a) in Figure 18 Figure (b) in Figure 18 Figure (c) in Figure 18 and Figure (d) in , the third anti-reflection layer 205c and the third hard mask material layer 204c are etched using the third mask 206c as a mask. The third anti-reflection layer 205c and the third hard mask material layer 204c covered by the third mask 206c are retained, and the third anti-reflection layer 205c and the third hard mask material layer 204c not covered by the third mask 206c are removed, thereby transferring the third mask pattern of the third mask 206c to the third anti-reflection layer 205c and the third hard mask material layer 204c. The retained third hard mask material layer 204c serves as the third hard mask layer. Thereafter, the first etch stop layer 203 and the stack structure 2 are etched using the third hard mask layer as a mask to form read transistor etch trenches E5 spaced apart in the second direction (e.g., the Y direction) within the stack structure 2.

[0187] Exemplarily, the method of etching the first etch stop layer 203 and the stack structure 2 may refer to the method of etching the first etch stop layer 203 and the stack structure 2 in the foregoing steps, which will not be elaborated herein.

[0188] As shown in Figure 19 Figure (a) in Figure 19 Figure (b) in Figure 19 Figure (c) in Figure 19 and Figure (d) in , the corresponding sidewalls of each layer of insulating material layer 201 in the stack structure 2 in the first direction (e.g., the X direction) are etched based on the read transistor etch trenches E5 to form a plurality of read transistor accommodation trenches E6 located between adjacent conductive material layers 202 or between the conductive material layer 202 and the substrate 1. The read transistor accommodation trenches E6 may expose the sidewall of one side of the initial support layer 208.

[0189] The embodiment of the present application does not specifically limit the method of etching the insulating material layer 201. As an example, but not limited to, a lateral etching process may be used to circumferentially remove a part of the insulating material layer 201 based on the read transistor etch trenches E5.

[0190] As shown in Figure 20 Figure (a) in Figure 20 Figure (b) in Figure 20 Figure (c) in Figure 20 and Figure (d) in , a storage gate dielectric layer 231 is conformally coated on the inner wall of the read transistor accommodation trenches E6, the exposed surface of the substrate 1, and the sidewalls of the read transistor etch trenches E5 in the second direction (e.g., the Y direction), and then a first semiconductor layer 22 is conformally coated on the surface of the storage gate dielectric layer 231.

[0191] In the embodiments of the present application, the constituent material of the storage gate dielectric layer 231 is not specifically limited. As an example, the constituent material of the storage gate dielectric layer 231 may include but is not limited to high-k dielectric materials. Exemplarily, the high-k dielectric materials may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). In the embodiments of the present application, the method for forming the storage gate dielectric layer 231 is also not specifically limited. As an example, but not limited to, the atomic layer deposition process can be used to conformally coat the inner wall of the read transistor accommodation groove E6, the exposed surface of the substrate 1, and the side walls of the read transistor etching groove E5 in the second direction (e.g., the Y direction) with the storage gate dielectric layer 231.

[0192] In the embodiments of the present application, the constituent material of the first semiconductor layer 22 is not specifically limited. As an example, the constituent material of the first semiconductor layer 22 may include at least one of polysilicon, amorphous silicon, oxide materials, and two-dimensional materials; the oxide material may be, for example, indium gallium zinc oxide (abbreviated as IGZO). In the embodiments of the present application, the method for forming the first semiconductor layer 22 is also not specifically limited. As an example, but not limited to, the atomic layer deposition process can be used to conformally coat the first semiconductor layer 22 on the surface of the storage gate dielectric layer 231.

[0193] In some embodiments, a planarization process can be used to process the storage gate dielectric layer 231 and the first semiconductor layer 22, so that the storage gate dielectric layer 231 and the first semiconductor layer 22 are parallel to the substrate 1 and the end faces away from the substrate 1 are flush with the surface of the stack structure 2 away from the substrate 1.

[0194] In step S220, a filling dielectric layer 212 is formed in the read transistor etching groove E5. As shown in Figure 21 Figure (a) in Figure 21 Figure (b) in Figure 21 Figure (c) in Figure 21 Figure (d) in

[0195] The embodiments of the present application do not specifically limit the constituent materials of the filling dielectric layer 212. As an example, the constituent materials of the filling dielectric layer 212 may include, but are not limited to, oxide materials. The embodiments of the present application also do not specifically limit the method of forming the filling dielectric layer 212. As an example, the filling dielectric layer 212 may be formed in the read transistor etching groove E5 and the read transistor accommodating groove E6 by, but not limited to, atomic layer deposition process.

[0196] As shown in Figure 22 Figure (a) in Figure 22 Figure (b) in Figure 22 Figure (c) in Figure 22 Figure (d) in Figure 22 and Figure (e) in

[0197] Exemplarily, the fourth hard mask material layer 204d, the fourth anti-reflection layer 205d and the fourth mask 206d may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a and the first mask 206a, and will not be elaborated here.

[0198] As shown in Figure 23 Figure (a) in Figure 23 Figure (b) in Figure 23 Figure (c) in Figure 23 and Figure (d) in

[0199] Exemplarily, the method of etching the first etch stop layer 203 and the stack structure 2 may refer to the method of etching the first etch stop layer 203 and the stack structure 2 in the foregoing steps, which will not be elaborated herein.

[0200] As shown in Figure 24 Figure (a) in Figure 24 Figure (b) in Figure 24 Figure (c) in Figure 24 and Figure (d) in

[0201] The embodiments of the present application do not specifically limit the method of etching the filling dielectric layer 212. As an example, but not limited to, a lateral etching process may be used to circumferentially remove a part of the filling dielectric layer 212 based on the ground wire etching groove E7.

[0202] As shown in Figure 25 Figure (a) in Figure 25 Figure (b) in Figure 25 Figure (c) in Figure 25 and Figure (d) in

[0203] The embodiments of the present application do not specifically limit the constituent material of the ground wire GND. As an example, the constituent material of the ground wire GND may include at least one of a metal material, an alloy material, a metal nitride material, and a metal oxide material. Among them, the metal material may be, for example, tungsten (W); the metal oxide material may be, for example, indium tin oxide (ITO). The embodiments of the present application do not specifically limit the method of forming the ground wire GND. As an example, an atomic layer deposition process may be used to form the ground wire GND in the ground wire accommodation groove E8 and the ground wire etching groove E7.

[0204] As shown in Figure 26 Figure (a) in Figure 26 Figure (b) in Figure 26 Figure (c) in Figure 26 Figure (d) in Figure 26As shown in FIG. (e), a fifth hard mask material layer 204e and a fifth anti-reflection layer 205e are formed on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the filling dielectric layer 212, and the ground wire GND away from the substrate 1, stacked in sequence from bottom to top along the direction perpendicular to the substrate 1, and a fifth mask plate 206e is formed on the surface of the fifth anti-reflection layer 205e away from the substrate 1. Among them, the fifth mask plate 206e has a fifth photomask pattern, and the fifth photomask pattern can be used to define the position and shape of the read word line isolation groove in the subsequent manufacturing process.

[0205] Exemplarily, the fifth hard mask material layer 204e, the fifth anti-reflection layer 205e, and the fifth mask plate 206e can be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a, and the first mask plate 206a, and will not be elaborated here.

[0206] As Figure 27 shown in FIG. (a), Figure 27 shown in FIG. (b), Figure 27 shown in FIG. (c), and Figure 27 shown in FIG. (d), using the fifth mask plate 206e as a mask to etch the fifth anti-reflection layer 205e and the fifth hard mask material layer 204e. The fifth anti-reflection layer 205e and the fifth hard mask material layer 204e covered by the fifth mask plate 206e are retained, and the fifth anti-reflection layer 205e and the fifth hard mask material layer 204e not covered by the fifth mask plate 206e are removed, so as to transfer the fifth photomask pattern of the fifth mask plate 206e to the fifth anti-reflection layer 205e and the fifth hard mask material layer 204e. The retained fifth hard mask material layer 204e serves as the fifth hard mask layer. Then, using the fifth hard mask layer as a mask to etch the stacked structure 2, so as to form read word line isolation grooves E9 arranged at intervals in the second direction (such as the Y direction) in the stacked structure 2.

[0207] Exemplarily, the method of etching the stacked structure 2 can refer to the method of etching the stacked structure 2 in the aforementioned steps, and will not be elaborated here.

[0208] As Figure 28 shown in FIG. (a), Figure 28 shown in FIG. (b), Figure 28 shown in FIG. (c), and Figure 28 shown in FIG. (d), a read word line isolation layer 213 is filled and formed in the read word line isolation groove E9.

[0209] The embodiments of the present application do not specifically limit the constituent materials of the read word line isolation layer 213. As an example, the constituent materials of the read word line isolation layer 213 may include but are not limited to silicon nitride. The embodiments of the present application do not specifically limit the manner of forming the read word line isolation layer 213. As an example, an atomic layer deposition process may be used to fill the read word line isolation layer 213 in the read word line isolation groove E9.

[0210] In step S230, the filling dielectric layer 212 is etched to form a read word line receiving groove. A read word line RWL is formed by filling in the read word line receiving groove. Among them, the first gate 21 may be the part of the read word line RWL corresponding to the first semiconductor layer 22.

[0211] As an example, step S230 may specifically include the following steps:

[0212] As shown in Figure 29 Figure (a) in Figure 29 Figure (b) in Figure 29 Figure (c) in Figure 29 Figure (d) in Figure 29 and Figure (e) in

[0213] Exemplarily, the sixth hard mask material layer 204f, the sixth anti-reflection layer 205f and the sixth mask 206f may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a and the first mask 206a, and will not be elaborated here.

[0214] As shown in Figure 30 Figure (a) in Figure 30 Figure (b) in Figure 30 Figure (c) in Figure 30As shown in FIG. (d), the sixth anti-reflection layer 205f and the sixth hard mask material layer 204f are etched using the sixth mask 206f as a mask. The sixth anti-reflection layer 205f and the sixth hard mask material layer 204f covered by the sixth mask 206f are retained, and the sixth anti-reflection layer 205f and the sixth hard mask material layer 204f not covered by the sixth mask 206f are removed, thereby transferring the sixth mask pattern of the sixth mask 206f to the sixth anti-reflection layer 205f and the sixth hard mask material layer 204f. The retained sixth hard mask material layer 204f serves as the sixth hard mask layer. Thereafter, the stacked structure 2 is etched using the sixth hard mask layer as a mask to form first gate etching trenches E10 spaced apart in the second direction (e.g., the Y direction) within the stacked structure 2.

[0215] Exemplarily, the method of etching the stacked structure 2 may refer to the method of etching the stacked structure 2 in the foregoing steps, which will not be elaborated herein.

[0216] As Figure 31 shown in FIG. (a), Figure 31 FIG. (b), Figure 31 FIG. (c), and Figure 31 FIG. (d), the corresponding sidewalls of the filling dielectric layer 212 filled in each read transistor accommodating trench E6 are etched based on the first gate etching trench E10 in the first direction (e.g., the X direction) to form first gate accommodating trenches E11 within each read transistor accommodating trench E6. The first gate accommodating trench E11 exposes at least a part of the sidewalls of the filling dielectric layer 212 in the second direction (e.g., the Y direction), and the first gate accommodating trench E11 can be used to define the position and shape of the first gate in subsequent processes. In the embodiments of the present application, the first gate etching trench E10 and the first gate accommodating trench E11 together constitute the read word line accommodating trench.

[0217] The embodiments of the present application do not specifically limit the method of etching the filling dielectric layer 212. As an example, but not limited to, a side etching process may be used to circumferentially remove a part of the filling dielectric layer 212 based on the first gate etching trench E10.

[0218] As Figure 32 shown in FIG. (a), Figure 32 FIG. (b), Figure 32 FIG. (c), and Figure 32 FIG. (d), the first gate dielectric layer 211 is conformally covered on the inner wall of the first gate accommodating trench E11. It can be understood that in the second direction (e.g., the Y direction), the first gate dielectric layer 211 surrounds the sidewall of the first semiconductor layer 22.

[0219] The embodiments of the present application do not specifically limit the constituent materials of the first gate dielectric layer 211. As an example, the constituent materials of the first gate dielectric layer 211 may also include but are not limited to high-k dielectric materials. The constituent materials of the first gate dielectric layer 211 and the storage gate dielectric layer 231 may be the same or different. The embodiments of the present application also do not specifically limit the method of forming the first gate dielectric layer 211. As an example, atomic layer deposition process may be used, but not limited to, to conformally coat the inner wall of the first gate recess E11 with the first gate dielectric layer 211.

[0220] As Figure 33 shown in FIG. (a) Figure 33 in FIG. (b) Figure 33 in FIG. (c) Figure 33 and FIG. (d) Figure 33 shown, a read word line RWL is formed by filling in the first gate recess E11 and the first gate etch groove E10. Among them, a part of the read word line RWL filled in the first gate recess E11 serves as the first gate 21.

[0221] The embodiments of the present application do not specifically limit the constituent materials of the read word line RWL. As an example, the constituent materials of the read word line RWL may also include but are not limited to tungsten, indium tin oxide, and the like. The constituent materials of the read word line RWL and the ground wire GND may be the same or different. The embodiments of the present application do not specifically limit the method of forming the read word line RWL. As an example, atomic layer deposition process may be used to fill and form the read word line RWL in the first gate recess E11 and the first gate etch groove E10.

[0222] As Figure 34 shown in FIG. (a) Figure 34 in FIG. (b) Figure 34 in FIG. (c) Figure 34 in FIG. (d) Figure 34 and FIG. (e) Figure 34 shown, a seventh hard mask material layer and a seventh anti-reflection layer (for ease of understanding, the seventh hard mask material layer and the seventh anti-reflection layer are not marked in the figure) are formed on the surfaces of the first etch stop layer 203, the storage cell isolation layer 207, the initial support layer 208, the ground wire GND, the filling dielectric layer 212, and the read word line isolation layer 213 away from the substrate 1, stacked in sequence from bottom to top along the direction perpendicular to the substrate 1. And a seventh mask 206g is formed on the surface of the seventh anti-reflection layer away from the substrate 1. Among them, the seventh mask 206g has a seventh photomask pattern, and the seventh photomask pattern can be used to define the position and shape of the first partition groove in the subsequent manufacturing process.

[0223] Exemplarily, the seventh hard mask material layer, the seventh anti-reflection layer, and the seventh mask 206g may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a, and the first mask 206a, and will not be elaborated here.

[0224] As shown in Figure 35 Figure (a) in Figure 35 Figure (b) in Figure 35 Figure (c) in Figure 35 and Figure (d) in

[0225] Exemplarily, the etching method for the stacked structure 2, the storage gate dielectric layer 231, and the first semiconductor layer 22 may refer to the etching method for the stacked structure 2 in the foregoing steps, which will not be elaborated herein.

[0226] As shown in Figure 36 Figure (a) in Figure 36 Figure (b) in Figure 36 Figure (c) in Figure 36 and Figure (d) in

[0227] In the embodiments of the present application, the constituent material of the first isolation layer 214 is not specifically limited. As an example, the constituent material of the first isolation layer 214 may also include but is not limited to oxide materials. The constituent material of the first isolation layer 214 and the constituent material of the filling dielectric layer 212 may be the same or different. In the embodiments of the present application, the method for forming the first isolation layer 214 is also not specifically limited. As an example, the first isolation layer 214 may be filled in the first isolation groove E12 by using but not limited to atomic layer deposition process.

[0228] It should be noted that, for the sake of easy understanding, the first isolation layer 214 is not marked in the following Figures 37 to 54 figure.

[0229] In some embodiments, the process of forming the first portion BL1 of the bit line may specifically be performed through the following steps: etching the fill dielectric layer 212 and a portion of the first semiconductor layer 22 to expose the second surface of the first semiconductor layer 22 close to the substrate 1, thereby forming the first bit line receiving groove E13; then, forming the first portion BL1 of the bit line within the first bit line receiving groove E13.

[0230] As Figure 37 shown in FIG. (a) of Figure 37 FIG. (b) of Figure 37 FIG. (c) of Figure 37 FIG. (d) of Figure 37 and FIG. (e) of Figure 37 shown in FIG. (a) of Figure 37 FIG. (b) of Figure 37 FIG. (c) of Figure 37 and FIG. (d) of

[0231] Exemplarily, the eighth hard mask material layer, the eighth anti-reflection layer, and the eighth mask 206h may be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a, and the first mask 206a, and thus will not be elaborated herein.

[0232] In some embodiments, the first portion of the bit line is arranged in a stepped pattern in the first direction (e.g., the X direction). The following provides an exemplary illustration of forming the first portion of the bit line located at the topmost layer.

[0233] Figure 38 shown in FIG. (a) of Figure 38 FIG. (b) of Figure 38 FIG. (c) of Figure 38In FIG. (d), the eighth anti-reflection layer 205 and the eighth hard mask material layer 204 are etched using the eighth mask plate 206h as a mask, the eighth anti-reflection layer and the eighth hard mask material layer covered by the eighth mask plate 206h are retained, and the eighth anti-reflection layer and the eighth hard mask material layer not covered by the eighth mask plate 206h are removed, thereby transferring the eighth mask pattern of the eighth mask plate 206h to the eighth anti-reflection layer and the eighth hard mask material layer. The retained eighth hard mask material layer serves as the eighth hard mask layer. Afterwards, the eighth hard mask layer is used as a mask to etch the topmost filling dielectric layer 212, the first semiconductor layer 22 and the storage gate dielectric layer 231 in the stacked structure 2 to form the first bit line accommodating groove E13. The first bit line accommodating groove E13 exposes the side wall of the topmost filling dielectric layer 212 away from the initial support layer 208 and makes the first semiconductor layer 22 and the side of the storage gate dielectric layer 231 away from the substrate 1 flush in the second direction (eg, Y direction).

[0234] For example, the method of etching the topmost filling dielectric layer 212, the first semiconductor layer 22 and the storage gate dielectric layer 231 in the stacked structure 2 can refer to the method of etching the stacked structure 2 in the aforementioned steps, which will not be described in detail here.

[0235] like Figure 39 Figure (a) in Figure 39 Figure (b) in Figure 39 Figure (c) and Figure 39 As shown in FIG. 7 (d), a first bit line material layer BL1' is formed in the first bit line accommodating groove E13, and on the surface of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the ground line HND, the filling dielectric layer 212 and the read word line isolation layer 213 away from the substrate 1.

[0236] The embodiment of the present application does not specifically limit the method for forming the first bit line material layer BL1'. As an example, the first bit line material layer BL1' can be formed in the first bit line accommodating groove E13, and on the surface of the first etch stop layer 203, the storage unit isolation layer 207, the initial support layer 208, the ground line HND, the filling dielectric layer 212 and the read word line isolation layer 213 away from the substrate 1 by using, but not limited to, a chemical vapor deposition process.

[0237] like Figure 40 Figure (a) in Figure 40 Figure (b) in Figure 40 Figure (c) and Figure 40As shown in FIG. (d), the first bit line material layer BL1' formed on the surfaces of the first etch stop layer 203, the storage cell isolation layer 207, the initial support layer 208, the ground wire HND, the filling dielectric layer 212, and the read word line isolation layer 213 away from the surface of the substrate 1 is removed, and the first bit line material layer BL1' filled in the first bit line receiving groove E13 is retained as the first part BL1 of the bit line. Exemplarily, a chemical mechanical polishing process can be used to planarize the first part BL1 of the bit line, so that the surface of the first part BL1 of the bit line away from the substrate 1 is flush with the first etch stop layer 203, thereby improving the surface flatness and thickness uniformity of the first part BL1 of the bit line.

[0238] The embodiment of the present application does not specifically limit the constituent material of the first part BL1 of the bit line. As an example, the constituent material of the first part BL1 of the bit line may include but is not limited to metal materials. The metal material can be, for example, tungsten. Exemplarily, when tungsten is used to prepare the first part BL1 of the bit line, the foregoing method of forming the first bit line material layer BL1' can adopt a tungsten chemical vapor deposition (abbreviated as WCVD) process.

[0239] As an example, after forming the first part BL1 of the bit line, a first protective layer 4 can also be formed on the surfaces of the first part BL1 of the bit line, the first etch stop layer 203, the storage cell isolation layer 207, the initial support layer 208, the ground wire HND, the filling dielectric layer 212, and the read word line isolation layer 213 away from the surface of the substrate 1. The first protective layer 4 can at least be used to protect the first part BL1 of the bit line to prevent damage to the first part BL1 of the bit line caused by subsequent processes.

[0240] The embodiment of the present application does not specifically limit the constituent material of the first protective layer 4. As an example, the constituent material of the first protective layer 4 may include but is not limited to oxide materials. The embodiment of the present application does not specifically limit the method of forming the first protective layer 4. As an example, but not limited to, a plasma enhanced chemical vapor deposition process can be used to deposit and form the first protective layer 4 on the surfaces of the first part BL1 of the bit line, the first etch stop layer 203, the storage cell isolation layer 207, the initial support layer 208, the ground wire HND, the filling dielectric layer 212, and the read word line isolation layer 213 away from the surface of the substrate 1.

[0241] In some embodiments, after forming the first gate 21, the first semiconductor layer 22, and the read word line RWL, the preparation method may further include the following steps S310 to S330:

[0242] S310: Etch the stacked structure 2 to form a writing line defining hole E14 and a writing transistor accommodating groove E15. The writing transistor accommodating groove E15 is located within the conductive material layer 202, surrounds the periphery of the writing line defining hole E14, and is in communication with the writing line defining hole E14.

[0243] As an example, the process of forming the writing line defining hole E14 and the writing transistor accommodating groove E15 can be specifically represented by the following steps:

[0244] As shown in Figure 41 Figure (a) in Figure 41 Figure (b) in Figure 41 Figure (c) in Figure 41 Figure (d) in Figure 41 Figure (e) in, form a second etch stop layer 301, a ninth hard mask material layer 302a, and a ninth anti-reflection layer 303a stacked in sequence from bottom to top in the direction perpendicular to the substrate 1 on the surface of the first protective layer 4 away from the substrate 1, and form a ninth mask plate 304a on the surface of the ninth anti-reflection layer 303a away from the substrate 1. The ninth mask plate 206h has a ninth photomask pattern, and the ninth photomask pattern can be used to define the position and shape of the writing line WWL in subsequent processes.

[0245] Exemplarily, the ninth hard mask material layer 302a, the ninth anti-reflection layer 303a, and the ninth mask plate 304a can be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a, and the first mask plate 206a, and will not be elaborated here.

[0246] As shown in Figure 42 Figure (a) in Figure 42 Figure (b) in Figure 42 Figure (c) in Figure 42 Figure (d) in, use the ninth mask plate 304a as a mask to etch the ninth anti-reflection layer 303a and the ninth hard mask material layer 302a. The ninth anti-reflection layer 303a and the ninth hard mask material layer 302a covered by the ninth mask plate 304a are retained, and the ninth anti-reflection layer 303a and the ninth hard mask material layer 302a not covered by the ninth mask plate 304a are removed, thereby transferring the ninth photomask pattern of the ninth mask plate 304a to the ninth anti-reflection layer 303a and the ninth hard mask material layer 302a. The retained ninth hard mask material layer 302a serves as the ninth hard mask layer. Then, use the ninth hard mask layer as a mask to etch the stacked structure 2 to form a writing line defining hole E14.

[0247] Exemplarily, the method of etching the stacked structure 2 can refer to the method of etching the stacked structure 2 in the aforementioned steps, and will not be elaborated here.

[0248] As shown inFigure 43 in figure (a) of Figure 43 in figure (b) of Figure 43 in figure (c) of Figure 43 and in figure (d) of, the corresponding sidewalls of each conductive material layer 202 are etched based on the writing line to define the hole E14, so as to form a plurality of writing transistor accommodation grooves E15 located between adjacent insulating material layers 201.

[0249] The embodiments of the present application do not specifically limit the manner of etching each conductive material layer 202. As an example, but not limited to, a back-etching process can be used to etch the corresponding sidewalls of each conductive material layer 202 based on the writing line.

[0250] In step S320, a second semiconductor layer 32 is conformally coated on the inner wall of the writing transistor accommodation groove E15, and a second gate 31 is filled in the writing transistor accommodation groove E15.

[0251] As an example, step S320 may specifically include the following steps:

[0252] As shown in Figure 44 figure (a) of Figure 44 figure (b) of Figure 44 figure (c) of Figure 44 and figure (d) of, a second semiconductor material layer 32', a second gate dielectric material layer 311' and a second gate material layer 31' are sequentially formed on the inner wall of the writing transistor accommodation groove E15 and the inner wall of the writing line defining hole E14. Among them, the second semiconductor material layer 32' may also cover the surface of the second etch stop layer 301 away from the substrate 1, the second gate dielectric material layer 311' may also cover the surface of the second etch stop layer 301 away from the second etch stop layer 301, the second gate material layer 31' fills the writing line defining hole E14 and the writing transistor accommodation groove E15, and may also cover the surface of the second gate dielectric material layer 311' away from the second semiconductor material layer 32'.

[0253] The embodiments of the present application do not specifically limit the manner of forming the second semiconductor material layer 32', the second gate dielectric material layer 311' and the second gate material layer 31'. As an example, but not limited to, an atomic layer deposition process can be used to sequentially form the second semiconductor material layer 32', the second gate dielectric material layer 311' and the second gate material layer 31' on the inner wall of the writing transistor accommodation groove E15 and the inner wall of the writing line defining hole E14. It can be understood that it is allowed that the manners of forming the second semiconductor material layer 32', the second gate dielectric material layer 311' and the second gate material layer 31' are the same or different.

[0254] As shown in Figure 45 figure (a) of Figure 45 figure (b) of Figure 45as shown in Figure (c) thereof and Figure 45 as shown in Figure (d) thereof, the second gate material layer 31' formed in the writing line defining hole E14 is removed, and the second gate material layer 31' formed in the writing transistor accommodating groove E15 is retained as the second gate 31.

[0255] The embodiments of the present application do not specifically limit the constituent material of the second gate 31. As an example, the constituent material of the second gate 31 may include but is not limited to indium tin oxide. The constituent material of the second gate 31 and the constituent material of the reading word line RWL may be the same or different. The embodiments of the present application do not specifically limit the method of removing the second gate material layer 31' formed in the writing line defining hole E14. As an example, the second gate material layer 31' formed in the writing line defining hole E14 can be removed by, but not limited to, a wet etching process.

[0256] As Figure 46 shown in Figure (a) thereof, Figure 46 shown in Figure (b) thereof, Figure 46 shown in Figure (c) thereof and Figure 46 shown in Figure (d) thereof, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the writing line defining hole E14 are removed, and the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the inner wall of the writing transistor accommodating groove E15 are retained as the second semiconductor layer 32 and the second gate dielectric layer 311 respectively.

[0257] The embodiments of the present application do not specifically limit the constituent material of the second semiconductor layer 32. As an example, the constituent material of the second semiconductor layer 32 may include but is not limited to indium gallium zinc oxide. The constituent material of the second semiconductor layer 32 and the constituent material of the first semiconductor layer 22 may be the same or different. The embodiments of the present application do not specifically limit the constituent material of the second gate dielectric layer 311. As an example, the constituent material of the second gate dielectric layer 311 may include but is not limited to high-k dielectric materials. The constituent material of the second gate dielectric layer 311 and the constituent material of the first gate dielectric layer 211 may be the same or different.

[0258] In addition, the embodiments of the present application do not specifically limit the method of removing the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the writing line defining hole E14. As an example, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the writing line defining hole E14 can be removed by, but not limited to, a wet etching process.

[0259] It can be understood that the second gate material layer 31' formed in the writing line definition hole E14, the second semiconductor material layer 32' formed on the side wall and bottom of the writing line definition hole E14, and the second gate dielectric material layer 311' can be removed simultaneously. For example, the second gate material layer 31' formed in the writing line definition hole E14, the second semiconductor material layer 32' formed on the side wall and bottom of the writing line definition hole E14, and the second gate dielectric material layer 311' can be removed by the same wet etching process; or, the second gate material layer 31' formed in the writing line definition hole E14, the second semiconductor material layer 32' formed on the side wall and bottom of the writing line definition hole E14, and the second gate dielectric material layer 311' can also be removed separately. For example, the second gate material layer 31' formed in the writing line definition hole E14, the second semiconductor material layer 32' formed on the side wall and bottom of the writing line definition hole E14, and the second gate dielectric material layer 311' can be formed by multiple wet etching processes.

[0260] As an example, after forming the second semiconductor layer 32 and the second gate dielectric layer 311, a plurality of grooves t can be formed on the end faces of the second semiconductor layer 32 and the second gate dielectric layer 311 perpendicular to the substrate 1.

[0261] As shown in Figure 47 Figure (a) in Figure 47 Figure (b) in Figure 47 Figure (c) in Figure 47 Figure (d) in

[0262] In the embodiments of the present application, the constituent material of the second partition layer 33 is not specifically limited. As an example, the constituent material of the second partition layer 33 may include but is not limited to silicon dioxide. As an example, the second partition layer 33 can be formed by the following steps but is not limited to: forming a second partition material layer in each groove t and on the end face of the second gate 31 perpendicular to the substrate 1; then, removing the second partition material layer formed on the end face of the second gate 31 perpendicular to the substrate 1, and retaining the second partition material layer formed in each groove t as the second partition layer 33.

[0263] Exemplarily, the second partition material layer can be formed by but is not limited to atomic layer deposition process. Exemplarily, the second partition material layer formed on the end face of the second gate 31 perpendicular to the substrate 1 can be removed by but is not limited to dry etching process.

[0264] In step S330, please refer to Figure 48 Figure (a) in Figure 48Figure (b) in Figure 48 Figure (c) in Figure 48 Figure (d) in, a write word line WWL is formed within the write word line definition hole E14.

[0265] In the embodiments of the present application, no specific limitation is imposed on the constituent material of the write word line WWL. By way of example, the constituent material of the write word line WWL may also include, but is not limited to, indium tin oxide. The constituent material of the write word line WWL and the constituent material of the read word line RWL may be the same or different. In the embodiments of the present application, no specific limitation is imposed on the manner of forming the write word line WWL. By way of example, the write word line WWL may be formed by the following steps: a write word line material layer is formed within the write word line definition hole E14 and on the surface of the second etch stop layer 301 away from the first protective layer 4; then, the write word line material layer formed on the surface of the second etch stop layer 301 away from the first protective layer 4 is removed, and the write word line material layer filled within the write word line definition hole E14 is retained as the write word line WWL.

[0266] Exemplarily, but not limited to, an atomic layer deposition process may be used to form the write word line material layer within the write word line definition hole E14 and on the surface of the second etch stop layer 301 away from the first protective layer 4. Exemplarily, after removing the write word line material layer formed on the surface of the second etch stop layer 301 away from the first protective layer 4, a chemical mechanical polishing process may be used to planarize the surface of the write word line WWL away from the substrate 1, so as to improve the surface flatness and thickness uniformity of the write word line WWL. As described above, during the process of planarizing the write word line WWL using the chemical mechanical polishing process, the second etch stop layer 301 may be used as a stop layer.

[0267] It can be understood that in some embodiments, the constituent material of the write word line WWL may be the same as the constituent material of the second gate 31. Thus, the write word line WWL and the second gate 31 may actually be formed as an integral structure.

[0268] By way of example, the second semiconductor layer 32 is formed to have an opposite first side and second side in a direction parallel to the substrate 1; wherein, the first side is the side close to the read transistor T1, and the second side is the side away from the read transistor T1. In the said example, the second part BL2 of the bit line may be formed on the second side of the second semiconductor layer 32.

[0269] Exemplarily, the part of the connection line CL corresponding to the first gate 21 may serve as the storage gate 23; the part of the connection line CL corresponding to the first part BL1 of the bit line may serve as the drain of the read transistor T1; and the part of the connection line CL corresponding to the second side of the second semiconductor layer 32 may serve as the drain of the write transistor T2.

[0270] As an example, the second part BL2 of the bit line can be a part of the connection line CL; for example, one end of the connection line CL far from the write transistor T2 is used as the second part BL2 of the bit line. The first part BL1 and the second part BL2 can jointly form the bit line BL.

[0271] As shown in Figure 49 Figure (a) in Figure 49 Figure (b) in Figure 49 Figure (c) in Figure 49 Figure (d) in Figure 49 and Figure (e) in

[0272] Exemplarily, the tenth hard mask material layer 302b, the tenth anti-reflection layer, and the tenth mask plate 206h can be similar to the aforementioned ninth hard mask material layer 302a, the ninth anti-reflection layer 303a, and the ninth mask plate 304a, and will not be elaborated here.

[0273] As shown in Figure 50 Figure (a) in Figure 50 Figure (b) in Figure 50 Figure (c) in Figure 50 and Figure (d) in

[0274] Exemplarily, the method of etching the stacked structure 2 can refer to the method of etching the stacked structure 2 in the aforementioned steps, and will not be elaborated here.

[0275] As shown in Figure 51 Figure (a) in Figure 51 Figure (b) in Figure 51 Figure (c) in Figure 51In FIG. (d), based on the support etching groove E3, the initial support layer 208 in each support groove E4 of the stacked structure 2 is removed.

[0276] The embodiments of the present application do not specifically limit the method for removing the initial support layer 208. As an example, but not limited to, a lateral etching process can be used to remove the initial support layer 208 in each support groove E4 of the stacked structure 2 based on the support etching groove E3.

[0277] Such as Figure 52 in FIG. (a), Figure 52 in FIG. (b), Figure 52 in FIG. (c), and Figure 52 in FIG. (d), based on the support etching groove E3 and the support groove E4, a part of the first semiconductor layer 22 is removed, so that the side of the first semiconductor layer 22 close to the write transistor is disconnected, thereby effectively further eliminating the parasitic channel effect in the read transistor T1, saving the process steps for removing the parasitic channel, and the process flow is simple and easy to implement.

[0278] The embodiments of the present application do not specifically limit the method for removing a part of the first semiconductor layer 22. As an example, but not limited to, a wet etching process can be used to remove the above-mentioned part of the first semiconductor layer 22.

[0279] Such as Figure 53 in FIG. (a), Figure 53 in FIG. (b), Figure 53 in FIG. (c), and Figure 53 in FIG. (d), a support layer 209 is filled in the support etching groove E3 and the support groove E4. The support layer 209 can play a supporting role in the memory.

[0280] The embodiments of the present application do not specifically limit the constituent material of the support layer 209. As an example, the constituent material of the support layer 209 can include but not be limited to high-k dielectric materials. Using high-k dielectric materials to prepare the support layer 209 is beneficial to improving the storage node capacitance in subsequent processes. The constituent material of the support layer 209 can be the same as or different from that of the initial support layer 208.

[0281] The embodiments of the present application also do not specifically limit the method for forming the support layer 209. As an example, but not limited to, an atomic layer deposition process can be used to fill the support layer 209 in the support etching groove E3 and the support groove E4.

[0282] As an example, such as Figure 54 in FIG. (a), Figure 54 in FIG. (b), Figure 54 in FIG. (c), and Figure 54In FIG. (d), after forming the support layer 209, a second protective layer 5 can also be formed on the surfaces of the second etch stop layer 301, the write line WWL, and the support layer 209 away from the substrate 1.

[0283] The embodiments of the present application do not specifically limit the constituent material of the second protective layer 5. As an example, the constituent material of the second protective layer 5 can include but is not limited to oxide materials. The constituent material of the second protective layer 5 can be the same as or different from that of the first protective layer 4. The embodiments of the present application do not specifically limit the manner of forming the second protective layer 5. As an example, but not limited to, a plasma enhanced chemical vapor deposition process can be used to form the second protective layer 5 on the surfaces of the second etch stop layer 301, the write line WWL, and the support layer 209 away from the substrate 1.

[0284] It should be noted that the preparation methods of the memories in the embodiments of the present application can all be used to prepare the corresponding memories. Therefore, the technical features between the embodiments of the preparation methods of the memories and the embodiments of the memories can be mutually replaced and supplemented without conflict, so that those skilled in the art can learn the technical content of the present application.

[0285] On the other hand, the present application also provides an electronic device according to some embodiments. The electronic device can be, for example, a device with a data storage function such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, or a computer. The electronic device can include the memory described in the foregoing some embodiments. Therefore, the technical advantages of the foregoing memory are also possessed by this electronic device, which will not be elaborated here.

[0286] In some embodiments, the electronic device includes a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The structure of the memory can refer to the relevant descriptions in the foregoing some embodiments. Other necessary elements or components can also be included in the electronic device, which are not limited in the embodiments of the present application.

[0287] In some embodiments, an external control device such as a processor or an actuator coupled to the memory can also be integrated on the circuit board. For example, the electronic device further includes a processor integrated on the circuit board. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0288] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered to be within the scope described in this specification.

[0289] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A memory device, characterized in that, comprising: a substrate; a plurality of memory cells; the plurality of memory cells are stacked on the substrate in a direction perpendicular to the substrate; each memory cell includes a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer, and a storage gate, and the write transistor includes a second gate and a second semiconductor layer; a read word line located on the substrate and extending in a direction perpendicular to the substrate; the first gate of the read transistor is a part of the read word line; a write word line located on the substrate and spaced apart from the read word line, the write word line extending in a direction perpendicular to the substrate; the second gate of the write transistor is a part of the write word line; a bit line including a connected first part and a second part; the first part of the bit line is disposed on a side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second part of the bit line is disposed on a side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer; wherein, the storage gate is located on a side of the first semiconductor layer facing away from the first gate.

2. The memory device according to claim 1, characterized in that, the first semiconductor layer has a second surface close to the substrate and a first surface away from the substrate in a direction perpendicular to the substrate, and the first part of the bit line is located on the first surface; the second semiconductor layer has opposite first and second sides in a direction parallel to the substrate, and the second part of the bit line is located on the second side of the second semiconductor layer.

3. The memory device according to claim 2, characterized in that, the memory device further includes: a connection line; the connection line is located on a side of the read transistor in a direction parallel to the substrate, and is located on the first side and the second side of the second semiconductor layer; the connection line is integrally connected to the second part of the bit line.

4. The memory device according to claim 2, characterized in that, the read word line surrounds a sidewall of the first semiconductor layer, and the second semiconductor layer surrounds a sidewall of the write word line.

5. The memory device according to claim 1, characterized in that, further including: a ground line; the ground line is located beside the read word line and is parallel to the read word line; the ground line is connected to the first semiconductor layer.

6. The memory device according to claim 5, characterized in that, the ground line includes a main body portion and a plurality of branch portions; wherein, the branch portions extend from the main body portion in a direction parallel to the substrate, and both a surface of the branch portion close to the substrate and a surface away from the substrate are connected to the first semiconductor layer.

7. The memory device according to claim 1, characterized in that, the first semiconductor layer is annular, and the first semiconductor layer surrounds the storage gate.

8. A method for manufacturing a memory device, characterized in that, comprising: providing a substrate; Form a plurality of memory cells stacked in a direction perpendicular to the substrate on the substrate; The memory cells include a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer, and a storage gate, and the write transistor includes a second gate and a second semiconductor layer; wherein, the storage gate is located on a side of the first semiconductor layer away from the first gate; Form a read word line extending in a direction perpendicular to the substrate on the substrate; use a part of the read word line as the first gate of the read transistor; Form a write word line spaced apart from the read word line on the substrate; the write word line extends in a direction perpendicular to the substrate, and use a part of the write word line as the second gate of the write transistor; Form a bit line; the bit line includes a connected first part and a second part; the first part of the bit line is formed on a side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second part of the bit line is formed on a side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer.

9. The method for manufacturing a memory according to claim 8, wherein, After providing the substrate, the method for manufacturing the memory further includes: Form a stacked structure on the substrate; the stacked structure includes a plurality of insulating material layers and a plurality of conductive material layers alternately stacked in a direction perpendicular to the substrate; Forming the first gate, the first semiconductor layer, and the read word line includes: Etch the insulating material layer to form a read transistor etch groove; conformally cover the inner wall of the read transistor etch groove with the first semiconductor layer; Form a filling dielectric layer in the read transistor etch groove; Etch the filling dielectric layer to form a read word line receiving groove; fill and form the read word line in the read word line receiving groove; the first gate is a part of the read word line corresponding to the first semiconductor layer.

10. The method for manufacturing a memory according to claim 9, wherein, After forming the first gate, the first semiconductor layer, and the read word line, the manufacturing method further includes: Etch the stacked structure to form a write transistor receiving groove and a write word line defining hole; the write transistor receiving groove is located in the conductive material layer, surrounds the periphery of the write word line defining hole and is communicated with the write word line defining hole; Conformally cover the inner wall of the write transistor receiving groove with the second semiconductor layer, and fill the second gate in the write transistor receiving groove; Form the write word line in the write word line defining hole.

11. The method for manufacturing a memory according to claim 10, wherein, The second semiconductor layer is formed to have an opposite first side and a second side in a direction parallel to the substrate, and the second part of the bit line is formed on the second side of the second semiconductor layer.

12. The method for manufacturing a memory according to claim 11, wherein, Forming the bit line includes: Etch the filled dielectric layer and a part of the first semiconductor layer to expose a second surface of the first semiconductor layer close to the substrate side, forming a first bit line accommodation groove; form a first part of the bit line in the first bit line accommodation groove.

13. An electronic device, characterized in that it includes: a memory as described in any one of claims 1 to 7.

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